S-1410J27-A8T1U4

S-1410/1411 Series www.ablic.com 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 © ABLIC Inc., 2015-2020 The S-1410/1411 Series is a watchdog timer developed using CMOS technology, which can operate with low current consumption of 3.8 μA typ. The reset function and the low voltage detection function are available.  Features • Detection voltage: • Detection voltage accuracy: • Input voltage: • Hysteresis width: • Current consumption during watchdog timer operation: • Reset time-out period: • Watchdog time-out period: • Watchdog operation is switchable: • Watchdog operation voltage range: • Watchdog mode switching function*1: • Watchdog input edge is selectable: • Product type is selectable: • Operation temperature range: • Lead-free (Sn 100%), halogen-free *1. 2.0 V to 5.0 V, selectable in 0.1 V step ±1.5% VDD = 0.9 V to 6.0 V 5% typ. 3.8 μA typ. 14.5 ms typ. (CPOR = 2200 pF) 24.6 ms typ. (CWDT = 470 pF) Enable, Disable VDD = 2.5 V to 6.0 V Time-out mode, window mode Rising edge, falling edge, both rising and falling edges S-1410 Series ___ ________ (Product with W / T pin (Output: WDO pin)) S-1411 Series ___ _______ ________ (Product without W / T pin (Output: RST pin, WDO pin)) Ta = −40°C to +105°C The S-1411 Series is fixed to the window mode.  Application • Power supply monitoring and system monitoring in microcontroller mounted apparatus  Packages • TMSOP-8 • HSNT-8(2030) 1 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Block Diagrams 1. S-1410 Series A / B / C Type CWDT VDD WEN Noise filter WDI Noise filter W/T Noise filter WDT circuit Reference voltage circuit WDO Voltage detection circuit VSS CPOR Figure 1 2. S-1410 Series D / E / F Type CWDT VDD WEN Noise filter WDI Noise filter W/T Noise filter WDT circuit Reference voltage circuit Voltage detection circuit VSS CPOR Figure 2 2 WDO 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 3. S-1410 Series G / H / I Type CWDT VDD WEN Noise filter WDI Noise filter W/T Noise filter WDT circuit WDO Voltage detection circuit Reference voltage circuit VSS CPOR Figure 3 4. S-1410 Series J / K / L Type CWDT VDD WEN Noise filter WDI Noise filter W/T Noise filter WDT circuit Reference voltage circuit WDO Voltage detection circuit VSS CPOR Figure 4 3 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 5. S-1411 Series A / B / C Type CWDT VDD WEN Noise filter WDI Noise filter RST WDT circuit Reference voltage circuit WDO Voltage detection circuit VSS CPOR Figure 5 6. S-1411 Series D / E / F Type CWDT VDD WEN Noise filter WDI Noise filter RST WDT circuit Reference voltage circuit Voltage detection circuit VSS CPOR Figure 6 4 WDO 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 7. S-1411 Series G / H / I Type CWDT VDD WEN Noise filter WDI Noise filter RST WDT circuit Reference voltage circuit WDO Voltage detection circuit VSS CPOR Figure 7 8. S-1411 Series J / K / L Type CWDT VDD WEN Noise filter WDI Noise filter RST WDT circuit Reference voltage circuit WDO Voltage detection circuit VSS CPOR Figure 8 5 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Product Name Structure Users can select the product type, detection voltage, and package type for the S-1410/1411 Series. Refer to "1. Product name" regarding the contents of product name, "2. Product type list" regarding the product types, "3. Packages" regarding the package drawings. 1. Product name S-141 x x xx - xxxx U 4 Environmental code U: Lead-free (Sn 100%), halogen-free Package abbreviation and IC packing specifications*1 K8T2: TMSOP-8, Tape A8T1: HSNT-8(2030), Tape Detection voltage 20 to 50 (e.g., when the detection voltage is 2.0 V, it is expressed as 20.) Product type 1*2 A to L Product type 2*3 0, 1 *1. *2. *3. 6 Refer to the tape drawing. Refer to "2. Product type list".___ 0: S-1410 Series (Product with W / T pin) ________ The WDO pin outputs the signals which are from the watchdog timer circuit and the voltage detection circuit. ___ 1: S-1411 Series (Product without W / T pin) ________ The WDO pin outputs the signals which are from the watchdog timer circuit and the voltage detection circuit. _______ The RST pin outputs the signal which is from the voltage detection circuit. The watchdog mode is fixed to the window mode. 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 2. Product type list Table 1 Product Type A 3. WEN Pin Logic Constant Current Source Pull-down for WEN Pin Active "H" Available Input Edge Rising edge Output Pull-up Resistor Available B Active "H" Available Falling edge Available C Active "H" Available Both rising and falling edges Available D Active "L" Unavailable Rising edge Available E Active "L" Unavailable Falling edge Available F Active "L" Unavailable Both rising and falling edges Available G Active "H" Available Rising edge Unavailable H Active "H" Available Falling edge Unavailable I Active "H" Available Both rising and falling edges Unavailable J Active "L" Unavailable Rising edge Unavailable K Active "L" Unavailable Falling edge Unavailable L Active "L" Unavailable Both rising and falling edges Unavailable Packages Table 2 Package Name TMSOP-8 HSNT-8(2030) Package Drawing Codes Dimension Tape Reel FM008-A-P-SD PP008-A-P-SD FM008-A-C-SD PP008-A-C-SD FM008-A-R-SD PP008-A-R-SD Land − PP008-A-L-SD 7 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Pin Configurations 1. TMSOP-8 Top view 1 2 3 4 Pin No. 8 7 6 5 Figure 9 1 2 3 4 5 6 7 8 Table 3 S-1410 Series Symbol Description ___ W / T*1 Watchdog mode switching pin CPOR Reset time-out period adjustment pin CWDT Watchdog time-out period adjustment pin VSS GND pin WEN Watchdog enable pin ________ WDO Watchdog output and reset output pin WDI Watchdog input pin VDD Voltage input pin Table 4 Pin No. 1 2 3 4 5 6 7 8 ___ *1. W / T pin = "H": Time-out mode ___ W / T pin = "L": Window mode 8 Symbol _______ RST CPOR CWDT VSS WEN ________ WDO WDI VDD S-1411 Series Description Reset output pin Reset time-out period adjustment pin Watchdog time-out period adjustment pin GND pin Watchdog enable pin Watchdog output pin Watchdog input pin Voltage input pin 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 2. HSNT-8(2030) Top view 1 8 4 5 Bottom view 8 1 5 4 Pin No. 1 2 3 4 5 6 7 8 Table 5 S-1410 Series Symbol Description ___ *2 W /T Watchdog mode switching pin CPOR Reset time-out period adjustment pin CWDT Watchdog time-out period adjustment pin VSS GND pin WEN Watchdog enable pin ________ WDO Watchdog output and reset output pin WDI Watchdog input pin VDD Voltage input pin *1 Figure 10 Table 6 Pin No. 1 2 3 4 5 6 7 8 Symbol RST CPOR CWDT VSS WEN ________ WDO WDI VDD _______ S-1411 Series Description Reset output pin Reset time-out period adjustment pin Watchdog time-out period adjustment pin GND pin Watchdog enable pin Watchdog output pin Watchdog input pin Voltage input pin *1. Connect the heat sink of backside at shadowed area to the board, and set electric potential GND. However, do not use it as the function of electrode. ___ *2. W / T pin = "H": Time-out mode ___ W / T pin = "L": Window mode 9 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Pin Functions Refer to " Operations" for details. 1. ____ W / T pin (Only S-1410 Series) This is a pin to switch the watchdog mode. ___ The S-1410 Series changes to the time-out mode when the W / T pin is "H", and changes to the window mode ___ when___the W / T pin is "L". Switching the mode is prohibited during the operation. The W / T pin is___connected to a constant current source (0.3 μA typ.) and is pulled down internally. In addition, the W / T pin has a noise filter. When the power supply voltage is 5.0 V, noise with a minimum pulse width of 200 ns can be eliminated. 2. ________ RST pin (Only S-1411 Series) This is a reset output pin. It outputs "L" when detecting a low voltage. _______ Be sure to connect an external pull-up resistor (RextR) to the RST pin in the product without an output pull-up resistor. 3. _________ WDO pin 3. 1 S-1410 Series This pin combines the reset output and the watchdog output (time-out detection, double pulse detection). ________ Be sure to connect an external pull-up resistor (R ) to the WDO pin in the product without an output pull-up extW ________ resistor. Table 7 shows the WDO pin output status. Table 7 Operation Status 3. 2 ________ WDO Pin___ ___ W / T Pin = "H" W / T Pin = "L" Normal operation "H" "H" Low voltage detection "L" "L" Time-out detection "L" "L" Double pulse detection "H" "L" When watchdog timer is in Disable "H" "H" S-1411 Series This is the watchdog output (time-out detection, double pulse detection) pin. ________ Be sure to connect an external pull-up resistor (RextW) to the WDO pin in the product without an output pull-up ________ _______ resistor. Table 8 shows the WDO pin and RST pin output statuses. Table 8 Operation Status 10 ________ WDO Pin _______ RST Pin Normal operation "H" "H" Low voltage detection "L" "L" Time-out detection "L" "H" Double pulse detection "L" "H" When watchdog timer is in Disable "H" "H" 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 4. CPOR pin This is a pin to connect an adjustment capacitor for reset time-out period (CPOR) in order to generate the reset time-out period (tRST). CPOR is charged and discharged by an internal constant current circuit, and the charge-discharge duration is tRST. Refer to " Recommended Operation Conditions" and consider variation of CPOR to select an appropriate CPOR. tRST is calculated by using the following equation. tRST [ms] = CPOR delay coefficient × CPOR [nF] + tRST0 [ms] Item CPOR delay coefficient tRST0 [ms] Table 9 Min. Typ. Max. 3.9 0.0 6.5 0.2 9.1 0.6 5. CWDT pin This is a pin to connect an adjustment capacitor for watchdog time-out period (CWDT) in order to generate the watchdog time-out period (tWDU) and the watchdog double pulse detection time (tWDL). CWDT is charged and discharged by an internal constant current circuit. Refer to " Recommended Operation Conditions" and consider variation of CWDT to select an appropriate CWDT. tWDU is calculated by using the following equation. tWDU [ms] = CWDT delay coefficient 1 × CWDT [nF] + tWDU0 [ms] Item CWDT delay coefficient 1 tWDU0 [ms] Table 10 Min. 30 0.0 Typ. Max. 50 1.1 70 3.0 In addition, tWDL is calculated by using the following equation. tWDU tWDL = 32 5. 1 Cautions on watchdog double pulse detection time The watchdog double pulse detection time (tWDL) noted in " Electrical Characteristics" is a value with a starting point at the time when the CWDT pin voltage (VCWDT) begins to rise from the CWDT charge lower limit threshold (VCWL). The double pulse detection in window mode is performed even during ΔtWDL shown in Timing Diagram 7-4. Therefore, if setting to a value with a starting point at the time when VCWDT begins to rise from 0 V, the watchdog double pulse detection time (tWDL2) is calculated adding ΔtWDL as shown in the following equations. tWDL2 [ms] = tWDL + ΔtWDL [ms] ΔtWDL [ms] = CWDT delay coefficient 2 × CWDT [nF] + tWDL0 [ms] Item CWDT delay coefficient 2 tWDL0 [ms] Table 11 Min. 0.00 0.00 Typ. Max. 0.27 0.01 0.65 0.02 11 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 6. WEN pin This is a pin to switch Enable / Disable of the watchdog timer. The voltage detection circuit independently operates at all times regardless of the watchdog timer operation. In addition, the WEN pin has a noise filter. When the power supply voltage is 5.0 V, noise with a minimum pulse width of 200 ns can be eliminated. 6. 1 S-1410/1411 Series A / B / C / G / H / I type (WEN pin logic active "H" product) The watchdog timer goes to Enable if the input is "H", and the charge-discharge operation is performed at the CWDT pin. The WEN pin is connected to a constant current source (0.3 μA typ.) and is pulled down internally. 6. 2 S-1410/1411 Series D / E / F / J / K / L type (WEN pin logic active "L" product) The watchdog timer goes to Enable if the input is "L", and the charge-discharge operation is performed at the CWDT pin. The WEN pin is not pulled down internally. 7. WDI pin This is an input pin to receive a signal from the monitored object. By inputting an edge at an appropriate timing, the WDI pin confirms the normal operation of the monitored object. The WDI pin is connected to a constant current source (0.3 μA typ.) and is pulled down internally. If the WEN pin is in Disable after the initialization and reset release are performed subsequent to the power supply voltage rise, the WDI pin will be able to receive input signals after the WEN pin goes to Enable and then the input setup time (tiset) elapses. In addition, the WDI pin has a noise filter. When the power supply voltage is 5.0 V, noise with a minimum pulse width of 200 ns can be eliminated. 12 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Absolute Maximum Ratings Table 12 (Ta = +25°C unless otherwise specified) Item Symbol Unit V V V V VCPOR V VCWDT V _______ A / B / C / D / E / F type V RST pin voltage V RST G / H / I / J / K / L type V ________ A / B / C / D / E / F type V VWDO WDO pin voltage G / H / I / J / K / L type V Operation ambient temperature Topr °C Storage temperature Tstg °C Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. VDD pin voltage WDI pin voltage WEN pin voltage ___ W / T pin voltage CPOR pin voltage CWDT pin voltage Absolute Maximum Rating VSS − 0.3 to VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VSS + 7.0 VSS − 0.3 to VDD + 0.3 ≤ VSS + 7.0 VSS − 0.3 to VSS + 7.0 −40 to +105 −40 to +150 VDD VWDI VWEN Vw / T ___ _______ ________  Thermal Resistance Value Table 13 Item Symbol Condition Min. Typ. Max. Unit Board A − 160 − °C/W Board B − 133 − °C/W Board C − − − °C/W Board D − − − °C/W Board E − − − °C/W Board A − 181 − °C/W Board B − − °C/W Board C − 135 40 − °C/W Board D − 42 − °C/W Board E Test environment: compliance with JEDEC STANDARD JESD51-2A − 32 − °C/W TMSOP-8 Junction-to-ambient thermal resistance*1 θJA HSNT-8(2030) *1. Remark Refer to " Power Dissipation" and "Test Board" for details.  Recommended Operation Conditions Table 14 Item Symbol Condition Min. Typ. Max. Unit Voltage detection circuit 0.9 − 6.0 V Watchdog timer circuit 2.5 − 6.0 V VDD pin voltage VDD Set detection voltage External pull-up resistor _______ for RST pin External pull-up resistor ________ for WDO pin Adjustment capacitance for reset time-out period Adjustment capacitance for watchdog time-out period −VDET(S) 0.1 V step 2.0 − 5.0 V RextR S-1411 Series G / H / I / J / K / L type 10 100 − kΩ RextW S-1410/1411 Series G / H / I / J / K / L type 10 100 − kΩ CPOR − 0.1 2.2 1000 nF CWDT − 0.1 0.47 1000 nF 13 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Electrical Characteristics 1. S-1410 Series Table 15 (1 / 2) (WEN pin logic active "H" product, VDD = 5.0 V, Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection voltage*1 −VDET − −VDET(S) × 0.985 −VDET(S) −VDET(S) × 1.015 V 1 Hysteresis width VHYS − −VDET × 0.03 −VDET × 0.05 −VDET × 0.07 V 1 Current consumption during watchdog timer operation Current consumption during watchdog timer stop ISS1 VWEN = VDD − 3.8 7.8 μA 2 ISS2 VWEN = 0 V − 2.7 5.7 μA 2 VDD − 1.0 − − V 5 − − 0.4 V 6 2.0 5.88 12.5 MΩ − VDD = 1.5 V 0.6 1.1 − mA 7 VDD = 1.8 V 1.1 1.6 − mA 7 VDD = 2.5 V 2.1 2.6 − mA 7 VDD = 3.0 V 2.8 3.3 − mA 7 − − 0.096 μA 8 Watchdog output voltage "H" VWOH Only A / B / C / D / E / F type Watchdog output voltage "L" VWOL External pull-up resistor of 100 kΩ is connected for G / H / I / J / K / L type Watchdog output pull-up resistance Only A / B / C / D / E / F type Watchdog output current Watchdog output leakage current RWUP IWOUT IWLEAK VDS = 0.4 V VDS = 6.0 V, VDD = 6.0 V Input pin voltage 1 "H" VSH1 WEN pin 0.7 × VDD − − V 9 Input pin voltage 1 "L" VSL1 − − 0.3 × VDD V 9 Input pin voltage 2 "H" VSH2 WEN pin ___ W / T pin 0.7 × VDD − − V 9 Input pin voltage 2 "L" VSL2 W / T pin − − 0.3 × VDD V 9 Input pin voltage 3 "H" VSH3 WDI pin 0.7 × VDD − − V 9 Input pin voltage 3 "L" VSL3 WDI pin − − 0.3 × VDD V 9 14 ___ 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series Table 15 (2 / 2) (WEN pin logic active "H" product, VDD = 5.0 V, Ta = +25°C unless otherwise specified) Item Input pin current 1 "H" Symbol ISH1 Input pin current 1 "L" ISL1 Input pin current 2 "H" ISH2 Input pin current 2 "L" ISL2 Input pin current 3 "H" ISH3 Input pin current 3 "L" ISL3 Condition A/B/C /G/H/I WEN pin, type VDD = 6.0 V, D/E/F Input pin voltage = 6.0 V /J/K/L type WEN pin, VDD = 6.0 V, Input pin voltage = 0 V ___ W / T pin, VDD = 6.0 V, Input pin voltage = 6.0 V ___ W / T pin, VDD = 6.0 V, Input pin voltage = 0 V WDI pin, VDD = 6.0 V, Input pin voltage = 6.0 V WDI pin, VDD = 6.0 V, Input pin voltage = 0 V Min. Typ. Max. Unit Test Circuit − 0.3 1.0 μA 9 −0.1 − 0.1 μA 9 −0.1 − 0.1 μA 9 − 0.3 1.0 μA 9 −0.1 − 0.1 μA 9 − 0.3 1.0 μA 9 −0.1 − 0.1 μA 9 Input pulse width "H"*2 thigh1 Timing Diagram 1 1.5 − − μs 10 Input pulse width "L"*2 tlow1 Timing Diagram 1 1.5 − − μs 10 Reset time-out period tRST CPOR = 2200 pF, Timing Diagram 2, 5 8.7 14.5 20 ms 3 Watchdog time-out period tWDU CWDT = 470 pF, Timing Diagram 4, 5 15 24.6 34 ms 3 Watchdog double pulse detection time tWDL 461 769 1077 μs 4 Watchdog output delay time tWOUT − 25 40 μs 3 − 25 40 μs 3 1.0 − − μs 3 Reset output delay time tROUT CWDT = 470 pF, Timing Diagram 7-1 to 7-4 Timing Diagram 2, 3-2, 7-1 to 7-3 Timing Diagram 2, 7-1 to 7-3 Input setup time tiset Timing Diagram 4 *1. *2. −VDET: Actual detection voltage, −VDET(S): Set detection voltage Inputs to the WEN pin and the WDI pin should be greater than or equal to the min. value specified in " Electrical Characteristics". 15 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 2. S-1411 Series Table 16 (1 / 2) (WEN pin logic active "H" product, VDD = 5.0 V, Ta = +25°C unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Detection voltage*1 −VDET − −VDET(S) × 0.985 −VDET(S) −VDET(S) × 1.015 V 11 Hysteresis width VHYS − −VDET × 0.03 −VDET × 0.05 −VDET × 0.07 V 11 Current consumption during watchdog timer operation Current consumption during watchdog timer stop Reset output voltage "H" ISS1 VWEN = VDD − 3.8 7.8 μA 12 ISS2 VWEN = 0 V − 2.7 5.7 μA 12 VDD − 1.0 − − V 15 − − 0.4 V 16 2.0 5.88 12.5 MΩ − VDD = 1.5 V 0.6 1.1 − mA 17 VDD = 1.8 V 1.1 1.6 − mA 17 VDD = 2.5 V 2.1 2.6 − mA 17 VDD = 3.0 V 2.8 3.3 − mA 17 − − 0.096 μA 18 VDD − 1.0 − − V 19 − − 0.4 V 20 2.0 5.88 12.5 MΩ − VDD = 1.5 V 0.6 1.1 − mA 21 VDD = 1.8 V 1.1 1.6 − mA 21 VDD = 2.5 V 2.1 2.6 − mA 21 VDD = 3.0 V 2.8 3.3 − mA 21 − − 0.096 μA 22 VROH Only A / B / C / D / E / F type Reset output voltage "L" VROL External pull-up resistor of 100 kΩ is connected for G / H / I / J / K / L type Reset output pull-up resistance RRUP Only A / B / C / D / E / F type Reset output current IROUT VDS = 0.4 V Reset output leakage current IRLEAK VDS = 6.0 V, VDD = 6.0 V Watchdog output voltage "H" VWOH Only A / B / C / D / E / F type Watchdog output voltage "L" VWOL External pull-up resistor of 100 kΩ is connected for G / H / I / J / K / L type Watchdog output pull-up resistance RWUP Only A / B / C / D / E / F type Watchdog output current IWOUT VDS = 0.4 V Watchdog output leakage current IWLEAK VDS = 6.0 V, VDD = 6.0 V Input pin voltage 1 "H" VSH1 WEN pin 0.7 × VDD − − V 23 Input pin voltage 1 "L" VSL1 − − 0.3 × VDD V 23 Input pin voltage 3 "H" VSH3 WEN pin WDI pin 0.7 × VDD − − V 23 Input pin voltage 3 "L" VSL3 WDI pin − − 0.3 × VDD V 23 16 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series Table 16 (2 / 2) (WEN pin logic active "H" product, VDD = 5.0 V, Ta = +25°C unless otherwise specified) Item Input pin current 1 "H" Symbol ISH1 Condition A/B/C /G/H/I WEN pin, type VDD = 6.0 V, D/E/F Input pin voltage = 6.0 V /J/K/L type WEN pin, VDD = 6.0 V, Input pin voltage = 0 V WDI pin, VDD = 6.0 V, Input pin voltage = 6.0 V WDI pin, VDD = 6.0 V, Input pin voltage = 0 V Min. Typ. Max. Unit Test Circuit − 0.3 1.0 μA 23 −0.1 − 0.1 μA 23 −0.1 − 0.1 μA 23 − 0.3 1.0 μA 23 −0.1 − 0.1 μA 23 Input pin current 1 "L" ISL1 Input pin current 3 "H" ISH3 Input pin current 3 "L" ISL3 Input pulse width "H"*2 thigh1 Timing Diagram 1 1.5 − − μs 24 Input pulse width "L"*2 tlow1 Timing Diagram 1 1.5 − − μs 24 Reset time-out period tRST CPOR = 2200 pF, Timing Diagram 2, 5 8.7 14.5 20 ms 13 Watchdog time-out period tWDU CWDT = 470 pF, Timing Diagram 4, 5 15 24.6 34 ms 13 Watchdog double pulse detection time tWDL CWDT = 470 pF, Timing Diagram 7-1 to 7-4 461 769 1077 μs 14 Watchdog output delay time tWOUT Timing Diagram 2, 3-2, 7-1 to 7-3 − 25 40 μs 13 Timing Diagram 2, 3-1, 7-1 to 7-3 − μs 25 40 13 Timing Diagram 4 − − μs Input setup time tiset 1.0 13 *1. −VDET: Actual detection voltage, −VDET(S): Set detection voltage *2. Inputs to the WEN pin and the WDI pin should be greater than or equal to the min. value specified in " Electrical Characteristics". Reset output delay time tROUT  Timing Diagrams on Electrical Characteristics (1) Timing Diagram 1 thigh1 WEN VSH1 VSH1 VSL1 VSL1 tlow1 thigh1 WDI VSH3 VSH3 VSL3 VSL3 tlow1 Figure 11 Input Pulse Width 17 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 (2) Timing Diagram 2 VDD +V DET 0V 1 2 3 4 V CPU CPOR V CPL 0V Δt RST*2 t INIT Δt*1 tRST WDO, RST*4 V WOH ,VROH t WOUT, t ROUT*4 Figure 12 (3) Timing Diagram 3-1 VDD Rising (4) Timing Diagram 3-2 VDD VDD -VDET -VDET VCPU CPOR VCWU CWDT VCWL VCPL Δt2*3 Δt 1*3 WDO, RST*4 RST*4 VWOL,VROL VROL t ROUT*4 Figure 13 VDD Falling during CPOR Pin Charge Operation tWOUT, t ROUT*4 Figure 14 VDD Falling during CWDT Pin Charge Operation *1. The CPOR pin voltage fall delay time (Δt) is sufficiently small compared to the reset time-out period (tRST). *2. The time (ΔtRST) the CPOR pin voltage (VCPOR) reaches the CPOR charge lower limit threshold (VCPL) from 0 V is proportional to the adjustment capacitance for reset time-out period (CPOR). Thus, large CPOR results in large ΔtRST. Refer to "12. Initialization time (tINIT) vs. Power supply voltage rise time (tr)" in " Characteristics (Typical Data)". *3. CPOR pin voltage forced fall delay time (Δt1) and the CWDT pin voltage forced fall delay time (Δt2) is sufficiently small compared to tRST in Timing Diagram 2. *4. Only the S-1411 Series Remark VCPU: CPOR charge upper limit threshold (1.25 V typ.), VCPL: CPOR charge lower limit threshold (0.20 V typ.) VCWU: CWDT charge upper limit threshold (1.25 V typ.), VCWL: CWDT charge lower limit threshold (0.20 V typ.) 18 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series (5) Timing Diagram 4 WEN VSH1 tSH1 VSL1 1 31 2 32 CWDT VCWU ･･･ tacp VCWL tiset tWDU ΔtWDL*2 Δt*1 Figure 15 Counter Reset due to VWEN (6) Timing Diagram 5 1 2 3 CPOR 4 V CPU V CPL 1 31 2 32 CWDT V CWU ･･･ V CWL Δt *3 Δt WDL (Δt + Δt WDL)*3 Δt*4 ΔtRST t WDU Figure 16 (Δt + ΔtRST)*4 t RST Watchdog Time-out Detection *1. CWDT pin voltage forced fall delay time (Δt) is sufficiently small compared to the watchdog time-out period (tWDU). *2. The CWDT pin voltage rise delay time (tiset + ΔtWDL) is sufficiently small (less than 1%) compared to tWDU. *3. The delay time (Δt + ΔtWDL) from when the CPOR pin voltage (VCPOR) falls to the CPOR charge lower limit threshold (VCPL) to when the CWDT pin voltage (VCWDT) reaches the CWDT charge lower limit threshold (VCWL) is sufficiently small (less than 1%) compared to tWDU. *4. The delay time (Δt + ΔtRST) from when VCWDT falls to VCWL to when VCPOR reaches VCPL is sufficiently small (less than 5%) compared to reset time-out period (tRST). Remark tiset: Input setup time (less than 1 μs) The time from when VWEN exceeds VSH1 (tSH1) to when the WDI pin is able to receive input signals (tacp). 19 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 (7) Timing Diagram 6-1 (8) Timing Diagram 6-2 WDI WDI 1 1 2 CWDT VCWU 2 CWDT VCWU VCWL VCWL 0V 0V Δt*2 Δt*1 ΔtWDL Figure 17 ΔtWDL*3 *3 VWDI Rising Edge Figure 18 (9) Timing Diagram 6-3 VWDI Falling Edge (10) Timing Diagram 6-4 WDI WDI 1 1 CWDT 1 VCWU 1 CWDT VCWU VCWL VCWL 0V 0V Δt *1 ΔtWDL*3 Figure 19 Δt *2 Δt *2 Δt WDL*3 VWDI Both Rising and Falling Edges 1 ΔtWDL Figure 20 *3 Δt*1 ΔtWDL*3 VWDI Both Rising and Falling Edges 2 *1. The delay time (Δt) from the WDI pin voltage (VWDI) rising edge to the CWDT pin voltage (VCWDT) rising start is sufficiently small (less than 1%) compared to tWDU in Timing Diagram 4 and 5. *2. The delay time (Δt) from the VWDI falling edge to the VCWDT rising start is sufficiently small (less than 1%) compared to tWDU in Timing Diagram 4 and 5. *3. The time (ΔtWDL) VCWDT reaches VCWL from 0 V is proportional to the adjustment capacitance for watchdog time-out period (CWDT). Thus, large CWDT results in large ΔtWDL. 20 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series (11) Timing Diagram 7-1 (12) Timing Diagram 7-2 WDI WDI CWDT VCWU CWDT VCWU VCWL VCWL 0V Δt*6 Δt*1 tWDL t WDL tWDL ΔtWDL*2 tWDL CPOR VCPU Δt WDL*2 CPOR VCPU VCPL 0V VCPL 0V Δt*3 Δt *7 ΔtRST*4 WDO, RST*5 ΔtRST*4 WDO, RST*5 VWOL,VROL tWOUT, t ROUT*5 Figure 21 Double Pulse Detection due to VWDI Rising Edge VWOL,VROL tWOUT, t ROUT*5 Figure 22 Double Pulse Detection due to VWDI Falling Edge *1. The delay time (Δt) from the VWDI rising edge to the VCWDT rising start is sufficiently small (less than 1%) compared the watchdog double pulse detection time (tWDL). *2. The time (ΔtWDL) VCWDT reaches VCWL from 0 V is proportional to CWDT. Thus, large CWDT results in large ΔtWDL. In window mode, a double pulse is detected during both periods of ΔtWDL and tWDL. *3. The delay time (Δt) from the VWDI rising edge to the VCPOR rising start is sufficiently small (less than 1%) compared tRST in Timing Diagram 2 and 5. *4. The time (ΔtRST) VCPOR reaches VCPL from 0 V is proportional to CPOR. Thus, large CPOR results in large ΔtRST. Refer "12. Initialization time (tINIT) vs. Power supply voltage rise time (tr)" in " Characteristics (Typical Data)". *5. Only the S-1411 Series *6. The delay time (Δt) from the VWDI falling edge to the VCWDT rising start is sufficiently small (less than 1%) compared tWDL. *7. The delay time (Δt) from the VWDI falling edge to the VCPOR rising start is sufficiently small (less than 1%) compared tRST in Timing Diagram 2 and 5. to to to to to 21 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 (13) Timing Diagram 7-3 (14) Timing Diagram 7-4 WDI WDI CWDT CWDT VCWU VCWU VCWL VCWL 0V 0V Δt *6 Δt *7 Δt*1 tWDL ΔtWDL*2 t WDL ΔtWDL*2 ΔtWDL*2 CPOR VCPU WDI *8 VCPL 0V Δt *3 ΔtRST*4 CWDT V CWU WDO, RST*5 V CWL V WOL,VROL 0V tWDL ΔtWDL*2 t WOUT, t ROUT*5 Figure 23 Double Pulse Detection due to VWDI Both Rising and Falling Edges tWDL2 Figure 24 Double Pulse Non-detection due to VWDI Both Rising and Falling Edges *1. The delay time (Δt) from the VWDI rising edge to the VCWDT rising start is sufficiently small (less than 1%) compared to tWDL. *2. The time (ΔtWDL) VCWDT reaches VCWL from 0 V is proportional to CWDT. Thus, large CWDT results in large ΔtWDL. In window mode, a double pulse is detected during both periods of ΔtWDL and tWDL. *3. The delay time (Δt) from the VWDI falling edge to the VCPOR rising start is sufficiently small (less than 1%) compared to tRST in Timing Diagram 2 and 5. *4. The time (ΔtRST) VCPOR reaches VCPL from 0 V is proportional to CPOR. Thus, large CPOR results in large ΔtRST. Refer to "12. Initialization time (tINIT) vs. Power supply voltage rise time (tr)" in " Characteristics (Typical Data)". *5. Only the S-1411 Series *6. The delay time (Δt) from the VWDI falling edge to the VCWDT rising start is sufficiently small (less than 1%) compared to tWDU in Timing Diagram 4 and 5. *7. The delay time (Δt) from the VWDI rising edge to the VCWDT rising start is sufficiently small (less than 1%) compared to tWDU in Timing Diagram 4 and 5. *8. As indicated by the waveform illustrated with dashed lines, if VCWDT does not fall to 0 V when the VWDI rising or falling edge is input, ΔtWDL may approach 0. Similar phenomena may occur in Timing Diagrams 6-1 to 6-4 and Timing Diagram 7-1 to 7-3 as well. 22 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Test Circuits Refer to " Recommended Operation Conditions" when setting constants of external pull-up resistors (RextR, RextW) and external capacitors (CPOR, CWDT). 1. S-1410 Series (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD CPOR VDD CPOR WDO CWDT CWDT WDI WEN V + V + WEN W/T V VSS Figure 25 + WDO WDI + V + W/T VSS Test Circuit 1 A VDD CPOR WDO CWDT WDI WEN W/T VSS Figure 26 Test Circuit 2 (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD VDD CPOR CPOR CWDT WDO CWDT WDI WEN V WDO WDI + WEN V + W/T W/T VSS VSS Figure 27 (1) A / B / C / D / E / F type Test Circuit 3 (2) G / H / I / J / K / L type VDD CPOR CWDT VDD CPOR WDO CWDT WDI WEN V WDO WDI + WEN W/T V + W/T VSS VSS Figure 28 Test Circuit 4 23 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 VDD CPOR CWDT WDO WDI WEN V W/T + VSS Figure 29 Test Circuit 5 (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD CPOR CWDT VDD CPOR WDO CWDT WDI WEN V WDI + WEN W/T V VSS Figure 30 VDD CPOR CWDT WDO A Test Circuit 6 VDD CPOR + CWDT WDI WDI WEN WEN W/T W/T VSS Test Circuit 7 Figure 32 + Test Circuit 8 VDD VDD CPOR CWDT WDO WEN, WDI, W / T CWDT V + + A Figure 33 Test Circuit 9 WDO WEN, WDI, W / T VSS VSS 24 A (2) G / H / I / J / K / L type CPOR A WDO VSS (1) A / B / C / D / E / F type + + W/T VSS Figure 31 WDO V + 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD VDD CPOR CPOR CWDT WDO WEN, WDI, W / T CWDT V + WDO WEN, WDI, W / T VSS V + VSS Figure 34 Test Circuit 10 25 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 2. S-1411 Series (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD CPOR VDD CPOR WDO CWDT CWDT WDI RST WEN V V Figure 35 RST WEN V VSS + WDI + + WDO V + + VSS Test Circuit 11 A VDD CPOR WDO CWDT WDI RST WEN VSS Figure 36 Test Circuit 12 (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD VDD CPOR CWDT CPOR WDO CWDT WDI WEN RST V WDI + WEN VSS RST V + VSS Figure 37 (1) A / B / C / D / E / F type Test Circuit 13 (2) G / H / I / J / K / L type VDD CPOR CWDT VDD CPOR WDO CWDT WDI WEN RST V WEN RST VSS Figure 38 WDO WDI + VSS 26 WDO Test Circuit 14 V + 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series VDD CPOR WDO CWDT WDI WEN RST V VSS Figure 39 + Test Circuit 15 (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD CPOR VDD CPOR WDO CWDT WDI WDI WEN WEN RST V VSS + Figure 40 VDD CPOR RST V VSS + Test Circuit 16 VDD CPOR WDO CWDT CWDT WDI RST WEN A WDO WDI + RST WEN VSS Figure 41 WDO CWDT A + VSS Test Circuit 17 Figure 42 Test Circuit 18 VDD CPOR CWDT WDO WDI RST WEN V + VSS Figure 43 Test Circuit 19 27 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 (1) A / B / C / D / E / F type (2) G / H / I / J / K / L type VDD CPOR CWDT VDD CPOR WDO CWDT WDI WEN RST V WDI + RST WEN VSS VDD CPOR WDO A VDD CPOR + CWDT RST + VSS Test Circuit 21 Figure 46 (1) A / B / C / D / E / F type Test Circuit 22 (2) G / H / I / J / K / L type VDD VDD CPOR CPOR CWDT WDO WEN, WDI RST CWDT V + + A WDO WEN, WDI RST VSS V + VSS Figure 47 (1) A / B / C / D / E / F type Test Circuit 23 (2) G / H / I / J / K / L type VDD VDD CPOR CPOR CWDT WDO WEN, WDI RST CWDT V + VSS Figure 48 WDO WEN, WDI RST VSS 28 A RST WEN VSS A WDO WDI WEN + + Test Circuit 20 WDI Figure 45 V VSS Figure 44 CWDT WDO Test Circuit 24 V + 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Standard Circuits 1. S-1410 Series A / B / C / D / E / F type VDD VDD WEN WDI WDO W/T VSS CPOR CWDT CWDT*2, *3 CPOR*1, *3 *1. Connect the adjustment capacitor for reset time-out period (CPOR) directly between the CPOR pin and the VSS pin. *2. Connect the adjustment capacitor for watchdog time-out period (CWDT) directly between the CWDT pin and the VSS pin. *3. A capacitor of 100 pF to 1 μF can be used for CPOR and CWDT. Even if the capacitance is within this range, cautions are still needed when the value is extremely large. Refer to "1. Low voltage operation when CPOR is extremely large" and "2. Relation between CPOR and CWDT" in " Precautions for Use". Figure 49 2. S-1410 Series G / H / I / J / K / L type VDD VDD RextW*1 WEN WDI WDO W/T VSS CPOR CPOR*2, *4 CWDT CWDT*3, *4 ________ *1. RextW is an external pull-up resistor for the WDO pin. *2. Connect the adjustment capacitor for reset time-out period (CPOR) directly between the CPOR pin and the VSS pin. *3. Connect the adjustment capacitor for watchdog time-out period (CWDT) directly between the CWDT pin and the VSS pin. *4. A capacitor of 100 pF to 1 μF can be used for CPOR and CWDT. Even if the capacitance is within this range, cautions are still needed when the value is extremely large. Refer to "1. Low voltage operation when CPOR is extremely large" and "2. Relation between CPOR and CWDT" in " Precautions for Use". Figure 50 Caution The above connection diagrams and constants will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constants. 29 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 3. S-1411 Series A / B / C / D / E / F type VDD VDD WDO WEN WDI RST VSS CPOR CWDT CWDT*2, *3 CPOR*1, *3 *1. *2. *3. Connect the adjustment capacitor for reset time-out period (CPOR) directly between the CPOR pin and the VSS pin. Connect the adjustment capacitor for watchdog time-out period (CWDT) directly between the CWDT pin and the VSS pin. A capacitor of 100 pF to 1 μF can be used for CPOR and CWDT. Even if the capacitance is within this range, cautions are still needed when the value is extremely large. Refer to "1. Low voltage operation when CPOR is extremely large" and "2. Relation between CPOR and CWDT" in " Precautions for Use". Figure 51 4. S-1411 Series G / H / I / J / K / L type RextW*1 VDD VDD WDO WEN RextR*2 WDI RST VSS CPOR*3, *5 CPOR CWDT CWDT*4, *5 ________ *1. RextW is an external pull-up resistor for the _______ WDO pin. *2. RextR is an external pull-up resistor for the RST pin. *3. Connect the adjustment capacitor for reset time-out period (CPOR) directly between the CPOR pin and the VSS pin. *4. Connect the adjustment capacitor for watchdog time-out period (CWDT) directly between the CWDT pin and the VSS pin. *5. A capacitor of 100 pF to 1 μF can be used for CPOR and CWDT. Even if the capacitance is within this range, cautions are still needed when the value is extremely large. Refer to "1. Low voltage operation when CPOR is extremely large" and "2. Relation between CPOR and CWDT" in " Precautions for Use". Figure 52 Caution The above connection diagrams and constants will not guarantee successful operation. Perform thorough evaluation using the actual application to set the constants. 30 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Operations 1. Voltage detector circuit 1. 1 Basic operation (1) When the power supply voltage (VDD) is release voltage (+VDET) of the detector or higher, the Nch transistor _______ (N2) is turned off and "H" is output to the RST pin. Since the Pch transistor (P1) is turned on, RB • VDD . the input voltage to the comparator (C1) is RA + RB _______ (2) Even if VDD decreases to +VDET or lower, "H" is output to the RST pin when VDD is the detection voltage (−VDET) or higher. When VDD decreases to −V DET (point A in Figure 54) or lower, N2 which is controlled by C1 is turned _______ on, and then "L" is output to the RST pin. At this time, P1 is turned off, and the input voltage to C1 is RB • VDD . RA + RB + RC _______ is "H". (3) If VDD further decreases to the IC's minimum operation voltage or lower, the RST pin output _______ (4) When VDD increases to the IC's minimum operation voltage or higher, "L" is output to the RST pin. In addition, even if VDD exceeds −VDET, the output is "L" when VDD is lower than +VDET. _______ (5) When VDD increases to +VDET (point B in Figure 54) or higher, N2 is turned off, and "H" is output to the RST pin after elapse of tINIT + tRST. VDD P1 RC _______ RA Reference voltage circuit + − C1 RST Delay circuit N2 RB VSS Figure 53 Operation of Voltage Detector Circuit (1) (2) (3) (4) B Hysteresis width (VHYS) A (5) Release voltage (+VDET) Detection voltage (−VDET) VDD Minimum operation voltage VSS _______ RST pin output*1, WDO pin output ________ VSS tINIT + tRST *1. Only the S-1411 Series Figure 54 Timing Chart of Voltage Detector Circuit 31 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 From power-on to reset release 1. 2 The S-1410/1411 Series initiates the initialization if the VDD pin voltage exceeds the release voltage (+VDET). The ________ charge-discharge operation_______ to the CPOR pin is initiated after the passage of the initialization time (tINIT), and the WDO pin output and the RST pin output change from "L" to "H" after the operation is performed 4 times. Refer to Figure 55. tINIT changes according to the power supply voltage rise time (tr). Refer to "12. Initialization time (tINIT) vs. Power supply voltage rise time (tr)" in " Characteristics (Typical Data)" for the relation between tINIT and tr. Power-on End of initialization Reset release VDD 0V 1 2 3 4 CPOR RST *1 WDO *1. Only the S-1411 Series Figure 55 1. 3 Operation of low voltage detection The voltage detection circuit________ detects a low voltage if the power supply voltage falls below the detection voltage, and _______ then "L" is output from the WDO pin and the RST pin (only the S-1411 Series). The output is maintained until the charge-discharge operation of the CPOR pin is performed 4 times. The S-1410/1411 Series can detect a low voltage even if either the CPOR pin or the CWDT pin performs the ___ charge-discharge operation. In this case, no influence is exerted on the status of the WEN pin or the W / T pin. End of initialization End of initialization Low voltage Low voltage Low voltage Power-on Reset release detection release detection VDD 0V 1 2 3 4 CPOR CWDT RST *1 WDO *1. Only the S-1411 Series Figure 56 32 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 2. Watchdog timer 2. 1 Watchdog mode (only S-1410 Series) ___ 2. 1. 1 Time-out mode (W / T pin = "H") The S-1410 Series detects an abnormality when not inputting an edge to the WDI pin during the watchdog time-out ________ period (tWDU). And then "L" is output from the WDO pin. Power-on End of initialization Reset release Double pulse Watchdog time-out VDD 0V W/T *1 WDI CPOR 1 1 2 3 4 CWDT 29 30 31 32 WDO *1. Only the S-1410 Series Figure 57 Abnormality Detection during Time-out Mode ___ 2. 1. 2 Window mode (W / T pin = "L") When not inputting an edge to the WDI pin during tWDU, or when an edge is input to the WDI pin again within a specific period of time (the discharge________ time due to an edge detection + 1 charge-discharge time (tWDL)) after inputting an edge to the WDI pin, the WDO pin output changes from "H" to "L". Power-on End of initialization Reset release Double pulse Reset time-out Watchdog time-out VDD 0V W/T *1 WDI 1 2 3 4 CPOR CWDT 1 1 2 3 30 31 32 WDO *1. Only the S-1410 Series Figure 58 Abnormality Detection during Window Mode 33 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 2. 2 From reset release to initiation of charge-discharge operation to CWDT pin The charge-discharge operation to the CWDT pin differs depending on the status of the WEN pin at the reset release. 2. 2. 1 When WEN pin is in Enable at reset release Since the watchdog timer is in Enable, the S-1410/1411 Series initiates the charge-discharge operation to the CWDT pin. Power-on End of initialization Reset release VDD 0V WEN CPOR CWDT RST *1 WDO *1. Only the S-1411 Series Figure 59 2. 2. 2 WEN Pin = "H" When WEN pin is in Disable at reset release Since the watchdog timer is in Disable after the CPOR pin performs the charge-discharge operation 4 times, the S-1410/1411 Series does not initiate the charge-discharge operation to the CWDT pin. If the input to the WEN pin changes to "H" in this status, the S-1410/1411 Series initiates the charge-discharge operation to the CWDT pin. End of Power-on initialization Reset release VDD 0V WEN (WDT (WDT ) CPOR CWDT RST *1 WDO *1. Only the S-1411 Series Figure 60 34 WEN Pin = "L" → "H" ) 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 2. 3 Watchdog time-out detection The watchdog timer detects a time-out after the charge-discharge operation to the CWDT pin is performed 32 times, ________ then the WDO pin output changes from "H" to "L". Power-on End of initialization Watchdog time-out Reset release Reset time-out VDD 0V WDI 1 2 3 4 CPOR 1 2 3 4 5 CWDT RST 29 30 31 32 *1 WDO *1. Only the S-1411 Series Figure 61 2. 4 Internal counter reset due to edge When the WDI pin detects an edge during the charge-discharge operation to the CWDT pin, the internal counter which counts the number of times of the charge-discharge operation is reset. The CWDT pin initiates the discharge operation when an edge is detected and initiates the charge-discharge operation again after the discharge operation is completed. 2. 4. 1 Counter reset due to rising edge (S-141xAxx, S-141xDxx, S-141xGxx, S-141xJxx) End of Power-on initialization Reset release Rising edge Watchdog time-out VDD 0V WDI CPOR 1 2 3 4 5 CWDT RST 29 30 31 32 *1 WDO *1. Only the S-1411 Series Figure 62 35 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 2. 4. 2 Counter reset due to falling edge (S-141xBxx, S-141xExx, S-141xHxx, S-141xKxx) Power-on End of initialization Reset release Falling edge Watchdog time-out VDD 0V WDI CPOR 1 2 3 4 5 CWDT RST 29 30 31 32 *1 WDO *1. Only the S-1411 Series Figure 63 2. 4. 3 Counter reset due to both rising and falling edges 1 (S-141xCxx, S-141xFxx, S-141xIxx, S-141xLxx) End of Power-on initialization Reset release Rising Falling Watchdog time-out VDD 0V WDI CPOR 1 2 1 2 3 CWDT RST *1 WDO *1. Only the S-1411 Series Figure 64 36 29 30 31 32 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 2. 4. 4 Counter reset due to both rising and falling edges 2 (S-141xCxx, S-141xFxx, S-141xIxx, S-141xLxx) End of Power-on initialization Reset release Falling Rising Watchdog time-out VDD 0V WDI CPOR 1 2 1 2 3 CWDT RST 29 30 31 32 *1 WDO *1. Only the S-1411 Series Figure 65 2. 5 Watchdog double pulse detection (only during window mode) If an edge is input to the WDI pin again within a specific period of time (the discharge time due to an edge detection + 1 charge-discharge time (tWDL)) after inputting an edge to the WDI pin when the S-1410/1411 Series is in the window ________ mode, the WDO pin output changes from "H" to "L". When the watchdog timer________ goes to Disable due to a change of the WEN pin ("H" → "L" → "H") after inputting an edge to the WDI pin, the WDO pin continues outputting "H" even if an edge is input to the WDI pin within the specific period of time mentioned above. 2. 5. 1 Double pulse detection due to rising edge (S-141xAxx, S-141xDxx, S-141xGxx, S-141xJxx) End of Power-on initialization Reset release Double pulse Reset time-out Rising Rising VDD 0V WDI 1 2 3 4 CPOR 1 CWDT RST 1 2 1 2 3 4 *1 WDO *1. Only the S-1411 Series Figure 66 37 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 2. 5. 2 Double pulse detection due to falling edge (S-141xBxx, S-141xExx, S-141xHxx, S-141xKxx) End of Power-on initialization Reset release Double pulse Reset time-out Falling Falling VDD 0V WDI 1 2 3 4 CPOR 1 CWDT RST 1 2 1 2 3 4 *1 WDO *1. Only the S-1411 Series Figure 67 2. 5. 3 Double pulse detection due to both rising and falling edges (S-141xCxx, S-141xFxx, S-141xIxx, S-141xLxx) The double pulse is detected only when edges are input in order of rising and falling. (1) When edges are input to WDI pin in order of rising and falling End of Power-on initialization Reset release Both edges Reset time-out Rising Falling VDD 0V WDI 1 2 3 4 CPOR 1 CWDT RST *1 WDO *1. Only the S-1411 Series Figure 68 38 Double Pulse Detection 1 2 1 2 3 4 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series (2) When edges are input to WDI pin in order of falling and rising In this case, no double pulse is detected, but the counter is reset. End of Power-on initialization Reset release Both edges Falling Rising VDD 0V WDI CPOR 1 1 2 CWDT RST 1 2 1 2 3 4 *1 WDO *1. Only the S-1411 Series Figure 69 2. 6 Double Pulse Non-detection Counter reset due to WEN pin during charge-discharge operation to CWDT pin When the WEN pin changes from "H" to "L" during the charge-discharge operation to the CWDT pin, the CWDT pin performs the discharge operation. In addition, the internal counter which counts the number of times of the charge-discharge operation for the CWDT pin is also reset. If the WEN pin changes to "H" again in this status, the CWDT pin initiates the charge-discharge operation. End of Power-on initialization Watchdog time-out Reset release VDD 0V Enable Enable Enable WEN Disable 1 2 3 4 Disable CPOR 1 2 3 CWDT RST 29 30 31 32 *1 WDO *1. Only the S-1411 Series Figure 70 39 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00  Precautions for Use A capacitor of 100 pF to 1 μF can be used for the adjustment capacitor for reset time-out period (CPOR) and the adjustment capacitor for watchdog time-out period (CWDT). Even if the capacitance is within this range, cautions are still needed when the value is extremely large. 1. Low voltage operation when CPOR is extremely large When the S-1410/1411 Series detects a low voltage during the CPOR charge-discharge operation, it will take time for the CPOR discharge operation to be performed if CPOR is extremely large. Therefore, the discharge operation may not be completed by the time the power supply voltage (VDD) exceeds the release voltage (+VDET). In this case, since the charge-discharge operation is performed after the discharge operation is completed, a delay time of the same length as the CPOR discharge operation time occurs by the time the reset time-out period (tRST) count starts. Low voltage detection VDD +VDET CPOR *1 VCPL tRST CPOR *2 VCPL tRST *3 *1. When the capacitance is sufficiently small. *2. When the capacitance is extremely large. *3. Delay time of the same length as the CPOR discharge operation time Figure 71 2. Relation between CPOR and CWDT Select a capacitor which satisfies the following expression for CPOR and CWDT. When this condition is not satisfied, the S-1410/1411 Series may not complete the CWDT discharge operation after a double pulse detection. Unless the CWDT discharge operation has been completed, the S-1410/1411 Series will not be able to initiate the next charge-discharge operation even if tRST has elapsed. For this reason, a delay time of the same length as the CWDT discharge operation time occurs by the time the watchdog time-out period (tWDU) count starts. CWDT / CPOR ≤ 600 Double pulse detection CPOR VCPL CWDT*1 VCWL tWDU CWDT*2 VCWL *3 *1. When CWDT / CPOR ≤ 600. *2. When CWDT / CPOR > 600. *3. Delay time of the same length as the CWDT discharge operation time Figure 72 40 t WDU 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series 3. Re-applying power supply If the power supply voltage (VDD) falls to 0.9 V or lower, a standby status for 20 μs is required by the time low voltage detection is released in order for the discharge operation of internal circuit to be performed fully. If an appropriate amount of time is not secured for the standby status to be completed by the time the power supply is re-applied, the initialization start will be delayed. For this reason, a delay time of the same length as the time until the standby status has been completed occurs by the time the tRST count starts after the power supply rises. 3. 1 If the time from when VDD falls below 0.9 V to when it rises again is longer than 20 μs +VDET V DD 0.9 V 20 μs Nomal operation Nomal operation Standby CPOR VCPL t INIT t RST Figure 73 3. 2 If the time from when VDD falls below 0.9 V to when it rises again is shorter than 20 μs +VDET VDD 0.9 V 20 μs Nomal operation Nomal operation Standby CPOR VCPL *1 *1. tINIT t RST Delay time of the same length as the time until standby status at power-on has been completed Figure 74 41 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 4. Low voltage detection at instantaneous voltage drop ________ In the S-1410/1411 Series, when the period of 0.9 V ≤ VDD ≤ −VDET is shorter than 20 μs, the WDO pin and the _______ RST pin may not output a low voltage detection signal. Even in this case, the S-1410/1411 Series carries out the charge-discharge operation for CPOR in the same manner at power-on. For this reason, a delay time of the same length as the CPOR charge-discharge operation time occurs by the time the tWDU count starts after the power supply rises. VDD −VDET +VDET 0.9 V < 20 μs CPOR *1 CWDT VCWL tWDU WDO "H" Undetection RST *2 "H" Undetection *1. Delay time of the same length as the CPOR discharge operation time (tINIT + tRST) *2. Only the S-1411 Series Figure 75  Precautions ___ • Since input pins (the WEN pin, the WDI pin and the W / T pin) in the S-1410/1411 Series are CMOS configurations, make sure that an intermediate potential is not input when the S-1410/1411 Series operates. ________ _______ • Since the WDO pin and the RST pin are affected by external resistance and external capacitance, use the S-1410/1411 Series after performing thorough evaluation with the actual application. 42 • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Characteristics (Typical Data) 1. Current consumption during watchdog timer stop (ISS2) vs. 2. Current consumption during watchdog timer operation (ISS1) vs. Input voltage (VDD) Input voltage (VDD) 5.0 WDT = OFF, −VDET(S) = 4.0 V, Ta = +25°C 5.0 − 4.5 ISS1 [μA] ISS2 [μA] 4.0 WDT = ON, −VDET(S) = 4.0 V, WDI input 3.0 2.0 1.0 °C 4.0 3.5 + °C + °C 3.0 0.0 0 1 2 3 4 5 4.0 6 4.5 5.0 5.5 VDD [V] VDD [V] 6.0 6.5 3. Current consumption during watchdog timer operation (ISS1) vs. 4. Detection voltage (−VDET), Release voltage (+VDET) vs. Temperature (Ta) Temperature (Ta) WDT = ON, −VDET(S) = 4.0 V, VDD = 5.0 V, WDI input 5.0 −VDET, +VDET [V] ISS1 [μA] 4.0 3.0 2.0 1.0 0.0 −40 −25 0 25 50 Ta [°C] 75 20 10 −40 −25 0 25 50 Ta [°C] 75 3.5 10 0 25 50 Ta [°C] 75 105 105 20 10 −40 −25 0 25 50 Ta [°C] 75 105 8. Watchdog output delay time (tWOUT) vs. Temperature (Ta) VDD = 5.0 V, CWDT = 470 pF 40 30 20 10 0 −40 −25 75 30 0 tWOUT [μs] 20 25 50 Ta [°C] VDD = 5.0 V, CWDT = 470 pF 40 VDD = −VDET(S) + 1.0 V → −VDET(S) − 1.0 V, CPOR = 2200 pF 30 0 6. Watchdog time-out period (tWDU) vs. Temperature (Ta) 105 7. Reset output delay time (tROUT) vs. Temperature (Ta) tROUT [μs] −VDET −40 −25 tWDU [ms] tRST [ms] 30 0 +VDET 4.0 105 VDD = 5.0 V, CPOR = 2200 pF 40 40 −VDET(S) = 4.0 V 3.0 5. Reset time-out period (tRST) vs. Temperature (Ta) 0 4.5 −40 −25 0 25 50 Ta [°C] 75 105 43 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION S-1410/1411 Series Rev.2.5_00 9. Reset time-out period (tRST) vs. CPOR 10. VDD = 5.0 V, Ta = +25°C 10 VDD = 5.0 V, Ta = +25°C 10 tWDU [s] tRST [s] 1 0.1 0.01 0.001 0.001 0.01 CPOR [μF] 100 4.0 − °C 10 tINIT [ms] + °C 2.0 + 0 1 2 3 VDD [V] 4 0.001 0.01 CWDT [μF] 1 0.1 12. Initialization time (tINIT) vs. Power supply voltage rise time (tr) VDS = 0.4 V, −VDET(S) = 4.0 V 6.0 IWOUT [mA] 0.1 0.001 0.0001 1 0.1 11. Nch driver output current (IWOUT) vs. Input voltage (VDD) 44 1 0.01 0.0001 0.0001 0.0 Watchdog time-out period (tWDU) vs. CWDT VDD = VWEN = 0 V → 6 V, CPOR = 100 pF, Ta = +25°C − 1 − − 0.1 °C 5 0.01 0.001 0.01 0.1 1 tr [ms] 10 100 1000 105°C OPERATION, 3.8 μA CURRENT CONSUMPTION WATCHDOG TIMER WITH RESET FUNCTION Rev.2.5_00 S-1410/1411 Series  Power Dissipation TMSOP-8 HSNT-8(2030) Tj = +125°C max. 0.8 B 0.6 A 0.4 0.2 0.0 0 25 50 75 100 125 150 175 Tj = +125°C max. 5 Power dissipation (PD) [W] Power dissipation (PD) [W] 1.0 4 E 3 C D 2 1 B 0 A 0 25 Ambient temperature (Ta) [°C] Board 50 75 100 125 150 175 Ambient temperature (Ta) [°C] Power Dissipation (PD) Board Power Dissipation (PD) A 0.63 W A 0.55 W B B 0.74 W C 0.75 W − C 2.50 W D − D 2.38 W E − E 3.13 W 45 TMSOP-8 Test Board (1) Board A IC Mount Area Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] 1 2 3 4 Thermal via Specification 114.3 x 76.2 x t1.6 FR-4 2 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 - (2) Board B Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] Thermal via 1 2 3 4 Specification 114.3 x 76.2 x t1.6 FR-4 4 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 - No. TMSOP8-A-Board-SD-1.0 ABLIC Inc. HSNT-8(2030) Test Board IC Mount Area (1) Board A Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] 1 2 3 4 Thermal via Specification 114.3 x 76.2 x t1.6 FR-4 2 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.070 - (2) Board B Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] 1 2 3 4 Thermal via Specification 114.3 x 76.2 x t1.6 FR-4 4 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 - (3) Board C Item Size [mm] Material Number of copper foil layer Copper foil layer [mm] Thermal via 1 2 3 4 Specification 114.3 x 76.2 x t1.6 FR-4 4 Land pattern and wiring for testing: t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 Number: 4 Diameter: 0.3 mm enlarged view No. HSNT8-A-Board-SD-2.0 ABLIC Inc. HSNT-8(2030) Test Board IC Mount Area (4) Board D Item Size [mm] Material Number of copper foil layer Specification 114.3 x 76.2 x t1.6 FR-4 4 Thermal via 2 Pattern for heat radiation: 2000mm t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 - Item Size [mm] Material Number of copper foil layer Specification 114.3 x 76.2 x t1.6 FR-4 4 Copper foil layer [mm] 1 2 3 4 enlarged view (5) Board E Copper foil layer [mm] Thermal via 1 2 3 4 2 Pattern for heat radiation: 2000mm t0.070 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.035 74.2 x 74.2 x t0.070 Number: 4 Diameter: 0.3 mm enlarged view No. HSNT8-A-Board-SD-2.0 ABLIC Inc. 2.90±0.2 8 5 1 4 0.13±0.1 0.2±0.1 0.65±0.1 No. FM008-A-P-SD-1.2 TITLE TMSOP8-A-PKG Dimensions No. FM008-A-P-SD-1.2 ANGLE UNIT mm ABLIC Inc. 2.00±0.05 4.00±0.1 4.00±0.1 1.00±0.1 +0.1 1.5 -0 1.05±0.05 0.30±0.05 3.25±0.05 4 1 5 8 Feed direction No. FM008-A-C-SD-2.0 TITLE TMSOP8-A-Carrier Tape FM008-A-C-SD-2.0 No. ANGLE UNIT mm ABLIC Inc. 16.5max. 13.0±0.3 Enlarged drawing in the central part 13±0.2 (60°) (60°) No. FM008-A-R-SD-1.0 TITLE TMSOP8-A-Reel No. FM008-A-R-SD-1.0 QTY. ANGLE UNIT mm ABLIC Inc. 4,000 2.0±0.1 8 5 (1.70) 1 4 +0.05 0.08 -0.02 0.5 0.23±0.1 The heat sink of back side has different electric potential depending on the product. Confirm specifications of each product. Do not use it as the function of electrode. No. PP008-A-P-SD-2.0 TITLE HSNT-8-A-PKG Dimensions No. PP008-A-P-SD-2.0 ANGLE UNIT mm ABLIC Inc. +0.1 ø1.5 -0 2.0±0.05 4.0±0.1 0.25±0.05 +0.1 ø1.0 -0 0.60±0.05 4.0±0.1 2.3±0.05 4 321 5 6 78 Feed direction No. PP008-A-C-SD-1.0 TITLE HSNT-8-A-Carrier Tape No. PP008-A-C-SD-1.0 ANGLE UNIT mm ABLIC Inc. +1.0 9.0 - 0.0 11.4±1.0 Enlarged drawing in the central part ø13±0.2 (60°) (60°) No. PP008-A-R-SD-1.0 HSNT-8-A-Reel TITLE No. PP008-A-R-SD-1.0 ANGLE QTY. UNIT mm ABLIC Inc. 5,000 1.6 0.30 0.50 No. PP008-A-L-SD-1.0 TITLE No. HSNT-8-A -Land Recommendation PP008-A-L-SD-1.0 ANGLE UNIT mm ABLIC Inc. Disclaimers (Handling Precautions) 1. All the information described herein (product data, specifications, figures, tables, programs, algorithms and application circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use of the information described herein. 3. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described herein. 4. Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to the use of the products outside their specified ranges. 5. Before using the products, confirm their applications, and the laws and regulations of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products are strictly prohibited from using, providing or exporting for the purposes of the development of weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear, biological or chemical weapons or missiles, or use any other military purposes. 8. The products are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by ABLIC, Inc. Do not apply the products to the above listed devices and equipments. ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of the products. 9. In general, semiconductor products may fail or malfunction with some probability. The user of the products should therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system in which the products are used must be sufficiently evaluated and judged whether the products are allowed to apply for the system on customer's own responsibility. 10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be careful when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright information and know-how of ABLIC Inc. The information described herein does not convey any license under any intellectual property rights or any other rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express permission of ABLIC Inc. 14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales representative. 15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into the English language and the Chinese language, shall be controlling. 2.4-2019.07 www.ablic.com