ASNT7121-KMA

Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ASNT7121-KMA 15GS/s, 4-bit Flash Analog-to-Digital Converter with PRBS 20GHz analog input bandwidth Selectable clocking mode: external high-speed clock or internal PLL with external reference clock Broadband operation in external clocking mode: DC-15GS/s On-chip PLL with a central frequency of 10GHz Optional external preset of the internal clock divider Internal demultiplexer 4-to-16 for the output data rate reduction Selectable on-chip PRBS 27-1 generator for output interface alignment Differential CML input clock buffer and linear input data buffer Proprietary low-power LVDS output interface Selectable output clock frequency and polarity Selectable on-chip digital-to-analog converter for self-testing Single +3.5V power supply Power consumption: 2.8W Custom 100-pin metal-ceramic package vee 75 vee 74 q11n 73 q11p 72 vcc 71 q12n 70 q12p 69 vcc 68 q13n 67 q13p 66 vcc 65 q14n 64 q14p 63 vcc 62 q15n 61 q15p 60 vee 59 vee 58 odn 57 odp 56 vcc 55 n/c 54 n/c 53 n/c 52 vee 51               Rev. 1.5.2 ASNT7121 vee 50 vrefcrl 49 vlsbcrl 48 ondac 47 res 46 onprbs 45 vcc 44 vee 43 vee 42 vcc 41 dp 40 dn 39 vcc 38 vee 37 vee 36 vcc 35 cep 34 cen 33 vcc 32 vee 31 vee 30 vcc 29 crp 28 crn 27 vcc 26 1 vee 2 vee 3 q02p 4 q02n 5 vcc 6 q01p 7 q01n 8 vcc 9 q00p 10 q00n 11 vcc 12 clop 13 clon 14 n/c 15 vee 16 cosel1 17 cosel2 18 cosel3 19 lol 20 ftr 21 vee 22 ceoff 23 nc 24 nc cpcsel 25 vcc 76 vcc 77 q10p 78 q10n 79 vcc 80 q09p 81 q09n 82 vcc 83 q08p 84 q08n 85 vcc 86 q07p 87 q07n 88 vcc 89 q06p 90 q06n 91 vcc 92 q05p 93 q05n 94 vcc 95 q04p 96 q04n 97 vcc 98 q03p 99 q03n 100 vcc 1 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com DESCRIPTION ondac DAC vrefcrl vlsbcrl dp/n LIB 15 4-bit TTB Flash 15 Encoder ADC SEL 1of2 x4 4:16 16 DMX 16 PRBS onprbs ftr lol crp/n cep/n odp/n LOB q00p/nq15p/n LVDS OBx17 CMU & Divider ceoff res cosel1 cosel2 cosel3 Clk Proc. clop/n Fig. 1. Functional Block Diagram The ASNT7121-KMA is a 4-bit flash analog to digital converter (ADC) featuring high sampling rate and wide analog front-end bandwidth. The ADC system shown in Fig. 1 includes a linear input buffer (LIB) with a tree architecture and a CML-type input interface with internal 50Ohm single-ended terminations to vcc. The buffer delivers 15 matching copies of the input analog data signal dp/dn to the 4-bit flash ADC. The ADC creates 15 samples of the input data in thermometer code, which are then converted by a thermometer-to-binary encoder (TTB Encoder) into 4-bit binary words with a data rate f. The encoded data is demultiplexed into 16-bit wide words with a data rate f/4 and sent to the output through 16 lowpower LVDS buffers. The output parallel interface can be aligned using a selectable PRBS generator that substitutes the encoded data with a test pattern. An optional digital-to-analog converter (DAC) can be used for the control of the ADC’s operation. All operations are synchronized by the internal clock multiplication unit (CMU) based on a PLL (phaselocked loop) with an integrated divider. The block can operate in two different modes: clock multiplication (PLL is on) and clock division (PLL is off). In both modes, the divider generates internal clock signals divided by 2, 4, 8, and 16. The generated clocks divided by 4, 8, and 16 are sent to the LVDS output clop/clon through a clock processor that selects the desired speed (cosel1, cosel2 control signals) and polarity (cosel3 control signal) of the output clock. In the CMU’s second operational mode, the divider can be preset by external signal res to allow synchronization of parallel-connected ADCs. A PLL lock control output lol is also provided. The part operates from a single +3.5V power supply. All external control signals are compatible with the 2.5V CMOS interface. Rev. 1.5.2 2 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Linear Input Buffer (LIB) The system includes a linear input buffer (LIB) with a tree-type architecture that delivers 15 matching copies of the wide-band input differential analog data signal dp/dn to the 4-bit flash section. Symmetry is closely followed in both schematic and layout to ensure minimal aperture jitter. Clock Multiplication Unit (CMU) & Divider The PLL-based CMU with external loop filter connected to the pin ftr as shown in Fig. 2 can operate in two different modes. In the first “clock multiplication” mode (ceoff=”1”), the CMU multiplies the external reference clock crp/crn with the speed of f/16 by means of a PLL with a central frequency of f and a wide tuning range of the internal VCO (voltage-controlled oscillator). The generated clock is processed by the divider in order to generate internal clock signals divided by 2, 4, 8, and 16. 100Ohm To pin 20 (ftr) 1nF vee Fig. 2. Recommended External Loop Filter Schematic In the second “clock division” mode (ceoff=”0”), the PLL is disabled and the internal clocks are generated from the external high-speed clock cep/cen. To align multiple ADCs in parallel, the divider should be preset by the active-high CMOS control signal res. HS External Clock Input Buffer The high-speed external clock input buffer can accept high-speed clock signals at its differential CML input port cep/cen. It can also accept a single-ended signal with a threshold voltage applied to the unused pin. HS CIB can handle a wide range of input signal amplitudes. The buffer utilizes on-chip single-ended termination of 50Ohm to vcc for each input line. LS Reference Clock Input Buffer The low-speed reference clock input buffer is a proprietary LVDS buffer with internal 100Ohm differential termination between its inputs crp/crn. The buffer exceeds the requirements of standards IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. It is designed to accept differential signals with amplitudes above 100mV peak-to-peak (p-p), a wide range of DC common mode voltages, and AC common mode noise with a frequency up to 5MHz and voltage levels ranging from 0 to 2.4V. 4-bit Flash Analog to Digital Converter (ADC) with Encoder This block samples the incoming analog data with the clock signal provided by the CMU in order to generate a 4-bit output digital signal (Bit 0 – Bit 3) with MSB corresponding to Bit 3. The threshold voltages (Vth) of the ADS can be adjusted through analog signals vrefcrl and vlsbcrl as shown in Table 1. Table 1. Threshold Adjustment Options Control signal Adjusted value Name Range Name Range vrefcrl vcc-1.0V -> vcc Vth 15 vcc -0.5V -> vcc -0.15V vlsbcrl vcc -0.6V -> vcc -0.2V Vth (X+1) – Vth X 550uV -> 55mV Rev. 1.5.2 3 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com As can be seen, vrefcrl shifts the DC levels of all the threshold voltages simultaneously by the same amount while vlsbcrl alters the voltage range of the least significant bit (LSB). If no external voltages are applied to vrefcrl and vlsbcrl, it is recommended that both pins are ACterminated by 50Ohm to vee through a DC block! Demultiplexer (4:16 DMX) This block deserializes the 4-bit words from the ADC into 16-bit output words as shown in Table 2. Table 2. Demultiplexer Bit Order First Second Third Fourth Serialized input words 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 ADC bits (3 is MSB) 00 04 08 12 01 05 09 13 02 06 10 14 03 07 11 15 DMX output bits PRBS Generator (PRBS) and Selector (SEL 1of2x4) The on-chip selectable generator provides a full 127-bit long pseudo-random binary sequence (PRBS) signal according to the polynomial (x7 + x6 + 1), where xD represents a delay of D clock cycles. This is implemented as a linear feedback shift register (LSFR) in which the outputs of the seventh and sixth flipflops are combined together by an XOR function and provided as an input to the first flip-flop of the register. The block is activated by the external 2.5V CMOS signal onprbs (onprbs=”0” – default state – PRBS generator off, onprbs=”1” – PRBS generator on). The same signal controls the selector SEL1of2x4 in such a way that the following demultiplexer receives either the PRBS signal when the generator is activated or the encoded signal from the ADC if the generator is disabled. Clock Processor (Clk Proc) To increase the adaptability of the designed ADC, a clock processor that provides a low-speed output clock signal with the options specified in Table 3, is included. Table 3. Output Clock Options External control signals Output clock signal cosel1 cosel2 cosel3 Speed Inversion 1 1 1 c4 Yes 1 1 0 c4 No 0 1 1 c8 Yes 0 1 0 c8 No x 0 1 c16 Yes x 0 0 c16 No Digital to Analog Converter (DAC) A DAC block is included to perform a quick test of the ADC’s functionality. When activated by the external control signal (ondac=”1”), it converts the digital data into a step-wise copy of the input signal that is sent to the output odp/odn through a linear differential output buffer. The circuit is not consuming any power when disabled (ondac=”0”). Rev. 1.5.2 4 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com LVDS Output Buffers The 16-bit differential digital data words q00p/q00n to q15p/q15n are delivered to the output through an array of proprietary low power LVDS buffers. The low speed differential clock clop/clon also utilizes a similar LVDS output buffer. The buffers satisfy all the requirements of the IEEE Std. 1596.3-1996 and ANSI/TIA/EIA-644-1995. Rev. 1.5.2 5 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com TERMINAL FUNCTIONS Pin # Pin name Pin type Pin # Pin name Pin type Pin # Pin name Pin type GND 3.5V LVDS 1 vee 35 vcc 69 q12p outputs GND GND 2 vee 36 vee 70 q12n LVDS GND 3.5V 3 q02p 37 vee 71 vcc outputs 3.5V LVDS 4 q02n 38 vcc 72 q11p outputs 3.5V HS CML 5 vcc 39 dn 73 q11n inputs LVDS GND 6 q01p 40 dp 74 vee outputs 3.5V GND 7 q01n 41 vcc 75 vee 3.5V GND 3.5V 8 vcc 42 vee 76 vcc LVDS GND LVDS 9 q00p 43 vee 77 q10p outputs outputs 3.5V 10 q00n 44 vcc 78 q10n 3.5V CMOS input 3.5V 11 vcc 45 onprbs 79 vcc LVDS CMOS input LVDS 12 clop 46 res 80 q09p outputs outputs CMOS input 13 clon 47 ondac 81 q09n Control 3.5V 14 n/c 48 vlsbcrl 82 vcc voltages GND LVDS 15 vee 49 vrefcrl 83 q08p outputs CMOS input GND 16 cosel1 50 vee 84 q08n CMOS input GND 3.5V 17 cosel2 51 vee 85 vcc CMOS input LVDS 18 cosel3 52 n/c 86 q07p outputs Control output 19 lol 53 n/c 87 q07n Filter 3.5V 20 ftr 54 n/c 88 vcc GND 3.5V LVDS 21 vee 55 vcc 89 q06p outputs CMOS input LS CML 22 ceoff 56 odp 90 q06n outputs 3.5V 23 n/c 57 odn 91 vcc GND LVDS 24 n/c 58 vee 92 q05p outputs 3.5V GND 25 vcc 59 vee 93 q05n 3.5V LVDS 3.5V 26 vcc 60 q15p 94 vcc outputs LVDS LVDS 27 crn 61 q15n 95 q04p inputs outputs 3.5V 28 crp 62 vcc 96 q04n 3.5V LVDS 3.5V 29 vcc 63 q14p 97 vcc outputs GND LVDS 30 vee 64 q14n 98 q03p outputs GND 3.5V 31 vee 65 vcc 99 q03n 3.5V LVDS 3.5V 32 vcc 66 q13p 100 vcc outputs HS CML 33 cen 67 q13n inputs 3.5V 34 cep 68 vcc Rev. 1.5.2 6 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL CHARACTERISTICS PARAMETER TYP MAX UNIT COMMENTS General Parameters 3. 4 3.5 3.6 V ±3% vcc 0.0 V External ground vee Ivcc 815/800 mA With PRBS enabled/disabled Power consumption 2.85/2.80 W With PRBS enabled/disabled Junction temperature -25 50 125 °C Analog Input Data (dp/dn) Bandwidth 0.0 20 GHz CM Level vcc-0.8 vcc V Must match for both inputs Linearity range ±110 mV Differential or SE, p-p HS Input Clock (cep/cen) Frequency DC 15 GHz Swing 0.2 0.8 V Differential or SE, p-p CM Voltage Level vcc-0.8 vcc V Must match for both inputs Duty Cycle 40 50 60 % LS Reference Input Clock (crp/crn) Frequency 560 688 MHz 1/16 of VCO frequency CM Level 0.2 vcc V Voltage Swing 100 800 mV Differential Duty Cycle 40 50 60 % Output Data (q00p/q00n to q15p/q15n) Data Rate DC 3.75 Gbps CM Level 1.2 V Nominal for LVDS interface Amplitude range 250 350 mV Rise/Fall Times TBD ps 20%-80% LS Output Clock (clop/clon) Frequency f/4 f/8 f/16 GHz Selectable. Here f is the PLL or HS input clock frequency CM Level 1.2 V Nominal for LVDS interface Amplitude range 250 350 V Jitter TBD ps Duty Cycle 50 % DAC Output (odp/odn) Voltage Swing 250 350 mV Single-ended. p-p CM Level vcc-(voltage swing)/2 V Analog Control Signals (vrfcrl, vlsbcrl) Voltage range V see Table 1 CMOS Control Signals (cosel1/2/3, ceoff, res, ondac, onprbs) Logic “1” level vee+2.3 vee+2.5 V Logic “0” level vee+0.2 V Frequency 3.5 GHz Rev. 1.5.2 MIN 7 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com ELECTRICAL SPECIFICATIONS Parameter ENOB (5GS/s) ENOB (10GS/s) SFDR (5GS/s) SFDR (10GS/s) SINAD (5GS/s) SINAD (10GS/s) DNL INL Conditions fin = 3.9GHz fin = 7.8GHz fin = 3.9GHz fin = 7.8GHz fin = 3.9GHz fin = 7.8GHz Min Typical 3.39 3.23 30.13 28.78 -22.15 -21.19 -0.2 -0.2 Max Units bits bits dBFS dBFS dB dB lsbs lsbs 0.2 0.2 ABSOLUTE MAXIMUM RATINGS Caution: Exceeding the absolute maximum ratings presented in Table 4 may cause damage to this product and/or lead to reduced reliability. Functional performance is specified over the recommended operating conditions for power supply and temperature only. AC and DC device characteristics at or beyond the absolute maximum ratings are not assumed or implied. All min and max voltage limits are referenced to ground (vee). Table 4. Absolute Maximum Ratings Parameter Supply Voltage (vcc) Power Consumption RF Input Voltage Swing (SE) Case Temperature Storage Temperature Operational Humidity Storage Humidity Min -40 10 10 Max 4.0 3.0 1.4 +100 +100 98 98 Units V W V ºC ºC % % PACKAGE INFORMATION The chip die is housed in a custom 100-pin CQFP package shown in Fig. 3. The package provides a center heat slug located on its back side to be used for heat dissipation. ADSANTEC recommends for this section to be soldered to the vcc plain, which is power for a positive supply. The part’s identification label is ASNT7121-KMA. The first 8 characters of the name before the dash identify the bare die including general circuit family, fabrication technology, specific circuit type, and part version while the 3 characters after the dash represent the package’s manufacturer, type, and pin out count. This device complies with the Restriction of Hazardous Substances (RoHS) per 2011/65/EU for all ten substances. Thermal resistance of junction to case bottom pad is 4°C/W. Rev. 1.5.2 8 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com Fig. 3. CQFP 100-Pin Package Drawing (All Dimensions in mm) Rev. 1.5.2 9 February 2020 Advanced Science And Novel Technology Company, Inc. 2790 Skypark Drive Suite 112, Torrance, CA 90505 Offices: 310-530-9400 / Fax: 310-530-9402 www.adsantec.com REVISION HISTORY Revision 1.5.2 1.4.2 1.4.1 1.3.1 Date 02-2020 07-2019 09-2015 08-2015 1.2.1 1.1.1 08-2015 07-2015 1.0.1 07-2015 1.0.0 09-2014 Rev. 1.5.2 Changes Updated Package Information Updated Letterhead Clock Multiplication Unit (CMU) & Divider section edited Corrected PRBS polynomial Removed prbsres function (Pinout diagram, block diagram, description, Terminal Functions table, Electrical Characteristics table) Removed cpcsel function (Pinout diagram, block diagram, description, Terminal Functions table, Electrical Characteristics table) Updated Electrical Specifications Updated title Revised Electrical Characteristics Revised Absolute Maximum Ratings section Added Electrical Specifications table Revised package information section Preliminary release 10 February 2020