SP690T/S/R, SP802T/S/R,
SP804T/S/R, and SP805T/S/R
®
3.0V/3.3V Low Power Microprocessor
Supervisory with Battery Switch-Over
■ RESET and RESET Outputs
■ Reset asserted down to VCC = 1V
■ Reset Time Delay - 200ms
■ Watchdog Timer - 1.6 sec timeout
■ 40µA Maximum VCC Supply Current
■ 1µA Maximum Battery Supply Current
■ Power Switching
50mA Output in VCC Mode (1.5Ω)
10mA Output in Battery Mode (15Ω)
■ Battery Can Exceed VCC in Normal Operation
■ Precision Voltage Monitor for Power-Fail
or Low-Battery Warning
■ Available in 8 pin SO and DIP packages
■ Pin Compatible Upgrades to
MAX690T/S/R, MAX802T/S/R,
MAX804T/S/R, MAX805T/S/R
DESCRIPTION
The SP690T/S/R, SP802T/S/R, SP804T/S/R and SP805T/S/R devices are a family of
microprocessor (µP) supervisory circuits that integrate a myriad of components involved in
discrete solutions to monitor power-supply and battery-control functions in µP and digital
systems. The series will significantly improve system reliability and operational efficiency
when compared to discrete solutions. The features of the SP690T/S/R, SP802T/S/R,
SP804T/S/R and SP805T/S/R devices include a watchdog timer, a µP reset and backupbattery switchover, and power-failure warning; a complete µP monitoring and watchdog
solution. The series is ideal for 3.0V or 3.3V applications in portable electronics, computers,
controllers, and intelligent instruments and is a solid match for designs where it is critical to
monitor the power supply to the µP and it’s related digital components. Refer to Sipex's
SP690A/692A/802L/802M/805L/805M series for similar devices designed for +5V systems.
Part Number
RESET
Active
RESET
Threshold
RESET
Accuracy
PFI
Accuracy
Watchdog
Input
Backup-Battery
Switch
SP690T/805T
LOW/HIGH
3.075V
±75mV
±4%
YES
YES
SP802T/804T
LOW/HIGH
3.075V
±60mV
±2%
YES
YES
SP690S/805S
LOW/HIGH
2.925V
±75mV
±4%
YES
YES
SP802S/804S
LOW/HIGH
2.925V
±60mV
±2%
YES
YES
SP690R/805R
LOW/HIGH
2.625V
±75mV
±4%
YES
YES
SP802R/804R
LOW/HIGH
2.625V
±60mV
±2%
YES
YES
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
1
© 2006 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation of the device at
these ratings or any other above those indicated in the operation
sections of the specifications below is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect
reliability and cause permanent damage to the device.
VCC..................................................................................-0.3V to 6.0V
VBATT................................................................................-0.3V to 6.0V
All Other Inputs (NOTE 1).................................-0.3V to the higher of VCC or VBATT
Continuous Input Current:
VCC..................................................................................100mA
VBATT..................................................................................20mA
GND..................................................................................20mA
WDI, PFI...........................................................................20mA
Continuous Output Current:
RESET, RESET, PFO.........................................................20mA
VOUT......................................................................................100mA
Power Dissipation per Package:
8pin NSOIC (derate 6.14mW/°C above +70°C)..............500mW
8pin PDIP (derate 11.8mW/°C above +70°C)..............1,000mW
Storage Temperature........................................-65°C to +160°C
Lead Temperature(soldering,10sec).............................................+300°C
ESD Rating........................................................4KV Human Body Model
SPECIFICATIONS
VCC = 3.17V to 5.50V for the SP690T/SP80_T, VCC = 3.02V to 5.50V for the SP690S/SP80_S, VCC = 2.72V to 5.50V for the SP690R/SP80_R, VBATT = 3.60V, and
TA = TMIN to TMAX unless otherwise noted. Typical values taken at TAMB = +25OC.
PARAMETERS
MIN.
Operating Voltage Range,
TYP.
MAX.
1.0
UNITS CONDITIONS
5.5
Volts
25
40
µA
20
40
µA
0.4
1
µA
0.001
0.5
µA
0.02
µA
VCC or VBATTERY, NOTE 1
VCC Supply Current, ISUPPLY
VCC Supply Current in Battery
Backup Mode
VBATTERY Supply Current in
Any Mode, NOTE 2
VBATTERY Leakage Current, NOTE 3
VBATTERY Leakage Current, NOTE 4
Output Voltage, VOUT
VOUT in Battery-Backup Mode
-0.1
VCC - 0.03
VCC - 0.0075
VCC - 0.3
VCC - 0.075
VCC - 0.0015
VCC - 0.0003
0.025
2.40
V
2.50
Battery Switch Threshold,
VCC rising, NOTE 7
SP690T/S/R JAN 30-06
excluding IOUT
3.3V > VCC >VBATTERY + 0.2V
IOUT = 50mA
IOUT = 250µA, VCC > 2.5V
VBATTERY - 0.02 VBATTERY - 0.0045
0.065
2.30
VCC=2.0V,VBATTERY=2.3V,
excluding IOUT
I = 5mA
V
VBATTERY - 0.018
VBATTERY - 0.15
Battery Switch Threshold,
VCC falling
excluding IOUT
IOUT = 250µA, VBATTERY = 2.3V
IOUT = 1mA, VBATTERY = 2.3V
IOUT = 10mA, VBATTERY = 3.3V
V
VBATTERY - VCC, VSW > VCC > 1.75V, NOTE 5
VBATTERY > VCC, NOTE 6
V
Values are identical to the Reset
Threshold values at VCC rising
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
SPECIFICATIONS (continued)
VCC = 3.17V to 5.50V for the SP690T/SP80_T, VCC = 3.02V to 5.50V for the SP690S/SP80_S, VCC = 2.72V to 5.50V for the SP690R/SP80_R, VBATT = 3.60V, and
TA = TMIN to TMAX unless otherwise noted. Typical values taken at TAMB = +25OC.
PARAMETERS
Reset Threshold, VRST
NOTE 8
Reset Timeout Period, tWP
RESET, PFO Output Voltage, VOH
MIN.
TYP.
MAX.
3.00
3.00
3.075
3.085
3.15
2 .8 5
2 .8 5
2.925
3 .1 7
3.00
2.935
2.625
3.02
2 .7 0
2.635
2 .7 2
3.00
3.00
3.075
3.085
3 .1 2
3 .1 4
2 .8 8
2 .8 8
2 .9 2 5
2 .9 3 5
3 .0 0
3 .0 2
2 .5 9
2 .5 9
2 .6 2 5
2 .6 3 5
2.70
2.72
140
200
280
VCC - 0.3
VCC - 0.15
2 .5 5
2 .5 5
UNITS CONDITIONS
V
SP690T/805T, VCC falling
SP690T/805T, VCC rising
SP690S/805S, VCC falling
SP690S/805S, VCC rising
SP690R/805R, VCC falling
SP690R/805R, VCC rising
V
SP802T/804T, VCC falling
SP802T/804T, VCC rising
SP802S/804S, VCC falling
SP802S/804S, VCC rising
SP802R/804R, VCC falling
SP802R/804R, VCC rising
ms
V
ISOURCE = 30µA
ISINK = 1.2mA, SP690_/802_ where
VCC = VRST minimum
RESET, PFO Output Voltage, VOL
0.06
0.30
V
RESET, PFO Output Voltage, VOL
0.13
0.30
V
VBATTERY = 0V, VCC = 1.0V, ISINK = 40µA
0.30
V
ISINK = 1.2mA, SP804_/805_ where
VCC = VRST maximum
-1
µA
VBATTERY = 0V, VCC = VRST minimum,
VRESET = 0V or VCC
180
500
µA
VCC = 3.3V, VOH = 0V
1.60
2.24
0.06
RESET Output Voltage, VOL
RESET Output Leakage Current,
NOTE 11
-1
Output Short to GND Current, IOS,
PFO and RESET
Watchdog Timeout, tWD
WDI Input Threshold
VIH
VIL
WDI Input Current
PFI Input Threshold
PFI Input Current
PFI Hysteresis, VPFH
SP690T/S/R JAN 30-06
1.12
s
VCC < 3.6V
µs
1
WDI Pulse Width
0.7 x VCC
V
µA
0V < VCC < 5.5V
V
SP690_/805_, VCC VBATT, VOUT remains connected to VCC until VCC drops below VBATT. The
VCC-to-VBATT comparator has a small 25mV typical hysteresis to prevent oscillation.
NOTE 6: When VBATT > VCC > VSW, VOUT remains connected to VCC until VCC drops below the battery
switch threshold, VSW.
NOTE 7: VOUT switches from VBATT to VCC when VCC rises above the reset threshold, independent of
VBATT. Switchover back to VCC occurs at the exact voltage that causes RESET to go HIGH (on the
SP804_ and SP805_ RESET goes LOW). Switchover occurs 200ms prior to reset.
NOTE 8: The reset threshold tolerance is wider for VCC rising than for VCC falling to accommodate the
10mV typical hysteresis, which prevents internal oscillation.
NOTE 9: SP690_ and SP802_ devices only.
NOTE 10: SP804_ and SP805_ devices only.
NOTE 11: The leakage current into or out of the RESET pin is tested with RESET asserted (RESET
output high impedance).
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
INTERNAL BLOCK DIAGRAM
VBATT 8
VCC
2
BATTERY
SWITCHOVER
CIRCUIT
1
VOUT
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
BATTERY
SWITCHOVER
COMPARATOR
1.25V
RESET
GENERATOR
RESET / RESET*
7
RESET
COMPARATOR
1.25V
WDI
PFI
WATCHDOG
TIMER
6
4
PFO
5
POWER-FAIL
COMPARATOR
1.25V
GND
SP690T/S/R JAN 30-06
3
*SP804T/S/R and SP805T/S/R only
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
PINOUT
VOUT
1
VCC
2 SP690T/S/R 7
SP802T/S/R
3 SP804T/S/R 6
SP805T/S/R
4
5
GND
PFI
8
VBATTERY
RESET / RESET*
WDI
PFO
*SP804T/S/R and SP805T/S/R only
PIN ASSIGNMENTS
Pin 7 for SP690_/802_ only — Active-LOW
Reset Output. — Whenever RESET is
triggered by a watchdog timeout, it goes
LOW for 200ms. It stays LOW whenever
VCC is below the reset threshold and remains LOW for 200ms after VCC rises
above the reset threshold or when the
watchdog triggers a reset.
Pin 1 —VOUT — Output Supply Voltage for
CMOS RAM. When VCC is above the
reset threshold, VOUT connects to VCC
through a P-channel MOSFET switch.
When VCC falls below the VSW and
VBATTERY, VBATTERY connects to VOUT.
Connect to VCC if no battery is used.
Pin 2 — VCC — +5V Supply Input
Pin 7 for SP804_/805_ only — Active-HIGH
Open-Drain Reset Output. — The
inverse operation of RESET.
Pin 3 — GND — Ground reference for all
signals
Pin 4 — PFI — Power-Fail Comparator Input.
When PFI is less than 1.25V or when VCC
falls below the VSW, PFO goes LOW,
otherwise PFO remains HIGH. Connect
to GND if unused.
Pin 5
Pin 8 — VBATTERY — Backup-Battery Input.
When VCC falls below VSW and VBATTERY,
VOUT switchesfrom VCC to VBATTERY.
When VCC rises above the reset threshold,
VOUT reconnects to VCC. VBATTERY may
exceed VCC. Connect to VCC if no battery
is used.
— PFO — Power-Fail Comparator
Output. Leave open if unused.
Pin 6 — WDI — Watchdog Input. If WDI
remains HIGH or LOW for 1.6 seconds,
the internal watchdog timer triggers a
reset. The internal watchdog timer clears
when reset is asserted or WDI sees a
rising or falling edge. The watchdog
function cannot be disabled.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
TYPICAL CHARACTERISTICS (TAMB = 25oC, unless otherwise noted)
10000
40
Battery Supply
Current (nA)
Supply Current (µA)
1000
35
30
100
10
25
1
20
-60
-40
-20
0
20
40
60
80
100 120
0.1
-60
140
-35
-10
Figure 1. VCC Supply Current vs. Temperature (Normal
Mode)
65
90
115
140
30
VBATTERY to VOUT On-Resistance (Ω)
1.26
PFI Threshold (Volts)
40
Figure 2. Battery Supply Current vs. Temperature
1.262
1.258
1.256
1.254
1.252
1.25
1.248
-60
15
Temperature (oC)
Temperature (oC)
-40
-20
0
20
40
60
80
100 120
25
20
15
10
5
0
-60
140
-40
-20
0
20
Temperature (oC)
40
60
80
100 120
140
Temperature (oC)
Figure 3. PFI Threshold vs. Temperature
Figure 4. VBATTERY to VOUT ON-Resistance vs. Temperature
3.15
3.5
Reset Threshold (Volts)
On Resistance (Ω)
3
2.5
2
1.5
1
3.11
3.09
3.07
0.5
0
-60
3.13
-40
-20
0
20
40
60
80
100 120
3.05
-60
140
Temperature ( C)
-35
-10
15
40
65
90
115
140
o
Temperature (oC)
Figure 5. VCC to VOUT On-Resistance vs. Temperature
SP690T/S/R JAN 30-06
Figure 6. Reset Threshold vs. Temperature
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
14000
10000
Reset Timeout (mS)
RESET Output Resistance (Ω)
185
12000
8000
6000
4000
180
2000
0
-60
175
-60
-35
-10
15
40
65
90
115
-40
-20
0
140
20
40
60
80
100 120
140
Temperature (oC)
Temperature ( C)
o
Figure 7. Reset Output Resistance vs. Temperature
Figure 8. Reset Timeout vs. Temperature
30
1E-06
Propagation Delay (µs)
26
decade
/div
22
18
14
1E-14
10
-60
.0000
V3
.5000/div
(V)
-40
-20
0
20
40
60
80
100 120
140
5.000
Temperature (oC)
Figure 9. Battery Current vs. VCC Voltage
Figure 10. Reset-Comparator Propagation Delay vs.
Temperature
1000
Voltage Drop (mV) [ VBATTERY - VOUT ]
1000
Voltage Drop (mV) [ VCC - VOUT ]
VCC = 4.5V
VBATTERY = 0V
100
10
1
1
100
10
1
10
IOUT (mA)
100
1
Figure 11. VCC to VOUT Vs. Output Current
SP690T/S/R JAN 30-06
VCC = 0V
VBATTERY = 4.5V
IOUT (mA)
10
Figure 12. VBATTERY to VOUT Vs. Output Current
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
VCC
VBATTERY = 0V
TA = +25 C
V CC
2V
div
VCC
2KΩ
T
0V
RESET
RESET
RESET
1
0V
330pF
1 sec / div
GND
Figure 13A. SP690A RESET Output Voltage vs.
Supply Voltage
Figure 13B. Circuit for the SP690A/802L RESET
Output Voltage vs. Supply Voltage
VCC
VCC
V CC
1V
div
VCC
10KΩ
0V
RESET
1
RESET
VBATTERY
0V
330pF
GND
1 sec /div
Figure 14A. SP805L RESET Output Voltage vs.
Supply Voltage
Figure 14B. Circuit for the SP805 RESET Output
Voltage vs. Supply Voltage
VCC
[
T
]
TA = +25 C
1V / div
3.1V
V CC
1
2V
VCC
10KΩ
RESET
3.1V
T
RESET
0
30pF
10µS / div
GND
Figure 15B. Circuit for the SP690A/802L RESET
Response Time
Figure 15A. SP690A RESET Response Time
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
[
T
VCC
]
VCC
1V / div
V CC
3.1V
VCC
1
2V
10KΩ
RESET
RESET
T
0V
330pF
GND
10 µs / div
Figure 16B. Circuit for the SP805 RESET Response
Time
Figure 16A. SP805L RESET Response Time
+5V
PFI
1.3V
VCC = +5V
TA = +25 C
1.2V
V CC= 5V
V BATTERY = 0
1KΩ
PFI
PFO
5V
0V
PFO
30pF
+1.25V
500ns / div
Figure 17B. Circuit for the Power-Fail Comparator
Response Time (fall)
Figure 17A. Power-Fail Comparator Response Time (fall)
+5V
1
1.3V
PFI
1.2V
VCC = +5V
TA = +25 C
V CC= 5
V BATTERY = 0
PFI
PFO
+1.25V
1
2
PFO
30pF
1KΩ
T
500ns / div
Figure 18A. Power-Fail Comparator Response Time (rise)
SP690T/S/R JAN 30-06
Figure 18B. Circuit for the Power-Fail Comparator
Response Time (rise)
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
3.0V or 3.3V
VRST
VSW
VCC
0V
3.0V or 3.3V
VBATTERY=3.6V
VOUT
VSW
0V
3.0V or 3.3V
RESET
tWP
0V
3.0V or 3.3V
RESET*
0V
3.0V or 3.3V
PFO
VBATTERY=PFI=3.6V
IOUT=0mA
0V
*SP804T/S/R and SP805T/S/R only; Reset externally pulled up to VCC.
Figure 19. Timing Diagram
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
FEATURES
THEORY OF OPERATION
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices provide four key
functions:
1. A battery backup switch for CMOS RAM,
CMOS microprocessors, or other logic.
2. A reset output during power-up, power-down
and brownout conditions.
3. A reset pulse if the optional watchdog timer
has not been toggled within a specified time.
4. A 1.25V threshold detector for power-fail
warning, low battery detection, or to monitor a
power supply other than 3.3V or 3.0V.
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices are microprocessor
(µP) supervisory circuits that monitor the power
supplied to digital circuits such as microprocessors, microcontrollers, or memory. The series is
an ideal solution for portable, battery-powered
equipment that requires power supply monitoring.
Implementing this series will reduce the
number of components and overall complexity.
The watchdog functions of this product family
will continuously oversee the operational status
of a system.
The SP690T/S/R, SP802T/S/R, SP804T/S/R
and SP805T/S/R devices differ in their resetvoltage threshold levels and are ideally suited
for applications in automotive systems, intelligent
instruments, and battery-powered computers and
controllers. The series is a solid match for
designs where it is critical to monitor the
power supply to the µP and it’s related digital
components.
These µP supervisory circuits are not shortcircuit protected. Shorting VOUT to ground excluding power-up transients such as charging
a decoupling capacitor - may potentially damage
these devices. Decouple both VCC and VBATTERY
pins to ground by placing 0.1µF capacitors as
close to the device as possible. The operational
features and benefits of the SP690T/S/R,
SP802T/S/R, SP804T/S/R and SP805T/S/R
devices are described in more detail below.
Reset Output
Regulated +3.3V or +3.0V
0.1µF
VCC
VCC
RESET
µP
PFO
I/O LINE
WDI
GND
PFI
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
VOUT
R2
RESET is guaranteed to be a logic LOW for 0V
< VCC < VRST, provided that VBATTERY is greater
than 1V. Without a backup battery, RESET is
guaranteed valid for VCC > 1V. Once VCC
exceeds the reset threshold, an internal timer
keeps RESET low for the reset timeout period.
After this period, RESET goes HIGH, as seen in
Figure 19.
VBATTERY
GND
BUS
CMOS
RAM
R1
pin 7*
NMI
The microprocessor's (µP's) reset input starts
the µP in a known state. When the µP is in an
unknown state, it should be held in reset. The
SP690T/S/R, SP802T/S/R, SP804T/S/R and
SP805T/S/R devices assert reset during
power-up and prevent code execution errors
during power-down or brownout conditions.
Unregulated
DC
3.6V
Lithium
Battery
VCC
0.1µF
GND
If a brownout condition occurs and VCC dips
below the reset threshold, RESET goes LOW.
Each time RESET is triggered, it stays low for
the reset timeout period. Any time VCC goes
below the reset threshold, the internal timer
restarts.
* RESET for the SP690T/S/R and the SP802T/S/R
RESET for the SP804T/S/R and the SP805T/S/R
Figure 20. Typical Operating Circuit
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
Watchdog Input
The watchdog timer can also initiate a reset.
Refer to the Watchdog Input section.
The watchdog circuit monitors the µP's activity.
If the µP does not toggle the watchdog input
(WDI) within 1.6sec, a reset pulse is triggered.
The internal 1.6sec timer is cleared by either a
reset pulse or by a transition (LOW-to-HIGH or
HIGH-to-LOW) at WDI. If WDI is tied HIGH
or LOW, a RESET pulse is triggered every
1.8sec (tWD plus tRS).
The SP804T/S/R and SP805T/S/R active-HIGH
RESET output is open drain and the inverse
of the SP690T/S/R and SP802T/S/R RESET
outputs.
RESET is also triggered by a watchdog timeout.
If WDI remains either high or low for a period
that exceeds the watchdog timeout period (1.6
sec), RESET pulses low for 200mS. As long as
RESET is asserted, the watchdog timer remains
cleared. When RESET comes high, the watchdog resumes timing and must be serviced within
1.6sec. If WDI is tied high or low, a RESET
pulse is triggered every 1.8sec (tWD plus tRS).
As long as reset is asserted, the timer remains
cleared and does not count. As soon as reset is
de-asserted, the timer starts counting. Unlike
the 5V SP690A series, the watchdog function
cannot be disabled.
Power-Fail Comparator
Reset Threshold
The power-fail comparator can be used as an
under-voltage detector to signal the failing of a
power supply (it is completely separate from the
rest of the circuitry and does not need to be
dedicated to this function). The PFI input is
compared to an internal 1.25V. If PFI is less than
VPFT, PFO goes low.
The SP690T and SP805T devices are designed
for 3.3V systems with a ±5% power-supply
tolerance and a 10% system tolerance. Except
for watchdog faults, reset will not assert as long
as the power supply remains above 3.15V (3.3V
- 5%). Reset is guaranteed to assert before the
power supply falls below 3.0V.
The power-fail comparator turns off and PFO
goes LOW when VCC falls below VSW on
power-down. The power-fail comparator turns
on as VCC crosses VSW on power-up. If the
comparator is not used, connect PFI to ground
and leave PFO unconnected.
The SP690S and SP805S devices are designed
for 3.3V ±10% power supplies. Except for
watchdog faults, they are guaranteed not to
assert reset as long as the supply remains above
3.0V (3.3V - 10%). Reset is guaranteed to
assert before the power supply fails below 2.85V
(VCC - 14%).
Backup-Battery Switchover
The SP690R and SP805R devices are optimized
for monitoring 3.0V ±10% power supplies. Reset
will not occur until VCC falls below 2.7V (3.0V
- 10%), but is guaranteed to occur before the
supply falls below 2.55V (3.0V - 15%).
In the event of a brownout or power failure, it
may be necessary to preserve the contents of
RAM. With a backup battery installed at
VBATTERY, the devices automatically switch
RAM to backup power when VCC fails.
The SP802T/S/R and SP804T/S/R devices are
respectively similar to the SP690T/S/R and
SP805T/S/R devices with tightened reset
and power-fail threshold tolerances.
This family of µP supervisors (designed for
3.3V and 3V systems) doesn't always connect
VBATTERY to VOUT when VBATTERY is greater
than VCC. VBATTERY connects to VOUT (through
a 15Ω switch) when VCC is below VSW and
VBATTERY is greater than VCC.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
A)
B)
3.0V or 3.3V
VCC
1N4148
3.0V or 3.3V
VCC
1N4148
VOUT
VBATTERY
pin 7*
0.1F
+5V
CONNECT TO
STATIC RAM
CONNECT
TO µP
pin 7*
0.1F
GND
CONNECT TO
STATIC RAM
VOUT
VBATTERY
CONNECT
TO µP
GND
* RESET for the SP690T/S/R and the SP802T/S/R
RESET for the SP804T/S/R and the SP805T/S/R
Figure 21. Using a High Capacity Capacitor as a Backup Power Source
Switchover at VSW (2.40V) ensures that batterybackup mode is entered before VOUT gets too
close to the 2.0V minimum required to reliably
retain data in CMOS RAM. Switchover at higher
VCC voltages would decrease backup-battery
life. When VCC recovers, switchover is deferred
until VCC rises above the reset threshold, VRST,
to ensure a stable supply. VOUT is connected to
VCC through a 1.5Ω PMOS power switch.
Replacing the Backup Battery
If VBATTERY is decoupled with a 0.1µF capacitor
to ground, the backup battery can be removed
while VCC remains valid without danger of
triggering RESET/RESET. As long as VCC
stays above VSW, battery-backup mode cannot
be entered.
Adding Hysteresis to the Power-Fail
Comparator
Using a High Capacity Capacitor as a
Backup Power Source
The power-fail comparator has a typical input
hysteresis of 10mV. This is sufficient for most
applications where a power-supply line is being
monitored through an external voltage divider
(refer to the Monitoring an Additional Power
Supply section).
Figure 21 shows two ways to use a High Value
Capacitor as a backup power source. The High
Value Capacitor may be connected through a
diode to the 3V input as in Figure 21A or, if a
5V supply is also available, the High Value
Capacitor may be charged up to the 5V supply
as in Figure 21B allowing a longer backup
period. Since VBATTERY can exceed VCC while VCC
is above the reset threshold, there are no
special precautions when using these µP
supervisors with a High Value Capacitor.
If additional noise margin is desired, connect a
resistor between PFO and PFI as shown in
Figure 22A. Select the ratio of R1 and R2 such
that PFI sees 1.25V when VIN falls to its trip
point (VTRIP). R3 adds the hysteresis and will
typically be more than 10 times the value of R1
or R2. The hysteresis window extends both
above (VH) and below (VL) the original trip
point (VTRIP).
Operation Without a Backup Power
Source
These µP supervisors were designed for
battery-backed applications. If a backup power
source is not used, connect both VBATTERY
and VOUT to VCC. Since there is no need to
switch over to any backup power source, VOUT
does not need to be switched. A direct connection to VCC eliminates any voltage drops across
the switch which may push VOUT below VCC.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
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© 2006 Sipex Corporation
VIN
VIN
A.)
B.)
R1
R1
VCC
VCC
PFI
PFI
+
+
R2
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
R3
*C1
R2
SP690T/S/R
SP802T/S/R
SP804T/S/R
SP805T/S/R
R3
*C1
PFO
PFO
GND
GND
TOµP
TOµP
*OPTIONAL
PFO
PFO
0V
0V
VL
VTRIP
0V
VH
( )
( )( )(
)
[ (
) ]
R1 + R2
R2
VTRIP = VPFT
VH =
0V
VIN
VPFT + VPFH
VL = R1
VPFT
R1
VTRIP = VPFT
1 + 1 + 1
R1 R2 R3
VL = R1
- VCC
R3
1 + 1 + 1
R1 R2 R3
VTRIP
(
[(
R1 + R2
R2
)
)(
VPFT + VPFH
VIN
VH
)
1 + 1 + 1 - (VCC - VD)
R1 R2 R3
R3
]
WHERE VPFT = 1.25V
VPFH = 10mV
WHERE VPFT = 1.25V
VD = DIOD FORWARD VOLTAGE DROP
VPFH = 10mV
Figure 22A. Adding Additional Hysteresis to the Power-Fail Comparator.
Figure 22B. Shifting the Additional Hysteresis above VPFT
The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max over extended
temperature range) PFI input current does not
shift the trip point. R3 should be larger than
10kΩ so it does not load down the PFO pin.
Capacitor C1 adds additional noise rejection.
Connecting an ordinary signal diode in series
with R3, as in Figure 22B, causes the lower trip
point (VL) to coincide with the trip point without
hysteresis (VTRIP), so the entire hysteresis
window occurs above VTRIP. This method provides additional noise margin without compromising the accuracy of the power-fail threshold
when the monitored voltage is falling. It is
useful for accurately detecting when a voltage
falls past a threshold.
VIN
3.0V OR 3.3V
VCC
VCC
R1
R1
SP690T/S/R
SP802T/S/R
PFI
PFI
PFO
PFO
SP804T/S/R
SP805T/S/R
R2
SP804T/S/R
SP805T/S/R
R2
SP690T/S/R
SP802T/S/R
GND
GND
V-
VCC
VCC
PFO
PFO
V-
VL
[(
[ (
VTRIP = R2
VTRIP
VTRIP
0V
)( ) ]
) ]
VPFT + VPFH
1 + 1
R1 R2
- VCC
R1
VTRIP = VPFT
1 + 1 - VCC
VL = R2 VPFT R1 R2
(
( )
)( )
VH = VPFT + VPFH
R3
VIN
VH
R1 + R2
R2
R1 + R2
R2
WHERE VPFT = 1.25V
VPFH = 10mV
NOTE: VTRIP IS NEGATIVE
Figure 23. Using the Power-Fail Comparator to Monitor an Additional Power Supply
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
15
© 2006 Sipex Corporation
Buffered RESET connects to System Components
VCC
1nF Capacitor
VOUT TO GND
VCC
µP
Above Line
RESET
Generated
RESET
RESET
4.7KΩ
GND
NO
RESET
Generated
GND
Figure 24. Interfacing to Microprocessors with
Bidirectional RESET I/O
Figure 25. Maximum Transient Duration without
Causing a Reset Pulse vs. Reset Comparator Overdrive
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive
or negative supplies using a resistor voltage
divider to PFI. PFO can be used to generate an
interrupt to the µP, as seen in Figure 23.
Figure 25 shows maximum transient duration
vs. reset-comparator overdrive, for which reset
pulses are not generated. The data was generated
using negative-going VCC pulses, starting at
3.3V and ending below the reset threshold by
the magnitude indicated (reset comparator
overdrive). The graph shows the maximum pulse
width a negative-going VCC transient may
typically have without causing a reset pulse to
be issued. As the amplitude of the transient
increases (i.e. goes farther below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a VCC transient that goes
100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be
issued. A 100nF bypass capacitor mounted close
to the VCC pin provides additional transient
immunity.
Interfacing to µPs with Bidirectional
Reset Pins
Any µPs with bidirectional reset pins, such as
the Motorola 68HC11 series, can interface with
the SP690_ and the SP802_ RESET outputs.
For example, if the RESET output is driven
HIGH and the µP wants to pull it LOW,
indeterminate logic levels may result. To correct
this, connect a 4.7kΩ resistor between the
RESET output and the µP reset I/O, as in
Figure 24. Buffer the RESET output to other
system components.
Negative-Going VCC Transients
While issuing resets to the µP during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to shortduration negative-going V CC transients
(glitches). It is usually undesirable to reset the
µP when VCC experiences only small glitches.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
16
© 2006 Sipex Corporation
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
E1 E
D1 = 0.005" min.
(0.127 min.)
A1 = 0.015" min.
(0.381min.)
D
A = 0.210" max.
(5.334 max).
C
A2
B1
B
e = 0.100 BSC
(2.540 BSC)
Ø
L
eA = 0.300 BSC
(7.620 BSC)
ALTERNATE
END PINS
(BOTH ENDS)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
8–PIN
14–PIN
16–PIN
18–PIN
20–PIN
22–PIN
A2
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
0.115/0.195
(2.921/4.953)
B
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
0.014/0.022
(0.356/0.559)
B1
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
0.045/0.070
(1.143/1.778)
C
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
0.008/0.014
(0.203/0.356)
D
0.355/0.400
0.735/0.775
0.780/0.800
0.880/0.920
0.980/1.060
1.145/1.155
(9.017/10.160) (18.669/19.685) (19.812/20.320) (22.352/23.368) (24.892/26.924) (29.083/29.337)
E
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
0.300/0.325
(7.620/8.255)
E1
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
0.240/0.280
(6.096/7.112)
L
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
0.115/0.150
(2.921/3.810)
Ø
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
0°/ 15°
(0°/15°)
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
17
© 2006 Sipex Corporation
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(NARROW)
E
H
h x 45°
D
A
Ø
e
B
A1
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
SP690T/S/R JAN 30-06
L
8–PIN
14–PIN
16–PIN
A
0.053/0.069
(1.346/1.748)
0.053/0.069
(1.346/1.748)
0.053/0.069
(1.346/1.748)
A1
0.004/0.010
(0.102/0.249
0.004/0.010
(0.102/0.249)
0.004/0.010
(0.102/0.249)
B
0.014/0.019
(0.35/0.49)
0.013/0.020
(0.330/0.508)
0.013/0.020
(0.330/0.508)
D
0.189/0.197
(4.80/5.00)
0.337/0.344
0.386/0.394
(8.552/8.748) (9.802/10.000)
E
0.150/0.157
(3.802/3.988)
0.150/0.157
(3.802/3.988)
0.150/0.157
(3.802/3.988)
e
0.050 BSC
(1.270 BSC)
0.050 BSC
(1.270 BSC)
0.050 BSC
(1.270 BSC)
H
0.228/0.244
(5.801/6.198)
0.228/0.244
(5.801/6.198)
0.228/0.244
(5.801/6.198)
h
0.010/0.020
(0.254/0.498)
0.010/0.020
(0.254/0.498)
0.010/0.020
(0.254/0.498)
L
0.016/0.050
(0.406/1.270)
0.016/0.050
(0.406/1.270)
0.016/0.050
(0.406/1.270)
Ø
0°/8°
(0°/8°)
0°/8°
(0°/8°)
0°/8°
(0°/8°)
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
18
© 2006 Sipex Corporation
ORDERING INFORMATION
Model
Temperature Range
Package Types
SP690TCN......................................................0°C to +70°C......................................................8-Pin NSOIC
SP690TCP......................................................0°C to +70°C.........................................................8-Pin PDIP
SP690TEN.....................................................-40°C to +85°C....................................................8-Pin NSOIC
SP690TEP.....................................................-40°C to +85°C.......................................................8-Pin PDIP
SP690SCN......................................................0°C to +70°C......................................................8-Pin NSOIC
SP690SCP......................................................0°C to +70°C.........................................................8-Pin PDIP
SP690SEN.....................................................-40°C to +85°C....................................................8-Pin NSOIC
SP690SEP.....................................................-40°C to +85°C.......................................................8-Pin PDIP
SP690RCN......................................................0°C to +70°C......................................................8-Pin NSOIC
SP690RCP......................................................0°C to +70°C.........................................................8-Pin PDIP
SP690REN.....................................................-40°C to +85°C....................................................8-Pin NSOIC
SP690REP.....................................................-40°C to +85°C.......................................................8-Pin PDIP
SP802TCN........................................................0°C to +70°C....................................................8-Pin NSOIC
SP802TCP........................................................0°C to +70°C.......................................................8-Pin PDIP
SP802TEN.......................................................-40°C to +85°C..................................................8-Pin NSOIC
SP802TEP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
SP802SCN........................................................0°C to +70°C....................................................8-Pin NSOIC
SP802SCP........................................................0°C to +70°C.......................................................8-Pin PDIP
SP802SEN.......................................................-40°C to +85......................................................8-Pin NSOIC
SP802SEP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
SP802RCN........................................................0°C to 0°C........................................................8-Pin NSOIC
SP802RCP........................................................0°C to+70°C...................................................... 8-Pin PDIP
SP802REN.......................................................-40°C to +85°C..................................................8-Pin NSOIC
SP802REP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
SP804TCN.......................................................0°C to +70°C.....................................................8-Pin NSOIC
SP804TCP.......................................................0°C to +70°C........................................................8-Pin PDIP
SP804TEN......................................................-40°C to +85°C...................................................8-Pin NSOIC
SP804TEP......................................................-40°C to +85°C......................................................8-Pin PDIP
SP804SCN.......................................................0°C to +70°C.....................................................8-Pin NSOIC
SP804SCP.......................................................0°C to +70°C........................................................8-Pin PDIP
SP804SEN......................................................-40°C to +85°C...................................................8-Pin NSOIC
SP804SEP......................................................-40°C to +85°C......................................................8-Pin PDIP
SP804RCN.......................................................0°C to +70°C.....................................................8-Pin NSOIC
SP804RCP.......................................................0°C to +70°C........................................................8-Pin PDIP
SP804REN......................................................-40°C to +85°C...................................................8-Pin NSOIC
SP804REP......................................................-40°C to +85°C......................................................8-Pin PDIP
SP805TCN........................................................0°C to +70°C....................................................8-Pin NSOIC
SP805TCP........................................................0°C to +70°C.......................................................8-Pin PDIP
SP805TEN.......................................................-40°C to +8C.................................................. ..8-Pin NSOIC
SP805TEP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
SP805SCN........................................................0°C to+70°C.....................................................8-Pin NSOIC
SP805SCP........................................................0°C to +70°C.......................................................8-Pin PDIP
SP805SEN.......................................................-40°C to +85°C..................................................8-Pin NSOIC
SP805SEP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
SP805RCN........................................................0°C to +70°C....................................................8-Pin NSOIC
SP805RCP........................................................0°C to +70°C.......................................................8-Pin PDIP
SP805REN.......................................................-40°C to +85°C..................................................8-Pin NSOIC
SP805REP.......................................................-40°C to +85°C.....................................................8-Pin PDIP
Please consult the factory for pricing and availability on a Tape-On-Reel option.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
19
© 2006 Sipex Corporation
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation
Headquarters and
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
SP690T/S/R JAN 30-06
SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory
20
© 2006 Sipex Corporation
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