74AUP2G0604GM,125

74AUP2G0604 Low-power inverting buffer with open-drain and inverter Rev. 1 — 23 November 2012 Product data sheet 1. General description The 74AUP2G0604 is a single inverting buffer with open-drain output and a single inverter. It features two input pins (nA), an output pin (2Y) and an open-drain output pin (1Y). Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits  Wide supply voltage range from 0.8 V to 3.6 V  High noise immunity  Complies with JEDEC standards:  JESD8-12 (0.8 V to 1.3 V)  JESD8-11 (0.9 V to 1.65 V)  JESD8-7 (1.2 V to 1.95 V)  JESD8-5 (1.8 V to 2.7 V)  JESD8-B (2.7 V to 3.6 V)  ESD protection:  HBM JESD22-A114F Class 3A exceeds 5000 V  MM JESD22-A115-A exceeds 200 V  CDM JESD22-C101E exceeds 1000 V  Low static power consumption; ICC = 0.9 A (maximum)  Latch-up performance exceeds 100 mA per JESD 78 Class II  Inputs accept voltages up to 3.6 V  Low noise overshoot and undershoot < 10 % of VCC  IOFF circuitry provides partial power-down mode operation  Multiple package options  Specified from 40 C to +85 C and 40 C to +125 C 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G0604GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP2G0604GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.5 mm SOT886 74AUP2G0604GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1  0.5 mm SOT891 74AUP2G0604GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9  1.0  0.35 mm 74AUP2G0604GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0  1.0  0.35 mm 4. Marking Table 2. Marking Type number Marking code[1] 74AUP2G0604GW a6 74AUP2G0604GM a6 74AUP2G0604GF a6 74AUP2G0604GN a6 74AUP2G0604GS a6 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram $   $ < $ < Logic symbol 74AUP2G0604 Product data sheet  < < $  $     *1' < $ DDD Fig 1.  Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 < DDD DDD Fig 3. Logic diagram © NXP B.V. 2012. All rights reserved. 2 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 6. Pinning information 6.1 Pinning $83* $83* $83* $   < *1'   9&& $    < *1'   9&& $   <  < Fig 5. Pin configuration SOT886  < *1'   9&& $   < 7UDQVSDUHQWWRSYLHZ 7UDQVSDUHQWWRSYLHZ Pin configuration SOT363  DDD DDD DDD Fig 4. $ $ Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 7. Functional description Table 4. Function table[1] Input Output 1A 1Y L Z H L [1] H = HIGH voltage level; L = LOW voltage level. Table 5. Function table[1] Input Output 2A 2Y L H H L [1] H = HIGH voltage level; L = LOW voltage level. 74AUP2G0604 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 3 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions Min Max Unit 0.5 +4.6 V 50 - mA 0.5 +4.6 V 50 - mA 0.5 +4.6 V 1Y - 20 mA 2Y - 20 mA VI < 0 V [1] VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC [1] ICC supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot Tamb = 40 C to +125 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Min Max Unit VCC supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V Tamb ambient temperature 40 +125 C t/V input transition rise and fall rate 0 200 ns/V 74AUP2G0604 Product data sheet Conditions VCC = 0.8 V to 3.6 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 4 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V VCC = 0.9 V to 1.95 V Typ Max Unit 0.70  VCC - - V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.75  VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.11 - V Tamb = 25 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 2Y; VI = VIH or VIL - IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V 1Y, 2Y; VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF 74AUP2G0604 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 5 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions CO VO = GND; VCC = 0 V output capacitance 1Y output; enabled Min Typ Max Unit - 1.7 - pF 1Y output; disabled - 1.1 - pF 2Y output - 1.7 - pF Tamb = 40 C to +85 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 0.8 V 0.70  VCC - - V VCC = 0.9 V to 1.95 V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.35  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V 2Y; VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7  VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3  VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V 1Y, 2Y; VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.5 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.6 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A 74AUP2G0604 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 6 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.75  VCC - - V VCC = 0.9 V to 1.95 V 0.70  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25  VCC V VCC = 0.9 V to 1.95 V - - 0.30  VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = 40 C to +125 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 2Y; VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V VCC  0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6  VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33  VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V 1Y, 2Y; VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A 74AUP2G0604 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 7 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 14.4 - - - - ns Max Max (85 C) (125 C) CL = 5 pF tpd propagation 1A to 1Y or 2A to 2Y; see Figure 7 delay VCC = 0.8 V [2] VCC = 1.1 V to 1.3 V 2.3 4.7 10.3 2.0 11.4 12.6 ns VCC = 1.4 V to 1.6 V 1.8 3.4 6.4 1.5 7.4 8.2 ns VCC = 1.65 V to 1.95 V 1.5 2.9 5.0 1.2 5.9 6.5 ns VCC = 2.3 V to 2.7 V 1.2 2.3 3.9 1.0 4.5 5.0 ns VCC = 3.0 V to 3.6 V 1.1 2.2 3.3 0.8 3.9 4.3 ns - 17.7 - - - - ns CL = 10 pF tpd propagation 1A to 1Y or 2A to 2Y; see Figure 7 delay VCC = 0.8 V [2] VCC = 1.1 V to 1.3 V 2.7 5.7 12.2 2.5 13.7 15.1 ns VCC = 1.4 V to 1.6 V 2.2 4.1 7.5 2.0 8.7 9.6 ns VCC = 1.65 V to 1.95 V 1.9 3.6 5.9 1.7 7.0 7.7 ns VCC = 2.3 V to 2.7 V 1.7 2.9 4.6 1.4 5.4 6.0 ns VCC = 3.0 V to 3.6 V 1.6 3.0 4.6 1.2 4.9 5.4 ns - 21.1 - - - - ns CL = 15 pF tpd propagation 1A to 1Y or 2A to 2Y; see Figure 7 delay VCC = 0.8 V [2] VCC = 1.1 V to 1.3 V 3.2 6.6 13.0 2.9 15.8 17.4 ns VCC = 1.4 V to 1.6 V 2.6 4.7 8.6 2.3 10.0 11.0 ns VCC = 1.65 V to 1.95 V 2.3 4.3 6.7 2.1 8.0 8.8 ns VCC = 2.3 V to 2.7 V 2.1 3.4 5.1 1.7 6.1 6.8 ns VCC = 3.0 V to 3.6 V 2.0 3.6 6.0 1.5 6.5 7.2 ns - 30.7 - - - - ns CL = 30 pF tpd propagation 1A to 1Y or 2A to 2Y; see Figure 7 delay VCC = 0.8 V 74AUP2G0604 Product data sheet [2] VCC = 1.1 V to 1.3 V 4.4 9.1 16.5 3.9 19.3 21.3 ns VCC = 1.4 V to 1.6 V 3.6 6.6 10.8 3.2 12.9 14.2 ns VCC = 1.65 V to 1.95 V 3.2 6.1 10.7 2.9 11.0 12.1 ns VCC = 2.3 V to 2.7 V 2.9 4.9 7.2 2.6 7.8 8.6 ns VCC = 3.0 V to 3.6 V 2.9 5.4 10.5 2.5 10.8 11.9 ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 8 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 0.5 - - - - pF - 0.6 - - - - pF Max Max (85 C) (125 C) CL = 5 pF, 10 pF, 15 pF and 30 pF power 1A to 1Y; fi=1 MHz; VI = GND to VCC dissipation VCC = 0.8 V capacitance VCC = 1.1 V to 1.3 V CPD [3][4] VCC = 1.4 V to 1.6 V - 0.7 - - - - pF VCC = 1.65 V to 1.95 V - 0.7 - - - - pF VCC = 2.3 V to 2.7 V - 1.0 - - - - pF - 1.2 - - - - pF VCC = 0.8 V - 2.5 - - - - pF VCC = 1.1 V to 1.3 V - 2.7 - - - - pF VCC = 1.4 V to 1.6 V - 2.8 - - - - pF VCC = 1.65 V to 1.95 V - 3.0 - - - - pF VCC = 2.3 V to 2.7 V - 3.5 - - - - pF VCC = 3.0 V to 3.6 V - 4.0 - - - - pF VCC = 3.0 V to 3.6 V 2A to 2Y; fi=1 MHz; VI = GND to VCC [1] [3][5] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL(2A to 2Y) and tPLZ and tPZL(1A to 1Y). [3] All specified values are the average typical values over all stated loads. [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N where: fi = input frequency in MHz; CL = load capacitance in pF; N = number of inputs switching; [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of the outputs. 74AUP2G0604 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 23 November 2012 © NXP B.V. 2012. All rights reserved. 9 of 20 74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 12. Waveforms 9, 9, $LQSXW 90 $LQSXW 90 90 *1' *1' W3+/ W3=/ W3/= 9&& W3/+ 92+