CD74ACT08M96

CD54ACT08, CD74ACT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002 D D D D D D D CD54ACT08 . . . F PACKAGE CD74ACT08 . . . E OR M PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays Buffered Inputs ±24-mA Output Drive Current – Fanout to 15 F Devices SCR-Latchup-Resistant CMOS Process and Circuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 1A 1B 1Y 2A 2B 2Y GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y description The ’ACT08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function Y + A • B or Y + A ) B in positive logic. ORDERING INFORMATION PDIP – E –55°C 55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SOIC – M Tube CD74ACT08E Tube CD74ACT08M Tape and reel CD74ACT08M96 TOP-SIDE MARKING CD74ACT08E ACT08M CDIP – F Tube CD54ACT08F3A CD54ACT08F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each gate) INPUTS A B OUTPUT Y H H H L X L X L L logic diagram, each gate (positive logic) A Y B Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CD54ACT08, CD74ACT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) TA = 25°C –40°C TO 85°C –55°C TO 125°C MIN MAX MIN MAX MIN MAX 4.5 5.5 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current –24 IOL ∆t/∆v Low-level output current Input transition rise or fall rate High-level input voltage 2 2 0.8 UNIT 2 V 0.8 V VCC VCC V –24 –24 mA 24 24 24 mA 10 10 10 ns/V VCC VCC 0.8 V 0 0 VCC VCC 0 0 V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS VI = VIH or VIL VOL VI = VIH or VIL II ICC VI = VCC or GND VI = VCC or GND, ∆ICC Ci VI = VCC – 2.1 V VCC TA = 25°C –40°C TO 85°C –55°C TO 125°C MIN MIN MIN MAX MAX UNIT MAX IOH = –50 µA IOH = –24 mA IOH = –50 mA‡ 4.5 V 4.4 4.4 4.5 V 3.94 3.8 IOH = –75 mA‡ IOL = 50 µA 5.5 V 4.5 V 0.1 0.1 0.1 IOL = 24 mA IOL = 50 mA‡ IOL = 75 mA‡ 4.5 V 0.36 0.44 0.5 4.4 3.7 5.5 V 3.85 5.5 V 1.65 5.5 V 5.5 V IO = 0 5.5 V 4.5 V to 5.5 V V 3.85 V 1.65 ±0.1 ±1 ±1 µA 4 40 80 µA 2.4 2.8 3 mA 10 10 10 pF ‡ Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CD54ACT08, CD74ACT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002 ACT INPUT LOAD TABLE INPUT UNIT LOAD A or B 0.3 Unit load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). switching characteristics over recommended operating free-air VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) A or B Y temperature –40°C TO 85°C –55°C TO 125°C MIN MAX MIN MAX 3.3 11.7 3.2 12.9 3.3 11.7 3.2 12.9 range, UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TYP Power dissipation capacitance 50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF 3 CD54ACT08, CD74ACT08 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCHS312B – JANUARY 2001 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.5 V 10% 90% 90% tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.5 V 10% 0 V tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3V Input 1.5 V 1.5 V 0V tPLH In-Phase Output 50% 10% 90% 90% tr 90% 1.5 V 1.5 V 0V tPHL tPHL Out-of-Phase Output 3V Output Control VOH 50% VCC 10% VOL tf tPLH 50% VCC 10% tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES Output Waveform 1 S1 at 2 × VCC (see Note B) tPLZ tPZL 20% VCC tPHZ tPZH Output Waveform 2 S1 at GND (see Note B) ≈VCC 20% VCC VOL 80% VCC VOH 80% VCC ≈0 V VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CD54ACT08F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54ACT08F3A CD74ACT08E ACTIVE PDIP N 14 25 Green (RoHS & no Sb/Br) NIPDAU N / A for Pkg Type -55 to 125 CD74ACT08E CD74ACT08M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 ACT08M CD74ACT08M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 ACT08M CD74ACT08ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 ACT08M CD74ACT08MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) NIPDAU Level-1-260C-UNLIM -55 to 125 ACT08M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of