MCDP6150C1

Datasheet Brief MCDP6150 DisplayPort 1.4a Link Training Tunable PHY Retimer Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kinetic Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change the circuitry and specifications without notice at any time. June 2021 – Revision 03g Page 1 of 5 Company Confidential Datasheet Brief MCDP6150 Features • DisplayPort 1.4a Link Training Tunable PHY Retimer (LTTPR) to support − • • 2kV HBM, ±500V CDM Package − 46 Ex-VQFN (6.5 mm x 4.5 mm) 1.8 V for I/O, 1.2 V for Core DP1.4a Compliant Retimer − Data rate 1.62 Gbps / 2.7 Gbps / 5.4 Gbps / 8.1 Gbps − Transparent mode with proprietary link training architecture − Non-transparent mode support as specified in DP1.4a standard − AUX_CH transaction snooping − DP1.4a Compliant Retimer DPCD registers − 8b/10b coding − Pattern generator and Error Checker − Down-spreading of link clock − Error detection − Adjustable TXEQ during the link training through AUX_CH − Adaptive equalizer with CTLE and DFE − DFE + CTLE for HBR3 to compensate 27dB insertion loss @4.05GHz − CTLE for HBR2 / HBR / RBR − Support of custom PHY configuration through TWI • Real time Eye Opening Monitor (EOM) • TWI (Two Wire Interface) slave to configure the integrated lane mapping and operation mode • ESD Specification − Power Supply Voltages − • 4/2/1-Lane DP1.4a (RBR/HBR/HBR2/HBR3) • − Compatible with I2C master − Support up to 4 unique TWI device ID Applications Low Power Operation − 460 mW for 4-lane HBR3 in typical condition − < 10mW in D3 mode − < 1mW in low power mode June 2021 – Revision 03g Page 2 of 5 • Desktop PC / Notebook / Tablet • Active cable • Virtual Reality / Augmented Reality head mount display • DP1.4a monitor (8K monitor / Gaming monitor) • Video card / converter • Video router / switch • 4K / 8K UHD camera • Video conferencing • Digital signage • Interactive display Company Confidential Datasheet Brief MCDP6150 MCDP6150 System Block Diagram in DPTX device I2C DIS_N DP source AUX_CH MCDP6150 ML x 4 DisplayPort Receptacle Figure 1. ML x 4 AUX_CH HPD Figure 2. MCDP6150 System Block Diagram in DPRX device I2C AUX_CH ML x 4 DP sink ML x 4 MCDP6150 DisplayPort Receptacle DIS_N AUX_CH HPD DP_PWR Embedded controller I2C Embedded controller DIS_N I2C ML x 4 DIS_N ML x 4 Cable AUX_CH AUX_CH DP_PWR PMIC ML x 4 MCDP6150 AUX_CH ML x 4 MCDP6150 DisplayPort Plug PMIC MCDP6150 System Block Diagram in DP active cable AUX_CH DisplayPort Plug Figure 3. HPD June 2021 – Revision 03g Page 3 of 5 Company Confidential Datasheet Brief MCDP6150 1. Description The MCDP6150 is a low power DisplayPort1.4a retimer targeted for high-end audio video applications. The MCDP6150 supports 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, and 8.1 Gbps data rates. The following use cases are supported. Table 1. DP1.4a Repeater Mode Mode AUX_CH Function Non-transparent mode Sample, Manipulate, and Forward to snoop or respond as defined in DP1.4a standard. Transparent mode Sample and Forward to snoop LT tunable PHY Repeater The DP1.4a repeater implements AUX_CH snooping function of DPCD addresses defined in the standard as well as the LT-tunable PHY Repeater DPCD registers. The DP1.4a repeater can support up to a 0.5% downspread link rate. The transmitter employs TXEQ, which adjusts its pre-emphasis level according to either the AUX_CH transaction during the link training or the Two Wire Interface (TWI). The receiver employs a fully adaptive Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE). The transmitter parameters to support the amplitude level and the pre-emphasis level defined in DP 1.4a standard are provided in default. The transmitter configuration can be also customized to extend the media length such as PCB trace and the cable. The MCDP6150 operates at two power supplies; 1.8 V and 1.2 V. The power consumption with the two supply voltages is: 1. 460 mW with an active 4 lane retimer (DP 4 lanes HBR3) in typical condition 2. < 10mW in D3 power mode The MCDP6150 is offered in a 46-pin, 6.5 mm x 4.5 mm Ex-VQFN package. June 2021 – Revision 03g Page 4 of 5 Company Confidential Datasheet Brief MCDP6150 2. Application Overview The target applications of MCDP6150 are high-end DPTX systems, DPRX systems and a DisplayPort 1.4a active cable. The MCDP6150 resides next to the DisplayPort™ source (CPU/GPU) device (DPTX device) or the DisplayPort sink (scaler, SoC) device (DPRX device). In addition, the MCDP6150 is implemented in the DisplayPort active cable paddle board. High speed serial interface tracks are typical microstrip lines with controlled impedance of 100 ohm. The MCDP6150 communicates with DPTX and/or DPRX devices through either TWI or AUX_CH. When the DisplayPort link is discovered by the DPTX via HPD signal, the link training is initiated by the DPTX device through the AUX_CH. DP source DPTX MCDP6150 MCDP6150 Use Case Active cable paddle board Active cable paddle board MCDP6150 MCDP6150 DPRX MCDP6150 DP sink Figure 4. 3. Ordering Information Part Number Operating Temperature Package MCDP6150C1 0°C to +70°C Ex-VQFN46 June 2021 – Revision 03g Page 5 of 5 Company Confidential