RFG70N06, RFP70N06, RF1S70N06,
RF1S70N06SM
Data Sheet
70A, 60V, 0.014 Ohm, N-Channel Power
MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA78440.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG70N06
TO-247
RFG70N06
RFP70N06
TO-220AB
RFP70N06
RF1S70N06
TO-262AA
F1S70N06
RF1S70N06SM
TO-263AB
F1S70N06
February 2005
Features
• 70A, 60V
• rDS(on) = 0.014Ω
• Temperature Compensated PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve (Single Pulse)
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
NOTE: When ordering use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in tape and reel, e.g. RF1S70N06SM9A.
Packaging
JEDEC STYLE TO-247
JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(BOTTOM
SIDE METAL)
DRAIN
(FLANGE)
GATE
SOURCE
JEDEC TO-262AA
JEDEC TO-220AB
DRAIN
(FLANGE)
©2005 Fairchild Semiconductor Corporation
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
RFG70N06, RFP70N06
RF1S70N06, RF1S70N06SM
60
60
70
Refer to Peak Current Curve
±20
Refer to UIS Curve
150
1.0
-55 to 175
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
A
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
60
-
-
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
VDS = 60V, VGS = 0V
-
-
1
µA
VDS = 0.8 x Rated BVDSS, TC = 150oC
-
-
25
µA
VGS = ±20V
-
-
±100
nA
ID = 70A, VGS = 10V (Figure 9)
-
-
0.014
Ω
VDD = 30V, ID ≈ 70A, RL = 0.43Ω,
VGS = 10V, RGS = 2.5Ω
(Figure 13)
-
-
190
ns
-
10
-
ns
tr
-
137
-
ns
td(OFF)
-
32
-
ns
tf
-
24
-
ns
t(OFF)
-
-
73
ns
-
120
156
nC
-
65
85
nC
-
5.0
6.5
nC
-
2250
-
pF
-
792
-
pF
-
206
-
pF
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance (Note 2)
rDS(ON)
Turn-On Time
t(ON)
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance, Junction to Case
RθJC
Thermal Resistance, Junction to Ambient
RθJA
VDD = 48V, ID = 70A,
RL = 0.68Ω
Ig(REF) = 2.2mA
(Figure 13)
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
-
-
1.0
oC/W
TO-220 and TO-263
-
-
62
oC/W
TO-247
-
-
30
oC/W
MIN
TYP
MAX
UNITS
ISD = 70A
-
1.5
V
ISD = 70A, dISD/dt = 100A/µs
-
52
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
VSD
Reverse Recovery Time
trr
TEST CONDITIONS
NOTES:
2. Pulse test: pulse width ≤300ms, duty cycle ≤2%.
3. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3) and Peak Current
Capability Curve (Figure 5).
©2005 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Typical Performance Curves
TC = 25oC, Unless Otherwise Specified
80
70
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
0.2
60
50
40
30
20
10
0
25
0
0
25
150
50
75
100
125
TC , CASE TEMPERATURE (oC)
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
1
THERMAL IMPEDANCE
Zθ JC, NORMALIZED
0.5
0.2
0.1
PDM
0.1
0.05
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x Zθ JC x Rθ JC + TC
0.02
0.01
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
100µs
100
1ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
10ms
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2005 Fairchild Semiconductor Corporation
100
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
500
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 – T C
I = I25 ----------------------
150
VGS = 10V
100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
50
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
101
FIGURE 5. PEAK CURRENT CAPABILITY
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
IAS, AVALANCHE CURRENT (A)
300
TC = 25oC, Unless Otherwise Specified (Continued)
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R) ln [(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
100
STARTING TJ = 25oC
STARTING TJ = 150oC
200
VGS = 10V
VGS = 20V
ID, DRAIN CURRENT (A)
Typical Performance Curves
VGS = 8V
VGS = 7V
160
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
120
80
VGS = 6V
40
VGS = 5V
VGS = 4.5V
10
0.01
1
0.1
tAV, TIME IN AVALANCHE (ms)
0
10
4
1
2
3
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
5
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
160
2.5
-55oC
25oC
175oC
120
80
40
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
1.5
1
0.5
0
-80
10
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.0
0.5
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2005 Fairchild Semiconductor Corporation
40
80
120
160
200
2.0
1.5
-40
0
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
VGS = VDS, ID = 250µA
0
-80
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
2.0
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 70A
2
0
0
NORMALIZED GATE
THRESHOLD VOLTAGE
FIGURE 7. SATURATION CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Typical Performance Curves
TC = 25oC, Unless Otherwise Specified (Continued)
60
C, CAPACITANCE (pF)
4000
CISS
3000
2000
COSS
1000
CRSS
0
0
10
VDD = BVDSS
VDD = BVDSS
45
7.5
RL = 0.86Ω
IG(REF) = 2.2mA
VGS = 10V
30
5
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
15
2.5
0
0
I
20 G(REF)
IG(ACT)
25
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS, GATE TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
VDS, DRAIN TO SOURCE VOLTAGE (V)
5000
t, TIME (µs)
I
80 G(REF)
IG(ACT)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
VDS
td(OFF)
tr
VDS
tf
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
90%
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
©2005 Fairchild Semiconductor Corporation
10%
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 17. SWITCHING WAVEFORMS
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
©2005 Fairchild Semiconductor Corporation
FIGURE 19. GATE CHARGE WAVEFORM
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM
PSPICE Electrical Model
.SUBCKT RFG70N06 2 1 3 ;
rev 3/20/92
CA 12 8 5.56e-9
CB 15 14 5.30e-9
CIN 6 8 2.63e-9
RLDRAIN
DPLCAP
10
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSCL2
5
51
6
8
RLGATE
GATE
1
9
LDRAIN 2 5 1e-9
LGATE 1 9 3.10e-9
LSOURCE 3 7 1.82e-9
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 4.66e-3
RLDRAIN 2 5 10
RGATE 9 20 1.21
RLGATE 1 9 31
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 3.92e-3
RLSOURCE 3 7 18.2
RVTO 18 19 RVTOMOD 1
18
8
-
LGATE
11
16
EVTO
20 +
ESCL
RDRAIN
+
RGATE
S1A
S1B
S2A
S2B
DBREAK
50
ESG
VTO
+
21
6
DBODY
+
EBREAK 17
18
-
MOS2
MOS1
RIN
CIN
RLSOURCE
8
S1A
12
2
DRAIN
RSCL1
+ 51
EBREAK 11 7 17 18 65.18
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
5
RSOURCE
7
3
SOURCE
LSOURCE
S2A
13
8
S1B
RBREAK
15
14
13
17
18
S2B
13
CA
RVTO
CB
+
6
8
EGS
-
EDS
-
IT
14
+
19
VBAT
+
5
8
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.605
.MODEL DBDMOD D (IS = 7.91e-12 RS = 3.87e-3 TRS1 = 2.71e-3 TRS2 = 2.50e-7 CJO = 4.84e-9 TT = 4.51e-8)
.MODEL DBKMOD D (RS = 3.9e-2 TRS1 =1.05e-4 TRS2 = 3.11e-5)
.MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.46 KP = 47 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 8.46e-4 TC2 = -8.48e-7)
.MODEL RDSMOD RES (TC1 = 2.23e-3 TC2 = 6.56e-6)
.MODEL RVTOMOD RES (TC1 = -3.29e-3 TC2 = 3.49e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -8.35 VOFF= -6.35)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.35 VOFF= -8.35)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 3.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2005 Fairchild Semiconductor Corporation
RFG70N06, RFP70N06, RF1S70N06, RF1S70N06SM Rev. D
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As used herein:
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1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I15
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