RFP50N06

RFP50N06 September 2013 Data Sheet Features N-Channel Power MOSFET 60V, 50A, 22 mΩ • 50A, 60V These N-Channel power MOSFETs are manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. These transistors can be operated directly from integrated circuits. • rDS(ON) = 0.022Ω • Temperature Compensating PSPICE® Model • Peak Current vs Pulse Width Curve • UIS Rating Curve • 175oC Operating Temperature Symbol Formerly developmental type TA49018. D Ordering Information PART NUMBER RFP50N06 PACKAGE TO-220AB BRAND G RFP50N06 S Packaging JEDEC TO-220AB DRAIN (FLANGE) ©2002 Fairchild Semiconductor Corporation SOURCE DRAIN GATE RFP50N06 Rev. C0 RFP50N06 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP50N06 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg UNITS V V V A 60 60 ±20 50 (Figure 5) (Figure 6) 131 0.877 -55 to 175 W W/oC oC oC oC 300 260 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS ID = 250µA, VGS = 0V (Figure 11) TEST CONDITIONS 60 - - V Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V - - 1 µA TC = 25oC TC = 150oC Zero Gate Voltage Drain Current IDSS VDS = 60V, VGS = 0V - - 50 µA Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA ID = 50A, VGS = 10V (Figures 9) - - 0.022 Ω VDD = 30V, ID = 50A RL = 0.6Ω, VGS = 10V RGS = 3.6Ω (Figure 13) - - 95 ns - 12 - ns - 55 - ns td(OFF) - 37 - ns tf - 13 - ns Drain to Source On Resistance rDS(ON) Turn-On Time tON Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time Fall Time Turn-Off Time tOFF Total Gate Charge Qg(TOT) VGS = 0 to 20V Gate Charge at 10V Qg(10) VGS = 0 to 10V Threshold Gate Charge Qg(TH) VGS = 0 to 2V Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDD = 48V, ID = 50A, RL = 0.96Ω Ig(REF) = 1.45mA (Figure 13) VDS = 25V, VGS = 0V f = 1MHz (Figure 12) - - 75 ns - 125 150 nC - 67 80 nC - 3.7 4.5 nC - 2020 - pF - 600 - pF - 200 - pF Thermal Resistance Junction to Case RθJC (Figure 3) - - 1.14 oC/W Thermal Resistance Junction to Ambient RθJA TO-220 - - 62 oC/W - - - - - Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage Reverse Recovery Time ©2002 Fairchild Semiconductor Corporation MIN TYP MAX UNITS ISD = 50A - - 1.5 V ISD = 50A, dISD/dt = 100A/µs - - 125 ns SYMBOL VSD trr TEST CONDITIONS RFP50N06 Rev. C0 RFP50N06 Unless Otherwise Specified 1.2 60 1.0 50 ID , DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER Typical Performance Curves 0.8 0.6 0.4 0.2 40 30 20 10 0 0 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 25 175 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 THERMAL IMPEDANCE ZθJC, NORMALIZED 1 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 0.01 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 0.01 -5 10 10-4 10-3 10-2 10-1 t1 , RECTANGULAR PULSE DURATION (s) 101 100 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 100µs 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms VDSS(MAX) = 60V 1 103 TJ = MAX RATED SINGLE PULSE TC = 25oC 1 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT CAPABILITY AS FOLLOWS: VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 100  175 – T C I = I 25  ------------------------ 150   VGS = 20V VGS = 10V TC = 25oC 102 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 100ms DC 10 ©2002 Fairchild Semiconductor Corporation IDM , PEAK CURRENT (A) ID , DRAIN CURRENT (A) 400 40 10-3 10-2 10-1 100 101 102 t, PULSE WIDTH (ms) 103 104 FIGURE 5. PEAK CURRENT CAPABILITY RFP50N06 Rev. C0 RFP50N06 Typical Performance Curves Unless Otherwise Specified (Continued) 300 125 100 ID , DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) VGS = 10V STARTING TJ = 25oC STARTING TJ = 150oC 10 If R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) VGS = 7V 75 50 0.1 1 VGS = 6V VGS = 5V 25 If R ≠ 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 1 0.01 VGS = 8V 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 4V 0 0 10 1.5 tAV, TIME IN AVALANCHE (ms) 3.0 4.5 6.0 7.5 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes 9321 and 9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDD = 15V 100 -55oC 2.5 25oC NORMALIZED DRAIN TO SOURCE ON RESISTANCE ID, DRAIN CURRENT (A) 125 FIGURE 7. SATURATION CHARACTERISTICS 175oC 75 50 25 0 0 1 2 3 4 5 6 7 8 9 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 50A 1.5 1.0 0.5 0 -80 10 -40 FIGURE 8. TRANSFER CHARACTERISTICS 80 120 160 200 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 40 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 1.5 1.0 0.5 0 -80 0 TJ , JUNCTION TEMPERATURE (oC) VGS , GATE TO SOURCE VOLTAGE (V) -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE ©2002 Fairchild Semiconductor Corporation ID = 250µA 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE RFP50N06 Rev. C0 RFP50N06 (Continued) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS = CDS + CGD 3000 VDS , DRAIN TO SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 10 60 4000 CISS 2000 COSS 1000 CRSS 0 0 5 10 15 20 VDD = BVDSS VDD = BVDSS 7.5 45 5.0 30 0.75 BVDSS 0.75 BVDSS 0.50 BVDSS 0.50 BVDSS 0.25 BVDSS 0.25 BVDSS RL = 1.2Ω Ig(REF) = 1.45mA VGS = 10V 15 2.5 VGS , GATE TO SOURCE VOLTAGE (V) Typical Performance Curves Unless Otherwise Specified 0 0 25 20 VDS , DRAIN TO SOURCE VOLTAGE (V) Ig(REF) t, TIME (µs) Ig(ACT) 80 Ig(REF) Ig(ACT) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tf tr VDS 90% 90% RL VGS + DUT RGS VGS - VDD ©2002 Fairchild Semiconductor Corporation 10% 90% VGS 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT 10% 0 10% 50% 50% PULSE WIDTH FIGURE 17. SWITCHING WAVEFORMS RFP50N06 Rev. C0 RFP50N06 Test Circuits and Waveforms (Continued) VDS VDD RL Qg(TOT) VDS VGS = 20V VGS Qg(10) + VDD DUT Ig(REF) VGS = 10V VGS - VGS = 2V 0 Qg(TH) Ig(REF) 0 FIGURE 18. GATE CHARGE TEST CIRCUIT ©2002 Fairchild Semiconductor Corporation FIGURE 19. GATE CHARGE WAVEFORMS RFP50N06 Rev. C0 RFP50N06 PSPICE Electrical Model .SUBCKT RFP50N06 2 1 3 REV 2/22/93 *NOM TEMP = 25oC CA 12 8 3.68e-9 CB 15 14 3.625e-9 CIN 6 8 1.98e-9 DRAIN 2 LDRAIN 5 DBODY 7 5 DBDMOD DBREAK 5 11DBKMOD DPLCAP 10 5 DPLCAPMOD DPLCAP + DBREAK EVTO GATE 9 1 LGATE 20 RGATE 18 8 - RDRAIN 6 8 VTO 16 + ESG + EBREAK 11 7 17 18 64.59 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 10 6 MOS1 RIN 8 12 LDRAIN 2 5 1e-9 LGATE 1 9 5.65e-9 LSOURCE 3 7 4.13e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 5 16 RDSMOD 1e-4 RGATE 9 20 0.690 RIN 6 8 1e9 RSOURCE 8 7 RDSMOD 12e-3 RVTO 18 19 RVTOMOD 1 13 8 S1B + EGS 6 - 8 17 EBREAK 18 RSOURCE + 7 LSOURCE S2A 14 13 15 17 RBREAK S2B 13 CA 11 CIN IT 8 17 1 S1A DBODY MOS2 21 3 SOURCE 18 RVTO CB 14 + 5 EDS 8 - IT 19 - VBAT + S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.678 .MODEL DBDMOD D (IS=9.85e-13 RS=4.91e-3 TRS1=2.07e-3 TRS2=2.51e-7 CJO=2.05e-9 TT=4.33e-8) .MODEL DBKMOD D (RS=1.98e-1 TRS1=2.35E-4 TRS2=-3.83e-6) .MODEL DPLCAPMOD D (CJO=1.42e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=3.65 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.23e-3 TC2=-2.34e-7) .MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.49e-5) .MODEL RVTOMOD RES (TC1=-5.03e-3 TC2=-5.16e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.75 VOFF=-2.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-6.75) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.7 VOFF=2.3) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.3 VOFF=-2.7) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; authors, William J. Hepp and C. Frank Wheatley. ©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0 RFP50N06 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. Sync-Lock™ F-PFS™ AccuPower™ ® FRFET® AX-CAP®* ®* ® SM BitSiC™ Global Power Resource PowerTrench GreenBridge™ PowerXS™ Build it Now™ TinyBoost® Green FPS™ Programmable Active Droop™ CorePLUS™ TinyBuck® ® Green FPS™ e-Series™ QFET CorePOWER™ TinyCalc™ QS™ Gmax™ CROSSVOLT™ TinyLogic® GTO™ Quiet Series™ CTL™ TINYOPTO™ IntelliMAX™ RapidConfigure™ Current Transfer Logic™ TinyPower™ ISOPLANAR™ DEUXPEED® ™ TinyPWM™ Dual Cool™ Marking Small Speakers Sound Louder TinyWire™ EcoSPARK® Saving our world, 1mW/W/kW at a time™ and Better™ TranSiC™ EfficentMax™ SignalWise™ MegaBuck™ TriFault Detect™ ESBC™ SmartMax™ MICROCOUPLER™ TRUECURRENT®* SMART START™ MicroFET™ ® SerDes™ Solutions for Your Success™ MicroPak™ SPM® MicroPak2™ Fairchild® ® STEALTH™ MillerDrive™ Fairchild Semiconductor UHC® SuperFET® MotionMax™ FACT Quiet Series™ ® Ultra FRFET™ ® SuperSOT™-3 mWSaver FACT UniFET™ SuperSOT™-6 OptoHiT™ FAST® ® VCX™ SuperSOT™-8 OPTOLOGIC FastvCore™ ® ® VisualMax™ OPTOPLANAR SupreMOS FETBench™ VoltagePlus™ SyncFET™ FPS™ XS™ tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. 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Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I66 ©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0