TSM3N80CH C5G

TSM3N80 Taiwan Semiconductor N-Channel Power MOSFET 800V, 3A, 4.2Ω FEATURES ● ● ● ● KEY PERFORMANCE PARAMETERS Low RDS(ON) 3.3Ω (Typ.) Low gate charge typical @ 19nC (Typ.) Low Crss typical @ 10.2pF (Typ.) Improved dv/dt capability PARAMETER VALUE UNIT VDS 800 V RDS(on) (max) 4.2 Ω Qg 19 nC ● Power Supply ● Lighting ITO-220 TO-251(IPAK) TO-252(DPAK) mm TO-220 en de d APPLICATION Notes: MSL 3 (Moisture Sensitivity Level) for TO-252 (D-PAK) per J-STD-020 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Drain-Source Voltage Gate-Source Voltage SYMBOL eco PARAMETER TC = 25°C (Note 1) Pulsed Drain Current IPAK/DPAK TC = 100°C (Note 2) ITO-220 TO-220 UNIT VDS 800 V VGS ±30 V 3 ID No tR Continuous Drain Current LIMIT A 1.83 IDM 12 A Single Pulsed Avalanche Energy (Note 3) EAS 48 mJ Single Pulsed Avalanche Current (Note 3) IAS 3 A (Note 3) EAR 9.4 mJ Repetitive Avalanche Energy (Note 4) dV/dt 4.5 V/ns Total Power Dissipation @ TC = 25°C PDTOT Repetitive Avalanche Energy Operating Junction and Storage Temperature Range 94 TJ, TSTG 32 94 - 55 to +150 W °C THERMAL PERFORMANCE PARAMETER SYMBOL LIMIT IPAK/DPAK ITO-220 TO-220 3.9 1.33 Junction to Case Thermal Resistance RӨJc 1.33 Junction to Ambient Thermal Resistance RӨJA 110 62.5 UNIT °C/W °C/W Notes: RӨJA is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined at the solder mounting surface of the drain pins. RӨJA is guaranteed by design while RӨCA is determined by the user’s board design. RӨJA shown below for single device operation on FR-4 PCB in still air Document Number: DS_P0000084 1 Version: F1706 TSM3N80 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (TA = 25°C unless otherwise noted) PARAMETER SYMBOL MIN TYP MAX UNIT VGS = 0V, ID = 250µA BVDSS 800 -- -- V Gate Threshold Voltage VDS = VGS, ID = 250µA VGS(TH) 2 -- 4 V Gate Body Leakage VGS = ±30V, VDS = 0V IGSS -- -- ±100 nA Zero Gate Voltage Drain Current VDS = 800V, VGS = 0V IDSS -- -- 10 μA Drain-Source On-State Resistance VGS = 10V, ID = 1.5A RDS(ON) -- 3.3 4.2 Ω Forward Transfer Conductance VDS = 30V, ID = 1.5A gfs -- 3.7 -- S VDS = 640V, ID = 3A, Dynamic (Note 6) Total Gate Charge d Drain-Source Breakdown Voltage de Static CONDITIONS (Note 5) Qg -- 19 -- Qgs -- 4 -- Qgd -- 7.6 -- Ciss -- 696 -- Coss -- 65 -- Crss -- 10.2 -- Rg -- 3.2 -- td(on) -- 48 -- tr -- 36 -- td(off) -- 106 -- tf -- 41 -- Integral reverse diode IS -- -- 3 A Source Current (Pulse) in the MOSFET ISM -- -- 12 A Diode Forward Voltage IS = 3A, VGS = 0V VSD -- -- 1.5 V Reverse Recovery Time VGS = 0V, IS =3A, trr -- 370 -- ns dIF/dt = 100A/us Qrr -- 1.8 -- μC Gate-Source Charge Gate-Drain Charge en VGS = 10V Input Capacitance VDS = 25V, VGS = 0V, Reverse Transfer Capacitance Gate Resistance Switching f = 1.0MHz mm Output Capacitance F = 1MHz, open drain (Note 7) Turn-On Delay Time Turn-On Rise Time VDD = 400V, RG =25Ω Turn-Off Delay Time Turn-Off Fall Time Source-Drain Diode e co VGS = 10V, ID = 3A, (Note 5) No tR Source Current Reverse Recovery Charge nC pF Ω ns Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature 3. L = 10mH, IAS = 3A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C 4. ISD ≤ 3A, dI/dt ≤ 200A/uS, VDD ≤ BVDSS, Starting TJ = 25ºC o 5. Pulse test: PW ≤ 300µs, duty cycle ≤ 2% 6. For DESIGN AID ONLY, not subject to production testing. 7. Switching time is essentially independent of operating temperature. Document Number: DS_P0000084 2 Version: F1706 TSM3N80 Taiwan Semiconductor ORDERING INFORMATION PACKAGE PACKING TSM3N80CZ C0G PART NO. TO-220 50pcs / Tube TSM3N80CI C0G TSM3N80CH C5G ITO-220 50pcs / Tube TO-251 (IPAK) 75pcs / Tube TSM3N80CP ROG TO-252 (DPAK) 2,500pcs / 13” Reel No tR e co mm en de d Note: 1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC 2. Halogen-free according to IEC 61249-2-21 definition Document Number: DS_P0000084 3 Version: F1706 TSM3N80 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Output Characteristics en de d Transfer Characteristics Gate Charge tR e co mm On-Resistance vs. Drain Current No Source-Drain Diode Forward Voltage On-Resistance vs. Junction Temperature Document Number: DS_P0000084 4 Version: F1706 TSM3N80 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Drain Current vs. Case Temperature en de d BVDSS vs. Junction Temperature Capacitance vs. Drain-Source Voltage No tR e co mm Maximum Safe Operating Area(TO-220, I/D-PAK) Maximum Safe Operating Area(ITO-220) Document Number: DS_P0000084 5 Version: F1706 TSM3N80 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) mm en de d Normalized Thermal Transient Impedance, Junction-to-Ambient (TO-220, I/D-PAK) No tR e co Normalized Thermal Transient Impedance, Junction-to-Ambient (ITO-220) Document Number: DS_P0000084 6 Version: F1706 TSM3N80 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) e co MARKING DIAGRAM mm en de d TO-220 No tR Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000084 7 Version: F1706 TSM3N80 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) = Halogen Free = Year Code = Week Code (01~52) = Factory Code No tR G Y WW F e co MARKING DIAGRAM mm en de d ITO-220 Document Number: DS_P0000084 8 Version: F1706 TSM3N80 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) MARKING DIAGRAM mm en de d TO-251(IPAK) No tR e co Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000084 9 Version: F1706 TSM3N80 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) tR e co mm SUGGESTED PAD LAYOUT (Unit: Millimeters) en de d TO-252(DPAK) No MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000084 F1706 10 Version: TSM3N80 No tR e co mm en de d Taiwan Semiconductor Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_P0000084 F1706 11 Version: