RFD16N05LSM

RFD16N05L, RFD16N05LSM Data Sheet 16A, 50V, 0.047 Ohm, Logic Level, N-Channel Power MOSFETs These are N-Channel logic level power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate biases in the 3V to 5V range, thereby facilitating true on-off power control directly from logic circuit supply voltages. December 2003 Features • 16A, 50V • rDS(ON) = 0.047Ω • UIS SOA Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drives • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Formerly developmental type TA09871. • Majority Carrier Device Ordering Information • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” PART NUMBER PACKAGE BRAND RFD16N05L TO-251AA RFD16N05L RFD16N05LSM TO-252AA RFD16N05LSM Symbol D NOTE: When ordering, include the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e. RFD16N05LSM9A G S Packaging JEDEC TO-251AA JEDEC TO-252AA SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (FLANGE) GATE SOURCE ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFD16N05L, RFD16N05LSM UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 50 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 16 45 A A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 0.48 W W/oC Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250mA, VGS = 0V, Figure 10 50 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250mA, Figure 9 1 - 2 V VDS = 40V, VGS = 0V - - 1 µA - - 50 µA VGS = ±10V, VDS = 0V - - 100 nA ID = 16A, VGS = 5V - - 0.047 Ω ID = 16A, VGS = 4V - - 0.056 Ω VDD = 25V, ID = 8A, VGS = 5V, RGS = 12.5Ω Figures 15, 16 - - 60 ns - 14 - ns tr - 30 - ns td(OFF) - 42 - ns tf - 14 - ns t(OFF) - - 100 ns - - 80 nC - - 45 nC - - 3 nC Zero Gate Voltage Drain Current IDSS TC = 150oC Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time t(ON) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Qg(TOT) VGS = 0V to 10V Gate Charge at 5V Qg(5) VGS = 0V to 5V Qg(TH) VGS = 0V to 1V Threshold Gate Charge VDD = 40V, ID = 16A, RL = 2.5Ω Figures 17, 18 Thermal Resistance Junction to Case RθJC - - 2.083 oC/W Thermal Resistance Junction to Ambient RθJA - - 100 oC/W MIN TYP MAX UNITS ISD = 16A - - 1.5 V ISD = 16A, dISD/dt = 100A/µs - - 125 ns Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage VSD Diode Reverse Recovery Time trr TEST CONDITIONS NOTES: 2. Pulse Test: Pulse Width ≤300ms, Duty Cycle ≤2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified 20 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 5 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 150 25 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 102 ID MAX CONTINUOUS 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) DC 1 0.1 102 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 45 VGS = 4V TC = 25oC PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. VGS = 5V 30 VGS = 3V 15 VGS = 2V 0 0 150 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS ©2003 Fairchild Semiconductor Corporation Idm STARTING TJ = 25oC 10 STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3 RATED BVDSS - VDD) If R ≠ 0 tAV = (L/R)ln[(IAS*R)/(1.3 RATED BVDSS - VDD) +1] 1 0.01 0.10 1 tAV, TIME IN AVALANCHE (ms) 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SOA (SINGLE PULSE UIS SOA) 7.5 IDS(ON), DRAIN TO SOURCE ON CURRENT (A) FIGURE 3. FORWARD BIAS SAFE OPERATING AREA VGS = 10V 75 100 125 TC , CASE TEMPERATURE (oC) 102 TC = 25oC TJ = MAX RATED 1 50 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 10 0.2 0 IDS, DRAIN TO SOURCE CURRENT (A) 15 45 VDS = 15V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 30 15 0 0 1.5 3.0 4.5 VGS, GATE TO SOURCE VOLTAGE (V) 6.0 FIGURE 6. TRANSFER CHARACTERISTICS RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Typical Performance Curves Unless Otherwise Specified (Continued) 2.5 ID = 16V VDS = 15V ID = 16A 1.2 1.1 1.0 0.9 0.8 0.7 0.6 2.0 1.5 1.0 0.5 0.5 4 6 5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. 0 -50 7 0 FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 1.4 ID = 250µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE NORMALIZED GATE THRESHOLD VOLTAGE 1.4 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 0 50 100 1.2 1.0 0.8 0.6 0 -50 200 150 TJ, JUNCTION TEMPERATURE (oC) 0 100 50 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 2000 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 0V f = 1MHz C, CAPACITANCE (pF) 1600 CISS 1200 CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 800 COSS 400 CRSS 0 5 10 15 20 25 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ©2003 Fairchild Semiconductor Corporation 200 150 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD vs JUNCTION TEMPERATURE 0 200 150 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE ID = 250µA VGS = VDS 1.3 100 50 TJ, JUNCTION TEMPERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V) 50 37.5 25 10 RL = 3.125Ω, VGS = 5V IG(REF) = 0.60mA PLATEAU VOLTAGES IN DESCENDING ORDER: VDD = BVDSS V = 0.75 BV VDD = BVDSS VDD = 0.50 BVDSS VDD = BVDSS DD DSS VDD = 0.25 BVDSS GATE SOURCE VOLTAGE 8 6 4 12.5 2 DRAIN SOURCE VOLTAGE 0 VGS , GATE TO SOURCE VOLTAGE (V) 1.3 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. NORMALIZED DRAIN TO SOURCE ON RESISTANCE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1.4 0 I G ( REF ) 20 ------------------------I G ( ACT ) t, TIME (µs) I G ( REF ) 80 ------------------------I G ( ACT ) FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + RG - VDD 10% 0 10% DUT 90% VGS VGS 0 FIGURE 15. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH 10% FIGURE 16. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR VDD 12V BATTERY 0.2µF Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 17. GATE CHARGE TEST CIRCUIT ©2003 Fairchild Semiconductor Corporation IG(REF) 0 FIGURE 18. GATE CHARGE WAVEFORMS RFD16N05L, RFD16N05LSM Rev. B1 RFD16N05L, RFD16N05LSM PSPICE Electrical Model .SUBCKT RFD16N05L 2 1 3 ; REV 4/8/92 Ca 12 8 3.33e-9 Cb 15 14 3.11e-9 Cin 6 8 1.21e-9 DPLCAP RSCL1 + 51 5 ESCL 51 50 ESG + 6 8 GATE 9 1 LGATE 20 RGATE VTO + 21 6 - MOS2 CIN 8 Mos1 16 6 8 8 MOSMOD M=0.99 Mos2 16 21 8 8 MOSMOD M=0.01 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD DBODY MOS1 RIN S1A RSOURCE 7 LSOURCE 3 SOURCE S2A 13 8 14 13 S1B RBREAK 15 17 18 S2B 13 RVTO CB CA + 11 17 EBREAK 18 16 EVTO + 18 8 12 DBREAK RDRAIN IT 8 17 1 Rin 6 8 1e9 Rbreak 17 18 RBKMOD 1 Rdrain 5 16 RDSMOD 27.38e-3 Rgate 9 20 2.98 Rsource 8 7 RDSMOD 0.614e-3 Rvto 18 19 RVTOMOD 1 DRAIN 2 LDRAIN RSCL2 Ebreak 11 7 17 18 70.9 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evto 20 6 18 8 1 Lgate 1 9 1.38e-9 Ldrain 2 5 1.0e-12 Lsource 3 7 1.0e-9 5 10 Dbody 7 5 DBDMOD Dbreak 5 11 DBKMOD Dplcap 10 5 DPLCAPMOD + 6 8 EGS + EDS - - 14 5 8 IT 19 VBAT + Vbat 8 19 DC 1 Vto 21 6 0.448 .MODEL DBDMOD D (IS=1.34e-13 RS=1.21e-2 TRS1=1.64e-3 TRS2=2.59e-6 +CJO=1.13e-9 TT=4.14e-8) .MODEL DBKMOD D (RS=8.82e-2 TRS1=-2.01e-3 TRS2=7.32e-10) .MODEL DPLCAPMOD D (CJO=0.522e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=2.054 KP=24.73 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.01e-3 TC2=5.21e-8) .MODEL RDSMOD RES (TC1=3.66e-3 TC2=1.46e-5) .MODEL RVTOMOD RES (TC1=-1.81e-3 TC2=1.41e-6) .MODEL S1AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-4.25 VOFF=-2.25) .MODEL S1BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-2.25 VOFF=-4.25) .MODEL S2AMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=-0.65 VOFF=4.35) .MODEL S2BMOD VSWITCH(RON=1e-5 ROFF=0.1 VON=4.35 VOFF=-0.65) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley. ©2003 Fairchild Semiconductor Corporation RFD16N05L, RFD16N05LSM Rev. B1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOSTM I2C™ TM EnSigna ImpliedDisconnect™ FACT™ ISOPLANAR™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I6