PSMN3R3-40MLHX

PSMN3R3-40MLH N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 11 November 2019 Product data sheet 1. General description 118 A, logic level N-channel enhancement mode MOSFET in 175 °C LFPAK33 package using advanced TrenchMOS Superjunction technology. This product has been designed and qualified for high efficiency applications at high switching frequencies. 2. Features and benefits • • • • • • • Avalanche rated, 100% tested NextPower-S3 technology delivers 'superfast switching with soft body-diode recovery' Low Qrr, QG and QGD for high system efficiency, especially at high switching frequencies Low spiking and ringing for low EMI designs High reliability clip bonded and solder die attach Mini Power SO8 package; no glue, no wire bonds, qualified to 175 °C Exposed leads can be wave soldered, visual solder joint inspection and high quality solder joints Low parasitic inductance and resistance 3. Applications • • • • Secondary side synchronous rectification DC-to-DC converters Brushless DC motor drive LED lighting 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - - 40 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - - 118 A Ptot total power dissipation Tmb = 25 °C; Fig. 1 - - 101 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 2.7 3.3 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 3.4 4.2 mΩ ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 1.2 4 8 nC 11 17 24 nC [1] Static characteristics RDSon drain-source on-state resistance Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge [1] 118A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S source 2 S source 3 S source G 4 G gate mbb076 mb D Mounting base; connected to drain D 1 2 3 S 4 LFPAK33 (SOT1210) 6. Ordering information Table 3. Ordering information Type number Package PSMN3R3-40MLH Name Description Version LFPAK33 Plastic, single ended surface mounted package (LFPAK33); 8 leads; 0.65 mm pitch SOT1210 7. Marking Table 4. Marking codes Type number Marking code PSMN3R3-40MLH 3H3L40 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 175 °C - 40 V VDSM peak drain-source voltage tp ≤ 20 ns; f ≤ 500 kHz; EDS(AL) ≤ 200 nJ; pulsed - 45 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 175 °C; RGS = 20 kΩ - 40 V VGS gate-source voltage -20 20 V Ptot total power dissipation Tmb = 25 °C; Fig. 1 - 101 W ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 2 - 118 A VGS = 10 V; Tmb = 100 °C - 84 A pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 3 - 475 A [1] IDM peak drain current Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 101 A Source-drain diode IS PSMN3R3-40MLH Product data sheet source current Tmb = 25 °C All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 2 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology Symbol Parameter Conditions Min Max Unit ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 475 A - 200 mJ - 80 A Avalanche ruggedness EDS(AL)S non-repetitive drainID = 25 A; Vsup ≤ 40 V; RGS = 50 Ω; source avalanche energy VGS = 10 V; Tj(init) = 25 °C; unclamped; tp = 308 µs IAS non-repetitive avalanche Vsup ≤ 40 V; VGS = 10 V; Tj(init) = 25 °C; current RGS = 50 Ω [1] [2] [2] 118A Continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Protected by 100% test 03aa16 120 aaa-030386 120 ID (A) 100 Pder (%) 80 80 60 40 40 20 0 Fig. 1. 0 50 100 150 Tmb (°C) 0 200 25 50 75 100 125 150 175 Tmb (°C) 200 VGS ≥ 10 V (1) 118A continuous current has been successfully demonstrated during application tests. Practically the current will be limited by PCB, thermal design and operating temperature. Normalized total power dissipation as a function of mounting base temperature Fig. 2. ID (A) 0 Continuous drain current as a function of mounting base temperature aaa-030382 103 Limit RDSon = VDS / ID 102 tp = 10 µs DC 100 µs 10 1 ms 10 ms 100 ms 1 10-1 10-1 1 10 VDS (V) 102 Tmb = 25 °C; IDM is a single pulse Fig. 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 3 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from Fig. 4 junction to mounting base - 1.3 1.48 K/W Rth(j-a) thermal resistance from Fig. 5 junction to ambient Fig. 6 - 50 - K/W - 130 - K/W aaa-028610 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 0.05 0.02 P single shot δ= 10-2 Fig. 4. 10-5 10-4 10-3 10-2 T 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration aaa-028026 aaa-028025 Copper square 25.4 mm square; 70 μm thick on FR4 board Fig. 5. T t tp 10-3 10-6 tp PCB layout for resistance from junction to ambient 70 μm thick copper on FR4 board Fig. 6. PCB layout with minimum footprint for thermal resistance from junction to ambient 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V Static characteristics V(BR)DSS drain-source breakdown voltage PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 4 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology Symbol Parameter Conditions Min Typ Max Unit VGS(th) gate-source threshold voltage ID = 1 mA; VDS=VGS; Tj = 25 °C 1.45 1.77 2.15 V ΔVGS(th)/ΔT gate-source threshold voltage variation with temperature 25 °C ≤ Tj ≤ 150 °C - -4.4 - mV/K IDSS drain leakage current VDS = 32 V; VGS = 0 V; Tj = 25 °C - 0.01 1 µA VDS = 32 V; VGS = 0 V; Tj = 125 °C - 1.6 - µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 2 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 2.7 3.3 mΩ VGS = 10 V; ID = 25 A; Tj = 175 °C; Fig. 11 - - 7.2 mΩ VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 10 - 3.4 4.2 mΩ VGS = 4.5 V; ID = 25 A; Tj = 175 °C; Fig. 11 - - 9.2 mΩ f = 1 MHz; Tj = 25 °C 0.3 0.8 2 Ω ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 11 17 24 nC ID = 25 A; VDS = 20 V; VGS = 10 V; Fig. 12; Fig. 13 24 38 54 nC ID = 0 A; VDS = 0 V - 20 - nC ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 12; Fig. 13 4 6.8 10.2 nC 2.4 4 6 nC RDSon RG drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gatesource charge QGS(th-pl) post-threshold gatesource charge 1.7 2.8 4.2 nC QGD gate-drain charge 1.2 4 8 nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 20 V; Fig. 12; Fig. 13 - 2.8 - V Ciss input capacitance 1761 2710 3794 pF Coss output capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; Fig. 14 407 627 877 pF Crss reverse transfer capacitance 30 101 222 pF td(on) turn-on delay time - 16 - ns tr rise time - 19 - ns td(off) turn-off delay time - 17 - ns tf fall time - 11 - ns Qoss output charge VGS = 0 V; VDS = 20 V; f = 1 MHz - 20 - nC IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 15 - 0.8 1 V VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V; RG(ext) = 5 Ω Source-drain diode VSD source-drain voltage PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 5 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology Symbol Parameter Conditions Min Typ Max Unit trr reverse recovery time - 27 - ns Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V; Fig. 16 - 22 - nC ta reverse recovery rise time - 16 - ns tb reverse recovery fall time - 11 - ns aaa-029075 120 ID (A) 100 aaa-029076 12 RDSon (mΩ) 10 V 9 VGS = 3 V 4.5 V 80 60 6 2.8 V 40 3 2.6 V 20 2.4 V 0 Fig. 7. 0 1 2 3 VDS (V) 0 4 0 5 10 15 VGS (V) 20 Tj = 25 °C Tj = 25 °C; ID = 25 A Output characteristics; drain current as a Fig. 8. function of drain-source voltage; typical values Drain-source on-state resistance as a function of gate-source voltage; typical values aaa-030383 120 aaa-029078 12 ID (A) RDSon (mΩ) 10 2.8 V 3V 90 8 60 3.5 V 6 4.5 V 4 30 175°C 0 0 1 2 25°C 3 2 4 VGS (V) 0 5 VDS = 8 V Fig. 9. Product data sheet 0 20 40 60 80 100 ID (A) 120 Tj = 25 °C Transfer characteristics; drain current as a function of gate-source voltage; typical values PSMN3R3-40MLH VGS = 10 V Fig. 10. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 6 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology a aaa-030384 2.4 VGS (V) aaa-030480 10 2 8 1.6 6 32 V 1.2 20 V 4 0.8 VDS = 8 V 2 0.4 0 -60 -30 0 30 60 90 120 150 Tj (°C) 0 180 0 10 20 30 40 QG (nC) 50 Tj = 25 °C; ID = 25 A Fig. 11. Normalized drain-source on-state resistance factor as a function of junction temperature Fig. 12. Gate-source voltage as a function of gate charge; typical values aaa-030542 104 VDS C (pF) ID Ciss 103 VGS(pl) Coss VGS(th) VGS QGS2 QGS1 QGS Crss 102 QGD QG(tot) 003aaa508 Fig. 13. Gate charge waveform definitions 10 10-1 1 10 VDS (V) 102 VGS = 0 V; f = 1 MHz Fig. 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 7 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology IS (A) 003aal160 aaa-030385 102 ID (A) trr ta tb 0 10 0.25 IRM 175°C 1 0 0.2 0.4 Tj = 25°C 0.6 0.8 1 VSD (V) IRM t (s) 1.2 Fig. 16. Reverse recovery timing definition VGS = 0 V Fig. 15. Source-drain (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 8 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 11. Package outline Plastic single ended surface mounted package (LFPAK33); 8 leads E A e1 A c1 b1 L1 SOT1210 D2 mounting base D1 (D) H E1 L 1 4 b e w A A1 C X c Lp y C detail X 0 2.5 5 mm scale Dimensions Unit(1) mm A A1 b(1) max 0.90 0.10 0.35 nom min 0.80 0.00 0.25 b1(1) c c1 2.4 0.20 0.30 2.2 0.10 0.20 D ref 2.60 D1 D2 2.35 1.90 0.50 E(1) E1 3.40 2.45 3.20 2.00 e e1 0.65 0.65 H L L1 Lp 3.40 0.65 0.25 0.50 3.20 0.45 0.13 0.30 w 0.20 0.10 Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version sot1210_po References IEC JEDEC y JEITA European projection Issue date 14-04-25 16-08-09 SOT1210 Fig. 17. Package outline LFPAK33 (SOT1210) PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 9 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 12. Soldering Footprint information for reflow soldering of LFPAK33 package SOT1210 2.35 2.25 0.635 0.617 0.05 (all around) 0.75 0.62 1.05 1.91 2.47 0.51 3.9 0.51 0.6 0.83 0.4 (x8) solder land occupied area solder paste aperture 0.65 (x6) 0.3 (x8) 0.25 (x6) Notes : 1. Dimensions in mm solder resist sot1210_fr Fig. 18. Reflow soldering footprint for LFPAK33 (SOT1210) PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 10 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology 13. Legal information injury, death or severe property or environmental damage. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 11 / 12 PSMN3R3-40MLH Nexperia N-channel 40 V, 3.3 mΩ, logic level MOSFET in LFPAK33 using NextPower-S3 technology Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Applications.................................................................. 1 4. Quick reference data....................................................1 5. Pinning information......................................................2 6. Ordering information....................................................2 7. Marking.......................................................................... 2 8. Limiting values............................................................. 2 9. Thermal characteristics............................................... 4 10. Characteristics............................................................ 4 11. Package outline.......................................................... 9 12. Soldering................................................................... 10 13. Legal information......................................................11 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 11 November 2019 PSMN3R3-40MLH Product data sheet All information provided in this document is subject to legal disclaimers. 11 November 2019 © Nexperia B.V. 2019. All rights reserved 12 / 12