SN65LBC184DR

UMW SN75LBC184/ SN65LBC184 R  
  
 


 D Integrated Transient Voltage Suppression D ESD Protection for Bus Terminals Exceeds: D D D D D D D D D D D ± 30 kV IEC 61000-4-2, Contact Discharge ± 15 kV IEC 61000-4-2, Air-Gap Discharge ± 15 kV EIA/JEDEC Human Body Model Circuit Damage Protection of 400-W Peak (Typical) Per IEC 61000-4-5 Controlled Driver Output-Voltage Slew Rates Allow Longer Cable Stub Lengths 250-kbps in Electrically Noisy Environments Open-Circuit Fail-Safe Receiver Design 1/4 Unit Load Allows for 128 Devices Connected on Bus Thermal Shutdown Protection Power-Up/-Down Glitch Protection Each Transceiver Meets or Exceeds the Requirements of TIA/EIA-485 (RS-485) and ISO/IEC 8482:1993(E) Standards Low Disabled Supply Current 300 µA Max Pin Compatible With SN75176 Applications: − Industrial Networks − Utility Meters − Motor Control (TOP VIEW) R RE DE D 1 8 2 7 3 6 4 5 VCC B A GND functional logic diagram (positive logic) 3 DE 4 D 2 RE 6 1 R 7 A B Bus description The SN75LBC184 and SN65LBC184 are differential data line transceivers in the trade-standard footprint of the SN75176 with built-in protection against high-energy noise transients. This feature provides a substantial increase in reliability for better immunity to noise transients coupled to the data cable over most existing devices. Use of these circuits provides a reliable low-cost direct-coupled (with no isolation transformer) data line interface without requiring any external components. The SN75LBC184 and SN65LBC184 can withstand overvoltage transients of 400-W peak (typical). The conventional combination wave called out in IEC 61000-4-5 simulates the overvoltage transient and models a unidirectional surge caused by overvoltages from switching and secondary lightning transients. www.umw-ic.com 1 V ± VP ± 1/2 VP 1.2 µs 50 µs t Figure 1. Surge Waveform — Combination Wave 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R description (continued) A biexponential function defined by separate rise and fall times for voltage and current simulates the combination wave. The standard 1.2 µs/50 µs combination waveform is shown in Figure 1 and in the test description in Figure 15. The device also includes additional desirable features for party-line data buses in electrically noisy environment applications including industrial process control. The differential-driver design incorporates slew-rate-controlled outputs sufficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and longer stub lengths from the main backbone than possible with uncontrolled and faster voltage transitions. A unique receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit). The SN75LBC184 and SN65LBC184 receiver also includes a high input resistance equivalent to one-fourth unit load allowing connection of up to 128 similar devices on the bus. The SN75LBC184 is characterized for operation from 0°C to 70°C. The SN65LBC184 is characterized from −40°C to 85°C. schematic of inputs and outputs VCC A Port Only 16 kΩ 12 µA Nominal 72 kΩ A or B I/O 16 kΩ B Port Only 12 µA Nominal www.umw-ic.com 2 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R DRIVER FUNCTION TABLE INPUT ENABLE D DE A B H H H L L H L H X L Z Z OUTPUTS H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) RECEIVER FUNCTION TABLE DIFFERENTIAL INPUTS ENABLE OUTPUT A−B RE R VID ≥ 0.2 V −0.2 V < VID < 0.2 V L H L ? VID ≤ − 0.2 V X L L H Z Open L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) AVAILABLE OPTIONS PACKAGE TA PLASTIC SMALL-OUTLINE† (JEDEC MS-012) PLASTIC DUAL-IN-LINE PACKAGE (JEDEC MS-001) 0°C to 70°C SN75LBC184D SN75LBC184P −40°C to 105°C SN65LBC184D † Add R suffix for taped and reel. SN65LBC184P logic symbol† DE RE D 3 2 EN1 EN2 1 4 1 R 1 6 7 A B 2 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. www.umw-ic.com 3 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R absolute maximum ratings over operating free−air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous voltage range at any bus terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −15 V to 15 V Data input/output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V Receiver output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Electrostatic discharge: Contact discharge (IEC61000-4-2) A, B, GND (see Note 2) . . . . . . . . . . . . . . . 30 kV Air discharge (IEC61000-4-2) A, B, GND (see Note 2) . . . . . . . . . . . . . . . 15 kV Human body model (see Note 3) A, B, GND (see Note 2) . . . . . . . . . . . . . . . 15 kV All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 kV All terminals (Class 3A) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 kV All terminals (Class 3B) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200 V Continuous total power dissipation (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input/output bus voltage, are with respect to network ground terminal. 2. GND and bus terminal ESD protection is beyond readily available test equipment capabilities for IEC 61000-4-2, EIA/JEDEC test method A114-A and MIL-STD-883C method 3015. Ratings listed are limits of test equipment; device performance exceeds these limits. 3. Tested in accordance with JEDEC Standard 22, Test Method A114-A. 4. The driver shuts down at a junction temperature of approximately 160°C. To operate below this temperature, see the Dissipation Rating Table. DISSIPATION RATING TABLE PACKAGE TA ≤ 25 25°C C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 70 70_C C POWER RATING TA = 85 85_C C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW P 1150 mW 9.2 mW/°C 736 mW 598 mW recommended operating conditions Supply voltage, VCC Voltage at any bus terminal (separately or common mode), VI or VIC High-level input voltage, VIH D, DE, and RE Low-level input voltage, VIL D, DE, and RE MIN‡ TYP MAX UNIT 4.75 5 5.25 V 12 V −7 2 0.8 Differential input voltage, |VID| 12 Driver High-level output current, IOH −60 Receiver Operating free-air temperature, TA V V mA −8 Driver Low-level output current, IOL V mA 60 Receiver 4 mA SN75LBC184 0 70 °C SN65LBC184 −40 105 °C ‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet. www.umw-ic.com 4 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R DRIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER ALTERNATE SYMBOLS TEST CONDITIONS MIN DE = RE = 5 V, No Load ICC Supply current NA DE = 0 V, No Load RE = 5 V, IIH IIL High-level input current (D, DE, RE) NA Low-level input current (D, DE, RE) NA VI = 2.4 V VI = 0.4 V −50 VO = −7 V −250 IOS I Short-circuit output current (see Note 5) IOZ High-impedance output current VO Output voltage VOC(PP) Peak-to-peak change in commonmode output voltage during state transitions VOC Common-mode output voltage |∆VOC(SS)| Magnitude of change, commonmode steady-state output voltage |VOD| Magnitude of differential output voltage |VA − VB| ∆|VOD| Change in differential voltage magnitude between logic states NA NA MAX 12 25 mA 175 300 µA 50 µA µA 250 VO = 12 V 250 See Receiver II Voa, Vob 0 IO = 0 See Figures 5 and 6 NA |Vos| See Figure 4 |Vos − Vos| See Figure 5 IO = 0 RL = 54 Ω, o 0.8 1.5 mA V V 3 V 0.1 V 6 V 1.5 V RL = 54 Ω ||Vt| − |Vt|| mA mA VCC 1 See Figure 4 UNIT −120 VO = VCC NA Vo TYP† 0.1 V † All typical values are measured with TA = 25°C and VCC = 5 V. NOTE 5: This parameter is measured with only one output being driven at a time. switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(DH) td(DL) Differential output delay time, low-to-high-level output 1.3 µs Differential-output delay time, high-to-low-level output 1.3 µs tPLH tPHL Propagation delay time, low-to-high-level output 0.5 1.3 µs 0.5 1.3 µs tsk(p) tr Pulse skew (| td(DH) − td(DL) |) 75 150 ns Rise time, single ended 0.25 1.2 µs tf tPZH Fall time, single ended 0.25 1.2 µs Output enable time to high level RL = 110 Ω, See Figure 2 3.5 µs tPZL tPHZ Output enable time to low level RL = 110 Ω, See Figure 3 3.5 µs Output disable time from high level RL = 110 Ω, See Figure 2 2 µs tPLZ Output disable time from low level RL = 110 Ω, See Figure 3 2 µs , L L Ω RL = 54 Ω, CL = 50 pF, See Figure 5 Propagation delay time, high-to-low-level output www.umw-ic.com 5 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R RECEIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER ICC II Supply current (total package) Input current TEST CONDITIONS DE = RE = 0 V, No Load RE = 5 V, No Load DE = 0 V, Other input = 0 V IOZ Vhys High-impedance-state output current VIT + VIT− Positive-going input threshold voltage VI = 12 V VI = 12 V, VI = − 7 V VI = − 7 V, MIN MAX VCC = 0 mA 300 µA 250 −200 VCC = 0 ± 100 70 −200 Figure 7 µA mV 200 Negative-going input threshold voltage µA A −200 VO = 0.4 V to 2.4 V IOH = − 8 mA IOL = 4 mA UNIT 3.9 250 Input hysteresis voltage VOH High-level output voltage VOL Low-level output voltage † All typical values are at VCC = 5 V, TA = 25°C. TYP† mV mV 2.8 V Figure 7 0.4 V switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 150 ns 150 ns 50 ns tPLH tPHL Propagation delay time, low-to-high-level output tsk(p) tr Pulse skew (| tpHL − tpLH |) tf tPZH Fall time, single ended Output enable time to high level 100 ns tPZL tPHZ Output enable time to low level 100 ns 100 ns tPLZ Output disable time from low level 100 ns CL = 50 pF, Propagation delay time, high-to-low-level output Rise time, single ended See Figure 7 See Figure 8 Output disable time from high level www.umw-ic.com 6 See Figure 7 20 ns 20 ns 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R PARAMETER MEASUREMENT INFORMATION Output 3V S1 Input 1.5 V 1.5 V 0 or 3 V RL = 110 Ω CL = 50 pF (see Note B) Generator (see Note A) 0V 0.5 V tPZH VOH 50 Ω Output 2.3 V tPHZ Voff ≈ 0 V VOLTAGE WAVEFORMS TEST CIRCUIT NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 2. Driver tPZH and tPHZ Test Circuit and Voltage Waveforms 5V S1 3V Input RL = 110 Ω 1.5 V 0V Output 0 or 3 V Generator (see Note A) 1.5 V tPZL tPLZ CL = 50 pF (see Note B) 50 Ω 2.3 V Output 5V 0.5 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1.25 kHz, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B. CL includes probe and jig capacitance. Figure 3. Driver tPZL and tPLZ Test Circuit and Voltage Waveforms A D Input 27 Ω VOD IO(A) 27 Ω II VO(A) Output B VOC IO(B) VO(B) CL CL NOTES: A. Resistance values are in ohms and are 1% tolerance. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit, Voltage, and Current Definitions www.umw-ic.com 7 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R PARAMETER MEASUREMENT INFORMATION 3V Input 50% 50% 0V tPHL tPLH VO(A) 10% 90% 50% 90% 50% tr tf tPHL 90% VO(B) 50% 10% 10% ∼ 3.5 V ∼ 2.3 V ∼1V 50% 10% tr tPLH 90% ∼ 3.5 V ∼ 2.3 V ∼1V tf td(DH) td(DL) ∼ 2.5 V 0V ∼ −2.5 V VOD VOC VOC(PP) ∆VOC(SS) Figure 5. Driver Timing, Voltage and Current Waveforms www.umw-ic.com 8 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R PARAMETER MEASUREMENT INFORMATION A 27 Ω VOD D 27 Ω Output B Inputs VOC DE CL CL 3V DE 0V Inputs 3V D 0V Output VOC(PP) NOTES: A. Resistance values are in ohms and are 1% tolerance. B. CL includes probe and jig capacitance (± 10%). Figure 6. Driver VOC(PP) Test Circuit and Waveforms II A Input VI B 1.5 V Inputs RE 50% VO 50 pF (see Note A) Output 3V 1.5 V 0V 50% tPLH Output IO R VID tPHL 90% 10% 90% 10% tr NOTE A: This value includes probe and jig capacitance (± 10%). VOH 50% VOL tf Figure 7. Receiver tPLH and tPHL Test Circuit and Voltage Waveforms www.umw-ic.com 9 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R PARAMETER MEASUREMENT INFORMATION 5V A 620 Ω 0 V or 3 V R 1.5 V B RE 620 Ω 50 pF (see Note A) VO Input 3V A 0V 3V Inputs RE 3V 1.5 V 0V tPHZ Output VO tPZH 0.5 V 0V tPLZ 0.5 V tPZL ∼ 2.5 V VOH ∼ 2.5 V 0.5 V 0.5 V VOL NOTE A: This value includes probe and jig capacitance (± 10%). Figure 8. Receiver tPZL, tPLZ, tPZH, and tPHZ Test Circuit and Voltage Waveforms www.umw-ic.com 10 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R TYPICAL CHARACTERISTICS DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE DRIVER PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 800 RL = 54 Ω 2.5 tpd − Driver Propagation Delay Time − ns VOD − Driver Differential Output Voltage − V 3.0 VCC = 5.25 V VCC = 5 V 2.0 VCC = 4.75 V 1.5 1.0 −40 −20 0 20 40 60 780 760 tPHL 740 720 tPLH 700 680 660 640 −40 80 TA − Free-Air Temperature − °C −20 Figure 9 40 60 80 DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT 900 4.5 4.0 VOD − Differential Output Voltage − V 800 tt − Driver Transition Time − ns 20 Figure 10 DRIVER TRANSITION TIME vs FREE-AIR TEMPERATURE tf 700 tr 600 500 400 300 −40 0 TA − Free-Air Temperature − °C −20 0 20 40 60 3.0 VCC = 5.5 V 2.5 VCC = 4.5 V 2.0 1.5 VCC = 5 V 1.0 0.5 0.0 80 0 TA − Free-Air Temperature − °C 10 20 30 40 50 60 70 80 90 100 IO − Output Current − mA Figure 11 www.umw-ic.com 3.5 Figure 12 11 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R TYPICAL CHARACTERISTICS RECEIVER INPUT CURRENT vs INPUT VOLTAGE 0.25 I(I) − Receiver Input Current − mA 0.20 0.15 0.10 0.05 −0.00 A, B (VCC = 0 V) −0.05 B (VCC = 5 V) −0.10 A (VCC = 5 V) −0.15 −0.20 −10 −5 0 5 10 15 VI − Input Voltage − V Figure 13 APPLICATION INFORMATION SN65LBC184 SN75LBC184 SN65LBC184 SN75LBC184 RT RT Up to 128 Transceivers NOTE A: The line should be terminated at both ends in its characteristic impedance (RT = ZO). Stub lengths off the main line should be kept as short as possible. Figure 14. Typical Application Circuit www.umw-ic.com 12 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R APPLICATION INFORMATION ’LBC184 test description The ’LBC184 is tested against the IEC 61000−4−5 recommended transient identified as the combination wave. The combination wave provides a 1.2-/50-µs open-circuit voltage waveform and a 8-/20-µs short-circuit current waveform shown in Figure 15. The testing is performed with a combination/hybrid pulse generator with an effective output impedance of 2 Ω. The setup for the overvoltage stress is shown in Figure 16 with all testing performed with power applied to the ’LBC184 circuit. NOTE High voltage transient testing is done on a sampling basis. VI(peak) II(peak) 0.5 VP 0.5 IP 1.2 µs 8 µs t 50 µs t 20 µs Figure 15. Short-Circuit Current Waveforms The ’LBC184 is tested and evaluated for both maximum (single pulse) as well as life test (multiple pulse) capabilities. The ’LBC184 is evaluated against transients of both positive and negative polarity and all testing is performed with the worst-case transient polarity. Transient pulses are applied to the bus pins (A & B) across ground as shown in Figure 16. Key Tech 1.2/50 − 8/20 Combination Pulse Generator 2-Ω Internal Impedance High IP 41.9 Ω 3Ω Low 7 Current Limiter VP 5 B/A SN75LBC184 GND Figure 16. Overvoltage-Stress Test Circuit An example waveform as seen by the ’LBC184 is shown in Figure 17. The bottom trace is current, the middle trace shows the clamping voltage of the device and the top trace is power as calculated from the voltage and current waveforms. This example shows a peak clamping voltage of 16 V, peak current of 33.6 A yielding an absorbed peak power of 538 W. NOTE A circuit reset may be required to ensure normal data communications following a transient noise pulse of greater than 250 W peak. www.umw-ic.com 13 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R APPLICATION INFORMATION Power 538 W Peak 0 16 V Peak, VI(peak) Clamping Voltage 0 33.6 A Peak, II(peak) Input Current 0 0 20 40 60 80 100 120 140 160 180 t − 20 µs/Div Figure 17. Typical Surge Waveform Measured At Terminals 5 and 7 www.umw-ic.com 14 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R SOP 8 www.umw-ic.com 15 友台半导体有限公司 UMW SN75LBC184/ SN65LBC184 R www.umw-ic.com 16 友台半导体有限公司