SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm,
Stratum 3, Elite Platform™ Precision Super-TCXO
Description
Features
The SiT5357 is a ±100 ppb precision MEMS Super-TCXO
that is fully compliant to Telcordia GR-1244-CORE Stratum
3 oscillator specifications. Engineered for best dynamic
performance, the SiT5357 is ideal for high reliability
telecom, wireless and networking, industrial, precision
GNSS and audio/video applications.
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Leveraging SiTime’s unique DualMEMS™ temperature
sensing and TurboCompensation™ technologies, the
SiT5357 delivers the best dynamic performance for timing
stability in the presence of environmental stressors such as
air flow, temperature perturbation, vibration, shock, and
electromagnetic interference. This device also integrates
multiple on-chip regulators to filter power supply noise,
eliminating the need for a dedicated external LDO.
The SiT5357 offers three device configurations that can be
ordered using Ordering Codes for:
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Output 60–189 MHz, and 208–220 MHz, in 1 Hz steps
Factory programmable options for short lead time
Best dynamic stability under airflow, thermal shock
▪ ±100 ppb stability across temperature
▪ ±1 ppb/C typical frequency slope (ΔF/ΔT)
▪ 1.5e-11 ADEV at 10 second averaging time
-40°C to +105°C operating temperature
No activity dips or micro jumps
Resistant to shock, vibration and board bending
On-chip regulators eliminate the need for external LDOs
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS output
Digital frequency pulling (DCTCXO) via I 2C
▪ Digital control of output frequency and pull range
▪ Up to ±3200 ppm pull range
▪ Frequency pull resolution down to 5 ppt
2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage
LVCMOS output
RoHS and REACH compliant
Pb-free, Halogen-free, Antimony-free
Applications
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The SiT5357 can be factory programmed for any
combination of frequency, stability, voltage, and pull range.
Programmability enables designers to optimize clock
configurations while eliminating long lead times and
customization costs associated with quartz devices where
each frequency is custom built.
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4G/5G radio, Small cell
IEEE1588 boundary and grandmaster clocks
Synchronous Ethernet
Optical transport – SONET/SDH, OTN, Stratum 3
DOCSIS 3.x remote PHY
Precision GNSS systems
Test and measurement
Refer to Manufacturing Guideline for proper reflow profile
and PCB cleaning recommendations to ensure best
performance.
Block Diagram
5.0 mm x 3.2 mm Package Pinout
SDA / NC
OE / VC / NC
1
9
VDD
SCL / NC
2
8
NC
NC
3
7
NC
GND
4
6
CLK
10
5
A0 / NC
Figure 1. SiT5357 Block Diagram
Rev 1.06
Figure 2. Pin Assignments (Top view)
(Refer to Table 11 for Pin Descriptions)
May 10, 2020
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Ordering Information
The part number guide illustrated below is for reference only, in which boxes identify order codes having more than one option.
To customize and build an exact part number, use the SiTime Part Number Generator. To validate the part number, use the
SiTime Part Number Decoder.
Package Size "F": 5.0 mm x 3.2 mm
Pin 1 Function – TCXO mode only
Output Waveform "-" : LVCMOS[1]
"E": Output Enable
"N": No Connect
Silicon Revision Letter
Part Family
TCXO
VCTCXO
DCTCXO
SiT5357AC - FQ - 33 E 0 - 98.123456 T
SiT5357AC - FQ - 33 V T - 98.123456 T
SiT5357AC - FQG33 J R - 98.123456 T
"I": Industrial, -40 to 85°C
"C": Extended Commercial, -20 to 70°C
"E": Extended Industrial, -40 to 105°C
Packaging
"T": 12 mm Tape & Reel, 3 ku reel
"Y": 12 mm Tape & Reel, 1 ku reel
“X”: 12 mm Tape & Reel, 250 u reel
(blank): bulk[2]
Frequency Stability
Frequency
"Q": for ±0.1 ppm
"P": for ±0.2 ppm
"N": for ±0.25 ppm
60.000001 MHz to 189.000000 MHz
208.000000 MHz to 220.000000 MHz
Temperature Range
Pull Range – DCTCXO mode only
I2C Address Mode – DCTCXO mode only
"T": ±6.25 ppm
"R": ±10 ppm
"Q": ±12.5 ppm
"M": ±25 ppm
"B": ±50 ppm
"C": ±80 ppm
"E": ±100 ppm
"F": ±125 ppm
“0”, “1”, “2”, “3”, “4”, “5”, “6”, “7”, “8”, “9”, “A”, “B”,
“C”, “D”, “E”, “F”: Order code representing hex
value of I2C address. When the I2C address is
factory programmed using this code, pin A0 is no
connect (NC).
“G”: I2C pin addressable mode. Address is set by
the logic on A0 pin.
"G":
"H":
"X":
"L":
"Y":
"S":
"Z":
"U":
±150 ppm
±200 ppm
±400 ppm
±600 ppm
±800 ppm
±1200 ppm
±1600 ppm
±3200 ppm
Pin 1 Function – DCTCXO mode only
Supply Voltage
"I": Output Enable
"J": No Connect, software OE control
"25": 2.5 V ±10%
"28": 2.8 V ±10%
"30": 3.0 V ±10%
"33": 3.3 V ±10%
Notes:
1. “-“ corresponds to the default rise/fall time for LVCMOS output as specified in Table 1 (Electrical Characteristics). Contact SiTime for other rise/fall time
options for best EMI or driving multiple loads. For differential outputs, contact SiTime.
2. Bulk is available for sampling only.
Rev 1.06
Page 2 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1
Ordering Information .................................................................................................................................................................... 2
Electrical Characteristics.............................................................................................................................................................. 4
Device Configurations and Pin-outs ............................................................................................................................................. 9
Pin-out Top Views................................................................................................................................................................. 9
Test Circuit Diagrams for LVCMOS Outputs .............................................................................................................................. 10
Waveforms................................................................................................................................................................................. 11
Timing Diagrams ........................................................................................................................................................................ 11
Stability Diagrams ...................................................................................................................................................................... 11
Typical Performance Plots ......................................................................................................................................................... 12
Architecture Overview ................................................................................................................................................................ 15
Frequency Stability ............................................................................................................................................................. 15
Output Frequency and Format ............................................................................................................................................ 15
Output Frequency Tuning ................................................................................................................................................... 15
Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 16
Device Configurations ................................................................................................................................................................ 16
TCXO Configuration ........................................................................................................................................................... 16
VCTCXO Configuration ...................................................................................................................................................... 17
DCTCXO Configuration ...................................................................................................................................................... 18
VCTCXO-Specific Design Considerations ................................................................................................................................. 19
Linearity .............................................................................................................................................................................. 19
Control Voltage Bandwidth ................................................................................................................................................. 19
FV Characteristic Slope KV ................................................................................................................................................. 19
Pull Range, Absolute Pull Range ........................................................................................................................................ 20
DCTCXO-Specific Design Considerations ................................................................................................................................. 21
Pull Range and Absolute Pull Range .................................................................................................................................. 21
Output Frequency ............................................................................................................................................................... 22
I2C Control Registers .......................................................................................................................................................... 24
Register Descriptions.......................................................................................................................................................... 24
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 24
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 25
Register Address: 0x02. DIGITAL PULL RANGE CONTROL[18] ........................................................................................ 26
Serial Interface Configuration Description .......................................................................................................................... 27
Serial Signal Format ........................................................................................................................................................... 27
Parallel Signal Format ........................................................................................................................................................ 28
Parallel Data Format ........................................................................................................................................................... 28
I2C Timing Specification ...................................................................................................................................................... 30
I2C Device Address Modes ................................................................................................................................................. 31
Schematic Example ............................................................................................................................................................ 32
Dimensions and Patterns ........................................................................................................................................................... 33
Layout Guidelines ...................................................................................................................................................................... 34
Manufacturing Guidelines .......................................................................................................................................................... 34
Additional Information ................................................................................................................................................................ 35
Revision History ......................................................................................................................................................................... 36
Rev 1.06
Page 3 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and 3.3V Vdd.
Table 1. Output Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Frequency Coverage
Nominal Output Frequency Range
F_nom
60.000001
–
189
MHz
208
–
220
MHz
Temperature Range
Operating Temperature Range
T_use
-20
–
+70
°C
Extended Commercial, ambient temperature
-40
–
+85
°C
Industrial, ambient temperature
-40
–
+105
°C
Extended Industrial, ambient temperature
Frequency Stability - Stratum 3+ Grade
–
±0.1
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range, in TCXO, DCTCXO, or VCTCXO
(VCTCXO with ±6.25 ppm pull range, Vc=Vdd/2)
–
–
±0.3
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
–
±0.7
±3.6
ppb
Vdd ±5%
F_load
–
±0.2
±1.5
ppb
15 pF ±10%
ΔF/ΔT
–
±0.9
±2
ppb/°C
0.5°C/min temperature ramp rate, -20 to 85°C
–
±1
±3.5
ppb/°C
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.9
±3.3
ppb/°C
0.5°C/min temperature ramp rate, 85 to 105°C
–
±0.008
±0.02
ppb/s
0.5°C/min temperature ramp rate, -20 to 85°C
–
±0.01
±0.035
ppb/s
0.5°C/min temperature ramp rate, -40 to -20°C
–
±0.008
±0.028
ppb/s
0.5°C/min temperature ramp rate, 85 to 105°C
F_24_Hold
–
–
±0.15
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
F_hys
–
±25
±42
ppb
-40 to 105°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
–
±15
±27
ppb
-40 to 85°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
–
±10
±20
ppb
-20 to 70°C, 0.5°C/min ramp rate, defined as ±ΔF/2 as
shown in Figure 13, contact SiTime for lower hysteresis
F_stab
–
Initial Tolerance
F_init
Supply Voltage Sensitivity
F_Vdd
Output Load Sensitivity
Frequency vs. Temperature Slope
Frequency Stability over
Temperature
Dynamic Frequency Change during
Temperature Ramp
24-hour holdover Stability
Hysteresis Over Temperature
F_dynamic
One-Day Aging
F_1d
–
±0.5
±2.0
ppb
At 85°C, after 30-days of continued operation. Aging is
measured with respect to day 31.
One-Year Aging
F_1y
–
±57
±230
ppb
5-Year Aging
F_5y
–
±73
±320
ppb
At 85°C, after 2-days of continued operation. Aging is
measured with respect to day 3.
10-Year Aging
F_10y
–
±80
±360
ppb
20-Year Aging
F_20y
–
±87
±400
ppb
Allan deviation
ADEV
–
1.5e-11
–
–
10 second averaging time [3]
Frequency Stability - Stratum 3 Grade
Initial Tolerance
F_init
–
–
±1
ppm
Initial frequency at 25°C at 48 hours after 2 reflows
Supply Voltage Sensitivity
F_Vdd
–
±4.7
±10.4
ppb
Vdd ±5%
Output Load Sensitivity
F_load
–
±1.3
±4.2
ppb
15 pF ±10%
Frequency Stability over
Temperature
F_stab
–
–
±0.2
ppm
–
–
±0.25
ppm
Referenced to (max frequency + min frequency)/2 over the
rated temperature range. Vc=Vdd/2 for VCTCXO
ΔF/ΔT
–
±6.4
±10
ppb/°C
Dynamic Frequency Change during
Temperature Ramp
F_dynamic
–
±0.05
±0.08
ppb/s
0.5°C/min temperature ramp rate
24-hour holdover Stability
F_24_Hold
–
–
±0.28
ppm
Inclusive of frequency variation due to temperature, ±10%
supply variation, ±1.5 pF load variation and 24-hour aging
F_1d
–
±3
±5
ppb
At 25°C, after 30-days of continued operation. Aging is
measured with respect to day 31
One-Year Aging
F_1y
–
±1
–
ppm
20-Year Aging
F_20y
–
±2
–
ppm
At 25°C, after 2-days of continued operation. Aging is
measured with respect to day 3
F_tot_20y
–
–
±4.6
ppm
Frequency vs. Temperature Slope
One-Day Aging
20-Year Total Stability
Rev 1.06
Page 4 of 37
-40 to 105°C
Complies with Stratum 3, per GR-1244-CORE. Actual
performance is better
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 1. Output Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
LVCMOS Output Characteristics
Duty Cycle
DC
45
–
55
%
60 to 150 MHz
42
–
55
%
150 to 189 MHz, 200 to 220 MHz
10% - 90% Vdd
Rise/Fall Time
Tr, Tf
0.8
1.2
1.9
ns
Output Voltage High
VOH
90%
–
–
Vdd
IOH = +3 mA
Output Voltage Low
VOL
–
–
10%
Vdd
IOL = -3 mA
Z_out_c
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.3 V
–
17
–
Ohms
Impedance looking into output buffer, Vdd = 3.0 V
–
18
–
Ohms
Impedance looking into output buffer, Vdd = 2.8 V
–
19
–
Ohms
Impedance looking into output buffer, Vdd = 2.5 V
Output Impedance
Start-up Characteristics
Start-up Time
Output Enable Time
Time to Rated Frequency Stability
T_start
–
2.5
3.5
T_oe
–
–
T_stability
–
5
ms
Time to first pulse, measured from the time Vdd reaches
90% of its final value. Vdd ramp time = 100 µs from 0 V to
Vdd
285
ns
See Timing Diagrams section below
45
ms
Time to first accurate pulse within rated stability, measured
from the time Vdd reaches 90% of its final value. Vdd
ramp time = 100 µs
Note:
3. Measured 2 hours after startup in a temperature chamber with a constant temperature in still air.
Rev 1.06
Page 5 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 2. DC Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Supply Voltage
Supply Voltage
Vdd
2.25
2.5
2.75
V
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
Contact SiTime for 2.25 V to 3.63 V continuous supply
voltage support
Current Consumption
Current Consumption
OE Disable Current
Idd
I_od
–
48
62
mA
F_nom = 100 MHz, No Load, TCXO and DCTCXO modes
–
52
66
mA
F_nom = 100 MHz, No Load, VCTCXO mode
–
45
52
mA
OE = GND, output weakly pulled down. TCXO, DCTCXO
–
49
56
mA
OE = GND, output weakly pulled down. VCTCXO mode
Typ.
Max.
Unit
Table 3. Input Characteristics
Parameters
Symbol
Min.
Condition
Input Characteristics – OE Pin
Input Impedance
Z_in
75
–
–
kΩ
Input High Voltage
VIH
70%
–
–
Vdd
Input Low Voltage
VIL
–
–
30%
Vdd
Internal pull up to Vdd
Frequency Tuning Range – Voltage Control or I2C mode
Pull Range
Absolute Pull Range[4]
PR
APR
±6.25
–
–
ppm
VCTCXO mode. Contact SiTime for ±12.5 and ±25 ppm
±6.25
±10
±12.5
±25
±50
±80
±100
±125
±150
±200
±400
±600
±800
±1200
±1600
±3200
–
–
ppm
DCTCXO mode
±5.31
–
–
ppm
±0.1 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.05
–
–
ppm
±0.2 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
±3.00
–
–
ppm
±0.25 ppm F_stab, DCTCXO, VCTCXO for PR = ±6.25 ppm
Upper Control Voltage
VC_U
90%
–
–
Vdd
VCTCXO mode
Lower Control Voltage
VC_L
–
–
10%
Vdd
VCTCXO mode
Control Voltage Input Impedance
VC_z
8
–
–
MΩ
VCTCXO mode
Control Voltage Input Bandwidth
VC_bw
–
10
–
kHz
VCTCXO mode; contact SiTime for other bandwidth options
1.0
%
Frequency Control Polarity
F_pol
Pull Range Linearity
PR_lin
Positive
–
0.5
VCTCXO mode
VCTCXO mode
I2C Interface Characteristics, 200 Ohm, 550 pF (Max I2C Bus Load)
Bus Speed
F_I2C
≤ 400
kHz
Over rated frequency range (F_rated)
≤ 1000
kHz
Over operating frequency range (F_oper)
Input Voltage Low
VIL_I2C
–
–
30%
Vdd
DCTCXO mode
Input Voltage High
VIH_I2C
70%
–
–
Vdd
DCTCXO mode
Output Voltage Low
VOL_I2C
–
–
0.4
V
DCTCXO mode
IL
0.5
–
24
µA
0.1 VDD< VOUT < 0.9 VDD. Includes typical leakage current
from 200 kΩ pull resister to VDD. DCTCXO mode
CIN
–
–
5
pF
DCTCXO mode
Input Leakage current
Input Capacitance
Note:
4. PR = PR – initial tolerance – 20-year aging – frequency stability over temperature. Refer to Table 14 for APR with respect to other pull range options.
Rev 1.06
Page 6 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 4. Jitter & Phase Noise, -40°C to 85°C
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
Jitter
T_phj
–
0.31
0.48
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
1.0
1.8
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6.6
13.4
ps
F_nom = 100 MHz, population 1 k, measured as absolute
value
1 Hz offset
–
-61
-54
dBc/Hz
10 Hz offset
–
-89
-83
dBc/Hz
100 Hz offset
–
-107
-103
dBc/Hz
1 kHz offset
–
-128
-124
dBc/Hz
10 kHz offset
–
-133
-131
dBc/Hz
100 kHz offset
–
-133
-130
dBc/Hz
1 MHz offset
–
-150
-146
dBc/Hz
5 MHz offset
–
-157
-151
dBc/Hz
10 MHz offset
–
-157
-152
dBc/Hz
20 MHz offset
–
-159
-152
dBc/Hz
–
-91
-86
dBc
Min.
Typ.
Max.
Unit
RMS Phase Jitter (random)
Phase Noise
T_spur
Spurious
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
F_nom = 100 MHz, 1 kHz to 40 MHz offsets
Table 5. Jitter & Phase Noise, -40°C to 105°C
Parameters
Symbol
Condition
Jitter
T_phj
–
0.31
0.50
ps
F_nom = 100 MHz, Integration bandwidth = 12 kHz to 20 MHz
RMS Period Jitter
T_jitt_per
–
1.0
1.8
ps
F_nom = 100 MHz, population 10 k
Peak Cycle-to-Cycle Jitter
T_jitt_cc
–
6.6
13.4
ps
F_nom = 100 MHz, population 1 k, measured as absolute
value
1 Hz offset
–
-61
-54
dBc/Hz
10 Hz offset
–
-89
-83
dBc/Hz
100 Hz offset
–
-107
-103
dBc/Hz
1 kHz offset
–
-128
-124
dBc/Hz
10 kHz offset
–
-133
-131
dBc/Hz
100 kHz offset
–
-133
-130
dBc/Hz
1 MHz offset
–
-150
-144
dBc/Hz
5 MHz offset
–
-157
-150
dBc/Hz
10 MHz offset
–
-157
-150
dBc/Hz
20 MHz offset
–
-159
-150
dBc/Hz
–
-91
-85
dBc
RMS Phase Jitter (random)
Phase Noise
Spurious
Rev 1.06
T_spur
Page 7 of 37
F_nom = 100 MHz
TCXO and DCTCXO modes, and VCTCXO mode with
±6.25 ppm pull range
F_nom = 100 MHz, 1 kHz to 40 MHz offsets
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 6. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maxi mum ratings.
Parameter
Test Conditions
Storage Temperature
Continuous Power Supply Voltage Range (Vdd)
Human Body Model (HBM) ESD Protection
JESD22-A114
Soldering Temperature (follow standard Pb-free soldering guidelines)
Junction Temperature[5]
Value
Unit
-65 to 125
°C
-0.5 to 4
V
2000
V
260
°C
130
°C
Input Voltage, Maximum
Any input pin
Vdd + 0.3
V
Input Voltage, Minimum
Any input pin
-0.3
V
Note:
5. Exceeding this temperature for an extended period of time may damage the device.
Table 7. Thermal Considerations[6]
Package
JA[7] (°C/W)
JC, Bottom (°C/W)
Ceramic 5.0 mm x 3.2 mm
54
15
Note:
6. Measured in still air. Refer to JESD51 for θJA and θJC definitions.
7. Devices soldered on a JESD51 2s2p compliant board.
Table 8. Maximum Operating Junction Temperature[8]
Max Operating Temperature (ambient)
Maximum Operating Junction Temperature
70°C
80°C
85°C
95°C
105°C
115°C
Note:
8. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 9. Environmental Compliance
Value
Unit
Mechanical Shock Resistance
Parameter
MIL-STD-883F, Method 2002
30000
g
Mechanical Vibration Resistance
MIL-STD-883F, Method 2007
70
g
Temperature Cycle
JESD22, Method A104
–
–
Solderability
MIL-STD-883F, Method 2003
–
–
Moisture Sensitivity Level
MSL1 @260°C
–
–
Rev 1.06
Test Conditions
Page 8 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Device Configurations and Pin-outs
Table 10. Device Configurations
I2C Programmable Parameters
Configuration
Pin 1
Pin 5
TCXO
OE/NC
NC
–
–
VCTCXO
VC
NC
DCTCXO
OE/NC
A0/NC
Frequency Pull Range, Frequency Pull Value, Output Enable control.
Pin-out Top Views
NC
OE/NC
1
9
VDD
VC
1
NC
2
8
NC
NC
NC
3
7
NC
GND
4
6
CLK
10
5
SDA
NC
OE / NC
1
NC
SCL
7
NC
6
CLK
9
VDD
2
8
NC
3
GND
4
NC
Figure 3. TCXO
10
5
9
VDD
2
8
NC
NC
3
7
NC
GND
4
6
CLK
10
5
A0 / NC
NC
Figure 4. VCTCXO
Figure 5. DCTCXO
Table 11. Pin Description
Pin
1
Symbol
OE/NC [11]/VC
I/O
Internal Pull-up/Pull Down
Resistor
OE – Input
100 kΩ Pull-Up
No Connect
–
H or L or Open: No effect on output frequency or other device functions
VC – Input
–
Control Voltage in VCTCXO Mode
SCL – Input
200 kΩ Pull-Up
Function
H[9]: specified frequency output
L: output is high impedance. Only output driver is disabled.
I2C serial clock input.
2
SCL / NC [11]
3
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
4
GND
Power
–
Connect to ground
No Connect
5
A0 / NC[11]
H or L or Open: No effect on output frequency or other device functions
Device I2C address when the address selection mode is via the A0 pin.
This pin is NC when the I2C device address is specified in the ordering
code.
A0 Logic Level I2C Address
0
1100010
1
1101010
A0 – Input
100 kΩ Pull-Up
NC – No Connect
–
H or L or Open: No effect on output frequency or other device functions.
6
CLK
Output
–
LVCMOS
7
NC[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
8
NC
[11]
No Connect
–
H or L or Open: No effect on output frequency or other device functions
9
VDD
Power
–
Connect to power supply[10]
SDA / NC [11]
SDA – Input/Output
200 kΩ Pull Up
10
NC – No Connect
–
I2C Serial Data.
H or L or Open: No effect on output frequency or other device functions.
Notes:
9. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use
the NC option.
10. A 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND. The 0.1 μF capacitor is recommended to place close to the
device, and place the 10 μF capacitor less than 2 inches away.
11. All NC pins can be left floating and do not need to be soldered down.
Rev 1.06
Page 9 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Test Circuit Diagrams for LVCMOS Outputs
VDD
9
+
8
7
VDD
6
10
10µF
1
5
2
3
9
+
0.1µF
Power
Supply
-
Test Point
CLK
(including probe
and fixture
capacitance)
4
8
7
6
2
3
4
Test Point
0.1µF
Power
Supply
15pF
CLK
10
5
10µF
-
1
15pF
(including probe
and fixture
capacitance)
Control
Voltage
Vdd
OE Function
VC Function
Figure 7. LVCMOS Test Circuit (VC Function)
Figure 6. LVCMOS Test Circuit (OE Function)
VDD
9
+
8
7
6
2
3
4
0.1µF
Power
Supply
10
10µF
-
Test Point
CLK
5
1
15pF
(including probe
and fixture
capacitance)
Any state
or floating
NC Function
Figure 8. LVCMOS Test Circuit (NC Function)
VDD
9
+
8
7
6
A0/NC
0.1µF
Power
Supply
-
Test Point
CLK
10
10µF
SDA
1
[11]
Any state
or floating
NC
Function
5
2
3
4
15pF
(including probe
and fixture
capacitance)
SCL
Figure 9. LVCMOS Test Circuit (I2C Control), DCTCXO mode for AC and DC Measurements
Note:
12. SDA is open-drain and may require pull-up resistor if not present in I2C test setup.
Rev 1.06
Page 10 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Waveforms
tr
tf
90 % Vdd
50 % Vdd
10 % Vdd
High Pulse
(TH)
Low Pulse
(TL)
Period
Figure 10. LVCMOS Waveform Diagram[13]
Note:
13. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
90% Vdd
Vdd
Vdd
50% Vdd
T_start
Vdd Pin
Voltage
OE Voltage
T_oe
CLK Output
CLK Output
HZ
HZ
T_oe: Time to re-enable the clock output
T_start: Time to start from power-off
Figure 12. OE Enable Timing (OE Mode Only)
Figure 11. Startup Timing
Stability Diagrams
Figure 13. Illustration of hysteresis, where ΔF is max
frequency difference between up and down cycles
across temperature
Rev 1.06
Page 11 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Typical Performance Plots
Breezy Air
Still Air
Breezy Air
Still Air
TDEV (s)
Allan Deviation
1E-09
1E-10
1E-11
1E-12
0.033
1E-11
1
10
100
1000
0.33
3.3
Figure 14. ADEV (±0.1 ppm) [14]
Breezy Air
Still Air
ITU-T G.8262, EEC2
1E-09
1E-10
1E-11
33
330
2.5
100
Frequency deviation (ppb)
MTIE (s)
1E-08
3.3
3300
0
-50
-100
-40
-20
0
Frequency deviation (ppm)
Frequency vs. Temperature
Slope (ppb/°C)
3.3 V
1.5
0.5
-0.5
-1.5
-2.5
-40
-20
0
20
40
60
80
20
40
Temperature (°C)
60
80
100
Figure 17. Frequency vs Temperature (±0.1 ppm), 105°C
Figure 16. MTIE (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
2.5 V
3.3
50
Observation interval (s)
2.5
330
Figure 15. TDEV (0.1 Hz loop bandwidth, ±0.1 ppm) [14]
1E-07
0.33
33
Averaging time (s)
Time (s)
10
8
6
4
2
0
-2
-4
-6
-8
-10
0.3
100
Temperature (°C)
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
Control Voltage (V)
Figure 18. Freq. vs. Temp. Slope (ΔF/ΔT), ±0.1 ppm device
Figure 19. VCTCXO frequency pull characteristic
5
50
4
40
3
30
Frequency drift (ppb)
Aging rate (ppb/day)
ITU-T G.8262, EEC2
1E-08
1E-10
2
1
0
-1
-2
-3
20
10
0
-10
-20
-30
-40
-4
-50
-5
30
35
40
45
Day
50
55
60
Figure 20. 1-day aging rate after 30 days, 0.1 ppm device
Rev 1.06
Page 12 of 37
30
40
50
60
Day
Figure 21. Frequency drift after 30 days [15]
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Typical Performance Plots (continued)
3.3 V
Frequency sensitivity (ppb)
Frequency sensitivity (ppb)
2.5 V
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
2.5 V
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-10
-5
0
5
10
-10
-5
Load variation (%)
2.5 V
55
2.8 V
5
10
3.0 V
Figure 23. VDD sensitivity (±0.1 ppm)
3.3 V
2.5 V
2.8 V
3.0 V
3.3 V
Current consumption (mA)
58
53
Duty cycle (%)
0
Power supply voltage variation (%)
Figure 22. Load sensitivity (±0.1 ppm)
51
49
47
45
56
54
52
50
48
46
44
42
40
70
90
110
130
150
170
190
210
70
90
110
Frequency (MHz)
2.5 V
2.8 V
130
150
170
190
210
Frequency (MHz)
Figure 24. Duty Cycle (LVCMOS)
3.0 V
Figure 25. IDD DCTCXO (LVCMOS)
3.3 V
2.5 V
2.8 V
3.0 V
3.3 V
60
Current consumption (mA)
58
Current consumption (mA)
3.3 V
56
54
52
50
48
46
44
42
40
58
56
54
52
50
48
46
70
90
110
130
150
170
190
210
70
90
110
Frequency (MHz)
Figure 26. IDD TCXO (LVCMOS)
2.5 V
500
2.8 V
130
150
170
190
210
Frequency (MHz)
Figure 27. IDD VCTCXO (LVCMOS)
3.0 V
3.3 V
2.5 V
3.3 V
Period Jitter (ps MS)
Phase Jitter (fs RMS)
1.90
400
300
200
100
1.70
1.50
1.30
1.10
0.90
0.70
0.50
0
70
90
110
130
150
170
190
70
210
Frequency (MHz)
110
130
150
170
190
210
Frequency (MHz)
Figure 28. RMS Phase Jitter, DCTCXO, TCXO (LVCMOS)
Rev 1.06
90
Page 13 of 37
Figure 29. RMS Period Jitter (LVCMOS)
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Typical Performance Plots (continued)
2.5 V
2.8 V
3.0 V
3.3 V
Frequency deviation (ppm)
Phase Jitter (fs RMS)
500
400
300
200
100
0
70
120
170
220
6.25
5
3.75
2.5
1.25
0
-1.25
-2.5
-3.75
-5
-6.25
-6.25
Frequency (MHz)
-5
-3.75 -2.5 -1.25
0
1.25
2.5
3.75
5
6.25
DCTCXO pull (ppm)
Figure 30. RMS Phase Jitter, VCTCXO (LVCMOS)
Figure 31. DCTCXO frequency pull characteristic
Note:
14. Measured 24 hours after start up in a temperature chamber with constant temperature.
15. Plotted with respect to the frequency measurement at the end of the 30th day.
Rev 1.06
Page 14 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Architecture Overview
Functional Overview
Based on SiTime’s innovative Elite Platform™, the SiT5357
delivers exceptional dynamic performance, i.e. resilience to
environmental stressors such as shock, vibration, and fast
temperature transients. Underpinning the Elite platform
are SiTime’s unique DualMEMS™ temperature sensing
architecture and TurboCompensation™ technologies.
The SiT5357 is designed for maximum flexibility with an
array of factory programmable options, enabling system
designers to configure this precision device for optimal
performance in a given application.
DualMEMS is a noiseless temperature compensation
scheme. It consists of two MEMS resonators fabricated on
the same die substrate. The TempFlat™ MEMS resonator
is designed with a flat frequency characteristic over
temperature whereas the temperature sensing resonator is
by design sensitive to temperature changes. The ratio of
frequencies between these two resonators provides an
accurate reading of the resonator temperature with 20 µK
resolution.
By placing the two MEMS resonators on the same die, this
temperature sensing scheme eliminates any thermal lag
and gradients between resonator and temperature sensor,
thereby overcoming an inherent weakness of legacy quartz
TCXOs.
The DualMEMS temperature sensor drives a state-of-theart CMOS temperature compensation circuit. The
TurboCompensation design, with >100 Hz compensation
bandwidth, achieves a dynamic frequency stability that is
far superior to any quartz TCXO. The digital temperature
compensation enables additional optimization of
frequency stability and frequency slope over temperature
within any chosen temperature range for a given system
design.
The Elite platform also incorporates a high resolution, low
noise frequency synthesizer along with the industry
standard I2C bus. This unique combination enables system
designers to digitally control the output frequency in steps
as low as 5 ppt and over a wide range up to ±3200 ppm.
For more information regarding the Elite platform and its
benefits please visit:
◼ SiTime's breakthroughs section
◼ TechPaper: DualMEMS Temperature Sensing Technology
◼ TechPaper: DualMEMS Resonator TDC
Rev 1.06
Frequency Stability
The SiT5357 comes in three factory-trimmed stability
grades that are optimized for different applications. Both
Stratum 3+ and Stratum 3 devices are compliant with
Stratum 3 stability of ±4.6 ppm over 20 years.
Table 12. Stability Grades vs. Ordering Codes
Frequency Slope
(ΔF/ΔT)
Frequency Stability
Over Temperature
Ordering
Code
Stratum 3+
±3.5 ppb/C
±0.1 ppm
Q
Stratum 3
±10 ppb/C
±0.2 ppm
P
±0.25 ppm
N
Grade
◼
◼
Stratum 3+ grade with ΔF/ΔT of ±3.5 ppb/C is
engineered to provide significantly better performance
than legacy quartz TCXOs in time and phase
synchronization applications such as IEEE1588, small
cells, and 5G C-RAN (cloud RAN).
Stratum 3 grade is designed to replace classic
Stratum 3 TCXOs in applications such as SyncE with
better dynamic performance and shorter lead time.
Output Frequency and Format
The SiT5357 can be factory programmed for an output
frequency without sacrificing lead time or incurring an
upfront customization cost typically associated with customfrequency quartz TCXOs.
Output Frequency Tuning
In addition to the non-pullable TCXO, the SiT5357 can also
support output frequency tuning through either an analog
control voltage (VCTCXO), or I2C interface (DCTCXO). The
I2C interface enables 16 factory programmed pull-range
options from ±6.25 ppm to ±3200 ppm. The pull range can
also be reprogrammed via I2C to any supported pull-range
value.
Refer to Device Configuration section for details.
Page 15 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Pin 1 Configuration (OE, VC, or NC)
Device Configurations
Pin 1 of the SiT5357 can be factory programmed to
support three modes: Output Enable (OE), Voltage Control
(VC), or No Connect (NC).
The SiT5357 supports 3 device configurations – TCXO,
VCTCXO, and DCTCXO. The TCXO and VCTCXO
options are directly compatible with the quartz TCXO and
VCTCXO.
The
DCTCXO
configuration
provides
performance enhancement by eliminating VCTCXO’s
sensitivity to control voltage noise with an I 2C digital
interface for frequency tuning.
Table 13. Pin Configuration Options
Pin 1 Configuration
Operating Mode
Output
OE
TCXO/DCTCXO
Active or High-Z
NC
TCXO/DCTCXO
Active
VC
VCTCXO
Active
When pin 1 is configured as OE pin, the device output is
guaranteed to operate in one of the following two states:
◼
Clock output with the frequency specified in the part
number when Pin 1 is pulled to logic high
◼
Hi-Z mode with weak pull down when pin 1 is pulled to
logic low.
When pin 1 is configured as NC, the device is guaranteed
to output the frequency specified in the part number at all
times, regardless of the logic level on pin 1.
In the VCTCXO configuration, the user can fine-tune the
output frequency from the nominal frequency specified in
the part number by varying the pin 1 voltage. The
guaranteed allowable variation of the output frequency is
specified as pull range. A VCTCXO part number must
contain a valid pull-range ordering code.
Figure 32. Block Diagram – TCXO
TCXO Configuration
The TCXO generates a fixed frequency output, as shown in
Figure 32. The frequency is specified by the user in the
frequency field of the device ordering code and then factory
programmed. Other factory programmable options include
supply voltage, and pin 1 functionality (OE or NC).
Refer to the Ordering Information section at the end of the
datasheet for a list of all ordering options.
Rev 1.06
Page 16 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
VCTCXO Configuration
A VCTCXO, shown in Figure 33, is a frequency control device
whose output frequency is an approximately linear function of
control voltage applied to the voltage control pin. VCTCXOs
have a number of use cases including the VCO portion of a
jitter attenuation/jitter cleaner PLL Loop.
Note that the output frequency of the VCTCXO is
proportional to the analog control voltage applied to
pin 1. Because this control signal is analog and directly
controls the output frequency, care must be taken to
minimize noise on this pin.
The SiT5357 achieves a 10x better pull range linearity of
250
nsec
FM+ (1 MHz)
>0
nsec
FM (400 KHz)
>0
nsec
SM (100 KHz)
>0
nsec
FM+
> 450
nsec
FM (400 KHz)
> 900
nsec
SM (100 KHz)
> 3450
nsec
tHOLD
tVD:AWK
tVD:DAT
Rev 1.06
NA (s-awk + s-data)/(m-awk/s-data)
Page 30 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Table 21. Pin Selectable I2C Address Control[20]
I2C Device Address Modes
A0
Pin 5
There are two I2C address modes:
I2C Address
0
1100010
1
1101010
Notes:
20. Table 21 is only valid for the DCTCXO device option which supports
I2C control and A0 Device Address Control Pin.
Table 20. Factory Programmed I2C Address Control[19]
I2C Address Ordering Code
Device I2C Address
0
1100000
1
1100001
2
1100010
3
1100011
4
1100100
5
1100101
6
1100110
7
1100111
8
1101000
9
1101001
A
1101010
B
1101011
C
1101100
D
1101101
E
1101110
F
1101111
Notes:
19. Table 20 is only valid for the DCTCXO device option which supports
I2C Control.
Rev 1.06
Page 31 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Schematic Example
Figure 46. DCTCXO schematic example
Rev 1.06
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Dimensions and Patterns
Package Size – Dimensions (Unit: mm)
Recommended Land Pattern (Unit: mm)
Rev 1.06
Page 33 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Layout Guidelines
◼
◼
◼
Manufacturing Guidelines
The SiT5357 uses internal regulators to minimize the
impact of power supply noise. For further reduction of
noise, it is essential to use two bypass capacitors
(0.1 μF and 10 μF). Place the 0.1 μF capacitor as
close to the VDD pin as possible, typically within
1 mm to 2 mm. Place the 10 μF capacitor within
2 inches of the device VDD and VSS pins.
It is also recommended to connect all NC pins to the
ground plane and place multiple vias under the GND
pin for maximum heat dissipation.
The SiT5357 Super-TCXOs are precision timing devices.
Proper PCB solder and cleaning processes must be
followed to ensure best performance and long-term
reliability.
◼
No Ultrasonic or Megasonic Cleaning: Do not subject
the SiT5357 to an ultrasonic or megasonic cleaning
environment. Otherwise, permanent damage or long-term
reliability issues to the device may result.
◼
No external cover. Unlike legacy quartz TCXOs, the
SiT5357 is engineered to operate reliably, without
performance degradation in the presence of ambient
disturbers such as airflow and sudden temperature
changes. Therefore, the use of an external cover
typically required by quartz TCXOs is not needed.
◼
Reflow profile: For mounting these devices to the PCB,
IPC/JEDEC J-STD-020 compliant reflow profile must be
used. Device performance is not guaranteed if soldered
manually or with a non-compliant reflow profile.
◼
PCB cleaning: After the surface mount (SMT)/reflow
process, solder flux residues may be present on the PCB
and around the pads of the device. Excess residual
solder flux may lead to problems such as pad corrosion,
elevated leakage currents, increased frequency aging, or
other performance degradation. For optimal device
performance and long-term reliability, thorough cleaning
to remove all the residual flux and drying of the PCB is
required as shortly after the reflow process as possible.
Water soluble flux is recommended. In addition, it is
highly recommended to avoid the use of any “no clean”
flux. However, if the reflow process necessitates the use
of “no clean” flux, then utmost care should be taken to
remove all residual flux between SiTime device and the
PCB. Note that ultrasonic PCB cleaning should not be
used with SiTime oscillators.
◼
For additional manufacturing guidelines and marking/
tape-reel instructions, refer to SiTime Manufacturing
Notes.
For additional layout recommendations, refer to the
Best Design Layout Practices.
Rev 1.06
Page 34 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Additional Information
Table 22. Additional Information
Document
Description
Download Link
ECCN #: EAR99
Five character designation used on the commerce
Control List (CCL) to identify dual use items for
export control purposes.
—
HTS Classification Code:
8542.39.0000
A Harmonized Tariff Schedule (HTS) code
developed by the World Customs Organization to
classify/define internationally traded goods.
—
Evaluation Boards
SiT6722EB Evaluation Board User Manual
https://www.sitime.com/support/user-guides
Demo Board
SiT6702DB Demo Board User Manual
https://www.sitime.com/support/user-guides
Time Machine II
MEMS oscillator programmer
http://www.sitime.com/support/time-machine-oscillator-programmer
Time Master Web-based
Configurator
Web tool to establish proper programming
https://www.sitime.com/time-master-web-based-configurator
Manufacturing Notes
Tape & Reel dimension, reflow profile and other
manufacturing related info
https://www.sitime.com/support/resource-library?filter=531
Qualification Reports
RoHS report, reliability reports, composition reports
http://www.sitime.com/support/quality-and-reliability
Performance Reports
Additional performance data such as phase noise,
current consumption and jitter for selected
frequencies
http://www.sitime.com/support/performance-measurement-report
Termination Techniques
Termination design recommendations
http://www.sitime.com/support/application-notes
Layout Techniques
Layout recommendations
http://www.sitime.com/support/application-notes
Rev 1.06
Page 35 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
Revision History
Table 23. Revision History
Version
Release Date
0.1
05/10/2016
First release, advanced information
0.15
08/04/2016
Replaced QFN package with SOIC-8 package
Added 10 µF bypass cap requirement
Updated test circuits to reflect both new bypass cap requirement and SOIC-8 package
Update Table 1 (Electrical Characteristics)
0.16
09/12/2016
Updated test circuit diagrams
0.2
09/21/2016
Revised Table 1 (Electrical Characteristics)
0.51
08/20/2017
Changed to preliminary
Added DCTCXO mode
Added I2C information
Added 5.0 mm x 3.2 mm package information
Updated test circuits
Updated Table 1 (Electrical Characteristics)
Updated part ordering info
Misc. corrections
0.52
11/27/2017
Updated the Thermal Characteristics table
Added more on Manufacturing Guideline section
0.55
02/05/2018
Added View labels to Package Drawings
Updated links and notes
0.60
03/01/2018
1.0
06/26/2018
1.01
1.02
1.03
07/03/2018
07/04/2018
08/02/2018
1.04
12/04/2018
1.05
03/28/2020
1.06
05/10/2020
Added 105°C support, updated Ordering Information
Updated Electrical Characteristics tables.
Added Typical Performance Plots.
Improved readability.
Fixed bad hyperlinks.
Updated I2C specifications, Table 3 (Input Characteristics).
Updated Mechanical Shock Resistance, Table 9 (Environmental Compliance).
Various formatting updates.
Updated package outline drawing.
Revised phase noise specifications.
Updated conditions for one day and one year aging specs.
Formatting updates
Corrected typos in package drawing dimensions
Added nominal value for LVCMOS output impedance
Increased Mechanical Shock Resistance to 30000g
Added “X” order code for 250u Tape and Reel
Improved 24 hour holdover stability specification for 0.2 and 0.25 ppm parts
Improved I2C bus frequency specification
Updated Manufacturing Guidelines to recommend water soluble flux
Corrected typos for write/read I2C polarity
Clarified PCB cleaning instructions
Added link for SiT6702DB
Added ECCN and HTS codes
Reduced Initial Tolerance for Stratum 3+ grade
Modified supply and load sensitivities
Updated typical performance plot for load sensitivity
Formatting updates
Added note to Theta Ja
Changed conditions for 24-hour holdover stability spec
Added Allan deviation spec and updated typical plot
Updated DCTCXO Delay and Settling Time table
Removed frequency support from 200 to 208 MHz
Added 5 and 10 year aging specs for Stratum 3+ grade
Added max and min aging specs for 1 and 20 years for Stratum 3+ grade, and changed ambient temperature to 85°C
Slightly reduced minimum pull range specs and updated Tables 14 and 15 for Stratum 3+ grade
Added max and min hysteresis specs for Stratum 3+ grade, clarified conditions with related figure
Clarified 24-hour holdover stability spec condition
Added max and min input voltage to Absolute Maximum Limits table
Updated output impedance typical spec
Updated ΔF/ΔT and F_dynamic min and max specs
Clarified Initial Tolerance specification condition
Relabeled “First Pulse Accuracy” parameter to “Time to Rated Frequency Stability” for clarity
Revised Parallel Data Format section description and figures
Rev 1.06
Change Summary
Page 36 of 37
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SiT5357 60 MHz – 220 MHz, ±0.1 to ±0.25 ppm, Stratum 3, Elite Platform™ Precision Super-TCXO
SiTime Corporation, 5451 Patrick Henry Drive, Santa Clara, CA 95054, USA | Phone: +1-408-328-4400 | Fax: +1-408-328-4439
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or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect
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Rev 1.06
Page 37 of 37
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