SIT8919BE-32-18E-125.003125 数据手册
SiT8919B
High Frequency, High Temperature Oscillator
Features
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Applications
Frequencies between 115.194001 MHz to 137 MHz accurate
to 6 decimal places
Operating temperature from -40°C to 125°C. For -55°C option,
refer to SiT8920 and SiT8921
Supply voltage of 1.8 V or 2.5 V to 3.3 V
Excellent total frequency stability as low as ±20 ppm
Low power consumption of 4.9 mA typical at 1.8 V
LVCMOS/LVTTL compatible output
Industry-standard packages: 2.0 x 1.6, 2.5 x 2.0, 3.2 x 2.5,
5.0 x 3.2, 7.0 x 5.0 mm x mm
Instant samples with Time Machine II and Field Programmable
oscillators
RoHS and REACH compliant, Pb-free, Halogen-free and
Antimony-free
For AEC-Q100 oscillators, refer to SiT8924 and SiT8925
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Industrial, medical, non AEC-Q100 automotive, avionics
and other high temperature applications
Industrial sensors, PLC, motor servo, outdoor
networking equipment, medical video cam, asset
tracking systems, etc.
Electrical Characteristics
Table 1. Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise stated.
Typical values are at 25°C and nominal supply voltage.
Parameters
Symbol
Min.
Typ.
Max.
Condition
Unit
Frequency Range
Output Frequency Range
f
115.194001
–
137
MHz
Refer to Table 13 for the exact list of supported frequencies
list of supported frequencies
Frequency Stability and Aging
Frequency Stability
F_stab
-20
–
+20
ppm
-25
–
+25
ppm
-30
–
+30
ppm
-50
–
+50
ppm
Inclusive of Initial tolerance at 25°C, 1st year aging at 25°C,
and variations over operating temperature, rated power
supply voltage and load (15 pF ±10%).
Operating Temperature Range
Operating Temperature
Range (ambient)
T_use
-40
-40
–
+105
°C
Extended Industrial
–
+125
°C
Automotive
Supply Voltage and Current Consumption
Supply Voltage
Current Consumption
OE Disable Current
Standby Current
Rev 1.02
Vdd
Idd
I_od
I_std
1.62
1.8
1.98
V
2.25
2.5
2.75
V
2.52
2.8
3.08
V
2.7
3.0
3.3
V
2.97
3.3
3.63
V
2.25
–
3.63
V
–
6.2
8
mA
No load condition, f = 125 MHz, Vdd = 2.8 V, 3.0 V or 3.3 V
–
5.4
7
mA
No load condition, f = 125 MHz, Vdd = 2.5 V
–
4.9
6
mA
No load condition, f = 125 MHz, Vdd = 1.8 V
–
–
4.7
mA
Vdd = 2.5 V to 3.3 V, OE = Low, Output in high Z state
–
–
4.5
mA
Vdd = 1.8 V, OE = Low, Output in high Z state
–
2.6
8.5
A
Vdd = 2.8 V to 3.3 V, ST
̅ ̅ ̅ = Low, Output is weakly pulled down
–
1.4
5.5
A
Vdd = 2.5 V, ST
̅ ̅ ̅ = Low, Output is weakly pulled down
–
0.6
4.0
A
Vdd = 1.8 V, ST
̅ ̅ ̅ = Low, Output is weakly pulled down
10 March 2021
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SiT8919B High Frequency, High Temperature Oscillator
Table 1. Electrical Characteristics (continued)
Parameters
Symbol
Min.
Typ.
Max.
Unit
Condition
LVCMOS Output Characteristics
Duty Cycle
Rise/Fall Time
DC
45
–
55
%
All Vdds
Tr, Tf
–
1.0
2.0
ns
Vdd = 2.5 V, 2.8 V, 3.0 V or 3.3 V, 20% - 80%
–
1.3
2.5
ns
Vdd = 1.8 V, 20% - 80%
–
1.0
3
ns
Vdd = 2.25 V - 3.63 V, 20% - 80%
IOH = -4 mA (Vdd = 3.0 V or 3.3 V)
IOH = -3 mA (Vdd = 2.8 V or 2.5 V)
IOH = -2 mA (Vdd = 1.8 V)
IOL = 4 mA (Vdd = 3.0 V or 3.3 V)
IOL = 3 mA (Vdd = 2.8 V or 2.5 V)
IOL = 2 mA (Vdd = 1.8 V)
Output High Voltage
VOH
90%
–
–
Vdd
Output Low Voltage
VOL
–
–
10%
Vdd
Input High Voltage
VIH
70%
–
Input Low Voltage
VIL
–
–
30%
Vdd
Pin 1, OE or ST
̅ ̅̅
Input Pull-up Impedance
Z_in
50
87
150
k
Pin 1, OE logic high or logic low, or ST
̅ ̅ ̅ logic high
2
–
–
M
Pin 1, ST
̅ ̅ ̅ logic low
Input Characteristics
–
Vdd
Pin 1, OE or ST
̅ ̅̅
Startup and Resume Timing
T_start
–
–
5
ms
T_oe
–
–
130
ns
T_resume
–
–
5
ms
Measured from the time Vdd reaches its rated minimum value
f = 115.194001 MHz. For other frequencies,
T_oe = 100 ns + 3 * clock periods
Measured from the time ST
̅ ̅ ̅ pin crosses 50% threshold
Startup Time
Enable/Disable Time
Resume Time
Jitter
RMS Period Jitter
T_jitt
Peak-to-peak Period Jitter
T_pk
RMS Phase Jitter (random)
T_phj
–
1.6
2.5
ps
f = 125 MHz, Vdd = 2.5 V, 2.8 V, 3.0 V or 3.3 V
–
1.8
3
ps
f = 125 MHz, Vdd = 1.8 V
–
12
20
ps
f = 125 MHz, Vdd = 2.5 V, 2.8 V, 3.0 V or 3.3 V
–
14
30
ps
f = 125 MHz, Vdd = 1.8 V
–
0.5
0.8
ps
f = 125 MHz, Integration bandwidth = 900 kHz to 7.5 MHz
–
1.3
2
ps
f = 125 MHz, Integration bandwidth = 12 kHz to 20 MHz
Table 2. Pin Description
Pin
Symbol
Top View
Functionality
[1]
Output Enable
1
OE/ST
̅ ̅ ̅ /NC
Standby
H : specified frequency output
L: output is high impedance. Only output driver is disabled.
H[1]: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode.
Supply current reduces to I_std.
2
GND
Power
Any voltage between 0 and Vdd or Open[1]: Specified
frequency output. Pin 1 has no function.
Electrical ground
3
OUT
Output
Oscillator output
4
VDD
Power
Power supply voltage[2]
No Connect
OE/ST
̅ ̅ ̅ /NC
VDD
GND
OUT
Figure 1. Pin Assignments
Notes:
1. In OE or ST
̅ ̅ ̅ mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the
NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Rev 1.02
Page 2 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Table 3. Absolute Maximum Limits
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Min.
Max.
Unit
Storage Temperature
Parameter
-65
150
°C
VDD
-0.5
4
V
Electrostatic Discharge
–
2000
V
Soldering Temperature (follow standard Pb free soldering guidelines)
–
260
°C
Junction Temperature[3]
–
150
°C
Note:
3.
Exceeding this temperature for extended period of time may damage the device.
Table 4. Thermal Consideration[4]
JA, 4 Layer Board (°C/W)
Package
Note:
4.
JA, 2 Layer Board (°C/W)
JC, Bottom (°C/W)
7050
142
273
30
5032
97
199
24
3225
109
212
27
2520
117
222
26
2016
152
252
36
Refer to JESD51-7 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
Table 5. Maximum Operating Junction Temperature[5]
Max Operating Temperature (ambient)
Note:
5.
Maximum Operating Junction Temperature
105°C
115°C
125°C
135°C
Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Table 6. Environmental Compliance
Parameter
Condition/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002
Mechanical Vibration
MIL-STD-883F, Method 2007
Temperature Cycle
JESD22, Method A104
Solderability
MIL-STD-883F, Method 2003
Moisture Sensitivity Level
MSL1 @ 260°C
Rev 1.02
Page 3 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Test Circuit and Waveform[6]
Vdd
Vout
Test Point
tr
Power
Supply
4
3
1
2
tf
80% Vdd
15pF
(including probe
and fixture
capacitance)
0.1 uF
50%
20% Vdd
High Pulse
(TH)
Vdd
Period
1 kΩ
OE/ST Function
Low Pulse
(TL)
Figure 3. Waveform
Figure 2. Test Circuit
Notes:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagram
90% Vdd
Vdd
Vdd
50% Vdd
[7]
T_start
Pin 4 Voltage
T_resume
ST Voltage
No Glitch
during start up
CLK Output
CLK Output
HZ
HZ
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ ST
̅ ̅ ̅ Mode)
Figure 5. Standby Resume Timing ( ST
̅ ̅ ̅ Mode Only)
Vdd
Vdd
50% Vdd
OE Voltage
50% Vdd
T_oe
OE Voltage
T_oe
CLK Output
CLK Output
HZ
HZ
T_oe: Time to re-enable the clock output
T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Note:
7.
Figure 7. OE Disable Timing (OE Mode Only)
SiT8919 has “no runt” pulses and “no glitch” output during startup or resume.
Rev 1.02
Page 4 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Idd (mA)
Frequency (ppm)
Performance Plots[8]
Figure 8. Idd vs Frequency
Figure 9. Frequency vs Temperature
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
55
54
Duty cycle (%)
RMS period jitter (ps)
53
52
51
50
49
48
47
46
45
115
Figure 10. RMS Period Jitter vs Frequency
1.8 V
2.5 V
2.8 V
3.0 V
117
119
121
123
125
127
129
131
133
135
137
Figure 11. Duty Cycle vs Frequency
1.8 V
3.3 V
2.5 V
2.8 V
3.0 V
3.3 V
2.5
Fall time (ns)
Rise time (ns)
2.0
1.5
1.0
0.5
0.0
-55 -45 -35 -25 -15
Figure 12. 20%-80% Rise Time vs Temperature
(125 MHz Output)
Rev 1.02
-5
5
15
25
35
45
55
65
75
85
95 105 115 125
Figure 13. 20%-80% Fall Time vs Temperature
(125 MHz Output)
Page 5 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Performance Plots[8]
2.8 V
3.0 V
3.3 V
IPJ (ps)
2.5 V
IPJ (ps)
1.8 V
Figure 15. RMS Integrated Phase Jitter Random
(900 kHz to 20 MHz) vs Frequency[9]
Figure 14. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency[9]
Notes:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
9. Phase noise plots are measured with Agilent E5052B signal source analyzer.
Rev 1.02
Page 6 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Programmable Drive Strength
The SiT8919 includes a programmable drive strength feature
to provide a simple, flexible tool to optimize the clock rise/fall
time for specific applications. Benefits from the programmable
drive strength feature are:
◼
Improves system radiated electromagnetic interference
(EMI) by slowing down the clock rise/fall time
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Improves the downstream clock receiver’s (RX) jitter by
decreasing (speeding up) the clock rise/fall time.
◼
Ability to drive large capacitive loads while maintaining full
swing with sharp edge rates.
For more detailed information about rise/fall time control and
drive strength selection, see the SiTime Applications Note
section.
EMI Reduction by Slowing Rise/Fall Time
Figure 16 shows the harmonic power reduction as the rise/fall
times are increased (slowed down). The rise/fall times are
expressed as a ratio of the clock period. For the ratio of 0.05,
the signal is very close to a square wave. For the ratio of 0.45,
the rise/fall times are very close to near-triangular waveform.
These results, for example, show that the 11th clock harmonic
can be reduced by 35 dB if the rise/fall edge is increased from
5% of the period to 45% of the period.
trise=0.05
trise=0.1
trise=0.15
trise=0.2
trise=0.25
trise=0.3
trise=0.35
trise=0.4
trise=0.45
10
Harmonic amplitude (dB)
0
-10
-20
The SiT8919 can support up to 30 pF or higher in
maximum capacitive loads with up to 3 additional drive
strength settings. Refer to the Rise/Tall Time Tables
(Tables 7 to 11) to determine the proper drive strength
for the desired combination of output load vs. rise/fall
time.
SiT8919 Drive Strength Selection
Tables 7 through 11 define the rise/fall time for a given
capacitive load and supply voltage.
1. Select the table that matches the SiT8919 nominal
supply voltage (1.8 V, 2.5 V, 2.8 V, 3.0 V, 3.3 V).
2. Select the capacitive load column that matches
the application requirement (5 pF to 30 pF)
3. Under the capacitive load column, select the
desired rise/fall times.
4. The left-most column represents the part number
code for the corresponding drive strength.
5. Add the drive strength code to the part number for
ordering purposes.
Calculating Maximum Frequency
Based on the rise and fall time data given in Tables 7
through 11, the maximum frequency the oscillator can
operate with guaranteed full swing of the output voltage
over temperature as follows:
Max Frequency =
-30
1
5 x T rf_20/80
where Trf_20/80 is the typical value for 20%-80% rise/fall
time.
-40
-50
-60
-70
-80
1
3
5
7
9
11
Harmonic number
Figure 16. Harmonic EMI reduction as a Function
of Slower Rise/Fall Time
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the
downstream chipset. One way to reduce this jitter is to speed
up the rise/fall time of the input clock. Some chipsets may also
require faster rise/fall time in order to reduce their sensitivity to
this type of jitter. Refer to the Rise/Fall Time Tables (Table 7
to 11) to determine the proper drive strength.
Example 1
Calculate fMAX for the following condition:
◼
Vdd = 3.3 V (Table 11)
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Capacitive Load: 30 pF
◼
Desired Tr/f time = 1.46 ns (rise/fall time part
number code = U)
Part number for the above example:
SiT8919BAU12-33E-136.986300
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of the
actual capacitive load the clock drives. At any given drive
strength, the rise/fall time becomes slower as the output load
increases. As an example, for a 3.3 V SiT8919 device with
default drive strength setting, the typical rise/fall time is 0.46
ns for 5 pF output load. The typical rise/fall time slows down
to 1 ns when the output load increases to 15 pF. One can
choose to speed up the rise/fall time to 0.72 ns by then
increasing the driven strength setting on the SiT8919 to “F.”
Rev 1.02
Page 7 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Rise/Fall Time (20% to 80%) vs CLOAD Tables
Table 7. Vdd = 1.8 V Rise/Fall Times
for Specific CLOAD
Table 8. Vdd = 2.5 V Rise/Fall Times
for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
T
E
0.93
0.78
n/a
n/a
n/a
n/a
U
F or "-": default
0.70
0.65
1.48
1.30
n/a
n/a
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.45
n/a
n/a
B
T
E
1.09
0.62
n/a
1.28
n/a
n/a
0.54
1.00
n/a
U or "-": default
F
0.43
0.34
0.96
0.88
n/a
n/a
Table 10. Vdd = 3.0 V Rise/Fall Times
for Specific CLOAD
Table 9. Vdd = 2.8 V Rise/Fall Times
for Specific CLOAD
Rise/Fall Time Typ (ns)
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.22
n/a
n/a
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
B
1.29
0.97
0.55
n/a
n/a
1.12
n/a
n/a
n/a
B
T or "-": default
0.89
n/a
n/a
0.51
1.00
n/a
0.44
0.34
0.29
1.00
0.88
0.81
n/a
n/a
1.48
E
0.38
0.92
n/a
U
F
0.30
0.83
n/a
0.27
0.76
1.39
T
E
U or "-": default
F
Table 11. Vdd = 3.3 V Rise/Fall Times
for Specific CLOAD
Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD
5 pF
15 pF
30 pF
R
1.16
n/a
n/a
B
T or "-": default
0.81
n/a
n/a
0.46
0.33
1.00
0.87
n/a
n/a
0.28
0.79
1.46
0.25
0.72
1.31
E
U
F
Note:
10. “n/a” in Table 7 to Table 11 indicates that the resulting rise/fall time from the respective combination of the drive strength and output load does not
provide rail-to-rail swing and is not available.
Rev 1.02
Page 8 of 18
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SiT8919B High Frequency, High Temperature Oscillator
Pin 1 Configuration Options
(OE, ST
̅ ̅ ̅ , or NC)
Pin 1 of the SiT8919 can be factory-programmed to support
three modes: Output enable (OE), standby (ST
̅ ̅ ̅ ) or No
Connect (NC). These modes can also be programmed with
the Time Machine using field programmable devices.
Vdd
Output Enable (OE) Mode
Clock Output
In the OE mode, applying logic Low to the OE pin only
disables the output driver and puts it in Hi-Z mode. The core
of the device continues to operate normally. Power
consumption is reduced due to the inactivity of the output.
When the OE pin is pulled High, the output is typically
enabled in