TH58BVG3S0HTAI0
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
8 GBIT (1G × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TH58BVG3S0HTAI0 is a single 3.3V 8Gbit (8,858,370,048 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 128) bytes × 64 pages × 4096 blocks.
The device has a 4224-byte static register which allows program and read data to be transferred between the register
and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block unit
(256 Kbytes + 8 Kbytes: 4224 bytes × 64 pages).
The TH58BVG3S0HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
The TH58BVG3S0HTAI0 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected
internally.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
x8
4224 × 128K × 8 × 2
4224 × 8
4224 bytes
(256K + 8K) bytes
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Read, Multi Page Program, Multi Block Erase, ECC Status Read
•
Mode control
Serial input/output
Command control
•
Number of valid blocks
Min 4016 blocks
Max 4096 blocks
• Power supply
VCC = 2.7V to 3.6V
•
Access time
Cell array to register 55 µs typ. (Single Page Read) / 90 µs typ. (Multi Page Read)
Read Cycle Time
25 ns min (CL=50pF)
•
Program/Erase time
Auto Page Program
Auto Block Erase
340 µs/page typ.
2.5 ms/block typ.
•
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max
30 mA max
30 mA max
100 µA max
•
Package
TSOP I 48-P-1220-0.50 (Weight: 0.54 g typ.)
•
8bit ECC for each 528Byte is implemented on the chip.
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PIN ASSIGNMENT (TOP VIEW)
TH58BVG3S0HTAI0
×8
NC
NC
NC
NC
NC
NC
NC
NC
VCC
VSS
NC
NC
CLE
ALE
NC
NC
NC
NC
NC
×8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
VCC
VSS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
PIN NAMES
I/O1 to I/O8
© 2013-2018 Toshiba Memory Corporation
I/O port
CE
Chip enable
WE
Write enable
RE
Read enable
CLE
Command latch enable
ALE
Address latch enable
WP
Write protect
RY/BY
Ready/Busy
VCC
Power supply
VSS
Ground
NC
No Connection
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BLOCK DIAGRAM
ECC Logic
Data register 1
VCC VSS
Status register
Address register
I/O1
to
Column buffer
I/O
Control circuit
Column decoder
I/O8
Command register
Data register 0
CLE
ALE
Logic control
Control circuit
Row address decoder
Row address buffer
decoder
Sense amp
Memory cell array
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
RATING
VALUE
UNIT
VCC
Power Supply Voltage
−0.6 to 4.6
V
VIN
Input Voltage
−0.6 to 4.6
V
VI/O
Input /Output Voltage
−0.6 to VCC + 0.3 (≤ 4.6 V)
V
PD
Power Dissipation
0.3
W
TSOLDER
Soldering Temperature (10 s)
260
°C
TSTG
Storage Temperature
−55 to 150
°C
TOPR
Operating Temperature
-40 to 85
°C
CAPACITANCE *(Ta = 25°C, f = 1 MHz)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
CIN
Input
VIN = 0 V
20
pF
COUT
Output
VOUT = 0 V
20
pF
*
This parameter is periodically sampled and is not tested for every device.
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VALID BLOCKS
SYMBOL
NVB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
TYP.
MAX
UNIT
4016
4096
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
2.7
3.6
V
VCC
Power Supply Voltage
VIH
High Level Input Voltage
VCC x 0.8
VCC + 0.3
V
VIL
Low Level Input Voltage
−0.3*
VCC x 0.2
V
−2 V (pulse width lower than 20 ns)
*
DC CHARACTERISTICS (Ta = -40 to 85°C, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
CONDITION
MIN
TYP.
MAX
UNIT
IIL
Input Leakage Current
VIN = 0 V to VCC
±20
µA
ILO
Output Leakage Current
VOUT = 0 V to VCC
±20
µA
ICCO1
Serial Read Current
CE = VIL, IOUT = 0 mA, tRC = 25 ns
30
mA
ICCO2
Programming Current
30
mA
ICCO3
Erasing Current
30
mA
ICCS
Standby Current
CE = VCC − 0.2 V, WP = 0 V/VCC
100
µA
VOH
High Level Output Voltage
IOH = −0.1 mA
VCC – 0.2
V
VOL
Low Level Output Voltage
IOL = 0.1 mA
0.2
V
IOL
( RY / BY )
Output Current of RY / BY pin VOL = 0.2 V
4
mA
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AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = -40 to 85°C, VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
12
ns
tCLH
CLE Hold Time
5
ns
tCS
CE Setup Time
20
ns
tCH
CE Hold Time
5
ns
tWP
Write Pulse Width
12
ns
tALS
ALE Setup Time
12
ns
tALH
ALE Hold Time
5
ns
tDS
Data Setup Time
12
ns
tDH
Data Hold Time
5
ns
tWC
Write Cycle Time
25
ns
tWH
WE High Hold Time
10
ns
tWW
WP High to WE Low
100
ns
tRR
Ready to RE Falling Edge
20
ns
tRW
Ready to WE Falling Edge
20
ns
tRP
Read Pulse Width
12
ns
tRC
Read Cycle Time
25
ns
tREA
RE Access Time
20
ns
tCEA
CE Access Time
25
ns
tCLR
CLE Low to RE Low
10
ns
tAR
ALE Low to RE Low
10
ns
tRHOH
RE High to Output Hold Time
25
ns
tRLOH
RE Low to Output Hold Time
5
ns
tRHZ
RE High to Output High Impedance
60
ns
tCHZ
CE High to Output High Impedance
20
ns
tCSD
CE High to ALE or CLE Don’t Care
0
ns
tREH
RE High Hold Time
10
ns
tIR
Output-High-Impedance-to- RE Falling Edge
0
ns
tRHW
RE High to WE Low
30
ns
tWHC
WE High to CE Low
30
ns
tWHR
WE High to RE Low
60
ns
tWB
WE High to Busy
100
ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
5/5/10/500
µs
*1: tCLS and tALS can not be shorter than tWP.
*2: tCS should be longer than tWP + 8ns.
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AC TEST CONDITIONS
CONDITION
PARAMETER
VCC: 2.7 to 3.6V
Input level
VCC-0.2V, 0.2V
Input pulse rise and fall time
3 ns
Input comparison level
VCC / 2
Output data comparison level
VCC / 2
Output load
Note:
CL (50 pF) + 1 TTL
Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document)
PROGRAMMING / ERASING / READING CHARACTERISTICS
(Ta = -40 to 85°C, VCC = 2.7 to 3.6V)
SYMBOL
MIN
TYP.
MAX
UNIT
Average Programming Time (Single Page)
340
700
µs
Average Programming Time (Multi Page)
370
700
µs
tDCBSYW1
Busy Time in Multi Page Program(following 11h)
0.5
1
µs
N
Number of Partial Program Cycles in the Same Page
4
tBERASE
Block Erasing Time
2.5
5
Memory Cell Array to Starting Address (Single Page)
55
220
Memory Cell Array to Starting Address (Multi Page)
90
420
tPROG
tR
PARAMETER
NOTES
(1)
ms
µs
(1) Refer to Application Note (12) toward the end of this document.
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on
tRHOH (25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend
on tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE, ALE, /CE or
falling edge of /WE, and waveforms look like Extended Data Output Mode.
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TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
CLE
ALE
Setup Time
Hold Time
tDS
tDH
I/O
: VIH or VIL
Command Input Cycle Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
ALE
tDS
tDH
I/O
: VIH or VIL
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Address Input Cycle Timing Diagram
tCLH
tCLS
CLE
tCH
tCS
tWP
tCS
tWH
tWC
tWP
tWH
tWP
tWC
tWH
tWP
tCH
tWH
tWP
tALS
tALH
ALE
tDS
I/O
tDH
tDS
CA0 to 7
tDH
tDS
CA8 to 12
tDH
tDS
PA0 to 7
tDH
tDS
PA8 to 15
tDH
PA16 to 17
: VIH or VIL
Data Input Cycle Timing Diagram
tCLS
tCLH
CLE
tCH
tCS
tCS
tCH
tALS
tALH
tWC
ALE
tWP
tWH
tDS
I/O
© 2013-2018 Toshiba Memory Corporation
tWP
tDH
tWP
tDS
DIN0
tDH
DIN1
8
tDS
tDH
DIN4223
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Serial Read Cycle Timing Diagram
tRC
tRP
tREA
I/O
tREH
tRHZ
tRHOH
tRP
tREA
tCHZ
tRP
tRHZ
tRHZ
tRHOH
tREA
tRHOH
tCEA
tCEA
tRR
: VIH or VIL
Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
tWP
tCH
tCEA
tCHZ
tWHC
tWHR
tDS
tDH
tRHOH
tIR
tREA
I/O
70h/71h*
: VIH or VIL
*: 70h/71h represents the hexadecimal number
© 2013-2018 Toshiba Memory Corporation
tRHZ
Status
output
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ECC Status Read Cycle Timing Diagram
tCLR
CLE
tCLS
tCLH
tCS
tWP
tCH
tCEA
tWHC
tWHR
tDS
tDH
tIR
tREA
I/O
7Ah*
Status
output
Sector1
tREA
Status
output
Sector2
tREA
Status
output
Sector3
tREA
Status
output
Sector4
tREA
Status
output
Sector8
: VIH or VIL
*: ECC Status output should be read for all 8 sector information.
**: 7Ah command can be input to the device from [after RY/BY returns to High] to [before Dout or Next command input].
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Read Cycle Timing Diagram
tCLR
CLE
tCLS tCLH
tCLS tCLH
tCS
tCS
tCH
tCLR
tCH
tWC
tALH
tALS
tALH
tALS
ALE
tRC
tR
tWB
tDS tDH
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
00h
I/O
CA8
to 12
PA0
to 7
PA8
to 15
tDS tDH
PA16
to 17
tREA
70h
30h
tREA
status
output
DOUT
N
00h
Data out from
Col. Add. N
Col. Add. N
Read Cycle Timing Diagram: When Interrupted by CE
tCLR
tCLR
CLE
tCLS
tCLH
tCLS
tCLH
tCS
tCH
tCS
tCH
tWC
tALH
tCSD
tALS
tALH
tALS
ALE
tR
tRC
tWB
tDS tDH
I/O
00h
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
CA0
to 7
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 17
30h
tRHZ
tREA
tREA
70h
tRHOH
status
output
00h
DOUT
N
DOUT
N+1
Data out from
Col. Add. N
Col. Add. N
© 2013-2018 Toshiba Memory Corporation
tDS tDH
tCHZ
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Column Address Change in Read Cycle Timing Diagram (1/2)
tCLR
tCLR
CLE
tCLS tCLH
tCS
tCLS tCLH
tCH
tCH
tCS
tWC
tALH tALS
tALH
tALS
ALE
tR
tRC
tWB
I/O
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
tDS tDH
00h
CA0
to 7
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 17
30h
Column address
A
tREA
70h
Status
Output
00h
DOUT DOUT
A
A+1
DOUT
A+N
Page address
P
Page address
P
Data out from
Column address A
1
Continues to
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Column Address Change in Read Cycle Timing Diagram (2/2)
tCLR
CLE
tCLS tCLH
tCS
tCLS
tCH
tCS
tRHW
tCLH
tCH
tCEA
tWC
tALH
tALS
tALH
tALS
ALE
tWHR
tDS tDH
DOUT
A+N
I/O
tDS tDH
tDS tDH
tDS tDH
tRC
tREA
tIR
CA0
to 7
05h
CA8
to 12
DOUT
B
E0h
DOUT
B+1
DOUT
B + N’
Page address
P
Column address
B
Data out from
Column address B
1
Continues from 1
of previous page
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Data Output Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tALH
ALE
tRC
tRP
tCHZ
tREH
tREA
tCEA
Dout
tRR
tDS tDH
tRLOH
Dout
tRHOH
© 2013-2018 Toshiba Memory Corporation
tRHZ
tREA
tRLOH
tREA
I/O
tRP
tRP
Dout
Command
tRHOH
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Auto-Program Operation Timing Diagram
CLE
tCLS
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tPROG
tWB
tALS
tRW
ALE
I/O
tDS
tDS
tDS tDH
tDS tDH
80h
CA0
to 7
tDH
tDH
CA8
to 12
PA0
to 7
PA8 PA16
to 15 to 17
DINN
DIN
N+1
DINM*
10h
70h
Status
output
Column address
N
: Do not input data while data is being output.
: VIH or VIL
*) M: up to 4223
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Multi-Page Program Operation Timing Diagram (1/2)
tCLS
CLE
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tDCBSYW1
tALS
tWB
ALE
tDS tDH
I/O
80h
tDS
tDS tDH
CA0
to 7
tDS
tDH
tDH
CA8
to 12
PA0
to 7
PA8
to 15
PA16
to 17
DINN
DIN
N+1
Page Address M
District-0
11h
81h
CA0
to 7
DIN4223
: Do not input data while data is being output.
: VIH or VIL
1
Continues to 1 of next page
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Multi-Page Program Operation Timing Diagram (2/2)
tCLS
CLE
tCLS tCLH
tCS
tCS
tCH
tALH
tALH
tALS
tPROG
tALS
tWB
ALE
tDS
tDS tDH
tDS tDH
81h
CA0
to 7
I/O
CA8
to 12
PA0
PA8 PA16
to 7
to 15 to 17
Page Address M
District-1
DINN
tDS
tDH
tDH
DIN
N+1
10h
71h
Status
output
DIN4223
: Do not input data while data is being output.
: VIH or VIL
1
Continues from
1 of previous page
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Auto Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
tALH
tALS
tWB
tBERASE
ALE
tDS tDH
I/O
60h
PA0
to 7
PA8
to 15
Auto Block
Erase Setup
command
: VIH or VIL
© 2013-2018 Toshiba Memory Corporation
PA16
to 17
D0h
Erase Start
command
70h
Busy
Status
output
Status Read
command
: Do not input data while data is being output.
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Multi Block Erase Timing Diagram
CLE
tCLS
tCLH
tCS
tCLS
tALH
tALS
tWB
tBERASE
ALE
tDS tDH
I/O
60h
PA0
to 7
PA8
to 15
PA16
to 17
Auto Block
Erase Setup
command
D0h
71h
Erase Start
command
Busy
Status
output
Status Read
command
Repeat 2 times (District-0,1)
: VIH or VIL
: Do not input data while data is being output.
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RY/BY
I/Ox
RE
ALE
WE
CE
CLE
00h
tWC
Column Address
Row Address
Col
Col Row Row Row
35h
Add1 Add2 Add1 Add2 Add3
tWB
70h I/O 00h
Data1
I/O1=0 Successful Read
I/O1=1 Error in Read
Busy
tR
Copy Back Program with Random Data Input
DataN
Column Address
Row Address
Col
Col Row Row Row
Add1 Add2 Add1 Add2 Add3
Copy Back Program Data
Input Command
85h
Data1
DataN
10h
tWB
70h
tWHR
I/O
I/O1=0 Successful Program
I/O1=1 Error in Program
Busy
Status Read command
tPROG
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ID Read Operation Timing Diagram
tCLS
CLE
tCLS
tCS
tCS
tCH
tCEA
tCH
tALH
tALH
tALS
tAR
ALE
tDH
tDS
I/O
tREA
tREA
tREA
tREA
tREA
90h
00h
98h
D3h
See
Table 5
See
Table 5
See
Table 5
ID Read
command
Address
00
Maker code
Device code
3rd Data
4th Data
5th Data
: VIH or VIL
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PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE
The device goes into a low-power Standby mode when CE goes High during the device is in Ready state.
The CE signal is ignored when device is in Busy state ( RY / BY = L), such as during a Program, Erase or
Read operation, and will not enter Standby mode even if the CE input goes High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available tREA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to
be pulled-up to VCC with an appropriate resistor.
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Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
I/O1
Data Cache
4096
128
Page Buffer
4096
128
I/O8
A page consists of 4224 bytes in which 4096 bytes are
used for main memory storage and 128 bytes are for
redundancy or for other uses.
1 page = 4224 bytes
1 block = 4224 bytes × 64 pages = (256K + 8K) bytes
Capacity = 4224 bytes × 64 pages × 4096 blocks
64 Pages=1 block
262144
pages
4096 blocks
An address is read in via the I/O port over five
consecutive clock cycles, as shown in Table 1.
8I/O
4224
Table 1. Addressing
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
L
L
L
CA12
CA11
CA10
CA9
CA8
Third cycle
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth cycle
PA15
PA14
PA13
PA12
PA11
PA10
PA9
PA8
L
L
L
L
L
L
PA17
PA16
First cycle
Second cycle
Fifth cycle
© 2013-2018 Toshiba Memory Corporation
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CA0 to CA12: Column address
PA0 to PA5: Page address in block
PA6 to PA17: Block address
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Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations
shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE ,
WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
Command Input
H
L
Data Input
L
Address Input
*1
RE
WP
L
H
*
L
L
H
H
L
H
L
H
*
Serial Data Output
L
L
L
H
During Program (Busy)
*
*
*
*
*
H
During Erase (Busy)
*
*
*
*
*
H
*
*
H
*
*
*
*
*
L
H (*2)
H (*2)
*
Program, Erase Inhibit
*
*
*
*
*
L
Standby
*
*
H
*
*
0 V/VCC
During Read (Busy)
WE
*
H: VIH, L: VIL, *: VIH or VIL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit.
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
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Table 3. Command table (HEX)
First Set
Second Set
Serial Data Input
80
Read
00
30
Column Address Change in Serial Data Output
05
E0
Auto Page Program
80
10
Column Address Change in Serial Data Input
85
80
11
81
10
Read for Copy-Back
00
35
Copy-Back Program
85
10
Auto Block Erase
60
D0
ID Read
90
Status Read
70
Status Read for Multi-Page Program or Multi Block Erase
71
ECC Status Read
7A
Reset
FF
Multi Page Program
Acceptable while Busy
HEX data bit assignment
(Example)
Serial Data Input: 80h
1
0
0
0
0
0
0
8
7
6
5
4
3
2 I/O1
0
Table 4. Read mode operation states
CLE
ALE
CE
WE
RE
I/O1 to I/O8
Power
Output select
L
L
L
H
L
Data output
Active
Output Deselect
L
L
L
H
H
High impedance
Active
H: VIH, L: VIL
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DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the
two commands, a start address for the Read mode needs to be issued. After initial power on sequence, “00h”
command is latched into the internal command register. Therefore read operation after power on sequence
is executed by the setting of only five address cycles and “30h” command. Refer to the figures below for the
sequence and the block diagram (Refer to the detailed timing chart).
CLE
ALE
Column Address M
I/O
Busy
Page Address N
00h
30h
tR
70h
Status
00h
M
M+1
M+2
Page Address N
Start-address input
Data Cache
M
m
Page Buffer
Select page
N
Cell array
I/O1 to 8: m = 4223
A data transfer operation from the cell array to the Data
Cache via Page Buffer starts on the rising edge of
in the
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the
clock
from the start address designated in the address input cycle.
Random Column Address Change in Read Cycle
CLE
ALE
Busy t
R
Col. M
I/O
30h
00h
Col. M
70h
Page N
M
Select page
N
© 2013-2018 Toshiba Memory Corporation
Statu
00h
M
M+1 M+2 M+3
Page N
Start from Col. M
M’
E0h
05h
Col. M’
M’
M’+1 M’+2 M’+3 M’+4
Page N
Start from Col. M’
During the serial data output from the register, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
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Multi Page Read Operation
The device has a Multi Page Read operation.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command
input
(3 cycles)
60
Address input
(3 cycles)
60
Address input
Page Address
PA0 to PA17
(District 0)
Command
input
A
B
(5 cycles)
Command
input
(5 cycles)
00
Address input
I/O1
”0”
”1”
A
Pass
Fail
tR
A
Address input
E0
Column Address
CA0 to CA12
(District 0)
B
Data output
(District 0)
B
(2 cycles)
05
Column + Page Address
CA0 to CA12, PA0 to PA17
(District 1)
District 0
70
(2 cycles)
05
Column + Page Address
CA0 to CA12, PA0 to PA17
(District 0)
A
B
Page Address
PA0 to PA17
(District 1)
Address input
00
30
Address input
Column Address
CA0 to CA12
(District 1)
E0
Data output
(District 1)
District 1
Reading
Selected
page
Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously with
the RE clock from the start address designated in the address input cycle.
ECC Status command can be used only for Single Page Read. It is not supported for Multi Page Read operation.
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Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
• The device consists of 2 Districts.
• Each District consists of 1024 erase blocks.
• The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052, Block 2054,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053, Block 2055,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Read operation
Make sure WP is held to High level when Multi Page Read operation is performed.
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ECC & Sector definition for ECC
Internal ECC logic generates Error Correction Code during busy time in program operation. The ECC logic
manages 9bit error detection and 8bit error correction in each 528Bytes of main data and spare data.
A section of main field (512Bytes) and spare field (16Bytes) are paired for ECC. During read, the device
executes ECC of itself. Once read operation is executed, Status Read Command (70h) can be issued to
check the read status. The read status remains until other valid commands are executed.
To use ECC function, below limitation must be considered.
- A sector is the minimum unit for program operation and the number of program per page must not
exceed 4.
4KByte Page Assignment
1st
Main
2nd
Main
3rd
Main
4th
Main
5th
Main
6th
Main
7th
Main
8th
Main
1st
Spare
2nd
Spare
3rd
Spare
4th
Spare
5th
Spare
6th
Spare
7th
Spare
8th
Spare
512B
512B
512B
512B
512B
512B
512B
512B
16B
16B
16B
16B
16B
16B
16B
16B
Note) The Internal ECC manages all data of Main area and Spare area.
Definition of 528Byte Sector
Sector
Column Address (Byte)
Main Field
Spare Field
1st Sector
0 to 511
4,096 to 4,111
2nd Sector
512 to 1,023
4,112 to 4,127
3rd Sector
1,024 to 1,535
4,128 to 4,143
4th Sector
1,536 to 2,047
4,144 to 4,159
5th Sector
2,048 to 2,559
4,160 to 4,175
6th Sector
2,560 to 3,071
4,176 to 4,191
7th Sector
3,072 to 3,583
4,192 to 4,207
8th Sector
3,584 to 4,095
4,208 to 4,223
Note) The ECC parity code generated by internal ECC is stored in column addresses 4224-4351 and the user cannot access
to these specific addresses.
While using the Partial Page Program, the user must program the data to main field and spare field simultaneously
by the definition of sector.
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Auto Page Program Operation
The device carries out an Automatic Page Program operation when it receives a "10h" Program command
after the address and data have been input. The sequence of command, address and data input is shown
below (Refer to the detailed timing chart).
CLE
ALE
I/O
Din Din Din
80h
Col. M
Page P
Din
70h
10h
Status
Out
Data
Data input
The data is transferred (programmed) from the Data Cache via
the Page Buffer to the selected page on the rising edge of
following input of the “10h” command. After programming, the
programmed data is transferred back to the Page Buffer to be
automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device
until success is achieved or until the maximum loop number set in
the device is reached.
Read & verification
Program
Selected
page
Random Column Address Change in Auto Page Program Operation
The column address can be changed by the 85h command during the data input sequence of the Auto Page
Program operation.
Two address input cycles after the 85h command are recognized as a new column address for the data input.
After the new data is input to the new column address, the 10h command initiates the actual data program into
the selected page automatically. The Random Column Address Change operation can be repeated multiple
times within the same page.
80h
Din
Col. M
Din
Din
Din
85h
Din
Col. M’
Page N
Col. M
Din
Din
Din
10h
70h
Status
Busy
Col. M’
Data input
Program
Read & verification
Selected
page
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Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to
Auto Page Program. The sequence of command, address and data input is shown below (Refer to the
detailed timing chart).
Although two districts are programmed simultaneously, pass/fail is not available for each page by “70h”
command when the program operation completes. Status bit of I/O 1 is set to “1” when any of the pages
fails. Limitation in addressing with Multi Page Program is shown below.
Multi Page Program
tPROG
tDCBSYW1
I/O1 to 8
80h
Address & Data Input
CA0 to CA12
PA0 to PA5
PA6
PA7 to PA17
11h
: Valid
: Valid’
: District0’
: Valid’
Address & Data Input
81h
Note
CA0 to CA12
PA0 to PA5
PA6
PA7 to PA17
: Valid
: Valid
: District1
: Valid
10h
70h/71h
”0”
I/O1
Pass
”1”
Fail
NOTE: Any command between 11h and 81h is prohibited except 70h and FFh.
80h
11h
81h
10h
Data
Input
District 0
(2048 Block)
District 1
(2048 Block)
Block 0
Block 1
Block 2
Block 3
Block 4092
Block 4093
Block 4094
Block 4095
The 71h command Status description is as below.
STATUS
OUTPUT
I/O1
Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O2
District 0 Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O3
District 1 Chip Status : Pass/Fail
Pass: 0
Fail: 1
I/O4
Not Used
Invalid
I/O5
Not Used
Invalid
I/O6
Ready/Busy
Ready: 1
Busy: 0
I/O7
Ready/Busy
Ready: 1
Busy: 0
I/O8
Write Protect
Protect: 0
© 2013-2018 Toshiba Memory Corporation
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows “Fail”.
I/O2 to 3 shows the Pass/Fail condition of
each district.
Not Protect: 1
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Internal addressing in relation with the Districts
To use Multi Page Program operation, the internal addressing should be considered in relation with the
District.
• The device consists of 2 Districts.
• Each District consists of 1024 erase blocks.
• The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052, Block 2054,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053, Block 2055,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
Address input restriction for the Multi Page Program operation
There are following restrictions in using Multi Page Program;
(Restriction)
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(80) [District 0, Page Address 0x00000] (11) (81) [District 1, Page Address 0x00040] (10)
(80) [District 0, Page Address 0x00001] (11) (81) [District 1, Page Address 0x00041] (10)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(80) [District 0] (11) (81) [District 1] (10)
(80) [District 1] (11) (81) [District 0] (10)
It requires no mutual address relation between the selected blocks from each District.
Operating restriction during the Multi Page Program operation
(Restriction)
The operation has to be terminated with “10h” command.
Once the operation is started, no commands other than the commands shown in the timing diagram is
allowed to be input except for Status Read command and reset command.
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Auto Block Erase
The Auto Block Erase operation starts on the rising edge of WE after the Erase Start command “D0h”
which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra
layer of protection from accidental erasure of data due to external noise. The device automatically executes
the Erase and Verify operations.
60
D0
Block Address
input: 3 cycles
70
Status Read
command
Erase Start
command
I/O
Pass
Fail
Busy
Multi Block Erase
The Multi Block Erase operation starts by selecting two block addresses before D0h command as in below
diagram. The device automatically executes the Erase and Verify operations and the result can be monitored
by checking the status by 71h status read command. For details on 71h status read command, refer to
section “Multi Page Program”.
60
Block Address
input: 3 cycles
District 0
60
D0
71
Status Read
command
Block Address Erase Start
input: 3 cycles command
District 1
I/O
Pass
Fail
Busy
Internal addressing in relation with the Districts
To use Multi Block Erase operation, the internal addressing should be considered in relation with the District.
• The device consists of 2 Districts.
• Each District consists of 1024 erase blocks.
• The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 2046
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 2047
(c) District 0: Block 2048, Block 2050, Block 2052, Block 2054,···, Block 4094
(d) District 1: Block 2049, Block 2051, Block 2053, Block 2055,···, Block 4095
Combination of (a) and (b) or (c) and (d) can only be selected.
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Address input restriction for the Multi Block Erase
There are following restrictions in using Multi Block Erase;
(Restriction)
Maximum one block should be selected from each District.
For example;
(60) [District 0] (60) [District 1] (D0)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 1] (60) [District 0] (D0)
It requires no mutual address relation between the selected blocks from each District.
Make sure to terminate the operation with D0h command. If the operation needs to be terminated before
D0h command input, input the FFh reset command to terminate the operation.
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READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE
Copy-Back operation is a sequence execution of Read for Copy-Back and of copy-back program with the
destination page address. A read operation with “35h” command and the address of source page moves the
whole 4224 bytes data into the internal data buffer. Bit errors are checked by sequential reading the data or
by reading the status in read after read busy time (tR) to check if uncorrectable error occurs. In the case
where there is no bit error or no uncorrectable error, the data don’t need to be reloaded. Therefore CopyBack program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page
address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the
program process starts, the Status Read command (70h) may be entered to read the status register. The
system controller can detect the completion of a program cycle by monitoring the RY / BY output, or the
Status Bit (I/O7) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit
(I/O1) may be checked. The command register remains in Status Read mode until another valid command
is written to the command register. During copy-Back program, data modification is possible using random
data input command (85h) as shown below.
Page Copy-Back Program Operation
tR
I/Ox
00h
Add.(5 Cycles)
tPROG
70h
35h
I/O1
Col. Add.1,2 & Page
Add.1,2,3
Source Address
”0”
”1”
Pass
00h
Data Output
Add.(5 Cycles)
85h
10h
70h
Col. Add.1,2 & Page
Add.1,2,3
Destination Address
Fail
I/O1
”0”
Pass
”1”
Fail
NOTE: 1. Copy-Back Program operation is allowed only within the same district.
Page Copy-Back Program Operation with Random Data Input
tR
I/Ox
00h Add.(5Cycles)
35h
A
70h
I/O1
Col. Add.1,2 & Page Add.1,2,3
Source Address
”0”
”1”
00h
Data Output
Pass
Fail
tPROG
A
I/Ox
A
A
85h Add.(5Cycles)
Data
Col. Add.1,2 & Page Add.1,2,3
Destination Address
85h Add.(2Cycles)
Data
10h
70h
Col. Add.1,2
There is no limitation for the number of repetition
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ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and
features of the device. The ID codes can be read out under the following timing conditions:
CLE
tCEA
tAR
ALE
tREA
I/O
90h
00h
98h
D3h
See
table 5
See
table 5
See
table 5
ID Read
command
Address 00
Maker code
Device code
3rd Data
4th Data
5th Data
Table 5. Code table
Description
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
Hex Data
1st Data
Maker Code
1
0
0
1
1
0
0
0
98h
2nd Data
Device Code
1
1
0
1
0
0
1
1
D3h
3rd Data
Chip Number, Cell Type
1
0
0
1
0
0
0
1
91h
4th Data
Page Size, Block Size
0
0
1
0
0
1
1
0
26h
5th Data
District Number
1
1
1
1
0
1
1
0
F6h
3rd Data
Description
Internal Chip Number
Cell Type
I/O8
I/O6
I/O5
I/O4
I/O3
1
2
4
8
0
0
1
1
2 level cell
4 level cell
8 level cell
16 level cell
Reserved
© 2013-2018 Toshiba Memory Corporation
I/O7
1
36
0
0
I/O2
I/O1
0
0
1
1
0
1
0
1
0
1
0
1
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4th Data
Description
Page Size
(without redundant area)
1 KB
2 KB
4 KB
8 KB
Block Size
(without redundant area)
64 KB
128 KB
256 KB
512 KB
I/O Width
I/O8
I/O7
I/O6
0
0
1
1
I/O5
I/O4
I/O3
I/O2
I/O1
0
0
1
1
0
1
0
1
I/O2
I/O1
1
0
0
1
0
1
0
1
x8
x16
Reserved
0
0
1
I/O4
I/O3
0
0
1
1
0
1
0
1
5th Data
Description
District Number
ECC engine on chip
I/O8
I/O6
I/O5
1 District
2 District
4 District
8 District
With ECC engine
1
Reserved
© 2013-2018 Toshiba Memory Corporation
I/O7
1
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Status Read
The device automatically implements the execution and verification of the Program and Erase operations.
The Status Read function is used to monitor the Ready/Busy status of the device, determine the result
(pass /fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The
device status is output via the I/O port using RE after a “70h” command input. The Status Read can also
be used during a Read operation to monitor the Ready/Busy status and to find out the ECC result (pass/fail).
The resulting information is outlined in Table 6.
Table 6. Status output table
Definition
Page Program
Block Erase
Read
Pass/Fail
Pass/Fail
Pass/Fail(Uncorrectable)
I/O1
Chip Status
Pass: 0
I/O2
Not Used
Invalid
Invalid
Invalid
I/O3
Not Used
0
0
0
0
0
Normal or uncorrectable /
Recommended to rewrite
0
0
0
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Ready/Busy
Write Protect
Write Protect
Write Protect
Fail: 1
Chip Read Status
I/O4
Normal or uncorrectable: 0
Recommended to rewrite : 1
I/O5
Not Used
I/O6
Ready/Busy
Ready: 1
Busy: 0
I/O7
Ready/Busy
Ready: 1
Busy: 0
I/O8
Write Protect
Not Protected :1
Protected: 0
The Pass/Fail status on I/O1 is only valid during a Program/Erase/Read operation when the device is in the Ready state.
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ECC Status Read
The ECC Status Read function is used to monitor the Error Correction Status. The device can correct up
to 8bit errors.
ECC can be performed on the NAND Flash main and spare areas. The ECC Status Read function can
also show the number of errors in a sector as a result of an ECC check in during a read operation.
8
7
6
5
4
Sector Information
3
2
I/O1
ECC Status
ECC Status
I/O4 to I/O1
ECC Status
0000
No Error
0001
1bit error(Correctable)
0010
2bit error(Correctable)
0011
3bit error(Correctable)
0100
4bit error(Correctable)
0101
5bit error(Correctable)
0110
6bit error(Correctable)
0111
7bit error(Correctable)
1000
8bit error(Correctable)
1111
Uncorrectable Error
Sector Information
I/O8 to I/O5
Sector Information
0000
1st Sector (Main and Spare area)
0001
2nd Sector (Main and Spare area)
0010
3rd Sector (Main and Spare area)
0011
4th Sector (Main and Spare area)
0100
5th Sector (Main and Spare area)
0101
6th Sector (Main and Spare area)
0110
7th Sector (Main and Spare area)
0111
8th Sector (Main and Spare area)
Other
Reserved
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Reset
The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally
generated voltage is discharged to 0 volt and the device enters the Wait state.
The response to a “FFh” Reset command input during the various device operations is as follows:
When a Reset (FFh) command is input during Program operation
80
10
FF
00
Internal
generated voltage
tRST (max 10 µs)
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When a Reset (FFh) command is input during Erase operation
D0
FF
00
Internal
generated voltage
tRST (max 500 µs)
When a Reset (FFh) command is input during Read operation
00
30
FF
00
tRST (max 5 µs)
When a Reset (FFh) command is input during Ready
FF
00
tRST (max 5 µs)
When a Status Read command (70h) is input after a Reset
FF
70
I/O status: Pass/Fail → Pass
: Ready/Busy → Ready
When two or more Reset commands are input in succession
10
The second
© 2013-2018 Toshiba Memory Corporation
FF
(1)
(2)
(3)
FF
FF
FF
command is invalid, but the third
41
FF
command is valid.
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APPLICATION NOTES AND COMMENTS
(1)
Power-on/off sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power
on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in
the figure below. In this time period, the acceptable commands are FFh or 70h.
The WP signal is useful for protecting against data corruption at power-on/off.
2.7 V
2.5 V
VCC
0 V
,
2.7 V
2.5 V
≥ 1ms
0.5 V
0.5 V
Don’t
care
Don’t
care
,
CLE, ALE
Don’t
care
VIH
VIL
VIL
1.2 ms max
Operation
100 µs max
100 µs max
Invalid
Invalid
1.2 ms max
Invalid
Ready/Busy
(2)
Power-on Reset
The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3)
Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in
Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the
command cycle.
(4)
Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h,71h and FFh.
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(5)
Acceptable commands after Serial Input command “80h”
Once the Serial Input command “80h” has been input, do not input any command other than the Column
Address Change in Serial Data Input command “85h”, Auto Program command “10h”, Multi Page
Program command “11h” or the Reset command “FFh”.
80
FF
Address input
If a command other than “85h”, “10h”, “11h” or “FFh” is input, the Program operation is not performed
and the device operation is set to the mode which the input command specifies.
80
XX
Mode specified by the command.
10
Programming cannot be executed.
Command other than
“85h”, “10h” , ”11h” or “FFh”
(6)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page
of the block to MSB (most significant bit) page of the block. Random page address programming is
prohibited.
From the LSB page to MSB page
DATA IN: Data (1)
Ex.) Random page program (Prohibition)
Data (64)
DATA IN: Data (1)
Data register
Data (64)
Data register
Page 0
Page 1
Page 2
(1)
(2)
(3)
Page 0
Page 1
Page 2
(2)
(32)
(3)
Page 31
(32)
Page 31
(1)
Page 63
(64)
Page 63
(64)
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(7)
Status Read during a Read operation
00
Command
00
30
[A]
70
Address N
Status Read
command input
Status output
Status Read
The device status can be read out by inputting the Status Read command “70h” in Read mode. Once
the device has been set to Status Read mode by a “70h” command, the device will not return to Read
mode unless the Read command “00h” is input during [A]. If the Read command “00h” is input during [A],
Status Read mode is reset, and the device returns to Read mode. In this case, data output starts
automatically from address N and address input is unnecessary.
(8)
Auto programming failure
80
10
70
Fail
I/O
80
Address Data
M
input
10
Address Data
N
input
80
10
If the programming result for page address M is Fail, do not try to program the page
to address N in another block without the data input sequence.
Because the previous input data has been lost, the same input sequence of 80h
command, address and data is necessary.
M
N
(9)
RY / BY : termination for the Ready/Busy pin ( RY / BY )
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open
drain circuit.
VCC
VCC
Ready
VCC
R
Busy
Device
VSS
1.5 µs
tr
This data may vary from device to device.
We recommend that you use this data as
a reference when selecting a resistor
value.
© 2013-2018 Toshiba Memory Corporation
tr
tf
CL
tf
1.0 µs
1 KΩ
15 ns
10 ns
tr
0.5 µs
0
VCC = 3.3 V
Ta = 25°C
CL = 50 pF
tf
5 ns
2 KΩ
3 KΩ
4 KΩ
R
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(10)
Note regarding the WP signal
The Erase and Program operations are automatically reset when WP goes Low. The operations are
enabled and disabled as follows:
Enable Programming
DIN
80
10
tWW (100 ns MIN)
Disable Programming
DIN
80
10
tWW (100 ns MIN)
Enable Erasing
DIN
60
D0
tWW (100 ns MIN)
Disable Erasing
DIN
60
D0
tWW (100 ns MIN)
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(11)
When six address cycles are input
Although the device may read in a sixth address, it is ignored inside the chip.
Read operation
CLE
ALE
I/O
00h
30h
Ignored
Address input
Program operation
CLE
ALE
I/O
80h
Ignored
Address input
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Data input
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(12)
Several programming cycles on the same page (Partial Page Program)
ECC Parity Code is generated during program operation on Main area (512 byte) + Spare area (16byte).
While using the Partial Page Program, the user must program the data to main field and spare field
simultaneously by the definition of sector in section “ECC & Sector definition for ECC”.
For example, each segment can be programmed individually as follows:
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(13)
Invalid blocks (bad blocks)
The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:
Bad Block
Bad Block
Please do not perform an erase operation to bad blocks. It may be
impossible to recover the bad block information if the information is
erased.
Check if the device has any bad blocks after installation into the
system. Refer to the test flow for bad block detection. Bad blocks which
are detected by the test flow must be managed as unusable blocks by
the system.
A bad block does not affect the performance of good blocks because it
is isolated from the bit lines by select gates.
The number of valid blocks over the device lifetime is as follows:
Valid (Good) Block Number
MIN
TYP.
MAX
UNIT
4016
4096
Blocks
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in whole pages.
Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as
a bad block.
For Bad Block Test Flow, during Read Check, regardless of Status Read result (ECC Pass or Fail), use the
read data value to make judgement for Bad Block.
Start
Block No = 1
Fail
Read Check
Block No. = Block No. + 1
No
Pass
Entry Bad Block *1
Last Block
Yes
End
*1: No erase operation is allowed to detected bad blocks.
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(14)
Failure phenomena for Program, Erase and Read operations
The device may fail during a Program, Erase or Read operation.
The following possible failure modes should be considered when implementing a highly reliable system.
FAILURE MODE
DETECTION AND COUNTERMEASURE SEQUENCE
Block
Erase Failure
Status Read after Erase → Block Replacement
Page
Programming Failure
Status Read after Program → Block Replacement
Read
9bit Failure (uncorrectable error)
Check the ECC correction status by Status Read or ECC Status Read and take
appropriate measures such as rewrite in consideration of Wear Leveling before
uncorrectable ECC error occurs.
• ECC: Error Correction Code. 8 bit correction per 528Bytes is executed in a device.
• Block Replacement
Program
Error occurs
Buffer
memory
Block A
When an error happens in Block A, try to reprogram the
data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses
to Block A (by creating a bad block table or by using
another appropriate scheme).
Block B
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block
(by creating a table within the system or by using another appropriate scheme).
(15)
Do not turn off the power before write/erase operation is complete. Avoid using the device when the
battery is low. Power shortage and/or power failure before write/erase operation is complete will cause
loss of data and/or damage to data.
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(16)
Reliability Guidance
This reliability guidance is intended to notify some guidance related to using NAND Flash with 8 bit ECC
for each 512 bytes. NAND Flash memory cells are gradually worn out and the reliability level of memory
cells is degraded by repeating Write and Erase operation of ‘0’ data in each block. For detailed reliability
data, please refer to the reliability note for each product.
Although random bit errors may occur during use, it does not necessarily mean that a block is bad.
Generally, a block should be marked as bad when a program status failure or erase status failure is
detected.
The reliability of NAND Flash memory cells during the actual usage on system level depends on the usage
and environmental conditions. TOSHIBA MEMORY adopts the checker pattern data, 0x55 & 0xAA for
alternative Write/Erase cycles, for the reliability test.
Write/Erase Endurance
Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a Status
Read after either an Auto Program or Auto Block Erase operation. The cumulative bad block count will
increase along with the number of Write/Erase cycles.
Data Retention
The data in NAND Flash memory may change after a certain amount of storage time. This is due to
charge loss or charge gain. After block erasure and reprogramming, the block may become usable again.
Data Retention time is generally influenced by the number of Write/Erase cycles and temperature.
Data Retention [Years]
Here is the combined characteristics image of Write/Erase Endurance and Data Retention.
Write/Erase Endurance [Cycles]
Read Disturb
A Read operation may disturb the data in NAND Flash memory. The data may change due to charge
gain. Usually, bit errors occur on other pages in the block, not the page being read. After a large number
of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft
programmed to another state. After block erasure and reprogramming, the block may become usable
again. Read Disturb capability is generally influenced by the number of Write/Erase cycles.
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(17)
NAND Management
NAND Management such as Bad Block Management, ECC treatment and Wear Leveling, but not limited
to these treatments, should be recognized and incorporated in the system design.
ECC treatment for read data is mandatory against random bit errors, and host should monitor ECC status
to take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable
Error occurs. To realize robust system design, generally it is necessary to prevent the concentration of
Write/Erase cycles at the specific blocks by adopting Wear Leveling which manages to distribute
Write/Erase cycles evenly among NAND Flash memory. And also it is necessary to avoid dummy ‘0’ data
write, e.g. ‘0’ data padding, which accelerate block endurance degradation.
Continuous Write and Erase cycling with high percentage of '0' bits in data pattern can lead to faster block
endurance degradation.
Example: NAND cell array with ‘0’ data padding
0 : “0” data cell
1 : “1” data cell
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
User data area
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
1
0
1
1
0
1
0
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
User data area
Remaining area
(a) Accelerate block endurance degradation
by fixed dummy “0” data write
© 2013-2018 Toshiba Memory Corporation
1
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Remaining area
(b) “1” data for Remaining area
(Recommended)
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Package Dimensions
Weight: 0.54 g (typ.)
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Revision History
Date
2013-09-20
2018-06-01
Rev.
1.00
1.10
© 2013-2018 Toshiba Memory Corporation
Description
Initial Release.
Corrected typo, and described some notes.
Attached Reliability Guidance and NAND Management.
Changed “RESTRICTIONS ON PRODUCT USE”.
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RESTRICTIONS ON PRODUCT USE
Toshiba Memory Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”.
Hardware, software and systems described in this document are collectively referred to as “Product”.
• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's
written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for
complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to
property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the
Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information,
including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and
conditions set forth in the " Reliability Information” in Toshiba Memory Corporation’s website and (b) the instructions for the application with
which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications,
including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and
determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application
circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA
ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE
EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY
CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT
("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation,
equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or
explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE,
TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative or contact us via our
website.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any
applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any
infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any
intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR
PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER,
INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING
WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2)
DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR
INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for
the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass
destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations
including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export
and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and
regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please
use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including
without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT
OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.
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