HG25Q40
3V 4M -BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI
FEATURES
Low power supply operation
- Single 2.3V-3.6V supply
overhead
Flexible Architecture with 4KB sectors
- Sector Erase (4K-bytes)
- Block Erase (32K/64K-bytes)
- Page Program up to 256 bytes
- More than 100K erase/program cycles
- More than 20-year data retention
4M/2M bit Serial Flash
- 4 M-bit/512K-byte/2,048 pages
- 2 M-bit/256K-byte/1,024 pages
- 256 bytes per programmable page
- Uniform 4K-byte Sectors, 32K/64K-byte Blocks
New Family of SpiFlash Memories
- Standard SPI: CLK, CS#, DI, DO, WP#,
HOLD# / RESET#
- Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# /
RESET#
- Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3
- Software & Hardware Reset
- Auto-increment Read capability
Advanced Security Feature
- Software and Hardware Write-Protect
- Power Supply Lock-Down and OTP
protection
- Top/Bottom, Complement array protection
- 64-Bit Unique ID for each device
- Discoverable parameters(SFDP) register
- 3X256-Bytes Security Registers with OTP
locks
- Volatile & Non-volatile Status Register Bits
Temperature Ranges
- Industrial (-40°C to +85°C)
- Extended (-20°C to +85°C)
High performance program/erase speed
- Page program time: 400us typical
- Sector erase time: 35ms typical
- Block erase time: 200ms typical
- Chip erase time: 10 Seconds typical
Low power consumption
- 9 mA typical active current
- 2 uA typical power down current
Package Options
- 8-pin SOIC 150/208-mil
- 8-pad WSON 6x5-mm
- 8-pin PDIP 300-mil
- All Pb-free packages are RoHS compliant
Efficient “Continuous Read” and Quad Read
- Continuous Read with 8/16/32/64-Byte Wrap
- As few as 8 clocks to address memory
- Quad Peripheral Interface reduces instruction
GENERAL DESCRIPTION
The HG25Q40/20 of non-volatile flash memory device supports the standard Serial Peripheral Interface
(SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two
bit (Dual I/O or DIO) and four bit (quad I/O) serial protocols. This multiple width interface is called SPI Multi-I/O
or MIO.
The SPI protocols use only 4 to 6 signals:
Chip Select (CS#)
Serial Clock (CLK)
Serial Data
- IO0 (DI)
- IO1 (DO)
- IO2 (WP#)
- IO3 (HOLD# / RESET#)
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The HG25Q 40/20 support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as
2-clocks instruction cycle Quad Peripheral Interface : Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 44MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O . These transfer rates can outperform standard Asynchronous 8 and
16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as
8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and
SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
The HG25Q40/20 provides an ideal storage solution for systems with limited space, signal connections,
and power. These memories' flexibility and performance is better than ordinary serial flash devices. They are
ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
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BLOCK DIAGRAM
Figure 2.1 Block Diagram
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CONNECTION DIAGRAMS
Figure 3.1 8-pin SOP (150/208mil)/ PDIP (300mil)
Figure 3.2 8-Contact 6 x 5 mm WSON
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SIGNAL DESCRIPTIONS
Table 4.1 Pin Descriptions
Symbol
Pin Name
CLK
Serial Clock Input
DI(IO0)
Serial Data Input(Data input output 0) (1)
DO(IO1)
Serial Data Output(Data input output 1) (1)
CS#
Chip Enable
WP#(IO2)(3)
Write Protect (Data input output 2) (2)
HOLD# / RESET#(3)(IO3)
Hold or Reset input(Data input output 3) (2)
VCC
Power Supply (2.3-3.6V)
GND
Ground
Notes:
(1)IO0 and IO1 are used for Standard and Dual SPI instructions.
(2)IO0—IO3 are used for QUAD SPI instructions.
(3)WP# and HOLD# / RESET# functions are only available for Standard and Dual SPI.
Serial Data Input (DI) / IO0
The SPI Serial Data Input (DI) pin is used to transfer data serially into the device. It receives instructions,
address and data to be programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
The DI pin becomes IO0 - an input and output during Dual and Quad commands for receiving instructions,
address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as
shifting out data (on the falling edge of CLK).
Serial Data Output (DO) / IO1
The SPI Serial Data Output (DO) pin is used to transfer data serially out of the device. Data is shifted out
on the falling edge of the Serial Clock (CLK) input pin. DO becomes IO1 - an input and output during Dual and
Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising
edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK).
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, CS# must transition from high to low before a new instruction will be accepted.
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Write Protect (WP#) / IO2
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status
Register Protect (SRP0) bits, a portion or the entire memory array can be hardware protected.
The WP# function is not available when the Quad mode is enabled. The WP# function is replaced by IO2
for input and output during Quad mode for receiving addresses and data to be programmed (values are
latched on rising edge of the CLK signal) as well as shifting out data (on the falling edge of CLK).
HOLD (HOLD#) / IO3
The HOLD# pin allows the device to be paused while it is actively selected. When HRSW bit is ‘0’ (factory
default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low, while CS# is low, the DO pin will be at
high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high,
device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same
SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the
HOLD# pin function is not available since this pin is used for IO3.
RESET (RESET#) / IO3
The RESET# pin allows the device to be reset by the controller. When HRSW bit is ‘1’ (factory default is
‘0’), the RESET# pin is enabled. Drive RESET# low for a minimum period of ~1us (tRESET*) will interrupt any
on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP#
and/or HOLD#). The Hardware Reset function is only available for standard SPI and Dual SPI operation,
when QE=0, the IO3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status
Register setting, when QE=1, this pin is the Serial Data IO (IO3) for Quad I/O operation.
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MEMORY ORGANIZATION
Flash Memory Array
The HG25Q40 memory is organized as:
- 524,288bytes
- Uniform Sector Architecture 8 blocks of 64-Kbyte
- 128 sectors of 4-Kbyte
- 2, 048 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 5.1(1) Memory Organization(HG25Q40)
Block/ Security
Register/SFDP
Security Register 3
Sector
Address range
-
003000H
0030FFH
Security Register 2
-
002000H
0020FFH
Security Register 1
Security Register 0
(SFDP)
-
001000H
0010FFH
-
000000H
0000FFH
127
07F000H
07FFFFH
......
......
......
112
070000H
070FFFH
Block 7
Block 6
......
......
Block 2
Block 1
Block 0
111
06F000H
06FFFFH
......
......
......
060FFFH
96
060000H
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
02FFFFH
47
02F000H
......
......
......
32
020000H
020FFFH
31
01F000H
01FFFFH
......
......
......
16
010000H
010FFFH
00FFFFH
15
00F000H
......
......
......
0
000000H
000FFFH
Notes:
(1)These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly
listed. All 4-kB sectors have the pattern XXX000h-XXXFFFh.
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The HG25Q20 memory is organized as:
- 262,144bytes
- Uniform Sector Architecture 4 blocks of 64-Kbyte
- 64 sectors of 4-Kbyte
- 1, 024 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
Table 5.2(1) Memory Organization(HG25Q20)
Block/ Security
Register/SFDP
Security Register 3
Sector
Address range
-
003000H
0030FFH
Security Register 2
-
002000H
0020FFH
Security Register 1
Security Register 0
(SFDP)
-
001000H
0010FFH
-
000000H
0000FFH
03FFFFH
Block 3
Block 2
Block 1
Block 0
63
03F000H
......
......
......
48
030000H
030FFFH
47
02F000H
02FFFFH
......
......
......
32
020000H
020FFFH
01FFFFH
31
01F000H
......
......
......
16
010000H
010FFFH
00FFFFH
15
00F000H
......
......
......
0
000000H
000FFFH
Notes:
(1)These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly
listed. All 4-kB sectors have the pattern XXX000h-XXXFFFh.
Security Registers
The HG25Q40/20 provides four 256-byte Security Registers. Each register can be used to store
information that can be permanently protected by programming One Time Programmable (OTP) lock bits in
Status Register-2.
Register 0 is used byFSRKto store and protect the Serial Flash Discoverable Parameters (SFDP)
information that is also accessed by the Read SFDP command. See Table 5.1.
The three additional Security Registers can be erased, programmed, and protected individually. These
registers may be used by system manufacturers to store and permanently protect security or other important
information separate from the main memory array.
Security Register 0
Serial Flash Discoverable Parameters (SFDP — JEDEC JESD216B):
This document defines the Serial Flash Discoverable Parameters (SFDP) revision B data structure for
HG25Q40/20 family.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate flash memory address
space for device identification, feature, and configuration information, in accord with the JEDEC JESD216B
standard for Serial Flash Discoverable Parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header
format that is supported and provides a revision number and pointer for each of the SFDP parameter tables
that are provided. The parameter tables follow the SFDP header. However, the parameter tables may be
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placed in any physical location and order within the SFDP address space. The tables are not necessarily
adjacent nor in the same order as their header table entries.
The SFDP header points to the following parameter tables:
Basic Flash
– This is the original SFDP table.
The physical order of the tables in the SFDP address space is: SFDP Header, and Basic Flash. The
SFDP address space is programmed byFSRK and read-only for the host system.
Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure
and provides a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC JESD216B
standard.
Table 5.2 SFDP Overview Map — Security Register 0
Byte Address
0000h
0010h
0030h
...
006Fh
0070h to 00FFh
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Description
Location zero within JEDEC JESD216B SFDP space – start of SFDP header
Undefined space reserved for future SFDP header
Start of SFDP parameter
Remainder of SFDP JEDEC parameter followed by undefined space
End of SFDP space
Reserved space
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SFDP Header Field Definitions
Table 5.3 SFDP Header
SFDP Byte
Address
00h
01h
02h
03h
SFDP Dword
Name
SFDP Header
1st DWORD
04h
Data
53h
46h
44h
50h
06h
SFDP Header
2nd DWORD
05h
01h
06h
07h
08h
00h
FFh
00h
09h
Parameter Header
0 1st DWORD
06h
0Ah
01h
0Bh
10h
0Ch
0Dh
0Eh
0Fh
Parameter Header
0 2nd DWORD
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30h
00h
00h
FFh
Description
This is the entry point for Read SFDP (5Ah) command i.e. location zero within
SFDP space
ASCII “S”
ASCII “F”
ASCII “D”
ASCII “P”
SFDP Minor Revision (06h = JEDEC JESD216 Revision B)
– This revision is backward compatible with all prior minor revisions. Minor
revisions are changes that define previously reserved fields, add fields to the
end, or that clarify definitions of existing fields. Increments of the minor revision
value indicate that previously reserved parameter fields may have been
assigned a new definition or entire Dwords may have been added to the
parameter table. However, the definition of previously existing fields is
unchanged and therefore remains backward compatible with earlier SFDP
parameter table revisions. Software can safely ignore increments of the minor
revision number, as long as only those parameters the software was designed
to support are used i.e. Previously reserved fields and additional Dwords must
be masked or ignored. Do not do a simple compare on the minor revision
number, looking only for a match with the revision number that the software is
designed to handle. There is no problem with using a higher number minor
revision.
SFDP Major Revision
– This is the original major revision. This major revision is compatible with all
SFDP reading and parsing software.
Number of Parameter Headers (zero based, 00h = 1 parameters
Unused
Parameter ID LSB (00h = JEDEC SFDP Basic SPI Flash Parameter)
Parameter Minor Revision (00h = JESD216)
–This older revision parameter header is provided for any legacy SFDP reading
and parsing software that requires seeing a minor revision 6 parameter header.
SFDP software designed to handle later minor revisions should continue
reading parameter headers looking for a higher numbered minor revision that
contains additional parameters for that software revision.
Parameter Major Revision (01h = The original major revision - all SFDP
software is compatible with this major revision.
Parameter Table Length (in double words = Dwords = 4-byte units) 10h = 16
Dwords
Parameter Table Pointer Byte 0 (Dword = 4-byte aligned) JEDEC Basic SPI
Flash parameter byte offset = 30h
Parameter Table Pointer Byte 1
Parameter Table Pointer Byte 2
Parameter ID MSB (FFh = JEDEC defined legacy Parameter ID)
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JEDEC SFDP Basic SPI Flash Parameter
SFDP
Parameter
Relative
Byte
Address
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 1 of 5)
SFDP Dword
Name
30h
31h
Data
E5h
JEDEC
Basic Flash
Parameter
Dword-1
20h
32h
F1h
33h
34h
35h
36h
FFh
FFh
FFh
1Fh/3Fh
00h
37h
38h
39h
3Ah
JEDEC
Basic Flash
Parameter
Dword-2
JEDEC
Basic Flash
Parameter
Dword-3
3Bh
3Ch
3Dh
3Eh
41h
42h
43h
44h
45h
46h
47h
EBh
08h
6Bh
JEDEC
Basic Flash
Parameter
Dword-4
3Fh
40h
44h
08h
3Bh
80h
BBh
JEDEC
Basic Flash
Parameter
Dword-5
JEDEC
Basic Flash
Parameter
Dword-6
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FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Description
Start of SFDP JEDEC parameter
Bits 7:5 = unused = 111b
Bit 4:3 = 05h is volatile status register write instruction and status register is
default non-volatile= 00b
Bit 2 = Program Buffer > 64 bytes = 1
Bits 1:0 = Uniform 4-kB erase is supported throughout the device = 01b
Bits 15:8 = Uniform 4-kB erase instruction = 20h
Bit 23 = Unused = 1b
Bit 22 = Supports QOR Read (1-1-4), Yes = 1b
Bit 21 = Supports QIO Read (1-4-4),Yes =1b
Bit 20 = Supports DIO Read (1-2-2), Yes = 1b
Bit19 = Supports DDR, No= 0 b
Bit 18:17 = Number of Address Bytes 3 only = 00b
Bit 16 = Supports SIO and DIO Yes = 1b
Binary Field: 1-1-1-1-0-00-1
Nibble Format: 1111_0001
Hex Format: F1
Bits 31:24 = Unused = FFh
Density in bits, zero based,
2 Mb = 001FFFFFh
4 Mb = 003FFFFFh
8 Mb = 007FFFFFh
Bits 7:5 = number of QIO (1-4-4)Mode cycles = 010b
Bits 4:0 = number of Fast Read QIO Dummy cycles = 00100b for default
latency code
Fast Read QIO (1-4-4)instruction code
Bits 23:21 = number of Quad Out (1-1-4) Mode cycles = 000b
Bits 20:16 = number of Quad Out Dummy cycles = 01000b for default latency
code
Quad Out (1-1-4)instruction code
Bits 7:5 = number of Dual Out (1-1-2)Mode cycles = 000b
Bits 4:0 = number of Dual Out Dummy cycles = 01000b for default latency code
Dual Out (1-1-2) instruction code
Bits 23:21 = number of Dual I/O Mode cycles = 100b
Bits 20:16 = number of Dual I/O Dummy cycles = 00000b for default latency
code
Dual I/O instruction code
Bits 7:5 RFU = 111b
Bit 4 = QPI (4-4-4) fast read commands not supported = 0b
Bits 3:1 RFU = 111b
Bit 0 = Dual All not supported = 0b
Bits 15:8 = RFU = FFh
Bits 23:16 = RFU = FFh
Bits 31:24 = RFU = FFh
Bits 7:0 = RFU = FFh
Bits 15:8 = RFU = FFh
Bits 23:21 = number of Dual All Mode cycles = 111b
Bits 20:16 = number of Dual All Dummy cycles = 11111b
Dual All instruction code
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SFDP
Parameter
Relative
Byte
Address
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 2 of 5)
SFDP Dword
Name
JEDEC
Basic Flash
Parameter
Dword-8
JEDEC
Basic Flash
Parameter
Dword-9
JEDEC
Basic Flash
Parameter
Dword-4
53h
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Data
Description
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Erase Type 1 size 2N Bytes = 4 kB = 0Ch (for Uniform 4 kB)
Erase Type 1 instruction
Erase Type 2 size 2N Bytes = 32 kB = 0Fh (for Uniform 32 kB)
Erase Type 2 instruction
Erase Type 3 size 2N Bytes =64 kB = 10h(for Uniform 64 kB)
Erase Type 3 instruction
Erase Type 4 size 2N Bytes = not supported = 00h
Erase Type 4 instruction = not supported = FFh
Bits 31:30 = Erase Type 4 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = RFU = 11b
Bits 29:25 = Erase Type 4 Erase, Typical time count = RFU = 11111b (typ erase
time = (count+1) * units) = RFU =11111
Bits 24:23 = Erase Type 3 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = RFU = 01b
Bits 22:18 = Erase Type 3 Erase, Typical time count = 01011b (typ erase time =
(count +1) *units) = 12*16 ms =200ms
Bits 17:16 = Erase Type 2 Erase, Typical time units (00b: 1 ms, 01b: 16 ms,
10b: 128 ms, 11b:1 s) = 16 ms = 01b
Bits 15:11 = Erase Type 2 Erase, Typical time count = 01000b (typ erase time =
(count +1) *units) = 9*16 ms = 150 ms
Bits 10:9 = Erase Type 1 Erase, Typical time units (00b: 1 ms, 01b: 16 ms, 10b:
128 ms, 11b: 1s) = 16ms = 01b
Bits 8:4 = Erase Type 1 Erase, Typical time count = 00001b (typ erase time =
(count +1) *units) = 2*16 ms = 35 ms
Bits 3:0 = Count = (Max Erase time / (2 * Typical Erase time))- 1 = 0011b
Multiplier from typical erase time to maximum erase time = 8x multiplier
Max Erase time = 2*(Count +1)*Typ Erase time
Binary Fields: 1111111_0101011_0101000_0100001_0011
Nibble Format: 1111_1110_1010_1101_0100_0010_0001_0011
Hex Format: FE_AD_42_13
13h
42h
ADh
FEh
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SFDP
Parameter
Relative Byte
Address
54h
55h
56h
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 3 of 5)
SFDP
Dword
Name
JEDEC
Basic
Flash
Parameter
Dword-11
Data
Description
81h
65h
Bits 23 = Byte Program Typical time, additional byte units (0b:1 μs, 1b:8 μs) = 1 μs
= 0b
Bits 22:19 = Byte Program Typical time, additional byte count, (count+1)*units,
count = 0010b,(typ Program time = (count +1) * units) = 3*1 μs =3 μs
Bits 18 = Byte Program Typical time, first byte units (0b:1 μs, 1b:8 μs) = 8 μs = 1b
Bits 17:14 = Byte Program Typical time, first byte count, (count+1)*units, count =
0001b, (typ Program time = (count +1) * units) = 2*8 μs = 16 μs
Bits 13 = Page Program Typical time units (0b:8 μs, 1b:64 μs) = 64 μs = 1b
Bits 12:8 = Page Program Typical time count, (count+1)*units, count = 00101b, (typ
Program time = (count +1) * units) = 6*64 μs = 400 μs
Bits 7:4 = N = 1000b, Page size= 2N = 256B page
Bits 3:0 = Count = 0001b = (Max Page Program time / (2 * Typ Page Program
time))- 1
Multiplier from typical Page Program time to maximum Page Program time = 4x
multiplier
Max Page Program time = 2*(Count +1)*Typ Page Program time
Binary Fields: 0-0010-1-0001-1-00101-1000-0001
Nibble Format: 0001_0100_0110_0101_1000_0001
Hex Format: 14_65_81
4 Mb = 1010_0101b = A5h
2 Mb = 1010_0011b = A3h
Bit 31 Reserved = 1b
Bits 30:29 = Chip Erase, Typical time units (00b: 16 ms, 01b: 256 ms, 10b: 4 s, 11b:
64 s) = 256ms= 01b
Bits 28:24 = Chip Erase, Typical time count, (count+1)*units, count = 00101b
(00011b), (typ Program time = (count +1) * units) = 6(4)*256ms = 1.5(1)s
Bit 31 = Suspend and Resume supported = 0b
Bits 30:29 = Suspend in-progress erase max latency units (00b: 128ns, 01b: 1us,
10b: 8 μs,11b: 64 μs) = 1 μs= 01b
Bits 28:24 = Suspend in-progress erase max latency count = 10011b, max erase
suspend latency = (count +1) * units = 20*1 μs = 20 μs
Bits 23:20 = Erase resume to suspend interval count = 0001b, interval = (count +1)
* 64 μs = 2* 64 μs = 128 μs
Bits 19:18 = Suspend in-progress program max latency units (00b: 128ns, 01b: 1us,
10b: 8 μs,11b: 64 μs) = 1 μs= 01b
Bits 17:13 = Suspend in-progress program max latency count = 10011b, max erase
suspend latency = (count +1) * units = 20*1 μs = 20 μs
Bits 12:9 = Program resume to suspend interval count = 0001b, interval = (count
+1) * 64 μs =2 * 64 μs = 128 μs
Bit 8 = RFU = 1b
Bits 7:4 = Prohibited operations during erase suspend
= xxx0b: May not initiate a new erase anywhere (erase nesting not permitted)
+ xx1xb: May not initiate a page program in the erase suspended sector size
+ x1xxb: May not initiate a read in the erase suspended sector size
+ 1xxxb: The erase and program restrictions in bits 5:4 are sufficient
= 1110b
Bits 3:0 = Prohibited Operations During Program Suspend
= xxx1b: May not initiate a new erase in the program suspended page size
+ xx0xb: May not initiate a new page program anywhere (program nesting not
permitted)
+ x1xxb: May not initiate a read in the program suspended page size
+ 1xxxb: The erase and program restrictions in bits 1:0 are sufficient
= 1101b
Binary Fields: 0-01-10011-0001-01-10011-0001-1-1110-1101
Nibble Format: 0011_0011_0001_0110_0110_0011_1110_1101
Hex Format: 33_16_63_ED
14h
57h
A5h/A3h
58h
59h
5Ah
EDh
63h
16h
5Bh
JEDEC
Basic
Flash
Parameter
Dword-12
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33h
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SFDP
Parameter
Relative Byte
Address
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 4 of 5)
SFDP
Dword
Name
JEDEC
Basic
Flash
Parameter
Dword-13
JEDEC
Basic
Flash
Parameter
Dword-14
7Ah
75h
7Ah
75h
F7h
A2h
D5h
5Ch
19h
F6h
DDh
64h
65h
66h
67h
Data
JEDEC
Basic
Flash
Parameter
Dword-15
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FFh
Description
Bits 31:24 = Erase Suspend Instruction = 75h
Bits 23:16 = Erase Resume Instruction = 7Ah
Bits 15:8 = Program Suspend Instruction = 75h
Bits 7:0 = Program Resume Instruction = 7Ah
Bit 31 = Deep Power-Down Supported = 0
Bits 30:23 = Enter Deep Power-Down Instruction = B9h
Bits 22:15 = Exit Deep Power-Down Instruction = ABh
Bits 14:13 = Exit Deep Power-Down to next operation delay units = (00b: 128 ns,
01b: 1 μs,
10b: 8 μs, 11b: 64 μs) = 1 μs = 01b
Bits 12:8 = Exit Deep Power-Down to next operation delay count = 00010b, Exit
Deep Power-Down to next operation delay = (count+1)*units = 3*1 μs=3 μs
Bits 7:4 = RFU = 1111b
Bit 3:2 = Status Register Polling Device Busy
= 01b: Legacy status polling supported = Use legacy polling by reading the Status
Register with 05h instruction and checking WIP bit[0] (0=ready; 1=busy).
Bits 1:0 = RFU = 11b
Binary Fields: 0-10111001-10101011-01-00010-1111-01-11
Nibble Format: 0101_1100_1101_0101_1010_0010_1111_0111
Hex Format: 5C_D5_A2_F7
Bits 31:24 = RFU = FFh
Bit 23 = Hold and WP Disable = set QE(bit 1 of SR2) high = 1b
Bits 22:20 = Quad Enable Requirements
= 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read
Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via
Write Status instruction 01h with two data bytes where bit 1 of the second byte is
one. It is cleared via Write Status with two data bytes where bit 1 of the second byte
is zero.
Bits 19:16 0-4-4 Mode Entry Method
= xxx1b: Mode Bits[7:0] = A5h Note: QE must be set prior to using this mode
+ x1xxb: Mode Bits[7:0] = Axh
+ 1xxxb: RFU
= 1101b
Bits 15:10 0-4-4 Mode Exit Method
= xx_xxx1b: Mode Bits[7:0] = 00h will terminate this mode at the end of the current
read operation
+ xx_1xxxb: Input Fh (mode bit reset) on DQ0-DQ3 for 8 clocks. This will terminate
the mode prior to the next read operation.
+ 11_x1xx: RFU
= 111101b
Bit 9 = 0-4-4 mode supported = 1
Bits 8:4 = 4-4-4 mode enable sequences = 0_0001b: set QE per QER description
above, then issue instruction 38h
Bits 3:0 = 4-4-4 mode disable sequences
= xxx1b: issue FFh instruction
+ 1xxxb: issue the Soft Reset 66/99 sequence
= 1001b
Binary Fields: 11111111-1-101-1101-111101-1-00001-1001
Nibble Format: 1111_1111-1101-1101-1111_0110_0001-1001
Hex Format: FF_DD_F6_19
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SFDP
Parameter
Relative Byte
Address
68h
69h
6Ah
6Bh
Table 5.4 Basic SPI Flash Parameter, JEDEC SFDP Rev B (Sheet 5 of 5)
SFDP
Dword
Name
JEDEC
Basic
Flash
Parameter
Dword-16
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Data
Description
E8h
30h
C0h
Bits 31:24 = Enter 4-Byte Addressing
= xxxx_xxx1b:issue instruction B7 (preceding write enable not required
+ xx1x_xxxxb: Supports dedicated 4-byte address instruction set. Consult vendor
data sheet
for the instruction set definition or look for 4-byte Address Parameter Table.
+ 1xxx_xxxxb: Reserved
= 10000000b not supported
Bits 23:14 = Exit 4-byte Addressing
= xx_xxxx_xxx1b:issue instruction E9h to exit 4-byte address mode (Write enable
instruction
06h is not required)
+ xx_xx1x_xxxxb: Hardware reset
+ xx_x1xx_xxxxb: Software reset (see bits 13:8 in this DWORD)
+ xx_1xxx_xxxxb: Power cycle
+ x1_xxxx_xxxxb: Reserved
+ 1x_xxxx_xxxxb: Reserved
= 11_0000_0000b not supported
Bits 13:8 = Soft Reset and Rescue Sequence Support
= x1_xxxxb: issue reset enable instruction 66h, then issue reset instruction 99h.
The reset enable, reset sequence may be issued on 1,2, or 4 wires depending on
the device operating mode
+ 1x_xxxxb: exit 0-4-4 mode is required prior to other reset sequences above if the
device may be operating in this mode.
= 11_0000b
Bit 7 = RFU = 1
Bits 6:0 = Volatile or Non-Volatile Register and Write Enable Instruction for Status
Register 1
= xxx_1xxxb: Non-Volatile/Volatile status register 1 powers-up to last written value
in the nonvolatile status register, use instruction 06h to enable write to non-volatile
status register. Volatile status register may be activated after power-up to override
the non-volatile status register, use instruction 50h to enable write and activate the
volatile status register.
+ x1x_xxxxb: Reserved
+ 1xx_xxxxb: Reserved
= 1101000b
Binary Fields: 10000000-1100000000-110000-1-1101000
Nibble Format: 1000_0000_1100_0000_0011_0000_1110_1000
Hex Format: 80_C0_30_E8
80h
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FUNCTION DESCRIPTION
SPI Operations
SPI Modes
The HG25Q40/20 can be driven by an embedded microcontroller (bus master) in either of the two
following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data is always latched in on the rising edge of the CLK signal and the output
data is always available on the falling edge of the CLK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and
not transferring any data.
CLK will stay at logic low state with CPOL = 0, CPHA = 0
CLK will stay at logic high state with CPOL = 1, CPHA = 1
Figure 6.1 SPI Modes
Timing diagrams throughout the rest of the document are generally shown as both mode 0 and 3 by
showing CLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0
with CLK low at the fall of CS#. In such case, mode 3 timing simply means clock is high at the fall of CS# so
no CLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.
CLK cycles are measured (counted) from one falling edge of CLK to the next falling edge of CLK. In
mode 0 the beginning of the first CLK cycle in a command is measured from the falling edge of CS# to the first
falling edge of CLK because CLK is already low at the beginning of a command.
Dual SPI Modes
The HG25Q 40/20 supports Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast
Dual I/O (BBh) instruction. These features allow data to be transferred from the device at twice the rate
possible with the standard SPI. These instructions are ideal for quickly downloading code to RAM upon
Power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When
using Dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI Modes
The HG25Q40/20 supports Quad SPI operation when using the Fast Read Quad Output (6Bh), Fast
Read Quad I/O (EBh) instruction, Word Read Quad I/O(E7h), and Octal Word Read Quad I/O(E3h). These
instructions allow data to be transferred to or from the device four times the rate of ordinary Serial Flash. The
Quad Read instructions offer a significant improvement in continuous and random access transfer rates
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allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins
become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
Hold Function
For Standard SPI and Dual SPI operations, the HOLD# / RESET# (IO3) signal allows the device interface
operation to be paused while it is actively selected (when CS# is low). The Hold function may be useful in
cases where the SPI data and clock signals are shared with other devices. For example, if the page buffer is
only partially written when a priority interrupt requires use of the SPI bus, the Hold function can save the state
of the interface and the data in the buffer so programming command can resume where it left off once the bus
is available again. The Hold function is only available for standard SPI and Dual SPI operation, not during
Quad SPI.
To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on
the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold
condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of
the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will
terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (DO) or IO0 and
IO1, are high impedance and Serial Data Input, (DI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The
Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid
resetting the internal logic state of the device.
Software Reset & Hardware RESET# pin
The HG25Q40/20 can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the
command sequence is successfully accepted, the device will take approximately 10us (tRST) to reset. No
command will be accepted during the reset period.
HG25Q40/20 can also be configured to utilize a hardware RESET# pin. The HRSW bit in the Status
Register-3 is the configuration bit for HOLD# pin function or RESET# pin function. When HRSW=0 (factory
default), the pin acts as a HOLD# pin as described above; when HRSW =1, the pin acts as a RESET# pin.
Drive the RESET# pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on
state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While
RESET# is low, the device will not accept any command input.
If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four
data I/O pins.
Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status
of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#).
Note:
1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to
ensure reliable operation.
Status Register
The Read and Write Status Registers commands can be used to provide status and control of the flash
memory device.
Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of
the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad
SPI setting, Security Register lock status, and Erase / Program Suspend status.
SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:0] that control sector protection,
OTP Register Protection, Status Register Protection, and Quad mode. Bits located in SR2[7], SR1[1], and
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SR1[0] are read only volatile bits for suspend, write enable, and busy status. These are updated by the
memory control logic. The SR1[1] write enable bit is set only by the Write Enable (06h) command and cleared
by the memory control logic when an embedded operation is completed.
Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status
Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable command (06h) preceding a Write
Status Registers command, and while Quad mode is not enabled, the WP# pin.
A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode is
used to control the behavior of these features after power up. During power up or software reset, these
volatile bits are loaded from the non-volatile version of the Status Register bits. The Write Enable for Volatile
Status Register (50h) command can be used to write these volatile bits when the command is followed by a
Write Status Registers (01h/31h) command. This gives more flexibility to change the system configuration and
memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the
endurance of the Status Register non-volatile bits.
Write access to the volatile SR1 and SR2 Status Register bits is controlled by the state of the non-volatile
Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable for Volatile Status Register
command (50h) preceding a Write Status Registers command, and the WP# pin while Quad mode is not
enabled.
Status Register-3 (SR3) is used to configure and provide status on the variable HOLD# or RESET#
function, Output Driver Strength, High Frequency Enable Bit and read latency.
Write access to the volatile SR3 Status Register bits is controlled by Write Enable for Volatile Status
Register command (50h) preceding a Write Status Register command. The SRP bits do not protect SR3.
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Table 6.1 Status Register-1 (SR1)
Bits
Default
State
Field
Function
Type
7
SRP0
Status Register
Protect 0
6
SEC
Sector / Block
Protect
5
TB
Top / Bottom
protect
4
3
2
BP2
BP1
BP0
Block Protect
Bits
1
WEL
Write Enable
Latch
Volatile,
Read only
0
0 = Not Write Enabled, no embedded
operation can start
1 = Write Enabled, embedded operation can
start
0
BUSY
Embedded
Operation
Status
Volatile,
Read only
0
0 = Not Busy, no embedded operation in
progress
1 = Busy, embedded operation in progress
Non-volatile
and Volatile
versions
Description
0
0 = WP# input has no effect or Power Supply
Lock Down mode
1 = WP# input can protect the Status
Register or OTP Lock Down.
0
0 = BP2-BP0 protect 64-kB blocks
1 = BP2-BP0 protect 4-kB sectors
0
0 = BP2-BP0 protect from the Top down
1 = BP2-BP0 protect from the Bottom up
0
0
0
000b = No protection
Table 6.2 Status Register-2 (SR2)
Bits
Field
Function
Type
Default
State
7
SUS
Suspend Status
Volatile, Read
Only
0
0 = Erase / Program not suspended
1 = Erase / Program suspended
6
CMP
Complement
Protect
Non-volatile and
Volatile versions
0
0 = Normal Protection Map
1 = Complementary Protection Map
5
LB3
0
Security Register
Lock Bits
4
LB2
3
LB1
0
2
Reserve
0
1
QE
0
OTP
Quad Enable
SRP1
Status Register
Protect 1
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19
OTP Lock Bits 3:0 for Security Registers
3:0
0 = Security Register not protected
1 = Security Register protected
0
0 = Quad Mode Not Enabled, the WP# pin
and HOLD# / RESET# are enabled
1 = Quad Mode Enabled, the IO2 and IO3
pins are enabled, and WP# and HOLD# /
RESET# functions are disabled
0
0 = SRP1 selects whether WP# input has
effect on protection of the status register
1 = SRP1 selects Power Supply Lock Down
or OTP Lock Down mode
Non-volatile and
Volatile versions
0
Description
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Bits
Field
7
HRSW(1)
6
DRV1(1)
Function
HOLD# or
RESET#
function
DRV0(1)
4
HFM
Type
Non-volatile
and Volatile
versions
Default State
0
The DRV1 & DRV0 bits are used to determine
the output driver strength for the Read
operations.
Volatile
0
High
Frequency
Mode Enable
Bit
Non-volatile
and Volatile
versions
0
3
2
Description
When HRSW=0, the pin acts as HOLD#; when
HRSW=1, the pin acts as RESET#. HRSW
functions are only available when QE=0.
0
Output Driver
Strength
5
Table 6.3 Status Register-3 (SR3)
0 =High Frequency Mode Disabled
1 =High Frequency Mode Enabled
0
0
Reserve
1
0
0
0
Note:
1.Default state for these three bits could be modified. please contact sales.
BUSY
BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is
executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction.
During this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled.
A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers
Command (see tW in Section 8.5). All, none or a portion of the memory array can be protected from Program
and Erase commands (see Section 6.4.2, Block Protection Maps). The factory default setting for the Block
Protection Bits is 0 (none of the array is protected.)
Top / Bottom Block Protect (TB)
The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0)
protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection
Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command
depending on the state of the SRP0, SRP1 and WEL bits.
Sector / Block Protect (SEC)
The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) of the array as shown in Section 6.4.2, Block
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Protection Maps. The default setting is SEC=0.
Complement Protect (CMP)
The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]).
It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be
reversed. For instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not;
when CMP=1, the top 4-kB sector will become unprotected while the rest of the array become read-only.
Refer to Section 6.4.2, Block Protection Maps for details. The default setting is CMP=0.
The Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register
(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down, or one time programmable (OTP) protection.
SRP1
SRP0
WP#
Table 6.4 Status Register Protect
Status Register
Description
0
0
X
Software Protection
WP# pin has no control. SR1 and SR2 can be written to after a
Write Enable command, WEL=1. [Factory Default]
0
1
0
Hardware Protected
When WP# pin is low the SR1 and SR2 are locked and cannot
be written.
0
1
1
Hardware
Unprotected
When WP# pin is high SR1 and SR2 are unlocked and can be
written to after a Write Enable command, WEL=1.
1
0
X
Power Supply Lock
Down
SR1 and SR2 are protected and cannot be written to again until
the next power-down, power-up cycle. (1)
1
1
X
One Time Program (2)
SR1 and SR2 are permanently protected and cannot be written.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up, or Software Reset cycle will change SRP1, SRP0 to (0, 0) state.
2. The One-Time Program feature is available upon special order. Contact Zbit for details.
3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status
Registers command.
4. The non-volatile version of HRSW, HFM, CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR3[7,4], SR2[6,1,0] and
SR1[6:2]) bits and the OTP LB3-LB1 bits are not writable when protected by the SRP bits and WP# as shown in the table.
The non-volatile version of these Status Register bits is selected for writing when the Write Enable (06h) command
precedes the Write Status Registers (01h) command.
5. The volatile version of HRSW, DRV1, DRV0, HFM, CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR3[7:4], SR2[6,1,0]
and SR1[6:2]) bits are not writable when protected by the SRP bits and WP# as shown in the table. The volatile version of
these Status Register bits is selected for writing when the Write Enable for volatile Status Register (50h) command precedes
the Write Status Registers (01h) command. There is no volatile version of the LB3-LB1 bits and these bits are not affected
by a volatile Write Status Registers command.
Erase / Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an
Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume
(7Ah) command as well as a power-down, power-up cycle.
Security Register Lock Bits (LB3, LB2, LB1)
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (SR2[5:2]) that provide the write protect control and status to the Security Registers. The default
state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using the Write
Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the corresponding
256-byte Security Register will become read-only permanently.
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows
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Quad SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# / RESET#
are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# /
RESET# functions are disabled.
Note: If the WP# or HOLD# / RESET# pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the
QE bit should never be set to a 1.
HOLD# or RESET# Pin Function (HRSW)
The HRSW bit is used to determine whether HOLD# or RESET# function should be implemented on the
hardware pin for 8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as
RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD#
and RESET# functions are disabled, the pin acts as a dedicated data I/O pin.
Output Driver Strength (DRV1, DRV0)
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
0, 0
0, 1
1, 0
1, 1
Driver Strength
50%
25%
75%(default)
100%
High Frequency Mode Enable Bit (HFM)
The HFM bit is used to determine whether the device is in High Frequency Mode. When HFM bit sets to 1,
it means the device is in High Frequency Mode, when HFM bit sets 0 (default), it means the device is not in
High Frequency Mode. After the HFM is executed, the device will maintain a slightly higher standby current
(ICC8) than standard SPI operation.
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HG25Q40
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the HG25Q40/20
provides the following data protection mechanisms:
Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-Up
Write enable / disable commands and automatic write disable after erase or program
Command length protection
- All commands that Write, Program or Erase must complete on a byte boundary (CS# driven high after
a full 8 bits have been clocked) otherwise the command will be ignored.
Software and Hardware write protection using Status Register control
- WP# input protection
- Lock Down write protection until next power-up or Software Reset
- One-Time Program (OTP) write protection
Write Protection using the Deep Power-Down command
Upon power-up or at power-down, the HG25Q40/20 will maintain a reset condition while VCC is below
the threshold value of VWI, (see Figure 8.1). While reset, all operations are disabled and no commands are
recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related
commands are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program,
Sector Erase, Block Erase, Chip Erase and the Write Status Registers commands. Note that the chip select
pin (CS#) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached.
If needed a pull-up resistor on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a
program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled main flash array write protection is facilitated using the Write Status Registers
command to write the Status Register (SR1,SR2) and Block Protect (SEC, TB, BP2, BP1 and BP0) bits.
The BP method allows a portion as small as 4-kB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be
enabled or disabled under hardware control. See the Table 6.4 for further information.
Additionally, the Deep Power-Down (DPD) command offers an alternative means of data protection as all
commands are ignored during the DPD state, except for the Release from Deep-Power-Down (RES ABh)
command. Thus, preventing any program or erase during the DPD state.
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HG25Q40
Block Protection Maps
Table 6.6 HG25Q40 Block Protection (CMP = 0)
Status Register (1)
HG25Q40(4 Mbit) Block Protection (CMP=0) (2)
Protected
Protected Block(s)
Protected Addresses
Density
Protected
Portion
SEC
TB
BP2
BP1
BP0
X
X
0
0
0
None
None
None
None
0
0
0
0
1
7
070000h – 07FFFFh
64 kB
Upper 1/8
0
0
0
1
0
6 and 7
060000h – 07FFFFh
128 kB
Upper 1/4
0
0
0
1
1
4 thru 7
040000h – 07FFFFh
256 kB
Upper 1/2
0
1
0
0
1
0
000000h – 00FFFFh
64 kB
Lower 1/8
0
1
0
1
0
0 and 1
000000h – 01FFFFh
128 kB
Lower 1/4
0
1
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/2
0
X
1
X
X
0 thru 7
000000h – 07FFFFh
512 kB
All
1
0
0
0
1
7
07F000h – 07FFFFh
4 kB
Upper
1/128
1
0
0
1
0
7
07E000h – 07FFFFh
8 kB
Upper 1/64
1
0
0
1
1
7
07C000h – 07FFFFh
16 kB
Upper 1/32
1
0
1
0
X
7
078000h – 07FFFFh
32 kB
Upper 1/16
1
0
1
1
0
7
078000h – 07FFFFh
32 kB
Upper 1/16
1
1
0
0
1
0
000000h – 000FFFh
4 kB
Lower
1/128
1
1
0
1
0
0
000000h – 001FFFh
8 kB
Lower 1/64
1
1
0
1
1
0
000000h – 003FFFh
16 kB
Lower 1/32
1
1
1
0
X
0
000000h – 007FFFh
32 kB
Lower 1/16
1
1
1
1
0
0
000000h – 007FFFh
32 kB
Lower 1/16
1
X
1
1
1
0 thru 7
000000h – 07FFFFh
512 kB
All
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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HG25Q40
Status Register (1)
Table 6.7 HG25Q40 Block Protection (CMP = 1)
HG25Q40(4 Mbit) Block Protection (CMP=1) (2)
Protected
Protected Block(s)
Protected Addresses
Density
Protected
Portion
SEC
TB
BP2
BP1
BP0
X
X
0
0
0
0 thru 7
000000h – 007FFFh
512 kB
All
0
0
0
0
1
0 thru 6
000000h – 06FFFFh
448 kB
Lower 7/8
0
0
0
1
0
0 thru 5
000000h – 05FFFFh
384 kB
Lower 3/4
0
0
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/2
0
1
0
0
1
1 thru 7
010000h – 07FFFFh
448 kB
Upper 7/8
0
1
0
1
0
2 thru 7
020000h – 07FFFFh
384 kB
Upper 3/4
0
1
0
1
1
4 thru 7
040000h – 07FFFFh
256 kB
Upper 1/2
0
X
1
X
X
None
None
None
None
1
0
0
0
1
0 thru 7
000000h – 07EFFFh
508 kB
1
0
0
1
0
0 thru 7
000000h – 07DFFFh
504 kB
1
0
0
1
1
0 thru 7
000000h – 07BFFFh
496 kB
1
0
1
0
X
0 thru 7
000000h – 077FFFh
480 kB
1
0
1
1
0
0 thru 7
000000h – 077FFFh
480 kB
1
1
0
0
1
0 thru 7
001000h – 07FFFFh
4 kB
1
1
0
1
0
0 thru 7
002000h – 07FFFFh
8 kB
1
1
0
1
1
0 thru 7
004000h – 07FFFFh
16 kB
1
1
1
0
X
0 thru 7
008000h – 07FFFFh
32 kB
1
1
1
1
0
0 thru 7
008000h – 07FFFFh
32 kB
1
X
1
1
1
None
None
None
Lower
127/128
Lower
63/64
Lower
31/32
Lower
15/16
Lower
15/16
Upper
127/128
Upper
63/64
Upper
31/32
Upper
15/16
Upper
15/16
None
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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HG25Q40
Page Program
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program
cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to
be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the
same page of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to be erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector
Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire
memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration tSE tBE or tCE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling during a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In Progress (WIP)
bit is provided in the Status Register so that the application program can monitor its value, polling it to
establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have
completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The
device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode
until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI)
instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Program or Erase instructions.
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HG25Q40
INSTRUCTIONS
The instruction set of the HG25Q40/20 consists of forty basic instructions that are fully controlled
through the SPI bus. Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data
clocked into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of
clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising
edge of edge CS#. Clock relative timing diagrams for each instruction are included in figures 7.1 through 7.43.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register and Erase/Program Suspend will be ignored until the program or erase cycle
completes.
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HG25Q40
Table 7.1 Command Set (Configuration, Status, Erase, Program Instructions (1), SPI Mode)
Command Name
BYTE 1
(Instruction)
BYTE 2
Read Status Register-1
05h
SR1[7:0](2)
Read Status Register-2
35h
SR2[7:0](2)
Read Status Register-3
15h/33h
SR3[7:0](2)
BYTE 3
BYTE 4
BYTE 5
Write Enable
06h
Write Enable for Volatile
Status Register
50h
Write Disable
04h
Write Status Registers-1
01h
SR1[7:0](5)
Write Status Registers-2
31h
SR2[7:0]
Write Status Registers-3
11h
SR3[7:0]
Set Burst with Wrap
77h
xxh
xxh
xxh
W[7:0](3)
Page Program
02h
A23—A16
A15—A8
A7—A0
D7—D0
Quad Page Program
32h
A23—A16
A15—A8
A7—A0
D7—D0(4)
Sector Erase (4 KB)
20h
A23—A16
A15—A8
A7—A0
Block Erase (32 KB)
52h
A23—A16
A15—A8
A7—A0
Block Erase (64 KB)
D8h
A23—A16
A15—A8
A7—A0
Chip Erase
BYTE 6
C7h/60h
Erase/Program
75h
Suspend
Erase/Program Resume
7Ah
Enable Reset
66h
Reset Device
99h
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data
being read from the device on the DO pin.
2. Status Register contents will repeat continuously until CS# terminates the command.
3. Set Burst with Wrap Input format.
IO0 = x, x, x, x, x, x, W4, x]
IO1 = x, x, x, x, x, x, W5, x]
IO2 = x, x, x, x, x, x, W6 x]
IO3 = x, x, x, x, x, x, x,x
4. Quad Page Program Input Data:
IO0 =(D4,D0,...)
IO1 = ( D5,D1,...)
IO2 = ( D6,D2,...)
IO3 =( D7,D3,...)
5. The 01h command could continuously write up to three bytes to registers SR1, SR2, SR3.
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Table 7.2 Command Set (Read Instructions (1), SPI Mode)
Command Name
BYTE 1
(Instruction)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Read Data
03h
A23—A16
A15—A8
A7—A0
(D7—D0,…)
Fast Read
Fast Read Dual
Output
Fast Read Quad
Output
0Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)
3Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)(1)
6Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)(3)
Fast Read Dual I/O
BBh
A23—A8(2)
A7—A0,M7
—M0(2)
(D7—D0,…)(1)
Fast Read Quad
I/O
EBh
A23—A0,M7
—M0(4)
(x,x,x,x,D7—
D0,...)
(D7—D0,…)(3)
QUAD I/O WORD
FAST READ(5)
E7H
A23—A0,M7
—M0(4)
(x,x,D7—D0,
...)
(D7—D0,…)(3)
Octal Word Read
Quad I/O(5)
E3h
A23—A0,M7
—M0(4)
(D7—D0,…)(
3)
(D7—D0,…)(3)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0),and for Octal Word Read Quad I/O, the lowest four
address bits must be 0. (A3, A2, A1, A0 = 0)
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HG25Q40
Table 7.3 Command Set (Read ID, OTP Instructions (1), SPI Mode)
Command
Name
BYTE 1
(Instruction)
Deep
Power-down
Release
Power down /
Device ID
Manufacturer/
Device ID(2)
Manufacturer/
Device ID by
Dual I/O
Manufacturer/
Device ID by
Quad I/O
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
ABh
dummy
dummy
dummy
Device ID(1)
90h
dummy
dummy
00h
Manufacturer
Device ID
92h
A23—A8
A7—A0,M[7:0]
(MF[7:0],ID[7:0])
94h
A23—A0,M[7:0]
XXXX,(MF[7:0],ID[7:0])
(MF[7:0],ID[7:0]...)
9Fh
Manufacturer
Memory Type
Capacity
5Ah
00h
00h
A7—A0
dummy
(D7—D0,…)
48h
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)
44h
A23—A16
A15—A8
A7—A0
42h
A23—A16
A15—A8
A7—A0
D7—D0,…
4Bh
dummy
dummy
dummy
dummy
B9h
JEDEC ID
Read SFDP
Register
Read
Security
Registers(3)
Erase
Security
Registers(3)
Program
Security
Registers(3)
Read Unique
ID
(ID63-ID0)
Notes:
1. The Device ID will repeat continuously until CS# terminates the command.
2. See Section 6.4.1, Legacy Device Identification Commands on page 51 for Device ID information. The 90h instruction is followed
by an address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table. Address = 1 selects Device ID as
the first returned data followed by Manufacturer ID.
3. Security Register Address:
Security Register 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
Table 7.4(1) Manufacturer and Device Identification(HG25Q40 )
OP Code
Data1
Data2
Data3
ABh
Device ID = 12h
-
-
90h/92h/94h
Manufacturer ID = 5E
Device ID = 12h
-
9Fh
Manufacturer ID = 5E
Memory Type =60h
Capacity = 13h
Notes:
(1)Please contact sales for more information
Table 7.5(1) Manufacturer and Device Identification(HG25Q 20 )
OP Code
Data1
Data2
Data3
ABh
Device ID = 11h
-
-
90h/92h/94h
Manufacturer ID = 5E
Device ID = 11h
-
9Fh
Manufacturer ID = 5E
Memory Type =60h
Capacity = 12h
Notes:
(1)Please contact sales for more information
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HG25Q40
Configuration and Status Commands
Read Status Register (05h/35h/15h)
The Read Status Register commands allow the 8-bit Status Registers to be read. The command is
entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status
Register-2, “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The Status Register bits are
then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 7.1. The Status Register bits are shown in Section 6.2, Status Registers.
The Read Status Register-1 (05h) command may be used at any time, even during a Program, Erase, or
Write Status Registers cycle. This allows the BUSY status bit to be checked to determine when the operation
is complete and if the device can accept another command.
Figure 7.1 Read Status Register Instruction
Write Enable (06h)
The Write Enable instruction (Figure 7.2) sets the Write Enable Latch (WEL) bit in the Status Register to
a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write
Status Register instruction. The Write Enable instruction is entered by driving CS# low, shifting the instruction
code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high.
Figure 7.2 Write Enable Instruction
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 6.2 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register
non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for
Volatile Status Register instruction (Figure 7.3) will not set the Write Enable Latch (WEL)bit, it is only valid for
the Write Status Register instruction to change the volatile Status Register bit values.
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Figure 7.3 Write Enable for Volatile Status Register Instruction
Write Disable (04h)
The Write Disable instruction (Figure 7.4) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the
DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
instructions.
Figure 7.4 Write Disable Instruction
Write Status Register (01h/31h/11h)
The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and the
volatile bits SR3[6:0] can be written. All other Status Register bit locations are read-only and will not be
affected by the Write Status Registers command. LB[3:0] are non-volatile OTP bits; once each is set to 1, it
cannot be cleared to 0. The Status Register bits are shown in Section 6.2, Status Registers. Any reserved bits
should only be written to their default value.
To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have
been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must
equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”,
and then writing the Status Register data bytes as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must
have been executed prior to the Write Status Registers command (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1 cannot be changed because of the OTP protection for these bits. Upon
power-off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values will
be restored when power on again.
To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of
a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status
Registers command will not be executed.
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal to 1). Once write enabled, the instruction is entered by driving CS# low, sending
the instruction code “01h”, and then writing the status register data byte as illustrated in Figure 7.5.
During non-volatile Status Register write operation (06h combined with 01h/31h), after CS# is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
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While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and
a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register
cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program
the Status Register-1, the Status Register-2 will not be affected.
Figure 7.5 Write Status Register Instruction
Program and Erase Commands
Page Program (PP) (02h)
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to
all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the
Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one
data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is
being sent to the device. The Page Program instruction sequence is shown in Figure 7.6.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more
than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite
previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still
be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the
Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Page Program instruction will not be executed if the addressed page is protected by the Block Protect (TB,
SEC, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
Figure 7.6a Page Program Instruction
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Quad Input Page Program (32h)
The Quad Input Page Program instruction allows up to 256 byte of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2 and IO3. The Quad Input Page Program can
improved performance for PROM Programmer and applications that have slow clock speeds
