TP2412-SR

3PEAK TP2411/TP2412 /TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Features Description  Gain-bandwidth Product: 10 MHz  Low Noise: 8.2 nV/√Hz(f= 1kHz)  Slew Rate: 7 V/μs  Offset Voltage: 1 mV (max)  EMIRR IN+: 88 dB( under 2.4GHz)  Low THD+N: 0.0005%  Supply Range: 2.2 V to 5.5 V  Supply Current: 1.4 mA/ch  Low Input Bias Current: 0.3pA Typical  Rail-to-Rail I/O The TP2411, TP2412, and TP2414 are low cost, single, dual, and quad rail-to-rail output, single-supply amplifiers featuring low offset and input voltages, low current noise, and wide signal bandwidth. The combination of low offset, low noise, very low input bias currents, and high speed make these amplifiers useful in a wide variety of applications. Filters, integrators, photodiode amplifiers, and high impedance sensors all benefit from this combination of performance features. Audio and other ac applications benefit from the wide bandwidth and low distortion of these devices.  High Output Current: 70 mA (1.0V Drop)  –40°C to 125°C Operation Range Applications for these amplifiers include power amplifier (PA) controls, laser diode control loops, portable and loop-powered instrumentation, audio amplification for portable devices, and ASIC input and output amplifiers. The TP2411 is single channel version available in 8-pin SOP and 5-pin SOT23 packages. The TP2412 is dual channel version available in 8-pin SOP, SOT, TSSOP and MSOP packages. The TP2414 is quad channel version available in 14-pin SOP and TSSOP packages. Applications  Sensor Signal Conditioning  Consumer Audio  Multi-Pole Active Filters  Control-Loop Amplifiers  Communications  Security  Scanners 3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All other trademarks are the property of their respective owners. Pin Configuration (Top View) TP2412 8-Pin SOP/MSOP/SOT/TSSOP (-S Suffix) (-S ,-V, -T, -TS Suffixes) NC 1 8 NC Out A 1 ﹣In 2 7 ﹢Vs ﹣In A 2 ﹢In 3 6 Out ﹢In A 3 ﹣Vs 4 5 NC ﹣Vs 4 Out 1 ﹣Vs 2 +In 3 A B 8 ﹢Vs 7 Out B 6 ﹣In B 5 ﹢In B TP2411 5-Pin SOT23 TP2414 14-Pin SOP/TSSOP (-T Suffix) (-S and -T Suffixes) 5 ﹢Vs Out A 1 14 Out D ﹣In A 2 13 ﹣In D A 4 -In www.3peakic.com.cn 1000 VCC= +5V RL= 1kΩ 100 10 D ﹢In A 3 12 ﹢In D ﹢Vs 4 11 ﹣Vs ﹢In B 5 10 ﹢In C ﹣In B 6 9 ﹣In C Out B 7 8 Out C B Input Voltage Noise Spectral Density Noise(nV/√Hz) TP2411 8-Pin SOP C 1 1 10 100 1k 10k 100k 1M Frequency(Hz) Rev. B 1 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Order Information Model Name TP2411 TP2412 TP2414 Order Number Package Marking Information Transport Media, Quantity TP2411-SR 8-Pin SOP Tape and Reel, 4,000 TP2411 TP2411-TR 5-Pin SOT23 Tape and Reel, 3,000 411 TP2412-SR 8-Pin SOP Tape and Reel, 4,000 TP2412 TP2412-VR 8-Pin MSOP Tape and Reel, 3,000 TP2412 TP2412-TSR 8-Pin TSSOP Tape and Reel, 3,000 TP2412 TP2412-TR 8-Pin SOT23 Tape and Reel, 3,000 412 TP2414-SR 14-Pin SOP Tape and Reel, 2,500 TP2414 TP2414-TR 14-Pin TSSOP Tape and Reel, 3,000 TP2414 Absolute Maximum Ratings Note 1 Supply Voltage: V+ – V– Note 2............................7.0V Input Voltage............................. V– – 0.3 to V+ + Operating Temperature Range........–40°C to 125°C 0.3 Maximum Junction Temperature................... 150°C Input Current: +IN, –IN Note 3.......................... ±20mA Storage Temperature Range.......... –65°C to 150°C Output Short-Circuit Duration Note 4…......... Indefinite Lead Temperature (Soldering, 10 sec) ......... 260°C Current at Supply Pins……………............... ±60mA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The op amp supplies must be established simultaneously, with, or before, the application of any input signals. Note 3: The inputs are protected by ESD protection diodes to each power supply. If the input extends more than 500mV beyond the power supply, the input current should be limited to less than 10mA. Note 4: A heat sink may be required to keep the junction temperature below the absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Thermal resistance varies with the amount of PC board metal connected to the package. The specified values are for short traces connected to the leads. ESD, Electrostatic Discharge Protection Symbol Parameter Condition Minimum Level Unit HBM Human Body Model ESD MIL-STD-883H Method 3015.8 2 kV CDM Charged Device Model ESD JEDEC-EIA/JESD22-C101E 1 kV Thermal Resistance 2 Package Type θJA θJC Unit 5-Pin SOT23 250 81 ° C/W 8-Pin SOP 158 43 ° C/W 8-Pin MSOP 210 45 ° C/W 8-Pin TSSOP 191 8-Pin SOT23 196 70 ° C/W 14-Pin SOP 120 36 ° C/W 14-Pin TSSOP 180 35 ° C/W Rev. B ° C/W www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Electrical Characteristics The specifications are at TA = 27° C. VS = 5V, RL = 2kΩ, CL =100pF.Unless otherwise noted. SYMBOL VOS VOS TC IB PARAMETER Input Offset Voltage Input Offset Voltage Drift Input Bias Current CONDITIONS MIN TYP MAX UNITS VCM = VS/2 -1 ± 0.25 +1 mV VCM = 0V -1 ± 0.25 1 +1 mV -40° C to 125° C μV/° C TA = 27 ° C 0.3 pA TA = 85 ° C 150 pA TA = 125 ° C 300 pA 0.3 pA IOS Input Offset Current Vn Input Voltage Noise f = 0.1Hz to 10Hz 3.14 μVPP en in Input Voltage Noise Density Input Current Noise 8.2 Input Capacitance 90 2 8 7 106 nV/√Hz fA/√Hz CIN f = 1kHz f = 1kHz Differential Common Mode VCM = 2.5V VCM = 0V to 3V 80 106 dB VCM = 0V to 5V 55 72 dB CMRR Common Mode Rejection Ratio pF dB PSRR Common-mode Input Voltage Range Power Supply Rejection Ratio VS = 2.2V to 5.5V, VCM = 0V 82 100 dB AVOL Open-Loop Large Signal Gain RLOAD = 2kΩ, VOUT = -2V to 2V 100 120 dB VOL, VOH Output Swing from Supply Rail RLOAD = 2kΩ 20 ROUT Closed-Loop Output Impedance G = 1, f =1MHz, IOUT = 0 0.2 Ω RO Open-Loop Output Impedance f = 1kHz, IOUT = 0 125 Ω ISC Output Short-Circuit Current Sink or source current 130 mA VS Supply Voltage IQ Quiescent Current per Amplifier VS = 5V 1.4 PM Phase Margin RLOAD = 1kΩ, CLOAD = 60pF 60 ° GM Gain Margin RLOAD = 1kΩ, CLOAD = 60pF 8 dB Gain-Bandwidth Product f = 1kHz AV = 1, VOUT = 0V to 10V, CLOAD = 100pF, RLOAD = 2kΩ 10 MHz 7 V/μs 414 0.75 0.85 kHz 0.0005 % 110 dB VCM GBWP SR FPBW tS THD+N Xtalk Slew Rate Full Power Bandwidth Note 1 Settling Time, 0.1% Settling Time, 0.01% Total Harmonic Distortion and Noise Channel Separation V– -0.1 100 V+-0.1 2.2 AV = –1, 1V Step f = 1kHz, AV =1, RL = 2kΩ, VOUT = 1Vp-p f = 1kHz, RL = 2kΩ 3.0 50 V mV 5.5 V 1.95 mA μs Note 1: Full power bandwidth is calculated from the slew rate FPBW = SR/π • VP-P www.3peakic.com.cn Rev. B 3 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. Offset Voltage Production Distribution Unity Gain Bandwidth vs. Temperature 1000 15 Number = 38300 pcs 14.9 800 14.8 700 14.7 600 GBW(MHz) Population 900 500 400 14.6 14.5 14.4 300 14.3 200 14.2 100 14.1 0 -990 -890 -790 -690 -590 -490 -390 -290 -190 -90 10 110 210 310 410 510 610 710 810 910 14 -40 -20 0 20 40 Open-Loop Gain and Phase 80 100 120 Input Voltage Noise Spectral Density 140 1000 330 120 100 VCC= +5V RL= 1kΩ 40 30 20 Phase (°) 130 60 -70 0 -20 Noise(nV/√Hz) 230 80 Gain(dB) 60 Temperature(℃) Offset Voltage(uV) 100 10 -170 -40 -60 0.1 10 1k 100k 10M 1 -270 1000M 1 10 Input Bias Current vs. Temperature 1k 10k 100k 1M Input Bias Current vs. Input Common Mode Voltage 5.00E-16 1.00E-11 Input Bias Current(A) 1.00E-13 Input Bias Current(A) 100 Frequency(Hz) Frequency (Hz) 1.00E-15 1.00E-17 5.00E-17 1.00E-19 5.00E-18 1.00E-21 -10 10 30 50 70 90 110 Temperature(℃) 4 Rev. B 130 150 0 1 2 3 4 5 Common Mode Voltage(V) www.3peakic.com.cn 6 TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) Common Mode Rejection Ratio CMRR vs. Frequency 180 140 160 120 140 120 CMRR(dB) CMRR(dB) 100 80 60 100 80 60 40 40 20 20 0 0 0 1 2 3 1 4 100 Quiescent Current vs. Temperature 1M 100M Short Circuit Current vs. Temperature 1.48 200 1.46 180 160 1.44 ISINK 140 1.42 Ishort(mA) Supply current(mA) 10k Frequency(Hz) Common Mode Voltage(V) 1.4 1.38 120 100 1.36 ISOURCE 80 60 1.34 40 1.32 20 0 1.3 -40 -15 10 35 60 85 -50 110 0 50 100 150 Temperature(℃) Temperature(℃) Power-Supply Rejection Ratio Quiescent Current vs. Supply Voltage 1.8 140 1.6 PSRR(dB) 100 PSRR+ 80 PSRR- 60 40 20 Supply current (mA) 120 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1 100 10k Frequency(Hz) www.3peakic.com.cn 1M 0 1.5 2.5 3.5 4.5 5.5 Supply Voltage (V) Rev. B 5 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) Power-Supply Rejection Ratio vs. Temperature CMRR vs. Temperature 140 120 120 100 80 CMRR(-dB) PSRR(-dB) 100 80 60 60 40 40 20 20 0 0 -50 0 50 100 -50 150 0 50 100 150 Temperature(℃) Temperature(℃) EMIRR IN+ vs. Frequency Large-Scale Step Response 100 90 Output Voltage (2V/div) EMIRR IN+ (dB) 80 70 60 50 40 30 20 Gain= +1 RL= 10kΩ 10 0 40 400 4000 Frequency (MHz) Time (20μs/div) Time (500ns/div) 6 Positive Over-Voltage Recovery 2V/div Gain= +10 ±V= ±2.5V 1V/div Gain= +10 ±V= ±2.5V 1V/div 2V/div Negative Over-Voltage Recovery Rev. B Time (500ns/div) www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Typical Performance Characteristics VS = ±2.75V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 0.1 Hz TO 10 Hz Input Voltage Noise Offset Voltage vs Common-Mode Voltage 500 2μV/div Offset voltage(μV) 0 Vcc=±2.5V -500 -1000 -1500 -2000 -2500 -3000 -2.5 5s/div -0.5 0.5 1.5 2.5 Common-mode voltage(V) Positive Output Swing vs. Load Current Negative Output Swing vs. Load Current 0 140 -20 -40℃ 120 25℃ -40 100 -60 Iout(mA) +125℃ Iout(mA) -1.5 80 60 -80 -100 -120 +125℃ -140 40 25℃ -160 20 -40℃ -180 0 0 1 2 3 Vout Dropout (V) www.3peakic.com.cn 4 5 -200 0 1 2 3 4 5 Vout Dropout (V) Rev. B 7 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Pin Functions -IN: Inverting Input of the Amplifier. possible should be used between power supply pins or +IN: Non-Inverting Input of Amplifier. between supply pins and ground. OUT: Amplifier Output. The voltage range extends to V- or -Vs: Negative Power Supply. It is normally tied to within mV of each supply rail. ground. It can also be tied to a voltage other than V+ or +Vs: Positive Power Supply. Typically the voltage ground as long as the voltage between V+ and V– is from is from 2.2V to 5.5V. Split supplies are possible as long 2.2V to 5.5V. If it is not connected to ground, bypass it as the voltage between V+ and V– is between 2.2V and with a capacitor of 0.1μF as close to the part as possible. 5.5V. A bypass capacitor of 0.1μF as close to the part as Operation The TP2411 series op amps can operate on a single-supply voltage (2.2 V to 5.5 V), or a split-supply voltage (±1.1 V to ±2.75 V), making them highly versatile and easy to use. The power-supply pins should have local bypass ceramic capacitors (typically 0.001 μF to 0.1 μF). These amplifiers are fully specified from +2.2 V to +5.5 V and over the extended temperature range of –40°C to +125°C. Parameters that can exhibit variance with regard to operating voltage or temperature are presented in the Typical Characteristics. Applications Information Input ESD Diode Protection The TP2411 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Many input signals are inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 1 shows how a series input resistor (RS) may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive applications. Current-limiting resistor required if input voltage exceeds supply rails by >0.5V. V+ 500Ω +2.5V IN+ Ioverload 10mA max TP2411 VIN Vout 5kΩ 500Ω IN- -2.5V VINPUT ESD DIODE CURRENT LIMITING- UNITY GAIN Figure1. Input ESD Diode 8 Rev. B www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps PHASE REVERSAL The TP2411 op amps are designed to be immune to phase reversal when the input pins exceed the supply voltages, therefore providing further in-system stability and predictability. Figure 2 shows the input voltage exceeding the supply voltage without any phase reversal. Figure 2. No Phase Reversal EMI SUSCEPTIBILITY AND INPUT FILTERING Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the device, the dc offset observed at the amplifier output may shift from the nominal value while EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible. The TP2411 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifier response to EMI. Both common-mode and differential mode filtering are provided by the input filter. The filter is designed for a cutoff frequency of approximately 500 MHz (–3 dB), with a roll-off of 20 dB per decade. 100 90 EMIRR IN+ (dB) 80 70 60 50 40 30 20 10 0 40 400 4000 Frequency (MHz) Figure 3. TP2411 EMIRR IN+ vs Frequency www.3peakic.com.cn Rev. B 9 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012Ω. A 5V difference would cause 5pA of current to flow, which is greater than the TP2411/2412/2414 OPA’s input bias current at +27°C (±3pA, typical). It is recommended to use multi-layer PCB layout and route the OPA’s -IN and +IN signal under the PCB surface. The effective way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 1 for Inverting Gain application. 1. For Non-Inverting Gain and Unity-Gain Buffer: a) Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (V IN–). This biases the guard ring to the Common Mode input voltage. 2. For Inverting Gain and Trans-impedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op-amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN–) to the input with a wire that does not touch the PCB surface. Guard Ring VIN+ VIN- +VS Figure 4 The Layout of Guard Ring Power Supply Layout and Bypass The TP2411/2412/2412 OPA’s power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01μF to 0.1μF) within 2mm for good high frequency performance. It can also use a bulk capacitor (i.e., 1μF or larger) within 100mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. Ground layout improves performance by decreasing the amount of stray capacitance and noise at the OPA’s inputs and outputs. To decrease stray capacitance, minimize PC board lengths and resistor leads, and place external components as close to the op amps’ pins as possible. Proper Board Layout To ensure optimum performance at the PCB level, care must be taken in the design of the board layout. To avoid leakage currents, the surface of the board should be kept clean and free of moisture. Coating the surface creates a barrier to moisture accumulation and helps reduce parasitic resistance on the board. Keeping supply traces short and properly bypassing the power supplies minimizes power supply disturbances due to output current variation, such as when driving an ac signal into a heavy load. Bypass capacitors should be connected as closely as possible to the device supply pins. Stray capacitances are a concern at the outputs and the inputs of the amplifier. It is recommended that signal traces be kept at least 5mm from supply lines to minimize coupling. A variation in temperature across the PCB can cause a mismatch in the Seebeck voltages at solder joints and other points where dissimilar metals are in contact, resulting in thermal voltage errors. To minimize these thermocouple effects, orient resistors so heat sources warm both ends equally. Input signal paths should contain matching numbers and types of components, where possible to match the number and type of thermocouple junctions. For example, dummy components such as zero value resistors can be used to match real resistors in the opposite input path. Matching components should be located in close proximity and should be oriented in the same manner. Ensure leads are of equal length so that thermal conduction is in equilibrium. Keep heat sources on the PCB as far away from amplifier input circuitry as is practical. The use of a ground plane is highly recommended. A ground plane reduces EMI noise and also helps to maintain a constant temperature across the circuit board. 10 Rev. B www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions SOT23-5 D A2 A1 θ L1 e Symbol E1 E e1 www.3peakic.com.cn Dimensions In Millimeters In Inches Min Max Min Max A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.400 0.012 0.016 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.650 2.950 0.104 0.116 e b Dimensions 0.950TYP 0.037TYP e1 1.800 2.000 0.071 0.079 L1 0.300 0.460 0.012 0.024 θ 0° 8° 0° 8° Rev. B 11 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions SOT-23-8 Symbol 12 Rev. B Dimensions Dimensions In In Millimeters Inches Min Max Min Max A 1.050 1.250 0.041 0.049 A1 0.000 0.100 0.000 0.004 A2 1.050 1.150 0.041 0.045 b 0.300 0.500 0.012 0.020 c 0.100 0.200 0.004 0.008 D 2.820 3.020 0.111 0.119 E 1.500 1.700 0.059 0.067 E1 2.600 3.000 0.102 0.118 e 0.65（BSC） 0.026(BSC) e1 0.975（BSC） 0.038(BSC) L 0.300 0.600 0.012 0.024 θ 0° 8° 0° 8° www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions SOP-8 A2 C θ L1 A1 e E D Symbol E1 b www.3peakic.com.cn Dimensions Dimensions In In Millimeters Inches Min Max Min Max A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 C 0.190 0.250 0.007 0.010 D 4.780 5.000 0.188 0.197 E 3.800 4.000 0.150 0.157 E1 5.800 6.300 0.228 0.248 e 1.270 TYP 0.050 TYP L1 0.400 1.270 0.016 0.050 θ 0° 8° 0° 8° Rev. B 13 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions MSOP-8 Dimensions Dimensions In In Millimeters Inches Min Max Min Max A 0.800 1.200 0.031 0.047 A1 0.000 0.200 0.000 0.008 A2 0.760 0.970 0.030 0.038 b 0.30 TYP 0.012 TYP C 0.15 TYP 0.006 TYP D 2.900 e 0.65 TYP E 2.900 3.100 0.114 0.122 E1 4.700 5.100 0.185 0.201 L1 0.410 0.650 0.016 0.026 θ 0° 6° 0° 6° Symbol E E1 A A2 e b D 3.100 0.114 0.122 0.026 A1 R1 R θ L1 14 Rev. B L L2 www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions TSSOP-8 Symbol Dimensions In Millimeters Min Dimensions In Inches Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 A 1.200 0.047 A2 0.800 1.000 0.031 0.039 A1 0.050 0.150 0.002 0.006 e 0.65(BSC) L 0.500 H 0.25(BSC) θ 1° www.3peakic.com.cn 0.026（BSC） 0.700 0.020 0.028 0.01（BSC） 7° 1° 7° Rev. B 15 TP2411 / TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions TSSOP-14 Dimensions E1 E A A2 e c D In Millimeters Symbol MIN TYP MAX A - - 1.20 A1 0.05 - 0.15 A2 0.90 1.00 1.05 b 0.20 - 0.28 c 0.10 - 0.19 D 4.86 4.96 5.06 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 e L A1 R1 R 0.65 BSC 0.45 0.60 L1 1.00 REF L2 0.25 BSC 0.75 R 0.09 - - θ 0° - 8° θ L1 16 Rev. B L L2 www.3peakic.com.cn TP2411/TP2412 / TP2414 Low Cost, Low Noise CMOS RRIO Op-amps Package Outline Dimensions SOP-14 D E1 Dimensions E In Millimeters Symbol e b A A2 A1 MIN TYP MAX A 1.35 1.60 1.75 A1 0.10 0.15 0.25 A2 1.25 1.45 1.65 b 0.36 D 8.53 8.63 8.73 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e L www.3peakic.com.cn 1.27 BSC 0.45 0.60 0.80 L1 1.04 REF L2 0.25 BSC θ L L1 0.49 0° 8° θ L2 Rev. B 17