GD32E230F4P6TR

GD32E230xx Datasheet GigaDevice Semiconductor Inc. GD32E230xx ARM® Cortex®-M23 32-bit MCU Datasheet GD32E230xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 4 List of Tables .................................................................................................................. 5 1 General description ................................................................................................. 7 2 Device overview ....................................................................................................... 8 3 2.1 Device information ...................................................................................................... 8 2.2 Block diagram ............................................................................................................ 10 2.3 Pinouts and pin assignment ..................................................................................... 11 2.4 Memory map .............................................................................................................. 14 2.5 Clock tree ................................................................................................................... 16 2.6 Pin definitions ............................................................................................................ 17 2.6.1 GD32E230Cx LQFP48 pin definitions .................................................................................. 17 2.6.2 GD32E230Kx LQFP32 pin definitions .................................................................................. 20 2.6.3 GD32E230Kx QFN32 pin definitions .................................................................................... 22 2.6.4 GD32E230Gx QFN28 pin definitions .................................................................................... 24 2.6.5 GD32E230Fx TSSOP20 pin definitions ................................................................................ 27 2.6.6 GD32E230Fx LGA20 pin definitions ..................................................................................... 28 2.6.7 GD32E230xx pin alternate functions .................................................................................... 31 Functional description .......................................................................................... 34 3.1 ARM® Cortex®-M23 core ............................................................................................ 34 3.2 Embedded memory ................................................................................................... 34 3.3 Clock, reset and supply management ...................................................................... 34 3.4 Boot modes ................................................................................................................ 35 3.5 Power saving modes ................................................................................................. 35 3.6 Analog to digital converter (ADC) ............................................................................ 36 3.7 DMA ............................................................................................................................ 37 3.8 General-purpose inputs/outputs (GPIOs) ................................................................ 37 3.9 Timers and PWM generation..................................................................................... 37 3.10 Real time clock (RTC) ............................................................................................ 38 3.11 Inter-integrated circuit (I2C) .................................................................................. 39 3.12 Serial peripheral interface (SPI) ............................................................................ 39 1 GD32E230xx Datasheet 4 5 3.13 Universal synchronous asynchronous receiver transmitter (USART) ............... 40 3.14 Inter-IC sound (I2S) ................................................................................................ 40 3.15 Comparators (CMP)................................................................................................ 40 3.16 Debug mode ........................................................................................................... 40 3.17 Package and operation temperature ..................................................................... 41 Electrical characteristics ....................................................................................... 42 4.1 Absolute maximum ratings ....................................................................................... 42 4.2 Operating conditions characteristics ....................................................................... 42 4.3 Power consumption .................................................................................................. 43 4.4 EMC characteristics .................................................................................................. 47 4.5 Power supply supervisor characteristics ................................................................ 49 4.6 Electrical sensitivity .................................................................................................. 49 4.7 External clock characteristics .................................................................................. 50 4.8 Internal clock characteristics ................................................................................... 52 4.9 PLL characteristics.................................................................................................... 53 4.10 Memory characteristics ......................................................................................... 53 4.11 NRST pin characteristics ....................................................................................... 53 4.12 GPIO characteristics .............................................................................................. 54 4.13 ADC characteristics ............................................................................................... 57 4.14 Temperature sensor characteristics ..................................................................... 58 4.15 Comparators characteristics ................................................................................. 58 4.16 TIMER characteristics ............................................................................................ 59 4.17 WDGT characteristics ............................................................................................ 59 4.18 I2C characteristics ................................................................................................. 60 4.19 SPI characteristics ................................................................................................. 60 4.20 I2S characteristics.................................................................................................. 61 4.21 USART characteristics ........................................................................................... 62 Package information.............................................................................................. 63 5.1 TSSOP package outline dimensions ........................................................................ 63 5.2 LGA package outline dimensions ............................................................................ 64 5.3 QFN package outline dimensions ............................................................................ 66 5.4 LQFP package outline dimensions .......................................................................... 68 2 GD32E230xx Datasheet 6 Ordering information ............................................................................................. 70 7 Revision history ..................................................................................................... 71 3 GD32E230xx Datasheet List of Figures Figure 2-1. GD32E230xx block diagram .................................................................................................. 10 Figure 2-2. GD32E230Cx LQFP48 pinouts ............................................................................................... 11 Figure 2-3. GD32E230Kx LQFP32 pinouts ............................................................................................... 11 Figure 2-4. GD32E230Kx QFN32 pinouts ................................................................................................ 12 Figure 2-5. GD32E230Gx QFN28 pinouts ................................................................................................ 12 Figure 2-6. GD32E230Fx TSSOP20 pinouts ............................................................................................ 12 Figure 2-7. GD32E230Fx LGA20 pinouts ................................................................................................. 13 Figure 2-8. GD32E230xx clock tree .......................................................................................................... 16 Figure 4-1. I/O port AC characteristics definition................................................................................... 57 Figure 5-1. TSSOP package outline ......................................................................................................... 63 Figure 5-2. LGA20 package outline ......................................................................................................... 64 Figure 5-3. QFN package outline.............................................................................................................. 66 Figure 5-4. LQFP package outline............................................................................................................ 68 4 GD32E230xx Datasheet List of Tables Table 2-1. GD32E230xx devices features and peripheral list .................................................................. 8 Table 2-2. GD32E230xx devices features and peripheral list (continued) ............................................. 9 Table 2-3. GD32E230xx memory map ...................................................................................................... 14 Table 2-4. GD32E230Cx LQFP48 pin definitions .................................................................................... 17 Table 2-5. GD32E230Kx LQFP32 pin definitions .................................................................................... 20 Table 2-6. GD32E230Kx QFN32 pin definitions ...................................................................................... 22 Table 2-7. GD32E230Gx QFN28 pin definitions ...................................................................................... 24 Table 2-8. GD32E230Fx TSSOP20 pin definitions .................................................................................. 27 Table 2-9. GD32E230Fx LGA20 pin definitions ....................................................................................... 28 Table 2-10. Port A alternate functions summary .................................................................................... 31 Table 2-11. Port B alternate functions summary .................................................................................... 32 Table 2-12. Port F alternate functions summary .................................................................................... 32 Table 4-1. Absolute maximum ratings ..................................................................................................... 42 Table 4-2. DC operating conditions ......................................................................................................... 42 Table 4-3. Clock frequency ....................................................................................................................... 43 Table 4-4. Operating conditions at Power up/ Power down .................................................................. 43 Table 4-5. Start-up timings of Operating conditions .............................................................................. 43 Table 4-6. Power saving mode wakeup timings characteristics ........................................................... 43 Table 4-7. Power consumption characteristics ...................................................................................... 43 Table 4-8. Peripheral current consumption characteristics .................................................................. 46 Table 4-9. EMS characteristics ................................................................................................................. 47 Table 4-10. EMI characteristics ................................................................................................................ 48 Table 4-11. Power supply supervisor characteristics............................................................................ 49 Table 4-12. ESD characteristics ............................................................................................................... 50 Table 4-13. Static latch-up characteristics .............................................................................................. 50 Table 4-14. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics . 50 Table 4-15. High speed external user clock characteristics (HXTAL in bypass mode) ...................... 50 Table 4-16. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .. 51 Table 4-17. Low speed external user clock characteristics (LXTAL in bypass mode) ....................... 51 Table 4-18. High speed internal clock (IRC8M) characteristics(1) ......................................................... 52 Table 4-19. High speed internal clock (IRC28M) characteristics(1) ....................................................... 52 Table 4-20. Low speed internal clock (IRC40K) characteristics(1)......................................................... 52 Table 4-21. PLL characteristics ................................................................................................................ 53 Table 4-22. Flash memory characteristics .............................................................................................. 53 Table 4-23. NRST pin characteristics ....................................................................................................... 53 Table 4-24. I/O port DC characteristics .................................................................................................... 54 Table 4-25. I/O port AC characteristics(1) (2) ............................................................................................. 55 Table 4-261. Temperature sensor characteristics .................................................................................. 58 Table 4-272. CMP characteristics............................................................................................................. 58 Table 4-283. TIMER characteristics ......................................................................................................... 59 5 GD32E230xx Datasheet Table 4-29. FWDGT min/max timeout period at 40 kHz (IRC40K) ......................................................... 59 Table 4-305. WWDGT min-max timeout value @72 MHz (fPCLK1) ........................................................... 60 Table 4-316. I2C characteristics ............................................................................................................... 60 Table 4-327. Standard SPI characteristics(1) ........................................................................................... 60 Table 4-338. I2S characteristics(1)............................................................................................................. 61 Table 4-349. USART characteristics(1) ..................................................................................................... 62 Table 5-1. TSSOP20 package dimensions .............................................................................................. 63 Table 5-2. LGA20 package dimensions ................................................................................................... 64 Table 5-3. QFN package dimensions ....................................................................................................... 67 Table 5-4. LQFP package dimensions ..................................................................................................... 69 Table 6-1. Part ordering code for GD32E230xx devices ........................................................................ 70 Table 7-1. Revision history ....................................................................................................................... 71 6 GD32E230xx Datasheet 1 General description The GD32E230xx device belongs to the value line of GD32 MCU family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M23 core. The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor delivers high energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier and a 17-cycle divider. The GD32E230xx device incorporates the ARM® Cortex®-M23 32-bit processor core operating at up to 72 MHz frequency with Flash accesses 0~2 wait states to obtain maximum efficiency. It provides up to 64 KB embedded Flash memory and up to 8 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer one 12-bit ADC and one comparator, up to five general 16-bit timers, a basic timer, a PWM advanced timer, as well as standard and advanced communication interfaces: up to two SPIs, two I2Cs, two USARTs, and an I2S. The device operates from a 1.8 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32E230xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, user interface, power monitor and alarm systems, consumer and handheld equipment, gaming and GPS, E-bike and so on. 7 GD32E230xx Datasheet 2 Device overview 2.1 Device information Table 2-1. GD32E230xx devices features and peripheral list Part Number GD32E230xx K4U6 K6U6 K8U6 K4T6 K6T6 K8T6 C4T6 C6T6 C8T6 16 32 64 16 32 64 16 32 64 SRAM (KB) 4 6 8 4 4 8 4 6 8 Connectivity Timers FLASH (KB) General 4 4 5 4 4 5 4 4 5 timer(16-bit) (2,13,15,16) (2,13,15,16) (2,13-16) (2,13,15,16) (2,13,15,16) (2,13-16) (2,13,15,16) (2,13,15,16) (2,13-16) Advanced 1 1 1 1 1 1 1 1 1 timer(16-bit) (0) (0) (0) (0) (0) (0) (0) (0) (0) SysTick 1 1 1 1 1 1 1 1 1 Basic 1 1 1 1 1 1 1 1 1 timer(16-bit) (5) (5) (5) (5) (5) (5) (5) (5) (5) Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 (0) (0-1) (0-1) (0) (0-1) (0-1) (0) (0-1) (0-1) 1 1 2 1 1 2 1 1 2 (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) 1/1 1/1 2/1 1/1 1/1 2/1 1/1 1/1 2/1 (0)/(0) (0)/(0) (0-1)/(0) (0)/(0) (0)/(0) (0-1)/(0) (0)/(0) (0)/(0) (0-1)/(0) GPIO 27 27 27 25 25 25 39 39 39 CMP 1 1 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 1 1 1 1 1 1 1 1 1 10 10 10 10 10 10 10 10 10 2 2 2 2 2 2 2 2 2 USART I2C SPI/I2S ADC Units Channels (External) Channels (Internal) Package QFN32 LQFP32 LQFP48 8 GD32E230xx Datasheet Table 2-2. GD32E230xx devices features and peripheral list (continued) GD32E230xx Part Number F4V6 F6V6 F8V6 F4P6 F6P6 F8P6 G4U6 G6U6 G8U6 16 32 64 16 32 64 16 32 64 SRAM (KB) 4 6 8 4 6 8 4 6 8 General 4 4 4 4 4 4 4 4 5 timer(16-bit) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13,15,16) (2,13-16) Advanced 1 1 1 1 1 1 1 1 1 timer(16-bit) (0) (0) (0) (0) (0) (0) (0) (0) (0) SysTick 1 1 1 1 1 1 1 1 1 Basic 1 1 1 1 1 1 1 1 1 timer(16-bit) (5) (5) (5) (5) (5) (5) (5) (5) (5) Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 (0) (0-1) (0-1) (0) (0-1) (0-1) (0) (0-1) (0-1) 1 1 2 1 1 2 1 1 2 (0) (0) (0-1) (0) (0) (0-1) (0) (0) (0-1) 1/1 1/1 2/1 1/1 1/1 2/1 1/1 1/1 2/1 (0)/(0) (0)/(0) (0-1)/(0) (0)/(0) (0)/(0) (0-1)/(0) (0)/(0) (0)/(0) (0-1)/(0) GPIO 15 15 15 15 15 15 23 23 23 CMP 1 1 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 1 1 1 1 1 1 1 1 1 9 9 9 9 9 9 10 10 10 2 2 2 2 2 2 2 2 2 Connectivity Timers FLASH (KB) USART I2C SPI/I2S ADC Units Channels (External) Channels (Internal) Package LGA20 TSSOP20 QFN28 9 GD32E230xx Datasheet 2.2 Block diagram Figure 2-1. GD32E230xx block diagram LDO 1.2V TPIU SW AHB2: Fma x = 72MHz AHB Matrix AHB BUS ARM Cortex-M23 Processor Fmax: 72MHz IBus NVIC GPIO Ports A, B, C, F SRAM Controller SRAM Flash Memory Controller Flash Memory POR/PDR LVD PLL Fmax: 72MHz HXTAL 4-32MHz DBus GP DMA 5chs AHB1: Fma x = 72MHz AHB to APB Bridge 2 CRC AHB to APB Bridge 1 IRC8M 8MHz RST/CLK Controller IRC40K 40KHz Powered by LDO (1.2V) PMU EXTI FWDGT 12-bit SAR ADC IRC28M 28MHz Powered by V DD/VDDA ADC WWDGT RTC USART0 I2C0 SPI0/I2S0 TIMER0 APB1: Fmax = 72MHz CMP APB2: Fmax = 72MHz SYS Config CMP I2C1 USART1 SPI1 TIMER5 TIMER14 TIMER2 TIMER15 TIMER13 TIMER16 10 GD32E230xx Datasheet 2.3 Pinouts and pin assignment Figure 2-2. GD32E230Cx LQFP48 pinouts PA14 PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 48 47 46 45 44 43 42 41 40 39 38 37 VDD 1 36 PF7 PC13 2 35 PF6 PC14-OSC32IN 3 34 PA13 PC15-OSC32OUT PF0-OSCIN 4 33 PA12 32 PA11 PF1-OSCOUT NRST VSSA 6 31 PA10 30 PA9 8 29 VDDA 9 28 PA8 PB15 PA0 10 27 PB14 PA1 PA2 11 26 PB13 25 PB12 5 GigaDevice GD32E230Cx LQFP48 7 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD VSS PB11 PB10 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 Figure 2-3. GD32E230Kx LQFP32 pinouts PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 Vss 32 31 30 29 28 27 26 25 VDD 1 24 PA14 PF0-OSCIN 2 23 PA13 PF1-OSCOUT 3 PA12 NRST VDDA 4 5 22 GigaDevice GD32E230Kx 21 LQFP32 20 PA0 6 19 PA9 PA1 PA2 7 18 PA8 8 17 VDD PA11 PA10 9 10 11 12 13 14 15 16 VSS PB1 PB0 PA7 PA6 PA5 PA4 PA3 11 GD32E230xx Datasheet Figure 2-4. GD32E230Kx QFN32 pinouts 5 PA1 7 PA2 8 PA15 PB3 VDDA PA0 PB4 OSCOUT/PF1 NRST PB5 2 3 PB6 OSCIN/PF0 PB7 BOOT0 PB8 1 VDD 32 31 30 29 28 27 26 25 24 PA14 23 PA13 22 PA12 21 PA11 20 PA10 19 PA9 18 PA8 17 VDD GigaDevice GD32E230Kx QFN32 4 6 VSS, VSSA 9 10 11 12 13 14 15 16 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 Figure 2-5. GD32E230Gx QFN28 pinouts PA14 PA15 PB3 PB4 OSCIN/PF0 PB5 PB6 PB7 BOOT0 28 27 26 25 24 23 22 1 21 2 20 OSCOUT/PF1 NRST 3 VDDA PA0 5 PA1 7 GigaDevice GD32E230Gx QFN28 4 6 8 9 10 11 12 13 14 PA13 PA10(PA12) 19 PA9(PA11) 18 PA8 17 VDD 16 VSS PB1 15 PB0 PA6 PA7 PA5 PA4 PA3 PA2 Figure 2-6. GD32E230Fx TSSOP20 pinouts PA14 1 20 OSCIN/PF0 2 19 PA13 OSCOUT/PF1 3 18 PA10(PA12) 17 PA9(PA11) BOOT0 NRST 4 VDDA 5 PA0 6 GigaDevice 16 GD32E230Fx TSSOP20 15 PA1 7 14 PB1 PA2 8 13 PA7 PA3 9 12 PA6 PA4 10 11 PA5 VDD Vss 12 GD32E230xx Datasheet Figure 2-7. GD32E230Fx LGA20 pinouts PA13 PA14 BOOT0 OSCIN/PF0 OSCOUT/PF1 20 19 18 17 16 NRST 1 15 PA10(PA12) VDDA PA0 PA1 2 14 PA9(PA11) PA2 GigaDevice 3 GD32E230Fx 13 4 LGA20 12 5 11 VSS PB1 PA3 PA6 PA5 9 10 PA7 8 PA4 6 7 VDD 13 GD32E230xx Datasheet 2.4 Memory map Table 2-3. GD32E230xx memory map Pre-defined ADDRESS Peripherals 0xE000 0000 - 0xE00F FFFF Cortex M23 internal peripherals External Device 0xA000 0000 - 0xDFFF FFFF Reserved External RAM 0x60000000 - 0x9FFFFFFF Reserved 0x5004 0000 - 0x5FFF FFFF Reserved 0x5000 0000 - 0x5003 FFFF Reserved 0x4800 1800 - 0x4FFF FFFF Reserved 0x4800 1400 - 0x4800 17FF GPIOF 0x4800 1000 - 0x4800 13FF Reserved 0x4800 0C00 - 0x4800 0FFF Reserved 0x4800 0800 - 0x4800 0BFF GPIOC 0x4800 0400 - 0x4800 07FF GPIOB 0x4800 0000 - 0x4800 03FF GPIOA 0x4002 4400 - 0x47FF FFFF Reserved 0x4002 4000 - 0x4002 43FF Reserved 0x4002 3400 - 0x4002 3FFF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1400 - 0x4002 1FFF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0400 - 0x4002 0FFF Reserved 0x4002 0000 - 0x4002 03FF DMA 0x4001 8000 - 0x4001 FFFF Reserved 0x4001 5C00 - 0x4001 7FFF Reserved 0x4001 5800 - 0x4001 5BFF DBG 0x4001 4C00 - 0x4001 57FF Reserved 0x4001 4800 - 0x4001 4BFF TIMER16 0x4001 4400 - 0x4001 47FF TIMER15 0x4001 4000 - 0x4001 43FF TIMER14 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0/I2S0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF ADC 0x4001 0800 - 0x4001 23FF Reserved Regions Bus AHB1 AHB2 AHB1 Peripherals APB2 14 GD32E230xx Datasheet Pre-defined Regions Bus APB1 SRAM Code ADDRESS Peripherals 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF SYSCFG + CMP 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF Reserved 0x4000 7000 - 0x4000 73FF PMU 0x4000 6400 - 0x4000 6FFF Reserved 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 4800 - 0x4000 53FF Reserved 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF Reserved 0x4000 3800 - 0x4000 3BFF SPI1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1400 - 0x4000 1FFF Reserved 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0800 - 0x4000 0FFF Reserved 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF Reserved 0x2000 2000 - 0x3FFF FFFF Reserved 0x2000 0000 - 0x2000 1FFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option bytes 0x1FFF EC00 - 0x1FFF F7FF System memory 0x0801 0000 - 0x1FFF EBFF Reserved 0x0800 0000 - 0x0800 FFFF Main Flash memory 0x0001 0000 - 0x07FF FFFF Reserved 15 GD32E230xx Datasheet Pre-defined Bus Regions ADDRESS Peripherals Aliased to Flash or 0x00000000 - 0x0000FFFF 2.5 system memory Clock tree Figure 2-8. GD32E230xx clock tree FMC CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (by hardware) (to FMC) HCLK CK_IRC8M 00 8 MHz IRC8M /2 0 PLL CK_PLL 1 10 AHB enable CK_SYS 72 MHz max AHB Prescaler ÷1,2...512 (to AHB bus,Cortex-M23,SRAM,DMA) CK_CST CK_AHB ÷8 72 MHz max (to Cortex-M23 SysTick) FCLK PLLSEL 01 PLLEN (free running clock) PREDV 4-32 MHz HXTAL Clock Monitor ÷1,2. ..16 TIMER2,5,13 ÷[apb1 prescaler/2] CK_TIMERx TIMERx enable to TIMER2,5,13 CK_HXTAL /32 APB1 Prescaler ÷1,2,4,8,16 11 CK_APB1 PCLK1 72 MHz max to APB1 peripherals Peripheral enable 32.768 KHz LXTAL CK_RTC 01 (to RTC) 10 40 KHz IRC40K RTCSRC[1:0] CK_FWDGT (to FWDGT) TIMER0,14,1 5,16 ÷[apb2 prescaler/2] APB2 Prescaler ÷1,2,4,8,16 CK_TIMERx TIMERx enable CK_APB2 PCLK2 72 MHz max ÷1,2,4...128 CKOUTDIV to APB2 peripherals Peripheral enable CKOUTSEL CK_OUT to TIMER0,14,15,16 0 CK_IRC28M CK_IRC40K CK_ LXTAL CK_SYS CK_IRC8M CK_HXTAL /1,2 CK_PLL CK_ IRC8M 11 CK_L XTAL 10 CK_ SYS 01 CK_ USART0 to USART0 00 USART0SEL[1:0] 28 MHz IRC28M ÷1,2 0 CK_ ADC to ADC 1 28 MHz max ADCSEL ADC Prescaler ÷2,4,6,8 ADC Prescaler ÷3,5,7, 9 Note: If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1. Otherwise, they are set to the AHB frequency divide by half of APB prescaler. Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC8M: Internal 8M RC oscillator IRC40K: Internal 40K RC oscillator IRC28M: Internal 28M RC oscillator 16 GD32E230xx Datasheet 2.6 Pin definitions 2.6.1 GD32E230Cx LQFP48 pin definitions Table 2-4. GD32E230Cx LQFP48 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VDD 1 P 2 I/O 3 I/O 4 I/O Default: VDD PC13TAMPER- Default: PC13 Additional: RTC_TAMP0, RTC_TS, RTC_OUT, WKUP1 RTC PC14OSC32IN PC15OSC32OUT Functions description Default: PC14 Additional: OSC32IN Default: PC15 Additional: OSC32OUT Default: PF0 PF0-OSCIN 5 I/O 5VT Alternate: I2C0_SDA Additional: OSCIN PF1OSCOUT Default: PF1 6 I/O 5VT Alternate: I2C0_SCL Additional: OSCOUT Default: NRST NRST 7 I/O VSSA 8 P Default: VSSA VDDA 9 P Default: VDDA Default: PA0 PA0-WKUP 10 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 11 I/O Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) Additional: ADC_IN1, CMP_IP Default: PA2 PA2 12 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 13 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 Default: PA4 PA4 14 I/O Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 17 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PA5 PA5 15 Alternate: SPI0_SCK, I2S0_CK I/O Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 16 TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, I/O CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 17 TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, I/O EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 18 Alternate: TIMER2_CH2, TIMER0_CH1_ON, I/O USART1_RX(4), EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 19 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 PB2 20 I/O 5VT PB10 21 I/O 5VT Default: PB2 Alternate: TIMER2_ETI Default: PB10 Alternate: I2C0_SCL(3),I2C1_SCL(5), SPI1_IO2(5), SPI1_SCK(5) Default: PB11 PB11 22 I/O 5VT Alternate: I2C0_SDA(3),I2C1_SDA(5), EVENTOUT, SPI1_IO3(5) VSS 23 P Default: VSS VDD 24 P Default: VDD Default: PB12 PB12 25 I/O 5VT Alternate: SPI0_NSS(3), SPI1_NSS(5), TIMER0_BRKIN, I2C1_SMBA(5), EVENTOUT Default: PB13 PB13 26 I/O 5VT Alternate: SPI0_SCK(3), SPI1_SCK(5), TIMER0_CH0_ON, I2C1_TXFRAME(5), I2C1_SCL(5) Default: PB14 PB14 27 I/O 5VT Alternate: SPI0_MISO(3), SPI1_MISO(5), TIMER0_CH1_ON, TIMER14_CH0(5), I2C1_SDA(5) Default: PB15 Alternate: SPI0_MOSI(3), SPI1_MOSI(5), PB15 28 I/O 5VT TIMER0_CH2_ON, TIMER14_CH0_ON(5), TIMER14_CH1(5) Additional: RTC_REFIN, WKUP6 18 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PA8 PA8 29 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT Default: PA9 PA9 30 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT Default: PA10 PA10 31 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA Default: PA11 PA11 32 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) Default: PA12 PA12 33 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) PA13 34 I/O 5VT PF6 35 I/O 5VT PF7 36 I/O 5VT PA14 37 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PF6 Alternate: I2C0_SCL(3), I2C1_SCL(5) Default: PF7 Alternate: I2C0_SDA(3), I2C1_SDA(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 38 I/O 5VT Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT PB3 39 I/O 5VT Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT Default: PB4 PB4 40 I/O 5VT Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN Default: PB5 PB5 41 I/O 5VT Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 PB6 42 I/O 5VT PB7 43 I/O 5VT BOOT0 44 I PB8 45 I/O 5VT PB9 46 I/O 5VT Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON Default: BOOT0 Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 Default: PB9 Alternate: I2C0_SDA, IFRP_OUT, TIMER16_CH0, 19 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description EVENTOUT, I2S0_MCK, SPI1_NSS(5) VSS 47 P Default: VSS VDD 48 P Default: VDD Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230C4 devices only. (4) Functions are available on GD32E230C8/6 devices. (5) Functions are available on GD32E230C8 devices only. 2.6.2 GD32E230Kx LQFP32 pin definitions Table 2-5. GD32E230Kx LQFP32 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins VDD 1 P PF0-OSCIN 2 I/O Functions description Default: VDD Default: PF0 5VT Alternate: I2C0_SDA Additional: OSCIN PF1OSCOUT Default: PF1 3 I/O 5VT Alternate: I2C0_SCL Additional: OSCOUT NRST 4 I/O VDDA 5 P Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) Additional: ADC_IN1, CMP_IP Default: PA2 PA2 8 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 9 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 Default: PA4 PA4 10 I/O Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) 20 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Additional: ADC_IN4, CMP_IM4 Default: PA5 PA5 11 Alternate: SPI0_SCK, I2S0_CK I/O Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 12 TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, I/O CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 13 TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, I/O EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 14 Alternate: TIMER2_CH2, TIMER0_CH1_ON, I/O USART1_RX(4), EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 15 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 VSS 16 P Default: VSS VDD 17 P Default: VDD PA8 18 I/O Default: PA8 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT Default: PA9 PA9 19 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT Default: PA10 PA10 20 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA Default: PA11 PA11 21 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) Default: PA12 PA12 22 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) PA13 23 I/O 5VT PA14 24 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) PA15 25 I/O 5VT Default: PA15 Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), 21 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description USART1_RX(4), SPI1_NSS(5), EVENTOUT PB3 26 I/O 5VT Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT Default: PB4 PB4 27 I/O 5VT Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN Default: PB5 PB5 28 I/O 5VT Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 Default: PB6 PB6 29 I/O 5VT PB7 30 I/O 5VT BOOT0 31 I Default: BOOT0 VSS 32 P Default: VSS Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230K4 devices only. (4) Functions are available on GD32E230K8/6 devices. (5) Functions are available on GD32E230K8 devices only. 2.6.3 GD32E230Kx QFN32 pin definitions Table 2-6. GD32E230Kx QFN32 pin definitions Pin Name Pins VDD 1 Pin I/O Type(1) Level(2) Functions description Default: VDD P Default: PF0 PF0-OSCIN 2 I/O 5VT Alternate: I2C0_SDA Additional: OSCIN PF1OSCOUT Default: PF1 3 I/O 5VT Alternate: I2C0_SCL Additional: OSCOUT NRST 4 I/O VDDA 5 P Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) 22 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Additional: ADC_IN1, CMP_IP Default: PA2 PA2 8 Alternate: USART0_TX(3), USART1_TX(4), I/O TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 9 Alternate: USART0_RX(3), USART1_RX(4), I/O TIMER14_CH1(5) Additional: ADC_IN3 Default: PA4 PA4 10 Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), I/O USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 Default: PA5 PA5 11 Alternate: SPI0_SCK, I2S0_CK I/O Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 12 TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, I/O CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 13 TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, I/O EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 14 Alternate: TIMER2_CH2, TIMER0_CH1_ON, I/O USART1_RX(4), EVENTOUT Additional: ADC_IN8 Default: PB1 PB1 15 Alternate: TIMER2_CH3, TIMER13_CH0, I/O TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 PB2 16 I/O VDD 17 P 5VT Default: PB2 Alternate: TIMER2_ETI Default: VDD Default: PA8 PA8 18 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT Default: PA9 PA9 19 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT Default: PA10 PA10 20 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA 23 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Default: PA11 PA11 21 I/O 5VT Alternate: USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2(5), I2C0_SMBA, I2C1_SCL(5) Default: PA12 PA12 22 I/O 5VT Alternate: USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3(5), I2C0_TXFRAME, I2C1_SDA(5) PA13 23 I/O 5VT PA14 24 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 25 I/O 5VT Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT PB3 26 I/O 5VT Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT Default: PB4 PB4 27 I/O 5VT Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN Default: PB5 PB5 28 I/O 5VT Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 PB6 29 I/O 5VT PB7 30 I/O 5VT BOOT0 31 I PB8 32 I/O Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate:I2C0_SDA, USART0_RX,TIMER16_CH0_ON Default: BOOT0 5VT Default: PB8 Alternate: I2C0_SCL, TIMER15_CH0 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230K4 devices only. (4) Functions are available on GD32E230K8/6 devices. (5) Functions are available on GD32E230K8 devices only. 2.6.4 GD32E230Gx QFN28 pin definitions Table 2-7. GD32E230Gx QFN28 pin definitions Pin I/O Type(1) Level(2) Pin Name Pins BOOT0 1 I PF0-OSCIN 2 I/O Functions description Default: BOOT0 5VT Default: PF0 24 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: I2C0_SDA Additional: OSCIN PF1OSCOUT Default: PF1 3 I/O 5VT Alternate: I2C0_SCL Additional: OSCOUT NRST 4 I/O VDDA 5 P Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT, TIMER14_CH0_ON(5) Additional: ADC_IN1, CMP_IP Default: PA2 PA2 8 I/O Alternate: USART0_TX(3), USART1_TX(4), TIMER14_CH0(5) Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 9 I/O Alternate: USART0_RX(3), USART1_RX(4), TIMER14_CH1(5) Additional: ADC_IN3 Default: PA4 PA4 10 I/O Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 Default: PA5 PA5 11 I/O Alternate: SPI0_SCK, I2S0_CK Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 12 I/O TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 13 I/O TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PB0 PB0 14 I/O Alternate: TIMER2_CH2, TIMER0_CH1_ON, USART1_RX(4), EVENTOUT Additional: ADC_IN8 PB1 15 I/O Default: PB1 Alternate: TIMER2_CH3, TIMER13_CH0, 25 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 VSS 16 P Default: VSS VDD 17 P Default: VDD Default: PA8 PA8 18 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX(4), EVENTOUT Default: PA9 PA9(6) 19 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, TIMER14_BRKIN(5), I2C0_SCL, CK_OUT Default: PA10 PA10(6) 20 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA PA13 21 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PA14 PA14 22 I/O 5VT Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) Default: PA15 PA15 23 I/O 5VT Alternate: SPI0_NSS, I2S0_WS, USART0_RX(3), USART1_RX(4), SPI1_NSS(5), EVENTOUT PB3 24 I/O 5VT Default: PB3 Alternate: SPI0_SCK, I2S0_CK, EVENTOUT Default: PB4 PB4 25 I/O 5VT Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME, TIMER16_BRKIN Default: PB5 PB5 26 I/O 5VT Alternate: SPI0_MOSI,I2S0_SD, I2C0_SMBA, TIMER15_BRKIN, TIMER2_CH1 Additional: WKUP5 PB6 27 I/O 5VT PB7 28 I/O 5VT Default: PB6 Alternate: I2C0_SCL, USART0_TX, TIMER15_CH0_ON Default: PB7 Alternate:I2C0_SDA,USART0_RX,TIMER16_CH0_ON Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230G4 devices only. (4) Functions are available on GD32E230G8/6 devices. (5) Functions are available on GD32E230G8 devices only. (6) Pin pair PA11/PA12 can be remapped instead of pin pair PA9/PA10 using SYSCFG_CFG0 register. Table 2-10. Port A alternate functions summary shows PA11/PA12 remap. 26 GD32E230xx Datasheet 2.6.5 GD32E230Fx TSSOP20 pin definitions Table 2-8. GD32E230Fx TSSOP20 pin definitions Pin Name Pins PF0-OSCIN 2 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PF0 Alternate: I2C0_SDA Additional: OSCIN PF1- Default: PF1 3 I/O NRST 4 I/O VDDA 5 P OSCOUT 5VT Alternate: I2C0_SCL Additional: OSCOUT Default: NRST Default: VDDA Default: PA0 PA0-WKUP 6 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 Default: PA1 PA1 7 I/O Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT Additional: ADC_IN1, CMP_IP Default: PA2 PA2 8 I/O Alternate: USART0_TX(3), USART1_TX(4) Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 9 I/O Alternate: USART0_RX(3), USART1_RX(4) Additional: ADC_IN3 Default: PA4 PA4 10 I/O Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 Default: PA5 PA5 11 I/O Alternate: SPI0_SCK, I2S0_CK Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 12 I/O TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 13 I/O TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, EVENTOUT Additional: ADC_IN7 Default: PB1 PB1 14 I/O Alternate: TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, SPI1_SCK(5) 27 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Additional: ADC_IN9 VSS 15 P Default: VSS VDD 16 P Default: VDD PA9(6) 17 I/O Default: PA9 5VT Alternate: USART0_TX, TIMER0_CH1, I2C0_SCL, CK_OUT Default: PA10 PA10(6) 18 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA PA13 19 I/O 5VT PA14 20 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PA14 Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) BOOT0 1 Default: BOOT0 I Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230F4 devices only. (4) Functions are available on GD32E230F8/6 devices. (5) Functions are available on GD32E230F8 devices only. (6) Pin pair PA11/PA12 can be remapped instead of pin pair PA9/PA10 using SYSCFG_CFG0 register. Table 2-10. Port A alternate functions summary shows PA11/PA12 remap. 2.6.6 GD32E230Fx LGA20 pin definitions Table 2-9. GD32E230Fx LGA20 pin definitions Pin Name Pins PF0-OSCIN 19 Pin I/O Type(1) Level(2) I/O 5VT Functions description Default: PF0 Alternate: I2C0_SDA Additional: OSCIN PF1OSCOUT Default: PF1 20 I/O 5VT Alternate: I2C0_SCL Additional: OSCOUT NRST 1 I/O VDDA 2 P Default: NRST Default: VDDA Default: PA0 PA0-WKUP 3 I/O Alternate: USART0_CTS(3), USART1_CTS(4), CMP_OUT, I2C1_SCL(5) Additional: ADC_IN0, CMP_IM6, RTC_TAMP1, WKUP0 PA1 4 I/O Default: PA1 28 GD32E230xx Datasheet Pin Name Pins Pin I/O Type(1) Level(2) Functions description Alternate: USART0_RTS(3), USART1_RTS(4), I2C1_SDA(5), EVENTOUT Additional: ADC_IN1, CMP_IP Default: PA2 PA2 5 Alternate: USART0_TX(3), USART1_TX(4) I/O Additional: ADC_IN2, CMP_IM7 Default: PA3 PA3 6 Alternate: USART0_RX(3), USART1_RX(4) I/O Additional: ADC_IN3 Default: PA4 PA4 7 Alternate: SPI0_NSS, I2S0_WS, USART0_CK(3), I/O USART1_CK(4), TIMER13_CH0, SPI1_NSS(5) Additional: ADC_IN4, CMP_IM4 Default: PA5 PA5 8 Alternate: SPI0_SCK, I2S0_CK I/O Additional: ADC_IN5, CMP_IM5 Default: PA6 Alternate: SPI0_MISO, I2S0_MCK, TIMER2_CH0, PA6 9 TIMER0_BRKIN, TIMER15_CH0, EVENTOUT, I/O CMP_OUT Additional: ADC_IN6 Default: PA7 Alternate: SPI0_MOSI, I2S0_SD, TIMER2_CH1, PA7 10 TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, I/O EVENTOUT Additional: ADC_IN7 Default: PB1 Alternate: TIMER2_CH3, TIMER13_CH0, PB1 11 I/O VSS 12 P Default: VSS VDD 13 P Default: VDD TIMER0_CH2_ON, SPI1_SCK(5) Additional: ADC_IN9 Default: PA9 PA9(6) 14 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, I2C0_SCL, CK_OUT Default: PA10 PA10(6) 15 I/O 5VT Alternate: USART0_RX, TIMER0_CH2, TIMER16_BRKIN, I2C0_SDA PA13 16 I/O 5VT Default: PA13 Alternate: SWDIO, IFRP_OUT, SPI1_MISO(5) Default: PA14 PA14 17 I/O 5VT Alternate: USART0_TX(3), USART1_TX(4), SWCLK, SPI1_MOSI(5) BOOT0 18 I Default: BOOT0 Notes: 29 GD32E230xx Datasheet (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available on GD32E230F4 devices only. (4) Functions are available on GD32E230F8/6 devices. (5) Functions are available on GD32E230F8 devices only. (6) Pin pair PA11/PA12 can be remapped instead of pin pair PA9/PA10 using SYSCFG_CFG0 register. Table 2-10. Port A alternate functions summary shows PA11/PA12 remap. 30 GD32E230xx Datasheet 2.6.7 GD32E230xx pin alternate functions Table 2-10. Port A alternate functions summary Pin Name AF0 AF1 AF2 AF3 USART0_CTS(1) /USART1_CTS(2 PA0 AF4 AF5 AF6 I2C1_SCL( CMP_ 3) OUT ) USART0_RTS(1) PA1 I2C1_SDA( EVENTOUT /USART1_RTS(2 3) PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 _CH0_O TIMER14_C USART0_TX(1)/ H0(3) USART1_TX(2) TIMER14_C USART0_RX(1)/ H1(3) USART1_RX(2) SPI0_NSS/I USART0_CK(1)/ 2S0_WS USART1_CK(2) TIMER13_ SPI1_N CH0 SS(3) SPI0_SCK/I 2S0_CK SPI0_MISO/ I2S0_MCK SPI0_MOSI/ I2S0_SD CK_OUT TIMER14_B RKIN(3) TIMER16_B RKIN TIMER2_CH0 TIMER2_CH1 USART0_CK USART0_TX USART0_RX TIMER0_BR SWCLK 2S0_WS CH0 0 OUT TIMER0_CH _CH0 OUT X(2) I2C0_SCL 1 TIMER0_CH I2C0_SDA 2 TIMER0_CH I2C0_SMB I2C1_SC SPI1_I CMP_ 3 A L(3) O2(3) RAME A(3) O3(3) SPI1_M ISO(3) USART0_TX(1)/ SPI1_M USART1_TX(2) OSI(3) USART1_RX(2) OUT I2C0_TXF I2C1_SD SPI1_I IFRP_OUT SPI0_NSS/I USART0_RX(1)/ OUT TIMER0_CH EVENT USART1_T USART0_RTS TIMER0_ETI PA14 OUT TIMER13_ TIMER16 EVENT 0_ON PA12 EVENTOUT SWDIO _CH0 TIMER0_CH USART0_CTS PA13 TIMER15 EVENT CMP_ KIN PA11 EVENTOUT PA15 TIMER14 N(3) ) PA2 AF7 EVENT SPI1_N OUT SS(3) 31 GD32E230xx Datasheet Table 2-11. Port B alternate functions summary Pin AF0 Name PB0 PB1 AF1 EVENTOUT TIMER2_CH2 TIMER13_CH 0 TIMER2_CH3 SPI0_SCK/I2 S0_CK SPI0_MISO /I2S0_MCK SPI0_MOSI PB5 /I2S0_SD TIMER2_CH1 PB7 USART0_RX I2C0_SDA PB8 I2C0_SCL PB9 IFRP_OUT 1_ON _RX(2) AF6 TIMER0_CH SPI1_S 2_ON CK(3) AF7 I2C0_SDA TIMER15_B RKIN TIMER1 I2C0_TX 6_BRKI FRAME N I2C0_SMBA TIMER15_C H0_ON TIMER16_C H0_ON TIMER15_C H0 TIMER16_C H0 EVENTOUT I2S0_M SPI1_N CK SS(3) I2C0_SCL(1)/I PB10 PB11 EVENTOUT PB15 USART1 TIMER2_CH0 EVENTOUT I2C0_SCL PB14 TIMER0_CH AF5 EVENTOUT PB6 USART0_TX PB13 AF4 I PB4 PB12 AF3 TIMER2_ET PB2 PB3 AF2 SPI0_NSS(1) /SPI1_NSS(3) SPI1_I SPI1_S 2C1_SCL(3) O2(3) I2C0_SDA(1)/I SPI1_I 2C1_SDA(3) O3(3) EVENTOUT TIMER0_BR I2C1_SM KIN BA(3) SPI0_SCK(1) I2C1_TXFRA TIMER0_CH /SPI1_SCK(3) ME(3) I2C1_S CL(3) 0_ON SPI0_MISO(1) TIMER14_CH TIMER0_CH /SPI1_MISO(3) 0(3) CK(3) I2C1_S DA(3) 1_ON SPI0_MOSI(1) TIMER14_CH TIMER0_CH TIMER14_CH /SPI1_MOSI(3) 1(3) 2_ON 0_ON(3) Table 2-12. Port F alternate functions summary Pin Name AF0 PF0 AF2 AF3 AF4 AF5 AF6 I2C0_SDA PF1 PF6 AF1 I2C0_SCL I2C0_SCL(1 32 GD32E230xx Datasheet Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 )/I2C1_SCL (3) I2C0_SDA( PF7 1)/I2C1_SD A(3) Notes: (1) Functions are available on GD32E230x4 devices only. (2) Functions are available on GD32E230x8/6 devices. (3) Functions are available on GD32E230x8 devices only. 33 GD32E230xx Datasheet 3 Functional description 3.1 ARM® Cortex®-M23 core The Cortex-M23 processor is an energy-efficient processor with a very low gate count. It is intended to be used for microcontroller and deeply embedded applications that require an area-optimized processor. The processor is highly configurable enabling a wide range of implementations from those requiring memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M23 processor core  Up to 72 MHz operation frequency  Single-cycle multiplication and hardware divider  Ultra-low power, energy-efficient operation  Excellent code density  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M23 processor is based on the ARMv8-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M23:  Internal Bus Matrix connected with AHB master, Serial Wire Debug Port and Single-cycle IO port 3.2  Nested Vectored Interrupt Controller (NVIC)  Breakpoint Unit(BPU)  Data Watchpoint and Trace (DWT)  Serial Wire JTAG Debug Port (SWJ-DP) Embedded memory  Up to 64 Kbytes of Flash memory  Up to 8 Kbytes of SRAM with hardware parity checking 64 Kbytes of inner Flash and 8 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with 0~2 wait states. Table 2-3. GD32E230xx memory map shows the memory map of the GD32E230xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 3.3 Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator 34 GD32E230xx Datasheet  Internal 28 MHz RC oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  1.8 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the AHB, APB2 and APB1 domains is 72 MHz/72 MHz/72 MHz. See Figure 2-8. GD32E230xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.6 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 1.8 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 1.8 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAK range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and backup registers (through power switch) when VDD is not present. 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM In default condition, boot from main Flash memory is selected. The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10) or USART1 (PA14 and PA15). 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance 35 GD32E230xx Datasheet between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, RTC tamper and timestamp, CMP output, LVD output and USART wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.  Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin. 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2 MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA  Temperature sensor One 12-bit 2 MSPS multi-channel ADC is integrated in the device. It has a total of 12 multiplexed channels: up to 10 external channels, 1 channel for internal temperature sensor (VSENSE) and 1 channel for internal reference voltage (VREFINT). The input voltage range is between VSSA and VDDA. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general level 0 timers (TIMERx) and the advanced timer (TIMER0) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 36 GD32E230xx Datasheet 3.7 DMA  5 channels DMA controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs and I2S The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory. Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.8 General-purpose inputs/outputs (GPIOs)  Up to 39 fast GPIOs, all mappable on 16 external interrupt lines  Analog input/output configurable  Alternate function input/output configurable There are up to 39 general purpose I/O pins (GPIO) in GD32E230xx, named PA0 ~ PA15 and PB0 ~ PB15, PC13 ~ PC15, PF0 ~ PF1, PF6 ~ PF7 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the Interrupt/event controller (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (pushpull open-drain or analog), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 3.9 Timers and PWM generation  One 16-bit advanced timer (TIMER0), up to five 16-bit general timers (TIMER2, TIMER13 ~ TIMER16), and one 16-bit basic timer (TIMER5)  Up to 4 independent channels of PWM, output compare or input capture for each general timer and external trigger input  16-bit, motor control PWM advanced timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (free watchdog timer and window watchdog timer) The advanced timer (TIMER0) can be used as a three-phase PWM multiplexed on 6 channels. 37 GD32E230xx Datasheet It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center- aligned counting modes) and single pulse mode output. If configured as a general 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other general timers together which have the same architecture and features. The general timer can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TIMER2 is based on a 16-bit auto-reload up/down counter and a 16-bit prescaler. TIMER13 ~ TIMER16 is based on a 16-bit auto-reload up counter and a 16-bit prescaler. The general timer also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TIMER5 can also be used as a simple 16-bit time base. The GD32E230xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler. It is clocked from an independent 40 KHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early wakeup interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. The features are shown below: 3.10  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  Independent binary-coded decimal (BCD) format timer/counter with five 32-bit backup registers.  Calendar with subsecond, second, minute, hour, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 0.954 ppm resolution for compensation of quartz crystal inaccuracy. 38 GD32E230xx Datasheet The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. 3.11 Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 1 MHz (Fast mode plus)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode  Supports SAM_V mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides different data transfer rates: up to 100 KHz in standard mode, up to 400 KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 3.12 Serial peripheral interface (SPI)  Up to two SPI interfaces with a frequency of up to 18 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking  Separate transmit and receive 32-bit FIFO with DMA capability (only in SPI1)  Data frame size can be 4 to 16 bits (only in SPI1)  Quad-SPI configuration available in master mode (only in SPI1) The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. Specially, SPI1 has separate transmit and receive 32bit FIFO with DMA capability and its data frame size can be 4 to 16 bits. Quad-SPI master mode is also supported in SPI1. 39 GD32E230xx Datasheet 3.13 Universal synchronous asynchronous receiver transmitter (USART)  Up to two USARTs with operating frequency up to 4.5 MBits/s  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication. 3.14 Inter-IC sound (I2S)  One I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz, multiplexed with SPI0  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32E230xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI0. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5% accuracy error. 3.15 Comparators (CMP)  One fast rail-to-rail low-power comparators with software configurable  Programmable reference voltage (internal or external I/O) One Comparator (CMP) is implemented within the devices. It can wake up from deep-sleep mode to generate interrupts and breaks for the timers and also can be combined as a window comparator. The internal voltage reference is also connected to ADC_IN17 input channel of the ADC. 3.16 Debug mode  Serial wire JTAG debug port (SWJ-DP) 40 GD32E230xx Datasheet The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.17 Package and operation temperature  LQFP48 (GD32E230CxTx), LQFP32 (GD32E230KxTx), QFN32 (GD32E230KxUx), QFN28 (GD32E230GxUx), TSSOP20 (GD32E230FxPx) and LGA20 (GD32E230FxVx).  Operation temperature range: -40°C to +85°C (industrial level) 41 GD32E230xx Datasheet 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings Symbol Min Max Unit VSS - 0.3 VSS + 3.6 V VSSA - 0.3 VSSA + 3.6 V VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V |ΔVDDx| Variations between different VDD power pins — 50 mV |VSSX −VSS| Variations between different ground pins — 50 mV IIO Maximum current for GPIO pins — 25 mA Injected current on 5V tolerant pin — ±5 mA Injected current on other I/O — ±5 mA ∑IINJ Injected current on all I/O(3) — ±25 mA TA Operating temperature range -40 +85 °C TSTG Storage temperature range -55 +150 °C TJ Maximum junction temperature — 125 °C VDD VDDA VIN IINJ Parameter External voltage range(1) External analog supply voltage Input voltage on 5V tolerant pin(2) (1) All main power and ground pins should be connected to an external power source within the allowable range. (2) VIN maximum value cannot exceed 6.5V and it must be below the maximum allowable injection current value refer to Table 4-1. Absolute maximum ratings (3) The maximum ΣIINJ(PIN) is the absolute sum of the negative and positive injection currents (instantaneous values). 4.2 Operating conditions characteristics Table 4-2. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 1.8 3.3 3.6 V 1.8 3.3 3.6 Analog supply voltage VDDA ADC not used Analog supply voltage ADC used — V 2.4 3.3 3.6 42 GD32E230xx Datasheet Table 4-3. Clock frequency Symbol Parameter Conditions Min Max Unit fHCLK AHB clock frequency — 0 72 MHz fAPB1 APB1 clock frequency — 0 72 MHz fAPB2 APB2 clock frequency — 0 72 MHz Min Max Unit VDD rise time rate 0 ∞ VDD fall time rate 20 ∞ Table 4-4. Operating conditions at Power up/ Power down Symbol tVDD Parameter Conditions us/V Table 4-5. Start-up timings of Operating conditions Symbol Parameter tstart-up(1) Start-up time Conditions Typ Clock source from HXTAL 432 Clock source from IRC8M 76 Unit us (1). After power-up, the start-up time is the time between the rising edge of NRST high and the main function. Table 4-6. Power saving mode wakeup timings characteristics Symbol Parameter Typ tSleep(1) Wakeup from Sleep mode 3.5 Wakeup from Deep-sleep mode（LDO On） 17.1 Wakeup from Deep-sleep mode（LDO in low power mode） 17.1 Wakeup from Standby mode 77.5 tDeep-sleep(1) tStandby(1) Unit μs (1).The wakeup times is measured from the wakeup event to the point at which the application code reads the first instruction under the the below conditions: VDD=VDDA=3.3V, IRC8M=System clock=8MHz. 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from embedded Flash with the following specifications. Table 4-7. Power consumption characteristics Symbol Parameter Conditions Min Typ Max Unit VDD=VDDA=3.3V, HXTAL=8MHz, System — 8.5 — mA — 5.4 — mA -— 6.2 -— mA — 4.2 — mA — 5.1 — mA -— 3.6 -— mA clock=72 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =72 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System IDD Supply current clock=48 MHz, All peripherals enabled (Run mode) VDD=VDDA=3.3V, HXTAL=8MHz, System clock =48 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock=36 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =36 MHz, All peripherals disabled 43 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max Unit VDD=VDDA=3.3V, HXTAL=8MHz, System — 4.0 — mA — 2.9 — mA -— 3.2 -— mA — 2.5 — mA — 2.4 — mA -— 2.1 -— mA — 0.8 — mA — 0.6 — mA -— 0.6 -— mA — 0.5 — mA — 7.4 — mA — 3.7 — mA -— 5.5 -— mA — 3.1 — mA — 4.5 — mA -— 2.7 -— mA — 3.6 — mA — 2.4 — mA clock=24 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =24 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock=16 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =16 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock=8 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =8 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock=4 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =4 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock=2 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, System clock =2 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =72 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =72 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =48 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =48 MHz, All peripherals Supply current disabled (Sleep mode) VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =36 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =36 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =24 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =24 MHz, All peripherals disabled 44 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max Unit -— 3.0 -— mA — 2.1 — mA — 2.3 — mA -— 1.9 -— mA — 0.7 — mA — 0.5 — mA -— 0.5 -— mA — 0.4 — mA — 25.5 — μA — 12.3 — μA — 3.8 — μA — 3.6 — μA — 3.1 — μA — 1.6 — μA — 1.43 — μA — 1.36 — μA — 1.23 — μA — 1.15 — μA VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =16 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =16 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =8 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =8 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =4 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =4 MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =2 MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL=8MHz, CPU clock off, System clock =2 MHz, All peripherals disabled VDD=VDDA=3.3V, LDO in run mode, IRC40K Supply current off, RTC off, All GPIOs analog mode (Deep-sleep VDD=VDDA=3.3V, LDO in low power mode, mode) IRC40K off, RTC off, All GPIOs analog mode VDD=VDDA=3.3V, LXTAL off, IRC40K on, RTC on VDD=VDDA=3.3V, LXTAL off, IRC40K on, Supply current RTC off (Standby mode) VDD=VDDA=3.3V, LXTAL off, IRC40K off, RTC off, VDDA Monitor on VDD=VDDA=3.3V, LXTAL off, IRC40K off, RTC off, VDDA Monitor off VDD=VDDA=3.6 V, LXTAL on with external crystal, RTC on, Higher driving ILXTAL+RTC LXTAL+RTC current VDD=VDDA=3.3 V, LXTAL on with external crystal, RTC on, Higher driving VDD=VDDA=2.5 V, LXTAL on with external crystal, RTC on, Higher driving VDD=VDDA=1.8 V, LXTAL on with external 45 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max Unit — 1.13 — μA — 1.06 — μA — 0.95 — μA — 0.86 — μA — 0.84 — μA — 0.76 — μA — 0.64 — μA — 0.56 — μA — 0.74 — μA — 0.67 — μA — 0.56 — μA — 0.47 — μA crystal, RTC on, Higher driving VDD=VDDA=3.6 V, LXTAL on with external crystal, RTC on, Medium High driving VDD=VDDA=3.3 V, LXTAL on with external crystal, RTC on, Medium High driving VDD=VDDA=2.5 V, LXTAL on with external crystal, RTC on, Medium High driving VDD=VDDA=1.8 V, LXTAL on with external crystal, RTC on, Medium High driving VDD=VDDA=3.6 V, LXTAL on with external crystal, RTC on, Medium Low driving VDD=VDDA=3.3 V, LXTAL on with external crystal, RTC on, Medium Low driving VDD=VDDA=2.5 V, LXTAL on with external crystal, RTC on, Medium Low driving VDD=VDDA=1.8 V, LXTAL on with external crystal, RTC on, Medium Low driving VDD=VDDA=3.6 V, LXTAL on with external crystal, RTC on, Low driving VDD=VDDA=3.3 V, LXTAL on with external crystal, RTC on, Low driving VDD=VDDA=2.5 V, LXTAL on with external crystal, RTC on, Low driving VDD=VDDA=1.8 V, LXTAL on with external crystal, RTC on, Low driving Notes: (1) When System Clock is less than 4MHz, an external source is used, and the HXTAL bypass function is needed, no PLL. (2) When System Clock is greater than 8MHz, a crystal 8MHz is used, and the HXTAL bypass function is closed, using PLL. (3) When analog peripheral blocks such as ADCs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an additional power consumption should be considered The power measurements specified in the tables represent that code with data executing from embedded Flash with the following specifications. Table 4-8. Peripheral current consumption characteristics Peripherials(1) APB1 Typical consumption at 25℃ （TYP） PMU 1.44 I2C1 1.38 I2C0 1.38 USART1 1.34 SPI1 1.37 WWDGT 1.32 Unit mA 46 GD32E230xx Datasheet Peripherials(1) APB2 AHB Typical consumption at 25℃ Unit （TYP） TIMER13 1.36 TIMER5 0.17 TIMER2 0.23 DBGMCU 1.3 TIMER16 1.42 TIMER15 1.42 TIMER14 1.49 USART0 1.63 SPI0 1.38 TIMER0 1.68 ADC(2) 0.95 CFG & CMP(3) 1.27 GPIOF 1.31 GPIOC 1.31 GPIOB 1.34 GPIOA 1.34 CRC 0.16 DMA 0.15 (1) Conditons: VDD = VDDA = 3.3V, IRC8M = 8MHz, system clock = fHCLK = 72MHz, fAPB1 = fAPB2 = fHCLK. (2) ADC: fADCCLK = IRC28M, ADCON bit set to 1 in ADC_CTL1. (3) CMP: CMP enabled by setting CMPEN bit in CMP_CS，CMP mode set to High Speed. 4.4 EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in Table 4-9. EMS characteristics, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-9. EMS characteristics Symbol VESD VFTB Parameter Voltage applied to all device pins to induce a functional disturbance Conditions Level/Class VDD = 3.3 V, TA = +25 °C, LQFP48, fHCLK = 72MHz 3A conforms to IEC 61000-4-2 Fast transient voltage burst applied to VDD = 3.3 V, TA = +25 °C, induce a functional disturbance through LQFP48, fHCLK = 72MHz 100 pF on VDD and VSS pins conforms to IEC 61000-4-4 4A EMI (Electromagnetic Interference) emission testing result is given in Table 4-10. EMI characteristics, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. 47 GD32E230xx Datasheet Table 4-10. EMI characteristics Symbol Parameter Conditions Peak level frequency band Conditions Unit 48M 72M 0.1 to 2 MHz — — TA = +25 °C, 2 to 30 MHz — — compliant with IEC 30 to 130 MHz — — 61967-2 130 MHz to 1GHz — — VDD = 3.3 V, SEMI Tested dBμV 48 GD32E230xx Datasheet 4.5 Power supply supervisor characteristics Table 4-11. Power supply supervisor characteristics Symbol Parameter Conditions Min Typ Max Unit LVDT[2:0]=000, rising edge — 2.11 — V LVDT[2:0]=000, falling edge — 2.01 — V LVDT[2:0]=001, rising edge — 2.25 — V LVDT[2:0]=001, falling edge — 2.16 — V LVDT[2:0]=010, rising edge — 2.39 — V LVDT[2:0]=010, falling edge — 2.29 — V LVDT[2:0]=011, rising edge — 2.52 — V Low Voltage Detector LVDT[2:0]=011, falling edge — 2.43 — V Threshold LVDT[2:0]=100, rising edge — 2.66 — V LVDT[2:0]=100, falling edge — 2.57 — V LVDT[2:0]=101, rising edge — 2.80 — V LVDT[2:0]=101, falling edge — 2.71 — V LVDT[2:0]=110, rising edge — 2.95 — V LVDT[2:0]=110, falling edge — 2.84 — V LVDT[2:0]=111, rising edge — 3.08 — V LVDT[2:0]=111, falling edge — 2.98 — V — — 100 — mV Rising edge — 1.71 — V Falling edge — 1.67 — V VLVD VLVDhyst(1) VPOR VPDR LVD hysteresis Power on reset threshold Power down reset threshold VPDRhyst(1) PDR hysteresis — — 40 — mV tRSTTEMP Reset temporization — — 2.5 — ms (1) Based on design, not actual test values. 4.6 Electrical sensitivity The device is strained in order to determine its performance in terms of electrical sensitivity. Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up 49 GD32E230xx Datasheet (LU) test is based on the two measurement methods. Table 4-12. ESD characteristics Symbol Parameter Conditions Electrostatic discharge TA=25 °C; JESD22- voltage (human body model) A114 Electrostatic discharge TA=25 °C; voltage (charge device model) JESD22-C101 VESD(HBM) VESD(CDM) Min Typ Max Unit — — 6000 V — — 2000 V Min Typ Max Unit — — ±200 mA — — 5.4 V Table 4-13. Static latch-up characteristics Symbol Parameter Conditions I-test LU TA=25 °C; JESD78 Vsupply over voltage 4.7 External clock characteristics Table 4-14. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics Symbol fHXTAL Parameter Crystal or ceramic frequency(1) RF Feedback resistor CHXTAL capacitance on OSCIN and Conditions Min Typ Max Unit VDD=3.3V 4 8 32 MHz VDD=3.3V — — — kΩ — — 20 30 pF VDD=3.3V, TA=25°C — 1.0 — mA Startup — — — mA/V VDD=3.3V, TA=25°C — 2 — ms Recommended matching OSCOUT IDD(HXTAL) gm(HXTAL) tS Crystal or ceramic operating current Crystal or ceramic transconductance Crystal or ceramic startup time (1) Based on design, not actual test values. Note: CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance (Typ. CS = 10pf). Table 4-15. High speed external user clock characteristics (HXTAL in bypass mode) Symbol fHXTAL_ext Parameter External clock source or oscillator frequency Conditions Min Typ Max Unit VDD=3.3V 1 8 50 MHz 0.7VDD — VDD VSS — 0.3VDD VHXTALH OSCIN input pin high level voltage VHXTALL OSCIN input pin low level voltage tH/L(HXTAL) (1) OSCIN high or low time — 5 — — (HXTAL) (1) OSCIN rise or fall time — — — 10 tR/F VDD=3.3V V ns 50 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max Unit CIN(1) OSCIN input capacitance — — 5 — pF DuCy(HXTAL) Duty cycle — 30 50 70 % (1) Based on design, not actual test values. Table 4-16. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics Symbol Parameter Conditions Min Typ Max Unit fLXTAL(1) Crystal or ceramic frequency VDD=3.3V — 32.768 — KHz Feedback resistor VDD=3.3V — — — MΩ — — — 15 pF VDD=3.3V, High Drive — 1.2 — — 1.0 — RF Recommended matching CLXTAL(1) capacitance on OSC32IN and OSC32OUT VDD=3.3V, Medium IDD(LXTAL) Crystal or ceramic operating High Drive current VDD=3.3V, Medium — 0.6 — VDD=3.3V, Low Drive — 0.5 — Startup — — — μA/V VDD=3.3V — 2 — s Low Drive Crystal or ceramic gm(LXTAL) tSULXTAL μA transconductance Crystal or ceramic startup time (1) Based on design, not actual test values. Note: CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic manufacturer. For CS, it is PCB and MCU pin stray capacitance (Typ. CS = 2pf ~ 7pf). Table 4-17. Low speed external user clock characteristics (LXTAL in bypass mode) Symbol fLXTAL_ext(1) VLXTALH VLXTALL Parameter External clock source or oscillator frequency Conditions Min VDD=3.3V — OSC32IN input pin high level voltage OSC32IN input pin low level 0.7VDD Typ Max Unit 32.768. 1000 kHz — VDD=3.3V voltage VSS — VDD 0.3VD V D tH/L(LXTAL) (1) OSC32IN high or low time — 450 — — tR/F(LXTAL) (1) OSC32IN rise or fall time — — — 50 CIN(1) OSC32IN input capacitance — — 5 — pF DuCy(LXTAL) Duty cycle — 30 50 70 % ns (1) Based on design, not actual test values. 51 GD32E230xx Datasheet 4.8 Internal clock characteristics Table 4-18. High speed internal clock (IRC8M) characteristics(1) Symbol fIRC8M Parameter Conditions Min Typ Max Unit VDD=3.3V — 8 — MHz — +5.0 % -2.0 — +2.0 % VDD=3.3V, TA=25°C -1.0 — +1.0 % — — 0.5 — % VDD=3.3V, fIRC8M=8MHz 45 50 55 % VDD=3.3V, fIRC8M=8MHz — 55 80 μA VDD=3.3V, fIRC8M=8MHz — 1.5 2 us Conditions Min Typ Max Unit VDD=3.3V — 28 — MHz — +5.0 % -3.0 — +3.0 % VDD=3.3V, TA=25°C -2.0 — +2.0 % — — 0.5 — % VDD=3.3V, fIRC28M=16MHz 45 50 55 % VDD=3.3V, fIRC28M=16MHz — 140 200 μA VDD=3.3V, fIRC28M=16MHz — 1.5 2 μs Min Typ Max Unit 30 38.5 60 KHz High Speed Internal Oscillator (IRC8M) frequency IRC8M oscillator Frequency accuracy, Factory-trimmed VDD=3.3V, TA=-40°C ~ +105°C(2) -4.0 VDD=3.3V, TA=0°C ~ ACCIRC8M IRC8M oscillator Frequency accuracy, User trimming step DIRC8M IDDIRC8M IRC8M oscillator duty cycle IRC8M oscillator operating current tSUIRC8M(3) IRC8M oscillator startup time +85°C(2) (1) VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. (2) Based on characterization, not actual test values. (3) Based on design, not actual test values. Table 4-19. High speed internal clock (IRC28M) characteristics(1) Symbol Parameter High Speed Internal fIRC28M Oscillator (IRC28M) frequency IRC28M oscillator Frequency accuracy, Factory-trimmed VDD=3.3V, TA=-40°C ~+105°C(2) -4.0 VDD=3.3V, TA=0°C ~ ACCIRC28M IRC28M oscillator Frequency accuracy, User trimming step DIRC28M IDDIRC28M tSUIRC28M(3) IRC28M oscillator duty cycle IRC28M oscillator operating current IRC28M oscillator startup time +85°C(2) (1) VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified. (2) Based on characterization, not actual test values. (3) Based on design, not actual test values. Table 4-20. Low speed internal clock (IRC40K) characteristics(1) Symbol fIRC40K(2) Parameter Conditions Low Speed Internal oscillator VDD=VDDA=3.3V, (IRC40K) frequency TA=-40°C ~ +85°C 52 GD32E230xx Datasheet Symbol IDDIRC40K(3) tSUIRC40K(3) Parameter IRC40K oscillator operating current IRC40K oscillator startup time Conditions Min Typ Max Unit VDD=VDDA=3.3V, TA=25°C — 0.41 — μA VDD=VDDA=3.3V, TA=25°C — 33 — μs (1). VDD = 3.3 V, TA = –40 to 105 °C unless otherwise stated. (2). Based on characterization, not actual test values. (3) .Based on design, not actual test values. 4.9 PLL characteristics Table 4-21. PLL characteristics Symbol Parameter Conditions Min Typ Max Unit fPLLIN PLL input clock frequency — 1(1) — 25 MHz fPLLOUT PLL output clock frequency — 16 — 72 MHz tLOCK PLL lock time — — — 300 μs VCO freq=72MHz — 130 — μA System clock — 300 — ps Current consumption on IDD(2) VDD JitterPLL(3) Cycle to cycle Jitter (1) Based on design, not actual test values. (2) Based on characterization, not actual test values. (3) Value given with main PLL running. 4.10 Memory characteristics Table 4-22. Flash memory characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit Number of guaranteed PECYC program /erase cycles TA=-40°C ~ +85°C 100 — — kcycles before failure (Endurance) tRET Data retention time 10k cycles at TA=85°C 10 — — years tPROG Word programming time TA=-40°C ~ +85°C 37 — 42 us tERASE Page erase time TA=-40°C ~ +85°C 0.8 — 1.1 ms tMERASE Mass erase time TA=-40°C ~ +85°C 3.2 — 4 ms (1) Based on characterization, not actual test values. 4.11 NRST pin characteristics Table 4-23. NRST pin characteristics Symbol VIL(NRST) (1) Parameter Conditions Min Typ Max Unit NRST Input low level voltage VDD=VDDA=1.8V -0.5 — 0.71 V 53 GD32E230xx Datasheet Symbol VIH(NRST) (1) Parameter Conditions Min Typ Max NRST Input high level voltage 1.08 — VDD+0.5 Schmidt trigger Voltage hysteresis — 370 — VIL(NRST) (1) NRST Input low level voltage -0.5 — 1.05 VIH(NRST) (1) NRST Input high level voltage 1.42 — VDD+0.5 Schmidt trigger Voltage hysteresis — 370 — VIL(NRST) (1) NRST Input low level voltage -0.5 — 1.4 (1) NRST Input high level voltage 1.8 — VDD+0.5 Vhyst Vhyst VIH(NRST) VDD=VDDA=2.5V VDD=VDDA=3.3V Unit mV V mV V Schmidt trigger Voltage hysteresis — 400 — VIL(NRST) (1) NRST Input low level voltage -0.5 — 1.53 VIH(NRST) (1) NRST Input high level voltage 1.95 — VDD+0.5 — 420 — mV — 40.3 — KΩ Vhyst Vhyst Rpu (2) VDD=VDDA=3.6V Schmidt trigger Voltage hysteresis Pull-up equivalent resistor — mV V (1).Based on design, not actual test values. (2).Based on characterization, not actual test values. 4.12 GPIO characteristics Table 4-24. I/O port DC characteristics Symbol Parameter Conditions Min Typ Max — 0.80 — 1.10 — 1.40 VDD=3.6V — 1.60 VDD=1.8V — 0.80 — 1.10 — 1.40 — 1.60 VDD=1.8V Standard IO Low level input VDD=2.5V voltage VDD=3.3V VIL 5V-tolerant IO Low level VDD=2.5V input voltage VDD=3.3V VSS VSS VDD=3.6V VDD=1.8V 1.10 — Standard IO High level VDD=2.5V 1.50 — input voltage VDD=3.3V 1.90 — VDD=3.6V 2.00 — VDD=1.8V 1.10 — 5V-tolerant IO High level VDD=2.5V 1.50 — input voltage VDD=3.3V 1.90 — VDD=3.6V 2.00 — VDD=1.8V — — 0.20 VDD=2.5V — — 0.20 VDD=3.3V — — 0.10 VDD=3.6V — — 0.10 Low level output voltage VDD=1.8V — — — for an IO Pin VDD=2.5V — — 0.50 VIH Low level output voltage VOL for an IO Pin (IIO = +8mA) VOL Unit V V VDD V VDD V V V 54 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max (IIO = +20mA) VDD=3.3V — — 0.40 VDD=3.6V — — 0.40 VDD=1.8V 1.50 — — VDD=2.5V 2.30 — — VDD=3.3V 3.10 — — VDD=3.6V 3.40 — — VDD=1.8V — — — VDD=2.5V 1.90 — — VDD=3.3V 2.80 — — VDD=3.6V 3.10 — — High level output voltage VOH for an IO Pin (IIO = +8mA) High level output voltage VOH for an IO Pin (IIO = +20mA) Unit V V RPU Internal pull-up resistor — — 40 — kΩ RPD Internal pull-down resistor — — 40 — kΩ Conditions Typ Max VDD=1.8V, CL=10pF 2 10 VDD=1.8V, CL=30pF 2 8 VDD=1.8V, CL=50pF 2 6 Table 4-25. I/O port AC characteristics(1) (2) GPIOx_OSPD[1:0] bit value Parameter Maximum GPIOx_OSPD0->OSPDy[1:0] frequency(3) =X0 （IO_Speed = 2MHz） Output high/ low to VDD=1.8V, CL=10pF 24.4/23.4 29.4/33.4 low/ high level fall/ VDD=1.8V, CL=30pF 31.6/29.8 37.6/36.8 rise time VDD=1.8V, CL=50pF 49/43.2 51/42.2 VDD=1.8V, CL=10pF 10 32 VDD=1.8V, CL=30pF 10 26 VDD=1.8V, CL=50pF 10 18 8.8/9.2 10.0/10.2 Maximum GPIOx_OSPD0->OSPDy[1:0] =01 （IO_Speed = 10MHz） frequency(3) Output high/ low to VDD=1.8V, CL=10pF low/ high level fall/ rise time =11 （IO_Speed = 50MHz） 20 VDD=1.8V, CL=30pF 50 54 VDD=1.8V, CL=50pF — 40 Output high/ low to VDD=1.8V, CL=10pF — 3.6/3.2 frequency(3) low/ high level fall/ VDD=1.8V, CL=30pF 8.0/5.0 7.4/4.0 rise time VDD=1.8V, CL=50pF — 7.8/6.2 VDD=3.3V, CL=10pF 2 16 VDD=3.3V, CL=30pF 2 16 VDD=3.3V, CL=50pF 2 12 frequency(3) MHz ns MHz ns 15/13.6 17.2/15.8 — Maximum GPIOx_OSPD0->OSPDy[1:0] VDD=1.8V, CL=50pF VDD=1.8V, CL=10pF Maximum GPIOx_OSPD0->OSPDy[1:0] VDD=1.8V, CL=30pF 12.0/12.8 12.0/11.0 Unit MHz ns MHz =X0 （IO_Speed = 2MHz） Output high/ low to VDD=3.3V, CL=10pF 13.8/11.4 16.4/11.8 low/ high level fall/ VDD=3.3V, CL=30pF 19.0/14.8 19.2/17.8 rise time VDD=3.3V, CL=50pF 28.2/22.8 27.2/24.4 GPIOx_OSPD0->OSPDy[1:0] Maximum VDD=3.3V, CL=10pF 10 72 =01 frequency(3) VDD=3.3V, CL=30pF 10 72 ns MHz 55 GD32E230xx Datasheet GPIOx_OSPD[1:0] bit value Parameter Conditions Typ Max VDD=3.3V, CL=50pF 10 40 Output high/ low to VDD=3.3V, CL=10pF 3.4/2.8 4.0/3.4 low/ high level fall/ VDD=3.3V, CL=30pF 4.6/3.4 5.2/4.0 rise time VDD=3.3V, CL=50pF 8.0/6.4 8.2/6.2 VDD=3.3V, CL=10pF — 32 VDD=3.3V, CL=30pF — 46 VDD=3.3V, CL=50pF — 40 Output high/ low to VDD=3.3V, CL=10pF — 2.4/2.6 low/ high level fall/ VDD=3.3V, CL=30pF — 2.6/2.4 rise time VDD=3.3V, CL=50pF — 8.4/3.2 VDD=3.6V, CL=10pF 2 16 VDD=3.6V, CL=30pF 2 16 VDD=3.6V, CL=50pF 2 12 （IO_Speed = 10MHz） Maximum GPIOx_OSPD0->OSPDy[1:0] =11 （IO_Speed = 50MHz） frequency(3) Maximum GPIOx_OSPD0->OSPDy[1:0] frequency(3) =X0 （IO_Speed = 2MHz） Output high/ low to VDD=3.6V, CL=10pF 13.2/10.6 12.0/10.4 low/ high level fall/ VDD=3.6V, CL=30pF 17.2/14.4 18.8/15.4 rise time VDD=3.6V, CL=50pF 26.8/22.2 26.4/21.8 VDD=3.6V, CL=10pF 10 72 VDD=3.6V, CL=30pF 10 72 VDD=3.6V, CL=50pF 10 40 Output high/ low to VDD=3.6V, CL=10pF 3.2/2.8 3.6/3.2 low/ high level fall/ VDD=3.6V, CL=30pF 3.8/3.2 4.4/3.4 rise time VDD=3.6V, CL=50pF 7.6/6.0 8.0/6.0 VDD=3.6V, CL=10pF — 42 VDD=3.6V, CL=30pF — 46 VDD=3.6V, CL=50pF — 36 Output high/ low to VDD=3.6V, CL=10pF — 3.0/9.6 low/ high level fall/ VDD=3.6V, CL=30pF — 2.4/2.4 rise time VDD=3.6V, CL=50pF — 3.2/3.2 Maximum GPIOx_OSPD0->OSPDy[1:0] =01 （IO_Speed = 10MHz） frequency(3) Maximum GPIOx_OSPD0->OSPDy[1:0] =11 （IO_Speed = 50MHz） frequency(3) Unit ns MHz ns MHz ns MHz ns MHz ns (1) Based on characterization, not actual test values. (2) The I/O speed is configured using the GPIOx_OSPD0->OSPDy [1:0] bits. Refer to the GD32E230xx user manual which is selected to set the GPIO port output speed. (3) The maximum frequency is defined in Figure 4-1. I/O port AC characteristics definition 56 GD32E230xx Datasheet Figure 4-1. I/O port AC characteristics definition 10% 90% EXTERNAL OUTPU T ON 50pF 50% 50% 10% 90% tr(IO)out tr(IO)out If (tr+tf)≤2/3 T,then maximum frequency is achieved . The duty cycle is （45%-55%）when loaded by 50 pF 4.13 ADC characteristics Table 4-19. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Operating voltage — 2.4 3.3 3.6 V VIN ADC input voltage range — 0 — VREF+ V fADC ADC clock — 0.1 — 28 MHz 12-bit 0.007 — 2 10-bit 0.008 — 2.3 MSP 8-bit 0.01 — 2.8 S 6-bit 0.011 — 3.5 fS(1) Sampling rate VIN Analog input voltage 10 external;2 internal 0 — VDDA V VREF+ Positive Reference Voltage — — VDDA — V — — 0 — V See Equation 2 — — 50.6 kΩ — — — 0.5 kΩ — — 4 pF VREFRAIN(1) RADC(1) Negative Reference Voltage External input impedance Input sampling switch resistance No pin/pad capacitance CADC(1) Input sampling capacitance tCAL Calibration time fADC=28MHz — 4.68 — μs ts Sampling time fADC=28MHz 0.05 — 8.55 μs 12-bit — 14 — 10-bit — 12 — 1/ 8-bit — 10 — fADC 6-bit — 8 — — — — 1 included Total conversion tCONV(1) time(including sampling time) tSU(1) Startup time μs (1).Based on design, not actual test values. Equation 2: RAIN max formula R AIN < Ts fADC ∗CADC ∗ln(2N+2 ) − R ADC 57 GD32E230xx Datasheet The formula above (Equation 2) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N=12 (from 12-bit resolution). Table 4-20. ADC RAIN max for fADC = 28MHz(1) Ts(cycles) ts(us) RAINmax (KΩ) 1.5 0.05 0.88 7.5 0.27 6.4 13.5 0.48 11.9 28.5 1.02 25.7 41.5 1.48 37.7 55.5 1.98 50.6 71.5 2.55 NA 239.5 8.55 NA (1). Based on design, not actual test values. 4.14 Temperature sensor characteristics Table 4-261. Temperature sensor characteristics Symbol TL (1) Parameter Min Typ Max Unit VSENSE linearity with temperature — ±1.5 — ℃ Average slope — 4.3 — mV/℃ Avg_Slope(1) Voltage at 25 °C — 1.45 — V (2) Startup time — — — μs (2) (3) ADC sampling time when reading the temperature — 17.1 — μs V25 (1) tSTART tS_temp (1). Based on characterization, not actual test values. (2) .Based on design, not actual test values. (3) .Shortest sampling time can be determined in the application. 4.15 Comparators characteristics Table 4-272. CMP characteristics Max(1) Unit Symbol Parameter Conditions Min Typ VDDA Operating voltage — 1.8 3.3 3.6 V VIN Input voltage range — 0 — VDDA V VBG Scaler input voltage — — 1.2 — V VSC Scaler offset voltage — — — — mV Ultra low power mode — 0.98 — μs Propagation delay for 200mv Low power mode — 0.25 — μs step with 100mV overdrive Medium power mode — 0.12 — μs High speed power mode — 33 — μs Propagation delay for full Ultra low power mode — — — μs range step with 100mV Low power mode — — — μs tD 58 GD32E230xx Datasheet Symbol IDD Conditions Min Typ overdrive Medium power mode — — — μs High speed power mode — — — ns Ultra low power mode — 2.2 — Low power mode — 3.2 — Medium power mode — 8.1 — High speed power mode — 46.9 — — — ±4 — No Hysteresis — 0 — Low Hysteresis — 11 — Medium Hysteresis — 22 — High Hysteresis — 43 — Current consumption Voffset Offset error Vhyst Max(1) Unit Parameter Hysteresis Voltage μA mV mV (1). Based on characterization, not actual test values. 4.16 TIMER characteristics Table 4-283. TIMER characteristics Symbol Parameter tres Timer resolution time fEXT RES Conditions Min Max Unit — 1 — tTIMERxCLK fTIMERxCLK = 72 MHz 13.9 — ns Timer external clock — 0 fTIMERxCLK/2 MHz frequency fTIMERxCLK = 72 MHz 0 36 MHz Timer resolution — — 16 bit — 1 65536 tTIMERxCLK 910 μs 16-bit counter clock period tCOUNTER when internal clock is selected tMAX_COUNT 4.17 Maximum possible count fTIMERxCLK = 72 MHz 0.0139 — — fTIMERxCLK = 72 MHz — 65536 × 65536 tTIMERxCLK 59.6 s WDGT characteristics Table 4-29. FWDGT min/max timeout period at 40 kHz (IRC40K) Prescaler divider PR[2:0] bits 1/4 Min timeout RLD[11:0]= Max timeout RLD[11:0]= 0x000 0xFFF 000 0.1 409.6 1/8 001 0.2 819.2 1/16 010 0.4 1638.4 1/32 011 0.8 3276.8 1/64 100 1.6 6553.6 1/128 101 3.2 13107.2 1/256 110 or 111 6.4 26214.4 Unit ms 59 GD32E230xx Datasheet Table 4-305. WWDGT min-max timeout value @72 MHz (fPCLK1) 4.18 Min timeout value Prescaler divider PSC[2:0] 1/1 00 56.9 1/2 01 113.8 1/4 10 227.6 1/8 11 455.1 Unit CNT[6:0] = 0x40 Max timeout value CNT[6:0] = 0x7F Unit 3.64 7.28 μs ms 14.56 29.13 I2C characteristics Table 4-316. I2C characteristics Symbol Parameter fSCL Conditi Standard mode(1) Fast mode(1) (2) Unit ons Min Max Min SCL clock frequency — 0 100 0 tSCL(H) SCL clock high time — 4.0 — 0.6 — μs tSCL (L) SCL clock low time — 4.7 — 1.3 — μs tsu(SDA) SDA setup time — 250 — 100 — ns SDA data hold time — 0(3) 3450 0 900 ns SDA and SCL rise time — — 1000 — 300 ns tf(SDA/SCL) SDA and SCL fall time — — 300 — 300 ns th(STA) Start condition hold time — 4.0 — 0.6 — us th(SDA) tr(SDA/SCL) Max 1000 KHz (1) Based on design, not actual test values. (2) To ensure the standard mode I2C frequency, fPCLK1 must be at least 2 MHz.To ensure the fast mode I2C frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode puls I2C frequency, fPCLK1 must be at least a multiple of 10 MHz. (3) The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the falling edge of SCL. 4.19 SPI characteristics Table 4-327. Standard SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 18 MHz tsck(H) SCK clock high time — 25 27 29 ns tsck (L) SCK clock low time — 25 27 29 ns SPI master mode tV(MO) Data output valid time — — — 2 ns tSU(MI) Data input setup time — 5 — — ns tH(MI) Data input hold time — 5 — — ns SPI slave mode 60 GD32E230xx Datasheet Symbol Parameter Conditions Min Typ Max Unit tSU(NSS) NSS enable setup time fPCLK=72MHz 4TPCLK — — ns tH(NSS) NSS enable hold time fPCLK=72MHz 2TPCLK — — ns tA(SO) Data output access time fPCLK=72MHz 2 — 55 ns tDIS(SO) Data output disable time — 3 — 10 ns tV(SO) Data output valid time — — — 29 ns tSU(SI) Data input setup time — 2 — — ns tH(SI) Data input hold time — 0 — — ns Min Typ Max Unit — — 6 — — 6 — — 83.33 ns — — 83.33 ns (1). Data based on characterization results, not tested in production. 4.20 I2S characteristics Table 4-338. I2S characteristics(1) Symbol Parameter Conditions Master mode (data: 16 bits, fCK Clock frequency Audio frequency = 48 kHz) Slave mode MHz tH Clock high time tL Clock low time tV(WS) WS valid time Master mode 0 — 2 ns tH(WS) WS hold time Master mode 0 — — ns tSU(WS) WS setup time Slave mode 0 — — ns tH(WS) WS hold time Slave mode 0.5 — — ns Slave mode 30 — 70 % DuCy(SCK) I2S slave input clock duty cycle fCK=6MHz tSU(SD_MR) Data input setup time Master mode 2 — — ns tsu(SD_SR) Data input setup time Slave mode 0 — — ns Master receiver 1.5 — — ns Slave receiver 1.5 — — ns — — 11 ns 3 — — ns — — 11 ns 0 — — ns tH(SD_MR) tH(SD_SR) Data input hold time tv(SD_ST) Data output valid time th(SD_ST) Data output hold time tv(SD_MT) Data output valid time th(SD_MT) Data output hold time Slave transmitter (after enable edge) Slave transmitter (after enable edge) Master transmitter (after enable edge) Master transmitter (after enable edge) (1). Data based on characterization results, not tested in production. 61 GD32E230xx Datasheet 4.21 USART characteristics Table 4-349. USART characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency — — — 36 MHz TSIK(H) SCK clock high time — 13.5 — — ns TSIK(L) SCK clock low time — 13.5 — — ns (1). Data based on characterization results, not tested in production. 62 GD32E230xx Datasheet 5 Package information 5.1 TSSOP package outline dimensions Figure 5-1. TSSOP package outline Table 5-1. TSSOP20 package dimensions Symbol Dimensions (mm) Min Typ Max A - - 1.2 A1 0.05 - A2 0.80 b Symbol Dimensions (mm) Min Typ Max c1 0.09 - 0.16 1.15 D 6.4 6.5 6.6 1.00 1.05 E1 4.3 4.4 4.5 0.19 - 0.30 E 6.40 B1 0.19 0.22 0.25 e 0.65 c 0.09 - 0.20 L 0.45 0.6 0.75 63 GD32E230xx Datasheet 5.2 LGA package outline dimensions Figure 5-2. LGA20 package outline Table 5-2. LGA20 package dimensions Symbol LGA20 Min Typ Max A 0.51 0.56 0.61 A1 - 0.015 0.022 A2 0.35 0.40 0.45 c 0.13 0.16 0.19 D 2.90 3.00 3.10 D1 1.95 2.00 2.05 E 2.90 3.00 3.10 E1 1.95 2.00 2.05 e 0.50 BASIC L1 0.50 0.55 0.60 L2 0.30 0.35 0.40 L3 L4 0.200 REF 0.30 0.35 L5 0.125 REF L6 0.234 REF L7 0.050 REF R1 0.125 REF K1 0.375 REF K2 0.375 REF 0.40 64 GD32E230xx Datasheet Symbol b LGA20 Min Typ Max 0.20 0.25 0.30 aaa 0.100 ccc 0.100 (Original dimensions are in millimeters) 65 GD32E230xx Datasheet 5.3 QFN package outline dimensions Figure 5-3. QFN package outline 66 GD32E230xx Datasheet Table 5-3. QFN package dimensions Symbol QFN28 QFN32 Min Typ Max Min Typ Max A 0.8 0.85 0.9 0.8 0.85 0.9 A1 0 0.035 0.05 0 0.035 0.05 A2 - 0.65 0.67 - 0.65 0.67 A3 - 0.203 - - 0.203 - D - 4.0 - - 5.0 - E - 4.0 - - 5.0 - D1 2.7 2.8 2.9 3.4 3.5 3.6 E1 2.7 2.8 2.9 3.4 3.5 3.6 L 0.25 0.35 0.45 0.3 0.4 0.5 e b 0.4 0.15 0.2 0.5 0.25 0.2 0.25 0.3 (Original dimensions are in millimeters) 67 GD32E230xx Datasheet 5.4 LQFP package outline dimensions Figure 5-4. LQFP package outline 68 GD32E230xx Datasheet Table 5-4. LQFP package dimensions Symbol LQFP32 LQFP48 Min Typ Max Min Typ Max A - - 1.60 - - 1.60 A1 0.05 - 0.15 0.05 - 0.15 A2 1.35 1.40 1.45 1.35 1.40 1.45 D - 9.00 - - 9.00 - D1 - 7.00 - - 7.00 - E - 9.00 - - 9.00 - E1 - 7.00 - - 7.00 - R1 0.08 - - 0.08 - - R2 0.08 - 0.20 0.08 - 0.20 θ 0° 3.5° 7° 0° 3.5° 7° θ1 0° - - 0° - - θ2 11° 12° 13° 11° 12° 13° θ3 11° 12° 13° 11° 12° 13° c 0.09 - 0.20 0.09 - 0.20 L 0.45 0.60 0.75 0.45 0.60 0.75 L1 - 1.00 - - 1.00 - S 0.20 - - 0.20 - - b 0.33 - 0.41 0.17 0.22 0.27 e - 0.80 - - 0.50 - D2 - 5.50 - - 5.50 - E2 - 5.50 - - 5.50 - aaa 0.20 0.20 bbb 0.20 0.20 ccc 0.08 0.08 (Original dimensions are in millimeters) 69 GD32E230xx Datasheet 6 Ordering information Table 6-1. Part ordering code for GD32E230xx devices Ordering code Flash (KB) Package Package type GD32E230F4V6 16 LGA20 Green GD32E230F6V6 32 LGA20 Green GD32E230F8V6 64 LGA20 Green GD32E230F4P6 16 TSSOP20 Green GD32E230F6P6 32 TSSOP20 Green GD32E230F8P6 64 TSSOP20 Green GD32E230G4U6 16 QFN28 Green GD32E230G6U6 32 QFN28 Green GD32E230G8U6 64 QFN28 Green GD32E230K4U6 16 QFN32 Green GD32E230K6U6 32 QFN32 Green GD32E230K8U6 64 QFN32 Green GD32E230K4T6 16 LQFP32 Green GD32E230K6T6 32 LQFP32 Green GD32E230K8T6 64 LQFP32 Green GD32E230C4T6 16 LQFP48 Green GD32E230C6T6 32 LQFP48 Green GD32E230C8T6 64 LQFP48 Green Temperature operating range Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C Industrial -40°C to +85°C 70 GD32E230xx Datasheet 7 Revision history Table 7-1. Revision history Revision No. Description Date 1.0 Initial Release Oct10, 2018 1.1 Add information about the QFN20 package Dec7, 2018 1.2 Delete QFN20 package, add information about the LGA20 package and electrical characteristics with few changes Dec28, 2018 71 GD32E230xx Datasheet Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide. The Company reserves all rights under such laws and treaties and does not grant any license under its patents, copyrights, trademarks, or other intellectual property rights. The names and brands of third party referred thereto (if any) are the property of their respective owner and referred to for identification purposes only. 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