JSM24C02

JSM24C02/04/08/16 Features Compatible with all I2C bidirectional data – Page Write within 3 ms transfer protocol – Partial Page Writes Allowed Memory array: Write Protect Pin for Hardware Data Protection - 2K bits (256X 8) / 4K bits (512 X 8) / Schmitt Trigger, Filtered Inputs for Noise 8K bits (1024 X 8) / 16K bits (2048 X 8) Suppression High-reliability - Page size: 16 bytes Single supply voltage and high speed: – 1 MHz Endurance: 1 Million Write Cycles – Data Retention: 100 Years Enhanced ESD/Latch-up protection Random and sequential Readmodes Write: HBM 8000V – uc 8-lead PDIP/SOP/TSSOP/UDFN and WLCSP4 packages Byte Write within 3 ms nd – – to r of EEPROM co Description The device is optimized for use in many The JSM24C02/24C04/24C08/24C16 provides 2048/4096/8192/16384 bits of serial electrically　 low-power mi erasable and programmable read-only memory　 (EEPROM), organized as 256/512/1024/2048 words of 8 bits each. industrial and commercial applications where 8-lead SOP 1 5 2 6 7 4 8 JS MI 3 low-voltage operation essential. Se CR O Pin Configuration 8-lead PDIP and 8-lead TSSOP 8-pad DFN 1 1 5 1 5 1 5 2 6 2 6 2 6 3 7 3 7 3 7 4 8 4 8 4 8 Bottem view www.jsmsemi.com WLCSP4 2 A Vcc Vss B SCL SDA Marking side (top view) 第１／１５页 are JSM24C02/04/08/16 Pin Descriptions Type Functions A0-A2 I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write Protect GND P Ground Vcc P Power Supply to r Pin Name Table 1 uc Block Diagram Vcc GND WP EN co nd START STOP LOGIC SCL SDA SERIAL CONTROL LOGIC LOAD Se LOAD A1 CR O A2 DATA WORD ADRESS COUNTER Y DECODER DIN JS MI INC X DECODER A0 DATA RECOVERY CCMP mi DEVICE ADDRESS COMPARATOR HIGH VOLTAGE PUMP/TIMING EEPROM SERIAL MUX DOUT/ACKNOWLEDGE DOUT Figure 1 DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the 24C02/24C04/24C08/24C16. Eight 2K/4K/8K/16K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. www.jsmsemi.com 第２／１５页 JSM24C02/04/08/16 WRITE PROTECT (WP): The JSM24C02/24C04/24C08/24C16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when　 connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection　 feature is enabled and operates as shown in the following Table 2. WP Pin Status JSM24C02/04/08/16 At VCC Full Array At GND Normal Read/Write Operations to r Table 2 Functional Description 1. Memory Organization uc JSM24C02, 2K SERIAL EEPROM: Internally organized with 16 pages of 16 bytes each, the 2K requires an 8- bit　data word address for random word addressing. co bit　data word address for random word addressing. nd JSM24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9JSM24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10- mi bit　data word address for random word addressing. JSM24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 2. Device Operation Se 11-bit data word address for random word addressing. CR O CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the　 SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high　 periods will indicate a start or stop condition as defined below. JS MI START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must　 precede any other command (see Figure 3). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read　 sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit　 words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during　 the ninth clock cycle. STANDBY MODE: The JSM24C02/24C04/24C08/24C16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal　 operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be　 reset by following these steps: www.jsmsemi.com 第３／１５页 JSM24C02/04/08/16 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. Figure 2. Data Validity uc to r SDA SCL DATA CHANGE DATA STABLE nd DATA STABLE mi co Figure 3. Start and Stop Definition SCL CR O Se SDA JS MI START SCL STOP Figure 4. Output Acknowledge 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE www.jsmsemi.com 第４／１５页 JSM24C02/04/08/16 3. Device Addressing The 2K/4K/8K/16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5) The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must to r compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. uc The A0 pin is no connect. nd The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are co no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page mi addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most Se significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. CR O Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. 4. Write Operations JS MI BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data www.jsmsemi.com 第５／１５页 JSM24C02/04/08/16 words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7). The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous to r data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the uc device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to 5. nd continue. Read Operations co Read operations are initiated the same way as write operations with the exception that the read/write random address read and sequential read. CURRENT ADDRESS READ: mi select bit in the device address word is set to "1". There are three read operations: current address read, Se The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page CR O to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop JS MI condition (see Figure 8). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9) SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the www.jsmsemi.com 第６／１５页 JSM24C02/04/08/16 microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10). Figure 5. Device Address MSB LSB 1 0 1 0 0 0 0 R/W 4K 1 0 1 0 0 0 P0 R/W 8K 1 0 1 0 0 P1 16K 1 0 1 0 P2 P1 to r 2K R/W P0 R/W uc P0 CR O Se mi co nd Figure 6. Byte Write S T A R T Figure 7. Page Write W R I T E JS MI DEVICE ADDRESS WORD ADDRESS DATA(n) DATA(n+1) S T O P DATA(n+1) SDA LINE M S B L R A S / C BWK L A S C B K A C K www.jsmsemi.com A C K A C K 第７／１５页 JSM24C02/04/08/16 Figure 8. Current Address Read S T A R T R E A D DEVICE ADDRESS S T O P DATA SDA LINE M S B L R A S / C BWK to r NO ACK W R I T E DEVICE ADDRESS S T A R T WORD ADDRESS M S B DEVICE ADDRESS E A D co SDA LINE R L A S C B K mi L R A S / C BWK S T O P DATA(n) nd S T A R T uc Figure 9. Random Read A C NO ACK Se K DUMMY WRITE R E A D JS MI DEVICE ADDRESS CR O Figure 10. Sequential Read DATA(n) DATA(n+1) DATA(n+2) S T O P DATA(n+x) SDA LINE R A / C WK A C K A C K www.jsmsemi.com A C K NO ACK 第８／１５页 JSM24C02/04/08/16 Electrical Characteristics Absolute Maximum Stress Ratings ： DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V Operating Ambient Temperature . . . . . -40℃ to +85℃ Storage Temperature . . . . . . . . . . . . -65℃ to +150℃ to r Electrostatic pulse (Human Body model) . . . . . . . 8000V Comments ： Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this These are stress ratings only. Functional operation of this device at these or any other uc device. conditions above those indicated in the operational sections of this specification is not implied or nd intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. co DC Electrical Characteristics (unless otherwise noted) Parameter Symbol mi Applicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V Min Typ Max Unit 1.7 - 5.5 V - VCC2 2.5 - 5.5 V - ICC1 - 0.14 0.3 mA READ at 400KHZ Supply Current VCC=5.0V ICC2 - 0.28 0.5 mA WRITE at 400KHZ Supply Current VCC=5.0V ISB1 - 0.03 0.5 μA VIN=VCC or VSS Input Leakage Current IL1 - 0.10 1.0 μA VIN=VCC or VSS Output Leakage Current ILO - 0.05 1.0 μA VOUT=VCC or VSS Input Low Level VIL1 -0.3 - VCC×0.3 V VCC=1.7V to 5.5V Input High Level VIH1 VCC×0.7 - VCC+0.3 V VCC=1.7V to 5.5V Output Low Level VCC=1.7V VOL1 - - 0.2 V IOL=0.15mA Output Low Level VCC=5.0V VOL2 - - 0.4 V IOL=3.0mA Supply Voltage JS MI CR O Supply Current VCC=5.0V Se VCC1 Supply Voltage Condition Table 5 Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Min Typ Max Unit Condition Input/Output Capacitance(SDA) CI/O - - 8 pF VIO=0V Input Capacitance(A0,A1,A2,SCL) CIN - - 6 pF VIN=0V Table 6 www.jsmsemi.com 第９／１５页 JSM24C02/04/08/16 AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Parameter Symbol 1.7V≤VCC ﹤2.5V 2.5V≤VCC ﹤5.5V Min Typ Max Min Typ Max Units fSCL - - 400 - - 1000 KHZ Clock Pulse Width Low t LOW 0.6 - - 0.6 - - μs Clock Pulse Width High t HIGH 0.4 - - 0.4 - - μs Noise Suppression Time tI - - 50 - Clock Low to Data Out Valid tAA 0.1 - 0.55 0.1 Time the bus must be free before a new transmission can start t BUF 0.5 - - 0.5 Start Hold Time t HD:STA 0.25 - - Start Setup Time tSU:DAT 0.25 Data In Hold Time t HD:DAT 0 Data in Setup Time tSU:DAT 100 Input Rise Time(1) tR Input Fall Time(1) tF Stop Setup Time Notes: - 0.55 μs - - μs uc ns 0.25 - - μs - 0.25 - - μs - - 0 - - μs nd - 100 - - ns - - 0.3 - - 0.3 μs - - 0.3 - - 0.3 μs tSu:STO 0.25 - - 0.25 - - μs tDH 50 - - 50 - - ns twR - 1.9 3 - 1.9 3 ms - - - - - Write Cycle mi - Endurance CR O 5.0V,25℃,Byte Mode(1) 50 co Write Cycle Time - - Se Data Out Hold Time to r Clock Frequency,SCL 1M Table 7 JS MI 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 k Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 VCC The value of RL should be concerned according to the actual loading on the user's system. www.jsmsemi.com 第１０／１５页 JSM24C02/04/08/16 Bus Timing Figure 11. SCL: Serial Clock, SDA: Serial Data I/O tF tHIGH tR tLOW tLOW SCL tSU.DAT tHD.DAT tHD.STA tSU.STA tSU.STO SDA_ IN tAA t BUF to r tDH uc SDA_ OUT Write Cycle Timing nd Figure 12. SCL: Serial Clock, SDA: Serial Data I/O Word n tWR(1) Se SDA mi ACK co SCL Notes: START CONDITION CR O STOP CONDITION JS MI The write cycle time tWR is the time from a valid stop condition of a write sequence to the end ofthe internal clear/write cycle. www.jsmsemi.com 第１１／１５页 JSM24C02/04/08/16 Package Information PDIP Outline Dimensions E to r E1 uc C eA Top View nd End View e A2 A SYMBOL A A2 b b2 b3 c D D1 E E1 e eA L B3 4PLCS b2 b Se mi D1 D co COMMON DIMENSIONS (Unit of Measure=inches) L NOM 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.130 0.018 0.060 0.039 0.010 0.365 0.115 0.310 0.250 0.100BSC 0.300BSC 0.130 MAX 0.210 0.195 0.022 0.070 0.045 0.014 0.400 NOTE 2 5 6 6 0.325 0.280 3 3 4 3 0.150 4 2 JS MI Notes: CR O Side View MIN 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). www.jsmsemi.com 第１２／１５页 JSM24C02/04/08/16 SOP 1 E to r E1 N L mi SYMBOL A A1 b C D E1 E e L Φ (Unit of Measure=mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 0" NOM 1.27BSC - MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE 1.27 8" JS MI Notes: A1 CR O D A Se B e co nd uc Φ These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. www.jsmsemi.com 第１３／１５页 JSM24C02/04/08/16 TSSOP 3 2 1 E to r E1 uc L1 End View Se A2 b e L L1 MIN 2.90 4.30 - 0.80 0.19 0.45 NOM 3.00 6.40BSC 4.40 - 1.00 - MAX 3.10 NOTE 2,5 4.50 1.20 1.05 0.30 3,5 4 0.65BSC 0.60 0.75 1.00REF CR O Side View Notes: SYMBOL D E E1 A A2 mi e D L COMMON DIMENSIONS Unit of Measure=mm co A b nd N Top View JS MI 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess ofthe b dimension at maximummaterial condition. Dambar cannot be located on the lower radius ofthe foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. www.jsmsemi.com 第１４／１５页 JSM24C02/04/08/16 UDFN D D2 L E E2 to r PIN 1 DOT BY MARKING TOP VIEW e b BOTTOM VIEW A3 co A1 COMMON DIMENSION(MM) UT:ULTRA THIN MIN NOM MAX >0.50 0.55 0.60 0.00 0.05 0.15REF 1.95 2.00 2.05 2.95 3.00 3.05 0.20 0.25 0.30 0.20 0.30 0.40 1.25 1.40 1.50 1.15 1.30 1.40 0.50BSC nd A PKG REF A A1 A3 D E uc PIN #1 IDENTIFICATION CHAMFER SIDE VIEW b Se mi L D2 E2 e WLCSP X1 CR O E JS MI D E1 X2 Y1 b D1 PIN1 Y2 TOP VIEW (MARK SIDE) BOTTOM VIEW (BALL SIDE) COMMON DIMENSIONS (UNITS OF MEASURE=MILLIMETER) A2 A1 SIDE VIEW A SYMBOL A A1 A2 D D1 E E1 MIN 0.270 0.045 0.215 0.738 b 0.160 x1 x2 y1 y2 www.jsmsemi.com 0.668 NOM 0.290 0.055 0.235 0.758 0.400BSC 0.688 0.400BSC 0.180 0.144 REF 0.144 REF 0.179 REF 0.179 REF MAX 0.310 0.065 0.255 0.778 0.708 0.200 第１５／１５页