74AHCT74PW,112

74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 8 — 22 April 2020 Product data sheet 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits • • • • • • • Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: • For 74AHC74: CMOS level • For 74AHCT74: TTL level ESD protection: • HBM EIA/JESD22-A114E exceeds 2000 V • MM EIA/JESD22-A115-A exceeds 200 V • CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74AHC74D Temperature range Name Description Version -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74AHCT74D 74AHC74PW 74AHCT74PW 74AHC74BQ 74AHCT74BQ 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 2 3 1D 1CP 1 1SD 2SD SD 1Q 1D D Q 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD Fig. 1. Q CP FF Q 1Q 1Q 5 6 10 5 9 12 6 8 11 4 1RD 3 2SD 2 1 2D 2CP SD D Q CP FF 2Q 9 10 11 Q 2Q 12 8 13 RD 1RD 2RD 1 13 SD D RD 4 10 2 12 3 11 1SD 13 mna418 Functional diagram Fig. 2. 2RD 5 C1 1D 6 R S 9 C1 1D 8 R mna420 Logic symbol mna419 Fig. 3. IEC logic symbol Q C C S C C C C D Q C RD C SD CP mna421 C C Fig. 4. Logic diagram (one flip-flop) 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 2 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1. Pinning 1 terminal 1 index area 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q 1SD 4 11 2CP 1Q 5 1Q 6 GND(1) 13 2RD 10 2SD 9 2Q 001aac450 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aac449 Fig. 5. 12 2D 8 14 VCC 3 2Q 1 2 7 1RD 1D 1CP GND 74AHC74 74AHCT74 14 VCC 1RD 74AHC74 74AHCT74 Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 6. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW to HIGH, edge-triggered) 1SD 4 asynchronous set direct input (active LOW) 1Q 5 true flip-flop output 1Q 6 complement flip-flop output GND 7 ground (0 V) 2Q 8 complement flip-flop output 2Q 9 true flip-flop output 2SD 10 asynchronous set direct input (active LOW) 2CP 11 clock input (LOW to HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset direct input (active LOW) VCC 14 supply voltage 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 3 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW to HIGH transition; Qn+1 = state after the next LOW to HIGH CP transition. Control Input Output nSD nRD nCP nD nQ nQ nQn+1 nQn+1 L H X X H L - - H L X X L H - - L L X X H H - - H H ↑ L - - L H H H ↑ H - - H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage -0.5 +7.0 V VI input voltage -0.5 +7.0 V IIK input clamping current VI < -0.5 V [1] -20 - mA IOK output clamping current VO < -0.5 V or VO > VCC + 0.5 V [1] -20 +20 mA IO output current VO = -0.5 V to (VCC + 0.5 V) -25 +25 mA ICC supply current - +75 mA IGND ground current -75 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = -40 °C to +125 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. For SOT762-1 (DHVQFN14) package: Ptot derates linearly with 9.6 mW/K above 98 °C. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions 74AHC74 74AHCT74 Unit Min Typ Max Min Typ Max 2.0 5.0 5.5 4.5 5.0 5.5 V input voltage 0 - 5.5 0 - 5.5 V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature -40 +25 +125 -40 +25 Δt/ΔV input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 - - - ns/V VCC = 4.5 V to 5.5 V - - 20 - - 20 ns/V VCC supply voltage VI 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © +125 °C Nexperia B.V. 2020. All rights reserved 4 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V IO = -50 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -50 μA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = -50 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = -8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V IO = 50 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC74 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA CI input capacitance VI = VCC or GND - 3 10 - 10 - 10 pF 74AHCT74 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = -50 μA 4.4 4.5 - 4.4 - 4.4 - V IO = -8.0 mA 3.94 - - 3.80 - 3.70 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 50 μA - 0 0.1 - 0.1 - 0.1 V IO = 8.0 mA - - 0.36 - 0.44 - 0.55 V VOL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 0.1 - 1.0 - 2.0 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 μA 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 5 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ Max Min Max Min Max Unit ΔICC additional supply current per input pin; VI = VCC - 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance VI = VCC or GND - 3 10 - 10 - 10 pF 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit, see Fig. 9. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Min Typ [1] Max Min Max Min Max Unit 74AHC74 tpd [2] propagation nCP to nQ, nQ; see Fig. 7 delay VCC = 3.0 V to 3.6 V; CL = 15 pF - 5.2 11.9 1.0 14.0 1.0 15.0 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 7.4 15.4 1.0 17.5 1.0 19.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.7 7.3 1.0 8.5 1.0 9.5 VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.2 9.3 1.0 10.5 1.0 12.0 ns VCC = 3.0 V to 3.6 V; CL = 15 pF - 5.4 12.3 1.0 14.5 1.0 15.5 ns VCC = 3.0 V to 3.6 V; CL = 50 pF - 7.7 15.8 1.0 18.0 1.0 20.0 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.7 7.7 1.0 9.0 1.0 10.0 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.3 9.7 1.0 11.0 1.0 12.5 ns VCC = 3.0 V to 3.6 V; CL = 15 pF 80 125 - 70 - 70 - MHz VCC = 3.0 V to 3.6 V; CL = 50 pF 50 75 - 45 - 45 - MHz VCC = 4.5 V to 5.5 V; CL = 15 pF 130 170 - 110 - 110 - MHz VCC = 4.5 V to 5.5 V; CL = 50 pF 90 115 - 75 - 75 - MHz VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 0.5 - - 0.5 - 0.5 - ns VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - 0.5 - ns ns nSD, nRD to nQ, nQ; see Fig. 8 fmax tW tsu th maximum frequency see Fig. 7 pulse width CP HIGH or LOW; nSD, nRD LOW; see Fig. 7 and Fig. 8 set-up time nD to nCP; see Fig. 7 hold time 74AHC_AHCT74 Product data sheet nD to nCP; see Fig. 7 All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 6 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ [1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns [3] - 12 - - - - - pF [2] propagation nCP to nQ, nQ; see Fig. 7 delay VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.3 7.8 1.0 9.0 1.0 10.0 ns - 4.8 8.8 1.0 10.0 1.0 11.0 ns VCC = 4.5 V to 5.5 V; CL = 15 pF - 3.7 10.4 1.0 12.0 1.0 13.0 ns VCC = 4.5 V to 5.5 V; CL = 50 pF - 5.3 11.4 1.0 13.0 1.0 14.5 ns VCC = 4.5 V to 5.5 V; CL = 15 pF 100 160 - 80 - 80 - MHz VCC = 4.5 V to 5.5 V; CL = 50 pF 80 140 - 65 - 65 - MHz tW pulse width CP HIGH or LOW; nSD, nRD LOW; VCC = 4.5 V to 5.5 V; see Fig. 7 and Fig. 8 5.0 - - 5.0 - 5.0 - ns tsu set-up time nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 7 5.0 - - 5.0 - 5.0 - ns th hold time nD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 7 0 - - 0 - 0 - ns trec recovery time nRD to nCP; VCC = 4.5 V to 5.5 V; see Fig. 8 3.5 - - 3.5 - 3.5 - ns CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance - 16 - - - - - pF trec recovery time CPD nRD to nCP; see Fig. 8 power fi = 1 MHz; VI = GND to VCC dissipation capacitance 74AHCT74 tpd VCC = 4.5 V to 5.5 V; CL = 50 pF nSD, nRD to nQ, nQ; see Fig. 8 fmax [1] [2] [3] maximum frequency see Fig. 7 [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). tpd is the same as tPLH and tPHL. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 Σ(CL × VCC × fo) = sum of the outputs. 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 7 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 10.1. Waveforms VI VM nD input GND th t su 1/fmax t su th VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH mna422 t PHL Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. Set and reset pulse widths, recovery time and input to output propagation delays 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 8 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Measurement points Type Input Output VM VM 74AHC74 0.5 × VCC 0.5 × VCC 74AHCT74 1.5 V 0.5 × VCC VI negative pulse VM tf tr tr VI GND VM 10 % GND positive pulse tW 90 % tf 90 % VM VM 10 % tW VCC G VI DUT VO RT CL 001aah768 For test data, see Table 9. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig. 9. Test circuit for measuring switching times Table 9. Test data Type Load Input Test VI tr, tf CL 74AHC74 VCC ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHCT74 3.0 V ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 9 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 10 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 11 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 12. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 12 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT74 v.8 20200422 Product data sheet - Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 5.1: Corrected pin configuration drawings (errata). Table 4: Derating values for Ptot total power dissipation updated. Fig. 12: Package outline drawing SOT762-1 (DHVQFN14) updated. 74AHC_AHCT74 v.7 20150421 Modifications: • 74AHC_AHCT74 v.6 20141020 Modifications: • 74AHC_AHCT74 v.5 20080609 Modifications: • • • 74AHC_AHCT74 v.7 Product data sheet - 74AHC_AHCT74 v.6 Table 7: minimum fmax values at 3.0 V to 3.6 V for 74AHC74 corrected (errata). Product data sheet - 74AHC_AHCT74 v.5 - 74AHC_AHCT74 v.4 Table 3 corrected (errata). Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT74 v.4 20050207 Product data sheet - 74AHC_AHCT74 v.3 74AHC_AHCT74 v.3 20040429 Product specification - 74AHC_AHCT74 v.2 74AHC_AHCT74 v.2 19990923 Product specification - 74AHC_AHCT74 v.1 74AHC_AHCT74 v.1 19990805 Product specification - - 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 13 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74AHC_AHCT74 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 14 / 15 74AHC74; 74AHCT74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................4 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms.................................................................8 11. Package outline........................................................ 10 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2020. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 April 2020 74AHC_AHCT74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 22 April 2020 © Nexperia B.V. 2020. All rights reserved 15 / 15