74ALVC574D,112

74ALVC574 Octal D-type flip-flop; positive edge-trigger; 3-state Rev. 3 — 30 April 2021 Product data sheet 1. General description The 74ALVC574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an outputs enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition. When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74ALVC574 is functionally identical to the 74ALVC374, but has a different pin arrangement. 2. Features and benefits • • • • • • • • Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: • JESD8-7 (1.65 V to 1.95 V) • JESD8-5 (2.3 V to 2.7 V) • JESD8B (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version -40 °C to +85 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74ALVC574PW -40 °C to +85 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74ALVC574BQ -40 °C to +85 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74ALVC574D SOT764-1 4. Functional diagram 11 1 11 2 3 4 5 6 7 8 9 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 OE 1 Fig. 1. 2 CP 19 C1 EN 19 1D 3 18 17 4 17 16 5 16 15 6 15 7 14 8 13 9 12 18 14 13 12 mna446 mna798 Logic symbol Fig. 2. IEC logic symbol 2 D0 Q0 19 3 D1 Q1 18 4 D2 5 D3 6 D4 7 D5 8 D6 Q6 13 9 D7 Q7 12 Q2 17 FF1 to FF8 3-STATE OUTPUTS Q3 16 Q4 15 Q5 14 11 CP 1 OE mna800 Fig. 3. Functional diagram 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state D0 D1 D Q D2 D CP D3 Q D CP FF1 Q D CP FF2 D4 Q D CP FF3 D5 Q D CP FF4 D6 Q D CP FF5 D7 Q D CP FF6 Q CP FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna801 Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 1 OE terminal 1 index area 1 D0 2 20 VCC 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 13 Q6 D7 9 12 Q7 GND 10 11 CP Pin configuration SOT163-1 (SO20) and SOT360-1 (TSSOP20) 74ALVC574 Product data sheet 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 14 Q5 D6 8 D7 9 GND(1) 13 Q6 12 Q7 001aad096 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. 001aad095 Fig. 5. 2 CP 11 OE D0 GND 10 74ALVC574 20 VCC 74ALVC574 Fig. 6. Pin configuration SOT764-1 (DHVQFN20) All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 5.2. Pin description Table 2. Pin description Symbol Pin Description D0, D1, D2, D3, D4, D5, D6, D7 2, 3, 4, 5, 6, 7, 8, 9 data input CP 11 clock input (LOW to HIGH, edge-triggered) OE 1 output enable input (active LOW) Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output VCC 20 supply voltage GND 10 ground (0 V) 6. Functional description Table 3. Function table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW to HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW to HIGH CP transition; Z = high-impedance OFF-state; ↑ = LOW to HIGH clock transition. Operating mode Load and read register Load register and disable outputs Internal flip-flop Output Input OE CP Dn Qn L ↑ l L L L ↑ h H H H ↑ l L Z H ↑ h H Z 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +4.6 V IIK input clamping current -50 - VI input voltage IOK output clamping current VO > VCC or VO < 0 V -0.5 +4.6 V - ±50 mA VO output voltage output HIGH or LOW state -0.5 VCC + 0.5 V output 3-state -0.5 +4.6 V power-down mode; VCC = 0 V -0.5 +4.6 V VI < 0 V [1] IO output current - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] VO = 0 V to VCC [1] mA Tamb = -40 °C to +85 °C The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage output HIGH or LOW state 0 VCC V output 3-state 0 3.6 V power-down mode; VCC = 0 V 0 3.6 V -40 +85 °C Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage Conditions -40 °C to +85 °C VCC = 1.65 V to 1.95 V Min Typ[1] Max 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC - 0.2 - - V IO = -6 mA; VCC = 1.65 V 1.25 1.51 - V IO = -12 mA; VCC = 2.3 V 1.8 2.10 - V IO = -18 mA; VCC = 2.3 V 1.7 2.01 - V IO = -12 mA; VCC = 2.7 V 2.2 2.53 - V IO = -18 mA; VCC = 3.0 V 2.4 2.76 - V IO = -24 mA; VCC = 3.0 V 2.2 2.68 - V 0.35 × VCC V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VOL Unit LOW-level output voltage VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 V IO = 6 mA; VCC = 1.65 V - 0.11 0.3 V IO = 12 mA; VCC = 2.3 V - 0.17 0.4 V IO = 18 mA; VCC = 2.3 V - 0.25 0.6 V IO = 12 mA; VCC = 2.7 V - 0.16 0.4 V IO = 18 mA; VCC = 3.0 V - 0.23 0.4 V IO = 24 mA; VCC = 3.0 V - 0.30 0.55 V II input leakage current VCC = 3.6 V; VI = 3.6 V or GND - ±0.1 ±5 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 1.65 V to 3.6 V; VO = 3.6 V or GND - ±0.1 ±10 μA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 3.6 V - ±0.1 ±10 μA 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 5 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Symbol Parameter Conditions -40 °C to +85 °C Unit Min Typ[1] Max ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 10 μA ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 750 μA CI input capacitance - 3.5 - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 10. Symbol Parameter tpd ten tdis tW tsu th propagation delay enable time disable time pulse width set-up time hold time 74ALVC574 Product data sheet Conditions -40 °C to +85 °C Unit Min Typ[1] Max VCC = 1.65 V to 1.95 V 1.0 3.1 6.4 ns VCC = 2.3 V to 2.7 V 1.0 2.3 3.9 ns VCC = 2.7 V 1.0 2.5 3.6 ns VCC = 3.0 V to 3.6 V 1.0 2.5 3.6 ns VCC = 1.65 V to 1.95 V 1.0 3.2 6.4 ns VCC = 2.3 V to 2.7 V 1.0 2.6 4.5 ns VCC = 2.7 V 1.0 3.2 4.6 ns VCC = 3.0 V to 3.6 V 1.0 2.4 4.0 ns VCC = 1.65 V to 1.95 V 1.5 3.6 7.0 ns VCC = 2.3 V to 2.7 V 1.0 2.3 4.4 ns VCC = 2.7 V 1.5 2.9 4.4 ns VCC = 3.0 V to 3.6 V 1.0 2.8 4.4 ns VCC = 1.65 V to 1.95 V 3.8 1.1 - ns VCC = 2.3 V to 2.7 V 3.3 0.9 - ns VCC = 2.7 V 3.3 0.8 - ns VCC = 3.0 V to 3.6 V 3.3 1.2 - ns VCC = 1.65 V to 1.95 V 0.8 -0.1 - ns VCC = 2.3 V to 2.7 V 0.8 0.1 - ns VCC = 2.7 V 0.8 0.3 - ns VCC = 3.0 V to 3.6 V 0.8 0.0 - ns VCC = 1.65 V to 1.95 V 0.8 -0.1 - ns VCC = 2.3 V to 2.7 V 0.8 0.1 - ns VCC = 2.7 V 0.8 0.4 - ns VCC = 3.0 V to 3.6 V 0.7 -0.1 - ns CP to Qn; see Fig. 7 OE to Qn; see Fig. 8 OE to Qn; see Fig. 8 [2] [2] [2] clock HIGH or LOW; see Fig. 7 Dn to CP; see Fig. 9 Dn to CP; see Fig. 9 All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 6 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Symbol Parameter fmax [3] -40 °C to +85 °C Unit Min Typ[1] Max VCC = 2.3 V to 2.7 V 100 200 - MHz VCC = 2.7 V 100 200 - MHz VCC = 3.0 V to 3.6 V 150 300 - MHz outputs HIGH or LOW state - 21 - pF outputs 3-state - 13 - pF see Fig. 7 maximum frequency CPD [1] [2] Conditions per flip-flop; VI = GND to VCC; VCC = 3.3 V power dissipation capacitance [3] Typical values are measured at Tamb = 25 °C tpd is the same as tPHL and tPLH. ten is the same as tPZH and tPZL. tdis is the same as tPHZ and tPLZ. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC x fi x N + Σ(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL x VCC x fo) = sum of the outputs 10.1. Waveforms and test circuit 1/f max VI CP input VM GND tW t PHL t PLH VOH VM Qn output VOL mna894 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig. 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width, and the maximum frequency Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY 1.65 V to 1.95 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 7 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state VI OE input VM GND tPLZ output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPHZ tPZH VOH output HIGH-to-OFF OFF-to-HIGH VY VM GND outputs enabled outputs enabled outputs disabled mna644 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. Fig. 8. Enable and disable times VI VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL mna202 Measurement points are given in Table 8. VOL and VOH are the typical output voltage levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predicable output performance. Fig. 9. Data set-up and hold times for the Dn input to the CP input 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 8 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 9 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 11. Package outline SOT163-1 (SO20) 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 10 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 12. Package outline SOT360-1 (TSSOP20) 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 11 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm B D SOT764-1 A A A1 E c detail X terminal 1 index area terminal 1 index area e1 C e b 2 9 v w C A B C y1 C y L 1 10 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.90 0.02 0.25 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 L v 0.2 4.6 4.5 4.4 3.15 3.00 2.85 2.6 2.5 2.4 1.15 1.00 0.85 0.5 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT764-1 --- MO-241 --- sot764-1_po European projection Issue date 03-01-27 14-12-12 Fig. 13. Package outline SOT764-1 (DHVQFN20) 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 12 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC574 v.3 20210430 Product data sheet - 74ALVC574 v.2 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 2: Reference to JESD36 removed. Section 7: Derating values for Ptot total power dissipation removed (errata). Package outline drawing of SOT764-1 (Fig. 13) updated. 74ALVC574 v.2 20071108 Modifications: • • • • • 74ALVC574 v.1 74ALVC574 Product data sheet Product data sheet - 74ALVC574 v.1 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 7: derating values added for DHVQFN20 package. Section 11: outline drawing added for DHVQFN20 package. 20020304 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 - © Nexperia B.V. 2021. All rights reserved 13 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 14 / 15 74ALVC574 Nexperia Octal D-type flip-flop; positive edge-trigger; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................5 10. Dynamic characteristics............................................ 6 10.1. Waveforms and test circuit........................................ 7 11. Package outline........................................................ 10 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 30 April 2021 74ALVC574 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 30 April 2021 © Nexperia B.V. 2021. All rights reserved 15 / 15