74ALVC74D,118

74ALVC74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 6 — 27 July 2021 Product data sheet 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits • • • • • • • • • Wide supply voltage range from 1.65 V to 3.6 V Complies with JEDEC standard: • JESD8-7 (1.65 to 1.95 V) • JESD8-5 (2.3 to 2.7 V) • JESD8B (2.7 to 3.6 V) 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: • HBM JESD22-A114E exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC74D -40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ALVC74PW -40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74ALVC74BQ -40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 4. Functional diagram 4 4 10 1SD 2SD 2 12 1D D 2D SD 3 1CP CP 11 2CP 2 1Q Q 2Q 5 9 1 FF RD 1Q Q 2Q 10 6 8 C1 1D 1RD 2RD 13 1 13 6 R 9 S 11 12 5 S 3 C2 2D 8 R aaa-008836 Fig. 1. Logic symbol 74ALVC74 Product data sheet aaa-008837 Fig. 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 4 1SD 2 1D 3 1CP SD D Q CP 1Q 5 1Q 6 2Q 9 2Q 8 FF1 Q RD 1 1RD 10 2SD 12 2D 11 2CP SD Q D CP FF2 Q RD 13 2RD aaa-008838 Fig. 3. Functional diagram Q C C C C C C D Q C C RD SD CP C aaa-008839 C Fig. 4. Logic diagram (one flip-flop) 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 5.1. Pinning 74ALVC74 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q 74ALVC74 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q aaa-027303 Fig. 5. aaa-027304 Pin configuration SOT108-1 (SO14) Fig. 6. Pin configuration SOT402-1 (TSSOP14) 1RD 1 terminal 1 index area 14 VCC 74ALVC74 1D 2 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 1Q 6 GND(1) 13 2RD 10 2SD 7 8 GND 2Q 9 2Q aaa-027305 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND Fig. 7. Pin configuration SOT762-1 (DHVQFN14) 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 4 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active-LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH), edge-triggered 1SD 4 asynchronous set-direct input (active-LOW) 1Q 5 true flip-flop output 1Q 6 complement flip-flop output GND 7 ground (0 V) 2Q 8 complement flip-flop output 2Q 9 true flip-flop output 2SD 10 asynchronous set-direct input (active-LOW) 2CP 11 clock input (LOW-to-HIGH), edge-triggered 2D 12 data input 2RD 13 asynchronous reset-direct input (active-LOW) VCC 14 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; nQn+1 = state after the next LOW-to-HIGH CP transition Input Output nSD nRD nCP nD nQ nQ nQn+1 nQ n+1 L H X X H L - - H L X X L H - - L L X X H H - - H H ↑ L - - L H H H ↑ H - - H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage -0.5 +4.6 V VI input voltage [1] -0.5 +4.6 V VO output voltage [1] -0.5 IIK input clamping current VI < 0 V [1] -0.5 +4.6 -50 - mA IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA Power-down mode; VCC = 0 V 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © VCC + 0.5 V V Nexperia B.V. 2021. All rights reserved 5 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter IGND Min Max Unit ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW Table 5. Recommended operating conditions Symbol Parameter Conditions Min Max Unit VCC supply voltage 1.65 3.6 V VI input voltage VO output voltage [1] [2] Conditions Tamb = -40 °C to +85 °C [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 8. Recommended operating conditions 0 3.6 V VCC = 1.65 to 3.6 V 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V -40 +85 °C 0 20 ns/V 0 10 ns/V Unit Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 3.6 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V VIL VOH LOW-level input voltage HIGH-level output voltage 74ALVC74 Product data sheet Min Typ [1] Max 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC - 0.2 - - V VCC = 1.65 V; IO = -6 mA 1.25 1.51 - V VCC = 2.3 V; IO = -12 mA 1.8 2.10 - V VCC = 2.3 V; IO = -18 mA 1.7 2.01 - V VCC = 2.7 V; IO = -12 mA 2.2 2.53 - V VCC = 3.0 V; IO = -18 mA 2.4 2.76 - V VCC = 3.0 V; IO = -24 mA 2.2 2.68 - V 0.35 × VCC V VI = VIH or VIL VCC = 1.65 V to 3.6 V; IO = -100 μA All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions Min Typ [1] Max Unit VOL LOW-level output voltage VI = VIH or VIL VCC = 1.65 V to 3.6 V; IO = 100 μA - - 0.2 V VCC = 1.65 V; IO = 6 mA - 0.11 0.3 V VCC = 2.3 V; IO = 12 mA - 0.17 0.4 V VCC = 2.3 V; IO = 18 mA - 0.25 0.6 V VCC = 2.7 V; IO = 12 mA - 0.16 0.4 V VCC = 3.0 V; IO = 18 mA - 0.23 0.4 V VCC = 3.0 V; IO = 24 mA - 0.30 0.55 V II input leakage current VCC = 3.6 V; VI = VCC or GND - ±0.1 ±5 μA IOFF power-off leakage current VCC = GND; VI or VO = 3.6 V - ±0.1 ±10 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 10 μA ΔICC additional supply current VCC = 3.0 V to 3.6 V; VI = VCC – 0.6 V; IO = 0 A - 5 750 μA CI input capacitance - 3.5 - pF Min Typ[1] Max Unit VCC = 1.65 to 1.95 V 1.0 3.7 6.2 ns VCC = 2.3 to 2.7 V 1.0 2.6 4.2 ns VCC = 2.7 V 1.0 2.8 4.2 ns VCC = 3.0 V to 3.6 V 1.0 2.7 3.8 ns VCC = 1.65 to 1.95 V 1.0 3.4 5.4 ns VCC = 2.3 to 2.7 V 1.0 2.4 3.8 ns VCC = 2.7 V 1.0 3.2 4.2 ns VCC = 3.0 V to 3.6 V 1.0 2.3 3.5 ns VCC = 1.65 to 1.95 V 1.0 3.5 5.4 ns VCC = 2.3 to 2.7 V 1.0 2.5 3.8 ns VCC = 2.7 V 1.0 3.1 4.3 ns VCC = 3.0 V to 3.6 V 1.0 2.3 3.5 ns [1] Typical values are measured at Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V): for test circuit, see Fig. 10 Symbol Parameter Conditions tpd propagation delay nCP to nQ, nQ; see Fig. 8 [2] nSD to nQ, nQ; see Fig. 9 nRD to nQ, nQ; see Fig. 9 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter Conditions Min Typ[1] Max tW pulse width nCP; HIGH or LOW; see Fig. 8 Unit VCC = 1.65 to 1.95 V 2.5 0.9 - ns VCC = 2.3 to 2.7 V 2.5 0.6 - ns VCC = 2.7 V 2.5 1.3 - ns VCC = 3.0 V to 3.6 V 2.5 1.3 - ns VCC = 1.65 to 1.95 V 2.5 0.9 - ns VCC = 2.3 to 2.7 V 2.5 0.9 - ns VCC = 2.7 V 2.5 1.0 - ns VCC = 3.0 V to 3.6 V 2.5 0.7 - ns VCC = 1.65 to 1.95 V 0.7 −0.2 - ns VCC = 2.3 to 2.7 V 0.7 −0.1 - ns VCC = 2.7 V 0.7 −0.1 - ns VCC = 3.0 V to 3.6 V 0.7 −0.1 - ns VCC = 1.65 to 1.95 V 1.2 0.6 - ns VCC = 2.3 to 2.7 V 1.2 0.8 - ns VCC = 2.7 V 1.1 0.5 - ns VCC = 3.0 V to 3.6 V 0.8 0.4 - ns VCC = 1.65 to 1.95 V 0.6 −0.4 - ns VCC = 2.3 to 2.7 V 0.6 −0.3 - ns VCC = 2.7 V 0.7 −0.4 - ns VCC = 3.0 V to 3.6 V 0.8 −0.1 - ns VCC = 1.65 to 1.95 V 150 275 - MHz VCC = 2.3 to 2.7 V 200 325 - MHz VCC = 2.7 V 250 375 - MHz VCC = 3.0 V to 3.6 V 300 425 - MHz - 35 - pF nSD or nRD; LOW; see Fig. 9 trec recovery time tsu set-up time th hold time fmax maximum frequency CPD [1] [2] [3] power dissipation capacitance nRD to nCP; see Fig. 9 nD to nCP; see Fig. 8 nD to nCP; see Fig. 8 nCP; see Fig. 8 per buffer; VI = GND to VCC; VCC = 3.3 V [3] Typical values are measured at Tamb = 25 °C. Typical values are measured at VCC = 1.8 V for VCC = 1.65 V to 1.95 V. Typical values are measured at VCC = 2.5 V for VCC = 2.3 V to 2.7 V. Typical values are measured at VCC = 3.3 V for VCC = 3.0 V to 3.6 V tpd is the same as tPHL and tPLH. 2 2 CPD is used to determine the dynamic power dissipation PD = CPD x VCC x fi x N + Σ (CL x VCC x fo), where: PD in μW fi = input frequency in MHz; fo = output frequency in MHz; N = total load switching outputs 2 Σ (CL x VCC x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 10.1. Waveforms and test circuit VI nD input VM GND tsu th 1/fmax VI nCP input tsu th VM GND tPHL VOH nQ output tW tPLH VM VOL VOH nQ output VM VOL tPLH tPHL aaa-008840 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 8. Clock pulse (nCP) to output (nQ, nQ) propagation delays, nCP pulse width, the nD to nCP set-up times, the nCP to nD hold times and maximum frequency VI nCP input VM GND trec VI nSD input VM GND tW VI VM nRD input GND VOH tW tPLH nQ output tPHL VM VOL VOH nQ output VOL VM tPHL tPLH aaa-008842 Measurement points are given in Table 8. Fig. 9. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, set (nSD) and reset (nRD) pulse widths and nRD to nCP recovery time 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Measurement points Supply voltage Input Output VCC VI VM VM 1.65 V to 1.95 V VCC 0.5VCC 0.5VCC 2.3 V to 2.7 V VCC 0.5VCC 0.5VCC 2.7 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 10. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VEXT Load VI tr, tf CL RL tPHL, tPLH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 11. Package outline SOT108-1 (SO14) 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 12. Package outline SOT402-1 (TSSOP14) 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm B D SOT762-1 A A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e v w b 2 6 C A B C y y1 C L 1 7 14 8 Eh e k 13 9 Dh X k 0 2 Dimensions (mm are the original dimensions) Unit mm max nom min A(1) 1 A1 b 0.05 0.30 0.02 0.25 0.00 0.18 4 mm scale c D(1) Dh E(1) Eh e e1 0.2 3.1 3.0 2.9 1.65 1.50 1.35 2.6 2.5 2.4 1.15 1.00 0.85 0.5 2 k L v 0.2 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. Outline version SOT762-1 References IEC JEDEC JEITA sot762-1_po European projection Issue date 15-04-10 15-05-05 MO-241 Fig. 13. Package outline SOT762-1 (DHVQFN14) 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC74 v.6 20210727 Product data sheet - 74ALVC74 v.5 Modifications: • 74ALVC74 v.5 20210430 Modifications: • • 74ALVC74 v.4 20170816 Modifications: • • Section 10: Minimum set-up time (tsu(min) at VCC = 2.7 V changed to 1.1 ns. (errata) Product data sheet - 74ALVC74 v.4 Section 2: Reference to JESD36 removed. Section 7: Derating values for Ptot total power dissipation have been updated. Product data sheet - 74ALVC74 v.3 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. 74ALVC74 v.3 20030526 Product specification - 74ALVC74 v.2 74ALVC74 v.2 20030124 Product specification - 74ALVC74 v.1 74ALVC74 v.1 20021115 Product specification - - 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 14 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74ALVC74 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74ALVC74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................4 5.1. Pinning.........................................................................4 5.2. Pin description............................................................. 5 6. Functional description................................................. 5 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 11 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 27 July 2021 74ALVC74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 27 July 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16