74ALVCH16843DGGS

74ALVCH16843 18-bit bus-interface D-type latch; 3-State Rev. 3 — 20 November 2017 1 Product data sheet General description The 74ALVCH16843 has two 9–bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits • • • • • • • • • • Wide supply voltage range of 1.2V to 3.6V CMOS low power consumption Direct interface with TTL levels Current drive ±24 mA at VCC = 3.0 V. MULTIBYTE flow-through standard pin-out architecture Low inductance multiple VCC and GND pins for minimize noise and ground bounce All data inputs have bushold Output drive capability 50 Ω transmission lines at 85 °C 3-state non-inverting outputs for bus oriented applications Complies with JEDEC standards: – JESD8-5 (2.3 V to 2.7 V) – JESD8B/JESD36 (2.7 V to 3.6 V) • ESD protection: – HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V – CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1. Ordering information Type number Package Temperature range Name 74ALVCH16843DGG -40 °C to +85 °C TSSOP56 Description Version plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 4 Functional diagram 1 55 2 56 1CLR 1PRE 1OE 1LE 3 1Q0 1D0 54 5 1Q1 1D1 52 6 1Q2 1D2 51 8 1Q3 1D3 49 9 1Q4 1D4 48 10 1Q5 1D5 47 12 1Q6 1D6 45 13 1Q7 1D7 44 14 1Q8 1D8 43 15 2Q0 2D0 42 16 2Q1 2D1 41 17 2Q2 2D2 40 19 2Q3 2D3 38 20 2Q4 2D4 37 21 2Q5 2D5 36 23 2Q6 2D6 34 24 2Q7 2D7 33 26 2Q8 2D8 31 2CLR 2PRE 2OE 2LE 28 30 27 29 1OE 1PRE 1CLR 1LE 2OE 2PRE 2CLR 2LE 1D 2, 3, 4 5D 6, 7, 8 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 aaa-027721 Figure 2. IEC logic symbol D Q CLR LATCH 10 1Q0 2D0 D 2CLR LE Q 2Q0 CLR PRE 1PRE EN4 S2 R3 C1 EN8 S6 R7 C5 aaa-027720 LATCH 1 1D0 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 Figure 1. Logic symbol 1CLR 2 55 1 56 27 30 28 29 PRE 2PRE 1LE 2LE 1OE 2OE to 8 other channels LE to 8 other channels aaa-027722 Figure 3. Logic diagram 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 2 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State VCC data input to internal circuit mna004 Figure 4. Bushold circuit 5 Pinning information 5.1 Pinning 74ALVCH16843 1CLR 1 56 1LE 1OE 2 55 1PRE 1Q0 3 54 1D0 GND 4 53 GND 1Q1 5 52 1D1 1Q2 6 51 1D2 VCC 7 50 VCC 1Q3 8 49 1D3 1Q4 9 48 1D4 1Q5 10 47 1D5 GND 11 46 GND 1Q6 12 45 1D6 1Q7 13 44 1D7 1Q8 14 43 1D8 2Q0 15 42 2D0 2Q1 16 41 2D1 2Q2 17 40 2D2 GND 18 39 GND 2Q3 19 38 2D3 2Q4 20 37 2D4 2Q5 21 36 2D5 VCC 22 35 VCC 2Q6 23 34 2D6 2Q7 24 33 2D7 GND 25 32 GND 2Q8 26 31 2D8 2OE 27 30 2PRE 2CLR 28 29 2LE aaa-027723 Figure 5. Pin configuration for TSSOP56 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 3 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 5.2 Pin description Table 2. Pin description Symbol Pin Description 1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7, 1D8 54, 52, 51, 49, 48, 47, 45, 44, 43 data inputs 1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7, 1Q8 3, 5, 6, 8, 9, 10, 12, 13, 14 data outputs 2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7, 2D8 42, 41, 40, 38, 37, 36, 34, 33, 31 data inputs 2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7, 2Q8 15, 16, 17, 19, 20, 21, 23, 24, 26 data outputs 1OE, 2OE 2, 27 output enable inputs (active LOW) 1PRE, 2PRE 55, 30 preset inputs (active LOW) 1CLR, 2CLR 1, 28 clear inputs (active LOW) 1LE, 2LE 56, 29 latch enable inputs (active HIGH) GND 4, 11, 18, 25, 32, 39, 46, 53 ground (0 V) VCC 7, 22, 35, 50 supply voltage 6 Functional description Table 3. Function selection [1] Inputs Output nPRE nCLR nOE nLE nDn nQn L X L X X H H L L X X L H H L H L L H H L H H H H H L L X NC X X H X X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; NC = no change; Z = high-impedance OFF-state. 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 4 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 7 Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit -0.5 +4.6 V For control pins [1] -0.5 +4.6 V For data inputs [1] -0.5 VCC + 0.5 V [1] -0.5 VCC + 0.5 V -50 - mA VO output voltage IIK input clamping current VI < 0 V IOK output clamping current VO > VCC or VO < 0 V - ±50 mA IO output current VO = 0 V to VCC - ±50 mA ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 °C - 600 mW Min Max Unit CL = 30 pF 2.3 2.7 V CL = 50 pF 3.0 3.6 V Ptot total power dissipation Tamb = -40 °C to +85 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 °C the value of Ptot derates linearly with 8 mW/K. 8 Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions VCC supply voltage maximum speed performance VI input voltage 0 VCC V VO output voltage 0 VCC V Tamb ambient temperature in free air -40 +85 °C Δt/ΔV input transition rise and fall rate VCC = 2.3 V to 3.0 V - 20 ns/V VCC = 3.0 V to 3.6 V - 10 ns/V 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 5 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 9 Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = -40 °C to +85 °C [1] Symbol Parameter Conditions Min Typ VIH HIGH-level input voltage VCC = 2.3 V to 2.7 V 1.7 1.2 - V VCC = 2.7 V to 3.6 V 2.0 1.5 - V LOW-level input voltage VCC = 2.3 V to 2.7 V - 1.2 0.7 V VCC = 2.7 V to 3.6 V - 1.5 0.8 V HIGH-level output voltage VI = VIH or VIL IO = -100 μA; VCC = 2.3 V to 3.6 V VCC - 0.2 VCC - V IO = -6 mA; VCC = 2.3 V VCC - 0.3 VCC - 0.08 - V IO = -12 mA; VCC = 2.3 V VCC - 0.6 VCC - 0.26 - V IO = -12 mA; VCC = 2.7 V VCC - 0.5 VCC - 0.14 - V IO = -12 mA; VCC = 3.0 V VCC - 0.6 VCC - 0.09 - V IO = -24 mA; VCC = 3.0 V VCC - 1.0 VCC - 0.28 - V IO = 100 μA; VCC = 2.3 V to 3.6 V - GND 0.20 V IO = 6 mA; VCC = 2.3 V - 0.07 0.40 V IO = 12 mA; VCC = 2.3 V - 0.15 0.70 V IO = 12 mA; VCC = 2.7 V - 0.14 0.40 V IO = 24 mA; VCC = 3.0 V - 0.27 0.55 V VIL VOH VOL LOW-level output voltage Max Unit VI = VIH or VIL II input leakage current VCC = 2.3 V to 3.6 V; VI = VCC or GND - 0.1 5 μA IOZ OFF-state output current VCC = 2.3 V to 3.6 V; VI = VIH or VIL; VO = VCC or GND - 0.1 10 μA ICC supply current VCC = 2.3 V to 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 40 μA ΔICC additional supply current VCC = 2.3 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 150 750 μA IBHL bus hold LOW current VCC = 2.3 V; VI = 0.7 V 45 - - μA VCC = 3.0 V; VI = 0.8 V 75 150 - μA bus hold HIGH current VCC = 2.3 V; VI = 1.7 V -45 - - μA VCC = 3.0 V; VI = 2.0 V -75 -175 - μA IBHLO bus hold LOW overdrive current VCC = 3.6 V 500 - - μA IBHHO bus hold HIGH overdrive current VCC = 3.6 V -500 - - μA CI input capacitance - 5.0 - pF IBHH [1] All typical values are measured at Tamb = 25 °C. 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 6 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 10 Dynamic characteristics Table 7. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11; Tamb = -40 °C to +85 °C Symbol tpd Parameter propagation delay Conditions Min Typ VCC = 2.3 V to 2.7 V 1.0 VCC = 2.7 V VCC = 3.0 V to 3.6 V [1] Max Unit 2.2 4.3 ns 1.0 2.3 4.0 ns 1.0 2.1 3.5 ns VCC = 2.3 V to 2.7 V 1.0 2.3 4.6 ns VCC = 2.7 V 1.0 2.1 3.9 ns 1.0 2.0 3.5 ns VCC = 2.3 V to 2.7 V 1.0 2.5 4.8 ns VCC = 2.7 V 1.0 2.6 4.5 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.8 ns VCC = 2.3 V to 2.7 V 1.0 2.5 4.8 ns VCC = 2.7 V 1.0 2.5 4.3 ns 1.0 2.3 3.9 ns VCC = 2.3 V to 2.7 V 1.0 2.8 5.8 ns VCC = 2.7 V 1.0 3.0 5.3 ns 1.0 2.5 4.4 ns VCC = 2.3 V to 2.7 V 1.1 2.2 4.3 ns VCC = 2.7 V 1.3 2.8 4.4 ns VCC = 3.0 V to 3.6 V 1.3 2.6 4.0 ns VCC = 2.3 V to 2.7 V 0.5 −0.1 - ns VCC = 2.7 V 0.5 −0.3 - ns VCC = 3.0 V to 3.6 V 0.5 0.0 - ns VCC = 2.3 V to 2.7 V 0.9 0.5 - ns VCC = 2.7 V 0.9 0.5 - ns VCC = 3.0 V to 3.6 V 0.9 0.5 - ns nDn to nQn; see Figure 6 [2] nLE to nQn; see Figure 7 VCC = 3.0 V to 3.6 V nPRE to nQn; see Figure 6 [3] nCLR to nQn; see Figure 6 VCC = 3.0 V to 3.6 V ten enable time nOE to nQn; see Figure 10 [3] VCC = 3.0 V to 3.6 V tdis tsu th disable time set-up time hold time 74ALVCH16843 Product data sheet nOE to nQn; see Figure 10 [4] nDn to nLE; see Figure 8 nDn to nLE; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 7 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State Symbol Parameter Conditions tW pulse width nLE HIGH; see Figure 7 [1] Min Typ Max Unit VCC = 2.3 V to 2.7 V 1.5 0.5 - ns VCC = 2.7 V 1.5 0.5 - ns VCC = 3.0 V to 3.6 V 1.5 0.5 - ns VCC = 2.3 V to 2.7 V 1.5 0.5 - ns VCC = 2.7 V 1.5 0.6 - ns VCC = 3.0 V to 3.6 V 1.5 0.5 - ns VCC = 2.3 V to 2.7 V 1.5 0.5 - ns VCC = 2.7 V 1.5 0.5 - ns VCC = 3.0 V to 3.6 V 1.5 0.5 - ns VCC = 2.3 V to 2.7 V 0.5 1.1 - ns VCC = 2.7 V 0.8 −0.2 - ns VCC = 3.0 V to 3.6 V 1.0 0.4 - ns VCC = 2.3 V to 2.7 V 0.5 1.0 - ns VCC = 2.7 V 0.6 −0.4 - ns 0.8 0.2 - ns transparent mode; outputs enabled - 17 - pF transparent mode; outputs disabled - 3 - pF clocked mode; outputs enabled - 19 - pF clocked mode; outputs disabled - 9 - pF nPRE LOW; see Figure 9 nCLR LOW; see Figure 9 trec recovery time nPRE to nLE; see Figure 9 nCLR to nLE; see Figure 9 VCC = 3.0 V to 3.6 V CPD power dissipation capacitance per latch; VI = GND to VCC [5] [1] Typical values are measured at Tamb = 25 °C Typical values for VCC = 2.3 V to 2.7 V are measured at VCC = 2.5 V. Typical values for VCC = 3.0 V to 3.6 V are measured at VCC = 3.3 V. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZL and tPZH. [4] tdis is the same as tPLZ and tPHZ. [5] CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + ∑ (CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; 2 ∑(CL × VCC × fo) = sum of outputs. 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 8 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 10.1 Waveforms and test circuit VI nCLR, nDn input nPRE VM VM GND tPHL tPLH VOH VM nQn output VM VOL aaa-027724 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Figure 6. Data input (nDn) to output (nQn), clear input (nCLR) to output (nQn) and preset input (nPRE) to output (nQn) propagation delay VI nLE input VM GND VM tW tPHL VOH nQn output VM tPLH VM VOL VM 001aam012 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Figure 7. Latch enable input (nLE) to data output (nQn) propagation delay and pulse width (nLE) VI nDn input VM GND VI nLE input th tsu th tsu VM GND 001aam013 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 8. Data setup and hold times for input (nDn) to input (nLE) 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 9 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State VI nCLR, nPRE input VM VM GND tW trec VI nLE input VM GND aaa-027725 Measurement points are given in Table 8. Figure 9. Clear (nCLR) and preset (nPRE) pulse width, the clear (nCLR) and preset (nPRE) to latch (nLE) recovery time VI nOE input VM VM GND tPLZ nQn output LOW-to-OFF OFF-to-LOW tPZL VCC VM VX VOL tPZH tPHZ nQn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs disabled outputs enabled 001aal795 Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Figure 10. 3-State enable and disable times Table 8. Measurement points Input Output VCC VI VM VM Vx Vy 2.3 V to 2.7 V VCC 0.5VCC 0.5VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 10 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State VI negative pulse tW 90 % VM 0V VI tf tr tr tf 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae235 Test data is given in Table 9. Definitions test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator; VEXT = External voltage for measuring switching times. Figure 11. Test circuit for measuring switching times Table 9. Test data Input Load VEXT VCC VI tr, tf RL CL tPHZ, tPZH tPLZ, tPZL tPLH, tPHL 2.3 V to 2.7 V VCC ≤ 2.0 ns 500 Ω 30 pF GND 2 × VCC open 2.7 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 500 Ω 50 pF GND 2 × VCC open 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 11 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 11 Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3 ) A1 pin 1 index A θ Lp L 1 28 w M bp e detail X 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 12. Package outline SOT364-1 (TSSOP56) 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 12 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 12 Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVCH16843 v.3 20171120 Product data sheet - 74ALVCH16843 v.2 Modifications: • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. • Legal texts have been adapted to the new company name where appropriate. 74ALVCH16843 v.2 19980804 Product specification - 74ALVCH16843 v.2 74ALVCH16843 v.1 19980804 Product specification - - 74ALVCH16843 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 13 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State 14 Legal information 14.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical 74ALVCH16843 Product data sheet systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 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All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 14 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia's warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia's specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer 74ALVCH16843 Product data sheet design and use of the product for automotive applications beyond Nexperia's standard warranty and Nexperia's product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 3 — 20 November 2017 © Nexperia B.V. 2017. All rights reserved. 15 / 16 74ALVCH16843 Nexperia 18-bit bus-interface D-type latch; 3-State Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 10.1 11 12 13 14 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 1 Functional diagram ............................................. 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 4 Functional description ........................................4 Limiting values .................................................... 5 Recommended operating conditions ................ 5 Static characteristics .......................................... 6 Dynamic characteristics .....................................7 Waveforms and test circuit ................................ 9 Package outline .................................................12 Abbreviations .................................................... 13 Revision history ................................................ 13 Legal information .............................................. 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © Nexperia B.V. 2017. All rights reserved. For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 20 November 2017 Document identifier: 74ALVCH16843