Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
or
e
CD4013
Dual D-type Flip-Flop
Specification
i-c
Product
Specification Revision History：
Version
Date
2019-05-A1
2019-05
Description
New
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
1/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
1、General Description
The CD4013 is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input
—
(CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the
or
e
output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inputs are
independent and override the D or CP inputs. The outputs are buffered for best system performance. The
clock input’s Schmitt-trigger action makes the circuit highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS (usually ground).
Unused inputs must be connected to VDD, VSS, or another input.
Features:
Wide supply voltage range from 3V to 15V
Fully static operation
5V, 10V, and 15V parametric ratings
Standardized symmetrical output characteristics
Tolerant of slow clock rise and fall times
Specified from -40℃ to +85℃
Packaging information: DIP14/SOP14/TSSOP14
Ordering Information:
Tube packing specifications:
Type number
DIP14
Marking
code
Tube
quantity
Boxed
tube
quantity
Boxed
quantity
Packing
box
number
Packing
quantity
CD4013
25
PCS/tube
40
tube/box
1000
PCS/box
10
box/pack
10000
PCS/pack
i-c
CD4013DA.TB
Packaging
form
CD4013SA.TB
SOP14
CD4013
50
PCS/tube
200
tube/box
10000
PCS/box
5
box/pack
50000
PCS/pack
CD4013TA.TB
TSSOP14
CD4013
94
PCS/tube
200
tube/box
18800
PCS/box
10
box/pack
188000
PCS/pack
Reel packing specifications:
Packaging
Type number
Marking code
form
Reel
quantity
Boxed reel
quantity
Packing
quantity
2500
PCS/reel
5000
PCS/box
40000
PCS/pack
Notes
Dimensions of
plastic enclosure:
19.0mm×6.4mm
Pin spacing: 2.54mm
Dimensions of
plastic enclosure:
8.7mm×3.9mm
Pin spacing: 1.27mm
Dimensions of
plastic enclosure:
5.0mm×4.4mm
Pin spacing: 0.65mm
Notes
Dimensions of plastic
enclosure:
CD4013SA.TR
SOP14
CD4013
8.7mm×3.9mm
Pin spacing: 1.27mm
Dimensions of plastic
3000
6000
48000
enclosure:
CD4013TA.TR
TSSOP14
CD4013
PCS/reel
PCS/box
PCS/pack
5.0mm×4.4mm
Pin spacing: 0.65mm
Note: If the physical information is inconsistent with the ordering information, please refer to the actual
product.
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
2/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
2、Block Diagram And Pin Description
e
2.1、Block Diagram
i-c
or
Figure 1. Functional diagram
Figure 2. Logic diagram (one flip-flop)
2.2、Pin Configurations
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
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VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
2.3、Pin Description
Pin No.
1
Pin Name
1Q
Description
true output
2
1Q
complement output
3
4
5
6
7
8
9
10
11
1CP
1CD
1D
1SD
VSS
2SD
2D
2CD
2CP
clock input (LOW to HIGH edge-triggered)
asynchronous clear-direct input (active HIGH)
data input
asynchronous set-direct input (active HIGH)
ground (0V)
asynchronous set-direct input (active HIGH)
data input
asynchronous clear-direct input (active HIGH)
clock input (LOW to HIGH edge-triggered)
12
2Q
13
14
2Q
VDD
e
—
—
complement output
or
true output
supply voltage
2.4、Function Table
Input
nSD
nCD
Output
nCP
nD
nQ
—
i-c
nQ
H
L
X
X
H
L
L
H
X
X
L
H
H
H
X
X
H
H
L
L
↑
L
L
H
L
L
↑
H
H
L
Note: H=HIGH voltage level; L=LOW voltage level; X=don’t care; ↑=LOW-to-HIGH clock transition.
3、Electrical Parameter
3.1、Absolute Maximum Ratings
(Voltages are referenced to VSS (ground=0V), unless otherwise specified.)
Parameter
supply voltage
DC input current
input voltage
storage temperature
total power
dissipation
device dissipation
Soldering
temperature
Symbol
VDD
IIK
VI
Tstg
Conditions
any one input
all inputs
-
Min.
-0.5
-0.5
-65
Max.
+18
±10
VDD+0.5
+150
Unit
V
mA
V
℃
Ptot
-
-
500
mW
P
per output transistor
DIP
10s
SOP
-
100
mW
℃
℃
TL
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
245
250
4/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
Note:
[1] For DIP14 packages: above 70℃ the value of Ptot derates linearly with 12mW/K.
[2] For SOP14 packages: above 70℃ the value of Ptot derates linearly with 8mW/K.
[3] For (T)SSOP14 packages: above 60℃ the value of Ptot derates linearly with 5.5mW/K.
3.2、Recommended Operating Conditions
Parameter
supply voltage
ambient
temperature
Symbol
VDD
Conditions
-
Min.
3
Typ.
-
Max.
15
Unit
V
Tamb
in free air
-40
-
+85
℃
i-c
or
e
VDD=5V
40
ns
set-up time
tsu
VDD=10V
20
ns
VDD=15V
15
ns
VDD=5V
140
ns
clock pulse width
twCL
VDD=10V
60
ns
VDD=15V
40
ns
VDD=5V
3.5
7
MHz
clock input
fCL
VDD=10V
8
16
MHz
frequency
VDD=15V
12
24
MHz
15
us
VDD=5V
clock rise and
VDD=10V
10
us
trCL, tfCL
fall time
VDD=15V
5
us
180
ns
VDD=5V
Set or reset pulse
twS/R
VDD=10V
80
ns
width
VDD=15V
50
ns
Note: If more than one unit is cascaded in a parallel clocked operation, trCL must be made less than or
equal to the sum of the fixed propagation delay time at 15pF and the transistion time of the output driving
stage for the estimated capacitive load.
3.3、Electrical Characteristics
3.3.1、DC Characteristics 1
(Tamb=25℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.)
Tamb=25℃
Conditions (V)
Parameter
Symbol
VO
VIN
VDD
Min.
Typ.
0, 5
5
0.02
supply current
IDD
0, 10
10
0.02
0, 15
15
0.02
0.4
0, 5
5
0.51
1
LOW-level
IOL
0.5
0, 10
10
1.3
2.6
output current
1.5
0, 15
15
3.4
6.8
4.6
0, 5
5
-0.51
-1
2.5
0,
5
5
-1.6
-3.2
HIGH-level
IOH
output current
9.5
0, 10
10
-1.3
-2.6
13.5
0, 15
15
-3.4
-6.8
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
Max.
1
2
4
-
Unit
uA
uA
uA
mA
mA
mA
mA
mA
mA
mA
5/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
VOL
HIGH-level
output voltage
VOH
LOW-level
input voltage
VIL
HIGH-level
input voltage
VIH
input leakage
current
II
0.5, 4.5
1, 9
1.5, 13.5
0.5, 4.5
1, 9
1.5, 13.5
0, 5
0, 10
0, 15
0, 5
0, 10
0, 15
-
5
10
15
5
10
15
5
10
15
5
10
15
4.95
9.95
14.95
3.5
7
11
0
0
0
5
10
15
-
0.05
0.05
0.05
1.5
3
4
-
V
V
V
V
V
V
V
V
V
V
V
V
-
0, 15
15
-
±10-5
±0.1
uA
e
LOW-level
output voltage
Number:CD4013-AX-LJ-D004EN
i-c
or
3.3.2、DC Characteristics 2
(Tamb=-40℃ to +85℃, voltages are referenced to VSS (ground=0V), unless otherwise specified.)
Tamb=-40℃
Tamb=+85℃
Conditions (V)
Parameter
Symbol
VO
VIN
VDD
Min.
Max.
Min.
Max.
0, 5
5
1
30
supply current
IDD
0, 10
10
2
60
0, 15
15
4
120
0.4
0, 5
5
0.61
0.42
LOW-level
0.5
0, 10
10
1.5
1.1
IOL
output current
1.5
0, 15
15
4
2.8
4.6
0, 5
5
-0.61
-0.42
2.5
0, 5
5
-1.8
-1.3
HIGH-level
IOH
output current
9.5
0, 10
10
-1.5
-1.1
13.5
0, 15
15
-4
-2.8
0, 5
5
0.05
0.05
LOW-level
0, 10
10
0.05
0.05
VOL
output voltage
0, 15
15
0.05
0.05
0, 5
5
4.95
4.95
HIGH-level
0, 10
10
9.95
9.95
VOH
output voltage
0, 15
15
14.95
14.95
0.5, 4.5
5
1.5
1.5
LOW-level
1, 9
10
3
3
VIL
input voltage
1.5, 13.5
15
4
4
0.5, 4.5
5
3.5
3.5
HIGH-level
1, 9
10
7
7
VIH
input voltage
1.5, 13.5
15
11
11
input leakage
II
0, 15
15
±0.1
±1
current
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
Unit
uA
uA
uA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
V
V
V
V
uA
6/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
3.3.3、AC Characteristics
(Tamb=25℃, VSS=0V, tr, tf=20ns, CL=50pF, RL=20kΩ, unless otherwise specified.)
Parameter
Symbol
Conditions
—
HIGH to LOW
propagation
delay
nCP to nQ, nQ;
see Figure 4
tPHL
—
nSD to nQ
or nCD to nQ
—
tPLH
nSD to nQ
—
or nCD to nQ
Max.
300
130
90
400
170
120
300
130
90
300
130
90
200
100
80
140
60
40
180
80
50
40
20
15
5
5
5
15
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
tt
see Figure 4
-
5
7.5
pF
or
transition time
Typ.
150
65
45
200
85
60
150
65
45
150
65
45
100
50
40
7
16
24
70
30
20
90
40
25
20
10
7
2
2
2
-
e
LOW to HIGH
propagation
delay
nCP to nQ, nQ;
see Figure 4
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
VDD=5V
VDD=10V
VDD=15V
Min.
3.5
8
12
-
maximum
clock
frequency
see Figure 4
fclk(max)
nCP input LOW;
see Figure 4
tW
nSD input HIGH
or nCD input HIGH;
see Figure 5
i-c
pulse width
set-up time
tsu
nD to nCP;
see Figure 4
hold time
th
nD to nCP;
see Figure 4
clock input rise
or fall time
trCL, tfCL
-
input
CI
capacitance
Note: tt is the same as tTLH and tTHL.
any input
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
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VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
4、Testing Circuit
4.1、AC Testing Circuit
e
Figure 3. Test circuit for switching times
or
Definitions for test circuit:
DUT=Device Under Test.
CL=Load capacitance including jig and probe capacitance.
RT=Termination resistance should be equal to the output impedance Zo of the pulse generator.
i-c
4.2、AC Testing Waveforms
Figure 4. Set-up time, hold time, minimum clock pulse width, propagation delays and transition times
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
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Wuxi I-CORE Electronics Co., Ltd.
rev:B3
Number:CD4013-AX-LJ-D004EN
e
Tab: 835-12
or
Figure 5. nSD, nCD pulse width
4.3、Measurement Points
Supply voltage
VDD
5V to 15V
VM
0.5×VDD
Output
VM
0.5×VDD
VX
0.1×VDD
Input
i-c
4.4、Test Data
Supply voltage
VDD
5V to 15V
Input
VI
VSS or VDD
VY
0.9×VDD
Load
tr , tf
≤ 20ns
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
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P.C.：214072
CL
50pF
9/ 13
VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
5、Package Information
i-c
or
e
5.1、DIP14
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
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Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
i-c
or
e
5.2、SOP14
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
http://www.i-core. cn
P.C.：214072
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Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
i-c
or
e
5.3、TSSOP14
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
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VER：2019-05-A1
Wuxi I-CORE Electronics Co., Ltd.
Tab: 835-12
rev:B3
Number:CD4013-AX-LJ-D004EN
6、Statements And Notes
6.1、The name and content of Hazardous substances or Elements in the product
Hazardous substances or Elements
Part name
Lead
and
lead
compo
unds
Mercur
y and
mercur
y
compo
unds
Cadm
ium
and
cadmi
um
comp
ounds
Hexaval
ent
chromiu
m
compoun
ds
Polybro
minated
biphenyl
s
Polybro
minate
d
biphen
yl
ethers
Dibutyl
phthala
te
Butylbe
nzyl
phthala
te
Di-2-et
hylhex
yl
phthala
te
Diisobu
tyl
phthala
te
○
○
○
○
○
○
○
○
○
○
Plastic resin
○
○
○
○
○
○
○
○
○
○
Chip
○
○
○
○
○
○
○
○
○
○
The lead
○
○
○
○
○
○
○
○
○
○
Plastic sheet
installed
○
○
○
e
Lead frame
○
○
○
○
○
○
○
○：Indicates that the content of hazardous substances or elements in the detection limit
of the following the SJ/T11363-2006 standard。
×：Indicates that the content of hazardous substances or elements exceeding the SJ/T11363-2006
Standard limit requirements。
or
explanation
6.2、Notion
Recommended carefully reading this information before the use of this product；
The information in this document are subject to change without notice；
This information is using to the reference only, the company is not responsible for any loss；
i-c
The company is not responsible for the any infringement of the third party patents or other rights of
the responsibility.
Address：Building B4,NO.777,Jianzhu Road,Binhu Distrct,Wuxi City,Jiangsu Province
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P.C.：214072
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