AS5115A-HSST

AS5115 Programmable 360° Magnetic Angle Encoder with Buffered Sine and Cosine Output Signals General Description The AS5115 is a contactless rotary encoder sensor for accurate angular measurement over a full turn of 360° and over an extended ambient temperature range of -40°C to 150°C. Based on an integrated Hall element array, the angular position of a simple two-pole magnet is translated into analog output voltages. The angle information is provided by means of buffered sine and cosine voltages. This approach gives maximum flexibility in system design, as it can be directly integrated into existing architectures and optimized for various applications in terms of speed and accuracy. An SSI Interface is implemented for signal path configuration as well as a one time programmable register block (OTP), which allows the customer to adjust the signal path gain to adjust for different mechanical constraints and magnetic field. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of AS5115, Programmable 360° Magnetic Angle Encoder with Buffered Sine and Cosine Output Signals are listed below: Figure 1: Added Value of Using AS5115 Benefits Features • Highest reliability and durability • Contactless high resolution rotational position encoding over a full turn of 360 degrees • Simple programming • Simple user-programmable over serial interface (SSI) • High precision analog output • Buffered sine and cosine output signals • Very low average power consumption • Low Power mode • Easy setup • Serial read-out of multiple interconnected devices using daisy chain mode • Fully automotive qualified • AEC-Q100, grade 0 • Small form factor • SSOP 16 • Robust environmental tolerance • Wide temperature range: -40°C to 150°C ams Datasheet [v1-16] 2016-Nov-17 Page 1 Document Feedback AS5115 − General Description Applications The AS5115 is ideal for several automotive and industrial applications such as • Microcontroller-based systems • Contactless rotary position sensing • General purpose for automotive and industrial applications Block Diagram The functional blocks of this device are shown below: Figure 2: AS5115 Block Diagram PROG OTP Register AS5115 Digital Part CS DCLK DIO SSI Interface Power Management Buffer Stage VDD VSS SINP/SINN SINN/SINP/CM_SIN Buffer Stage Hall Array & Frontend Amplifier Page 2 Document Feedback COSP/COSN COSN/COSP/CM_COS ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Pin Assignments Pin Assignments Figure 3: Pin Diagram (Top View) DCLK 1 16 VDD CS 2 15 TB0 DIO 3 14 TB1 TC 4 13 TB2 A_TST 5 12 TB3 PROG 6 11 COSN/COSP/CM_COS VSS 7 10 COSP/COSN SINP/SINN 8 9 AS5115 SINN/SINP/CM_SIN Pin Description Figure 4: Pin Description Pin Name Pin Number DCLK 1 CS 2 DIO 3 Digital input/output Data I/O for digital interface, Scan input TC 4 Analog input/output Test coil A_TST 5 Analog output/Digital output Analog test pin, Scan output PROG 6 VSS 7 SINP/SINN 8 SINN/SINP/CM_SIN 9 COSP/COSN 10 COSN/COSP/CM_COS 11 Pin Type Clock input for digital interface Digital input with Schmitt trigger Clock input for digital interface, Scan enable OTP programming pad Supply pad Analog output ams Datasheet [v1-16] 2016-Nov-17 Description Also used as VSS of test coil + EasyZapp (double bond) Buffered analog output Page 3 Document Feedback AS5115 − Pin Assignments Pin Name Pin Number TB3 12 TB2 13 TB1 14 TB0 15 Analog output Test bus, analog output VDD 16 Supply pad Digital + analog supply Pin Type Description Test bus, analog output Page 4 Document Feedback Analog output/Digital input Test bus, analog output; external clock → sync. prod. test ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings Figure 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Comments Electrical Parameters VDD Supply voltage -0.3 7 V V_in Input pin voltage -0.3 VDD+ 0.3 V I_scr Input current (latchup immunity) -100 100 mA EIA/JESD78 Class II Level A Electrostatic Discharge ESDHBM Electrostatic discharge ±2 kV JESD22-A114E Continuous Power Dissipation Ptot Q_JA Total power dissipation 275 mW Package thermal resistance 110 °C/W Velocity =0; Multi Layer PCB; Jedec Standard Testboard Temperature Ranges and Storage Conditions T_strg T_body Storage temperature -65 150 Package body temperature RHNC Relative humidity non-condensing MSL Moisture sensitivity level ams Datasheet [v1-16] 2016-Nov-17 5 3 °C 260 °C 85 % IPC/JEDEC J-STD-020. The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin(100% Sn). Represents a maximum floor time of 168h Page 5 Document Feedback AS5115 − Electrical Characteristics Electrical Characteristics All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or SQC (Statistical Quality Control) methods. Figure 6: Operating Conditions Symbol Parameter VDD Positive supply voltage VSS T_amb Conditions Min Typ Max Unit 4.5 5.5 V Negative supply voltage 0.0 0.0 V Ambient temperature -40 150 °C Figure 7: DC/AC Characteristics for Digital Inputs and Outputs Symbol Parameter Conditions Min Typ Max Unit CMOS Input V_IH High level input voltage 0.7 * VDD VDD V V_IL Low level input voltage 0 0.3 * VDD V I_LEAK Input leakage current 1 μA CMOS Output V_OH High level output voltage 4mA VDD - 0.5 VDD V V_OL Low level output voltage 4mA 0 VSS + 0.4 V C_L Capacitive load 35 pF 1 μA CMOS Output Tristate I_OZ Tristate leakage current Figure 8: Magnetic Input Specification Symbol Parameter Conditions Min Typ Max Unit BZpp Magnetic input field amplitude Peak to peak at the radius (=1mm) of the hall array 32 160 mT B_offset Magnetic field offset Within the linear range of the magnet -10 10 mT Rotational speed Maximum 30,000 RPM 0 500 Hz frot Page 6 Document Feedback ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Electrical Characteristics Figure 9: Electrical System Specifications Symbol IDD tpower_on tprop M VPP AMTemp AM Parameter Current consumption Min Typ Maximum value derived at maximum I_H (Hall Bias Current) Power up time Propagation delay Magnetic sensitivity -40°C to 150°C 18 Version: AS5115 10 22 Max Unit 28 mA 1.275 ms 30 μs 60 mV / mT Version: AS5115A 20.72 28 35.28 Version: AS5115F 13.5 24 34.5 1.38 1.94 2.5 V Analog output voltage amplitude (peak to peak) AM tracking accuracy over temperature -40°C to 150°C -1 1 % Sin / Cos amplitude mismatch 25°C -2 2 % 1.47 1.5 1.53 Output DC offset voltage At no input signal; programmable OTP setting (see Device Communication / Programming) 2.45 2.5 2.55 -40°C to 150°C -50 50 μV/°C VSS + 0.25 VDD 0.5 V -1 1 mA 1000 pF Voffset1 Voffset2 DCoffdrift Conditions DC offset drift VOUT Analog output range IOUT Output current CLOAD Capacitive load ams Datasheet [v1-16] 2016-Nov-17 V Page 7 Document Feedback AS5115 − Electrical Characteristics Timing Characteristics Figure 10: Timing Characteristics Symbol Parameter Condition Min Typ Max Unit t1_3 Chip select to positive edge of DCLK 30 ns t2_3 Chip select to drive bus externally 0 ns t3 Setup time command bit Data valid to positive edge of DCLK 30 ns t4 Hold time command bit Data valid after positive edge of DCLK 15 ns t5 Float time positive edge of DCLK for last command bit to bus float t6 Bus driving time Positive edge of DCLK for last command bit to bus drive t7 Data valid time positive edge of DCLK to bus valid 1 ---------------------------------------------( 2 + 0 ) ⋅ f – DCLK t8 Hold time data bit Data valid after positive edge of DCLK 1 ---------------------------------------------( 2 + 0 ) ⋅ f – DCLK ns Hold time chip select positive edge DCLK to negative edge of chip select 1 ----------------------------------------------( 2 + 0 ) ⋅ f – DCLK ns t9_3 Page 8 Document Feedback 1 ---------------------------------------------( 2 + 0 ) ⋅ f – DCLK see Figure 18 and Figure 19 1 ---------------------------------------------( 2 + 0 ) ⋅ f – DCLK ns ns 1 ------------------------------------------------( 2 + 30 ) ⋅ f – DCLK ns ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Electrical Characteristics Symbol Parameter Condition Min Typ Max Unit 30 ns t10_3 Bus floating time negative edge of chip select to float bus t11 Setup time data bit at write access Data valid to positive edge of DCLK 30 ns t12 Hold time data bit at write access Data valid after positive edge of DCLK 15 ns t13_3 Bus floating time negative edge of chip select to float bus - 30 ns Note(s): 1. The digital interface will be reset during the low phase of the CS signal. ams Datasheet [v1-16] 2016-Nov-17 Page 9 Document Feedback AS5115 − Detailed Description Detailed Description Sleep Mode The target is to provide the possibility to reduce the total current consumption. No output signal will be provided when the IC is in sleep mode. Enabling or disabling sleep mode is done by sending the SLEEP or WAKEUP commands via. the SSI interface. Analog blocks are powered down with respect to fast wake up time. SSI Interface The setup for the device is handled by the digital interface. Each communication starts with the rising edge of the chip select signal. The synchronization between the internal free running analog clock oscillator and the external used digital clock source for the digital interface is done in a way that the digital clock frequency can vary in a wide range. Figure 11: SSI Interface Pin Description Port Symbol Chip select CS DCLK DCLK Bidirectional data input output DIO Page 10 Document Feedback Function Indicates the start of a new access cycle to the device. CS = LO → reset of the digital interface Clock source for the communication over the digital interface. Command and data information over one single line. The first bit of the command defines a read or write access. ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Detailed Description Figure 12: SSI Interface Parameter Description Symbol Parameter Clock frequency at normal operation f_DCLK Clock frequency at easy zap read write access f_EZ_RW f_EZ_PROG f_EZ_ARB Notes The nominal value for the clock frequency can be derived from a 10MHz oscillator source. Min Typ Max Unit No limit 5 6 MHz No limit 5 6 kHz 650 kHz 162.5 kHz Clock frequency at easy zap accessprogram OTP Correct access to the programmable zener diode block needs a strict timing – the zappulse is exact one period. The nominal value for the clock frequency can be derived from a 10MHz oscillator source. 200 Clock frequency at easy zap analog readback 20pF external load allowed. The nominal value for the clock frequency can be derived from a 10MHz oscillator source. No limit Parameter 156.3 Notes Interface General at Normal Mode Protocol: 5 command bit + 16 data input output Command 5-bit command: cmd ← bit Data 16-bit data: data ← bit Interface General at Extended Mode Protocol: 5 command bit + 46 data input output Command 5-bit command: cmd ← bit Data 34-bit data: data ← bit Interface Modes Normal read operation mode cmd = → 1 DCLK per data bit Extended read operation mode cmd = → 4 DCLK per data bit Normal write operation mode cmd = → 1 DCLK per data bit Extended write operation mode cmd = → 4 DCLK per data bit ams Datasheet [v1-16] 2016-Nov-17 Page 11 Document Feedback A S 5 1 1 5 − Detailed Description Device Communication / Programming Figure 13: Digital Interface at Normal Mode # Command Bin Mode 15 14 23 WRITE_CONFIG 10111 write go2sleep gen_rst 16 EN_PROG 10000 write 1 0 Page 12 Document Feedback 13 0 12 0 11 1 10 1 9 8 analog_ sig OB_bypassed 0 0 7 6 5 4 3 2 1 0 1 0 1 0 1 1 1 0 Name Functionality go2sleep Enter/leave low power mode (no output signals) gen_rst Generates global reset analog_sig Switches the channels to the test bus after the PGA OB_bypassed Disable and bypass output buffer for testing purpose ams Datasheet [v1-16] 2016-Nov-17 A S 5 1 1 5 − Detailed Description Figure 14: Digital Interface at Extended Mode Factory Settings # Command Bin Mode User Settings 31 WRITE_OTP 11111 xt write r r r r r r r r invert_ channel cm_ sin cm_ cos gain dc_ offset hall_ bias 25 PROG_OTP 11001 xt write r r r r r r r r invert_ channel cm_ sin cm_ cos gain dc_ offset hall_ bias 15 RD_OTP 01111 xt read r r r r r r r r invert_ channel cm_ sin cm_ cos gain dc_ offset hall_ bias 9 RD_OTP_ANA 01001 xt read Note(s): 1. “r” stands for reserved bits. They must not be modified, unless otherwise noted. 2. Send EN PROG (command 16) in normal mode before accessing the OTP in extended mode. 3. OTP assignment will be defined/updated. ams Datasheet [v1-16] 2016-Nov-17 Page 13 Document Feedback AS5115 − Detailed Description Figure 15: User Settings Description Name invert_channel Inverts Functionality SIN and COS channel before the PGA for inverted output function (0 → SIN/COS, 1 → SINN/COSN) cm_sin Common mode voltage output enabled at SINN / CM pin (0 → differential, 1 → common) cm_cos Common mode voltage output enabled at COSN / CM pin (0 → differential, 1 → common) gain dc_offset Hall_b PGA gain setting (influences overall magnetic sensitivity), 2-bit Output DC bias offset (0 → Voffset1=1.5V, 1 → Voffset2=2.5V) Hall bias setting (influences overall magnetic sensitivity), 6-bit Figure 16: Sensitivity Gain Settings - Relative Sensitivity in % The amplitude of the output signal is programmable via sensitivity (6bit) and/or gain (2bit) settings (see Figure 16). Page 14 Document Feedback ams Datasheet [v1-16] 2016-Nov-17 AS5115 − Detailed Description Figure 17: Sensitivity Gain Settings - Sensitivity [mV/mT] Waveform – Digital Interface at Normal Operation Mode Figure 18: Digital Interface at Normal Operation Mode CMD_PHASE DATA_PHASE DCLK t9_3 t1_3 CS t5 t2_3 DIO DIO CMD4 t3 t4 CMD3 CMD2 CMD1 CMD0 CMD t7 t6 t10_3 t8 D14 D15 D13 t11 ams Datasheet [v1-16] 2016-Nov-17 D15 D14 READ t13_3 t12 DIO D0 D13 D0 WRITE Page 15 Document Feedback Waveform – Digital Interface at Extended Mode In the extended mode, the digital interface needs four clocks for one data bit due to the internal structure. During this time, the device is able to handle internal signals for special access (e.g. the easy zap interface). Figure 19: Digital Interface at Extended Mode CMD_PHASE DATA_PHASE DCLK t1_3 t9_3 CS t7 t5 t2_3 DIO CMD4 CMD3 CMD2 CMD1 CMD CMD0 t3 t4 DIO t10_3 t8 t6 D45 t11 D44 t13_3 t12 DIO READ D0 D45 D44 WRITE D0 Waveform – Digital Interface at Analog Readback of the Zener Diodes To be sure that all Zener-Diodes are correctly burned, an analog readback mechanism is defined. Perform the ‘READ OTP ANA’ sequence according to the command table and measure the value of the diode at the end of each phase. Figure 20: Digital Interface at Analog Readback of Zener Diodes CMD_PHASE DATA_PHASE_EXTENDED EXT D45 EXT D44 EXT D1 OTP D44 OTP D43 OTP D0 EXT D0 DCLK CS DIO CMD4 CMD3 CMD2 CMD1 CMD0 OTP D45 PROG perform analog measurements at PROG Page 16 Document Feedback ams Datasheet [v1-16] 2016-Nov-17 A S 5 1 1 5 − Detailed Description Figure 21: Serial Bit Sequence (16-Bit Read/ Write) Write Command C4 C3 C2 C1 Read / Write Data C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 One Time Programming Content The AS5115 die has an integrated 46-bit OTP ROM (Easyzapp) for trimming and configuration purposes. The PROM can be programmed via. the serial interface. For irreversible programming, an external programming voltage at PROG pin is needed. For security reasons, the factory trim bits can be locked by a lock bit. As shown in the figure below, the OTP holds 46 bits. Bit number 44 and 45 are used for OTP testing purposes and ESD protection of the remaining cells. Figure 22: OTP User Settings Name Bit Count OTP Start OTP End Access Comments Hall_b 6 0 5 User Sets overall sensitivity dc_offset 1 6 6 User Output DC offset setting gain 2 7 8 User Output Buffer Gain setting Lock 1 13 13 ams Set in production test invert_channel 1 11 11 User Inverts SIN and COS channel before the PGA for inverted output function cm_sin 1 10 10 User Common mode voltage output enabled at SINN / CM pin cm_cos 1 9 9 User Common mode voltage output enabled at COSN / CM pin Remark: OTP assignment will be defined/updated. ams Datasheet [v1-16] 2016-Nov-17 Page 17 Document Feedback AS5115 − Detailed Description Analog Sin/Cos Outputs with External Interpolator Figure 23: Sine and Cosine Outputs for External Angle Calculation +5V VDD 100k VDD VDD PROG SINN/SINP/CM_SIN D A SINP/SINN Micro Controller AS5130 AS5115 100n COSN/COSP/CM_COS D A COSP/COSN VSS VSS VSS Note(s): 1. It is recommended to use a 100k pull-up resistance. 2. Default conditions for unused pins are: DCLK, CS, DIO, TC, A_TST, TBO, TB1, TB2, TB3 connect to VSS. The AS5115 provides analog sine and cosine outputs (SINP, COSP) of the Hall array front-end for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + μC, e.g. to compute the angle with a high resolution. The signal lines must be kept as short as possible. In the case of longer lines, they must be shielded in order to achieve best noise performance. Through the programming of one bit, you have the possibility to choose between the analog sine and cosine outputs (SINP, COSP) and their inverted signals (SINN, COSN). Furthermore, by programming the bits you can enable the common mode output signals of SIN and COS. Page 18 Document Feedback ams Datasheet [v1-16] 2016-Nov-17 OTP Programming and Verification Figure 24: OTP Programming Connection +5V VDD VDD VDD CS Output DCLK I/O Micro Controller AS5115 Output AS5130 DIO 100n 8.0 - 8.5V PROG + VSS 10μF 100n VSS - VSS Special Case Standard Case maximum parasitic cable inductance VSUPPLY C1 Vprog C2 L