AW9962EDNR

AW9962E Jan 2019 V1.2 High Efficiency, Support 0.3% PWM Dimming Boost WLED Driver GENERAL DESCRIPTION  Support 0.3% PWM dimming  PWM control input for CABC operation  1.1MHz Switching Frequency  38V Over-voltage Protection for up to 10 LEDs in Series The AW9962E is a white LED (WLED) driver with integrated boost converter. The boost converter runs at 1.1MHz fixed switching frequency, with an internal 40V, 2A switch FET, the AW9962E can drive one string (up to 10 LEDs) and parallel LED strings.  200mV Reference Voltage  2.7V to 5.5V Input Voltage Range  Over-current and Over-temperature Protection  Built-in Soft-start Limits Inrush Current  DFN 2mm X2mm X0.75mm-6L package n ti a l FEATURES e The full-scale WLED current can be set by the equation 200mV/RSET. RSET should be changed for parallel applications. fi d The current of WLED can also be set with duty cycle of PWM signal applied to the CTRL pin with 20kHz~100kHz. Mobile Phones  Portable Media Players  PDAs  GPS Receivers C  o n APPLICATIONS AW9962E integrates built-in soft-start function to minimize the power supply inrush current. AW9962E also integrates over-current protection, LED open protection and over temperature protection(OTP) to prevent chip from entering abnormal operating conditions. ic TYPICAL APPLICATION CIRCUIT 10μH * CIN2 optional 100nF ON/OFF DIMMING CONTROL 6 VIN 5 w in CIN1 10μF Schottky Diode L1 VIN 4 SW AW9962EDNR CTRL FB * COUT2 optional 33pF/50V COUT1 1μF/50V 1 RSET 10Ω GND a 3,7 Figure 1 www.awinic.com.cn Typical Application Circuit of AW9962E 1 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 PIN CONFIGURATION AND TOP MARK AW9962EDNR (Top View) 2 GND 3 7 GND VIN 5 CTRL 4 SW l NC 6 ti a 1 AL65 XXXX FB AW9962EDNR Marking (Top View) Pin Configuration and Top Mark fi d Figure 2 e n AL65—AW9962EDNR XXXX—Production Tracing Code PIN DEFINITION NAME DESCRIPTION 1 FB Feedback pin. Connect RSET from FB to GND. 2 NC No Connection 3 GND 4 SW 5 CTRL 6 VIN 7 GND o Ground. n No. Switching node. C Enable pin. It also can be used for PWM digital dimming. Power a w in ic Exposed pad should be soldered to PCB board and Connected to GND. www.awinic.com.cn 2 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 FUNCTIONAL BLOCK DIAGRAM 1 6 FB 4 VIN SW UVLO PWM Control and Gate Drive Soft-Start CTRL Current Amp + GND fi d 7 GND 3 FUNCTIONAL BLOCK DIAGRAM a w in ic C o n Figure 3 e Oscillator Ramp Generator l OVP n 5 Reference Control Thermal Shutdown ti a Input Logic Error Amp + www.awinic.com.cn 3 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 TYPICAL APPLICATION CIRCUITS Schottky Diode L1 VIN 10μH * CIN2 optional 100nF *optional COUT2 4 33pF/50V SW 6 VIN COUT1 1μF/50V ti a l CIN1 10μF AW9962EDNR 5 ON/OFF DIMMING CONTROL CTRL FB 1 RSET 5Ω n GND Typical Application of AW9962E L1 VIN 10μH * CIN2 optional 100nF *optional COUT2 4 SW 33pF/50V o 6 VIN C CIN1 10μF Schottky Diode n Figure 4 fi d e 3,7 COUT1 1μF/50V AW9962EDNR 5 CTRL FB GND 1 RSET 3.3Ω 3,7 Figure 5 Drive 18 White LEDs for Large Screen Display a w in ic ON/OFF DIMMING CONTROL Notice for Typical Application Circuits: 1：Recommended device for AW9962E: L: LQH3NPN100NM0 CIN1: Murata GRM188R61C106MA73 CIN2: Murata GRM155R61C104K COUT1: Murata GRM21BR71H105KA www.awinic.com.cn 4 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 COUT2: Murata GRM1555C1H330GA Schottky Diode: ONsemi MBR0540 2：CIN2 and COUT2 are recommended to use in parallel with the input capacitor and output capacitor to suppress high frequency noise. 3：Red lines are high current paths, reference to the section APPLICATION INFORMATION. l 4：The capacitors (CIN1, CIN2, COUT1, COUT2) should be placed as close to the pins of the IC as possible. ti a 5：Minimize trace lengths between the IC and the inductor, the Schottky diode and the output capacitor, keep these traces short, direct, and wide. a w in ic C o n fi d e n 6：Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize inter-plane coupling. www.awinic.com.cn 5 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 ORDERING INFORMATION Temperature Package Marking Moisture Sensitivity Level Environmental Information Delivery Form AW9962EDNR -40°C～85°C DFN 2mmx2mm-6L AL65 MSL1 ROHS+HF 3000 units/ Tape and Reel ti a l Part Number AW9962E R: Tape & Reel DN:DFN PARAMETERS o Supply voltage range VIN(NOTE 2) n ABSOLUTE MAXIMUM RATINGS(NOTE1) fi d Figure 6 Package Information e Package Type n Shipping RANGE -0.3V to 6V -0.3V to 6V Voltage on SW (NOTE 2) -0.3V to 40V C Voltage on FB,CTRL (NOTE 2) Junction-to-ambient thermal resistance θJA 120°C/W Operating free-air temperature range -40°C to 85°C ic Operating Junction temperature TJ -40°C to 150°C Storage temperature TSTG -65°C to 150°C Lead Temperature (Soldering 10 Seconds) 260°C in ESD(NOTE 3) ALL PINS HBM (human body model) (NOTE 4) ±2kV ALL PINS CDM (charge device model) (NOTE 5) ±1.5kV w Latch-up(NOTE 6) +IT：200mA -IT：-200mA a Latch-up current maximum rating per JEDEC standard NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages to the device. In spite of the limits above, functional operation conditions of the device should within the ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for prolonged periods may affect device reliability. NOTE2: All voltage values are with respect to network ground terminal. www.awinic.com.cn 6 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 NOTE3: This integrated circuit can be damaged by ESD if you don’t pay attention to ESD protection. AWINIC recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method: MIL-STD-883H Method 3015.8. l NOTE5: Test Condition: JEDEC EIA/JESD22-C101E. a w in ic C o n fi d e n ti a NOTE6: Test Condition: JEDEC STANDARD NO.78D NOVEMBER 2011. www.awinic.com.cn 7 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 ELECTRICAL CHARACTERISTICS Test Condition: TA = 25°C, VIN = 3.6V, VCTRL = VIN (Unless otherwise specified). PARAMETER TEST CONDITION MIN TYP MAX UNIT 5.5 V 2.39 V VIN Input voltage range 2.7 VUVLO Under-voltage lockout threshold VHYS Under-voltage lockout hysteresis ISD Shutdown current VCTRL = GND, VIN=4.2V 0.1 IQ Operating quiescent current VFB = 1V 250 2.2 DPWM PWM dimming duty cycle tMIN_ON Minimum on pulse width Voltage feedback regulation voltage VREF_PWM Voltage feedback regulation voltage under brightness control BOOST CONVERTER 0.3 100 % ic Oscillator frequency DMAX Maximum duty cycle ns 200 205 mV 1.575 2.25 2.925 mV 0.6 VIN = 3.6V 90 mV 0.1 1 A 0.4 0.7 Ω 0.7 Ω VIN = 3.0V in fS 50 194 PWM duty cycle = 0.3% N-channel MOSFET on-resistance RDS(on) A kHz C Voltage feedback input bias current IFB PWM duty cycle = 1% A 100 o VREF n VOLTAGE AND CURRENT CONTROL 1 10 fi d Frequency of PWM dimming e PWM DIMMING CONTROL fPWM mV n 100 ti a VIN falling l SUPPLY VOLTAGE AND CURRENT 1100 kHz 93 % 2 A OCP AND OVP w ILIM N-channel MOSFET current limit Open LED overvoltage protection threshold tREF VREF filter time constant a VOVP Measured on the SW pin 36 38 40 V s 480 CTRL INTERFACE VCTRL_H CTRL logic high voltage VIN = 2.7V to 5.5V VCTRL_L CTRL logic low voltage VIN = 2.7V to 5.5V RCTRL CTRL pull down resistor tOFF CTRL pulse width to shutdown www.awinic.com.cn 1.4 V 0.4 600 8 CTRL high to low 2.5 V kΩ ms Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 PARAMETER TEST CONDITION MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal shutdown threshold 165 °C THYS Thermal shutdown threshold hysteresis 15 °C a w in ic C o n fi d e n ti a l TOTP www.awinic.com.cn 9 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 TYPICAL CHARACTERISTICS Table 1 TABLE OF FIGURES FIGURE No. VIN=3.6V,4,6,8,10LEDs, L=10 FIGURE 7 Efficiency 2 VIN=4.2/3.6/3.0V,10LEDs, L=10 FIGURE 8 Efficiency 3 VIN=2.5~5.5V,1P10S, 2P8S,3P6S LEDs, L=10 FIGURE 9 PWM dimming linearity PWM Freq=20kHz FIGURE 10 Feedback voltage line regulation VIN=2.5~5.5V FIGURE 11 Open LED protection VIN=3.6V,10LEDs,L=10 Soft-start waveform VIN=3.6V,10LEDs,L=10 Switching waveform VIN=3.6V,10LEDs,L=10 n e FIGURE 12 FIGURE 13 FIGURE 14 fi d 100 n 100 o C 80 VIN=3.6V 70 Efficiency (%) 90 90 Efficiency (%) ti a Efficiency 1 l INDEX 80 2P10S 70 2P4S 2P6S 50 0 ic 60 10 20 VIN=3V 60 VIN=3.6V 2P8S VIN=4.2V 2P10S 30 50 40 Output Current (mA) 0 10 20 30 40 in Output Current (mA) Fig8. EFFICIENCY vs OUTPUT CURRENT a w Fig7. EFFICIENCY vs OUTPUT CURRENT www.awinic.com.cn 10 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 200 100 160 70 1P10S 2P8S 3P6S 3 3.5 4 4.5 5 40 0 60 2.5 80 l 80 120 0 5.5 20 Input Voltage (V) 40 60 80 100 PWM Duty Cycle (%) Fig10. FB vs PWM DUTY CYCLE n Fig9. EFFICIENCY vs INPUT VOLTAGE 210 e VOUT 205 DC Coupled 10.0V/div fi d 200 195 190 185 3 3.5 4 4.5 Input Voltage (V) 5 5.5 SW DC Coupled 10.0V/div IL DC Coupled 200mA/div o 2.5 n FB Voltage (mV) ti a FB Voltage (mV) Efficiency (%) 90 Time (200μs/div) Fig12. OPEN LED PROTECTION C Fig11. FB vs INPUT VOLTAGE ic IL DC Coupled 100mA/div in CTRL DC Coupled 1.0V/div w VOUT DC Coupled 10.0V/div VOUT AC Coupled 100mV/div a IL DC Coupled 200mA/div Time (1μs/div) Time (2ms/div) Fig 13. Fig 14. SOFT-START WAVEFORM www.awinic.com.cn 11 SWITCHING WAVEFORM Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 DETAILED FUNCTIONAL DESCRIPTION The AW9962E is a white LED backlight driver IC, which operates in pulse width modulation (PWM) mode with 1.1MHz constant switching frequency and integrates 40V/2.0A switch FET. The duty cycle of boost regulator is set by the error amplifier output and the inductor current signal applied to the PWM comparator. When duty cycle exceeds 50%, slope compensation is added to the current signal for current loop stableness . l SOFT START ti a When the device is enabled, the error amplifier output ramps up to the target voltage in a specific time. This ensures that the output voltage rises slowly to reduce the input inrush current. OPEN LED OVER-VOLTAGE PROTECTION e n The over-voltage protection function monitors the output voltage via the SW pin voltage. The OVP threshold voltage is 38V typically. Once the LED is open, the output voltage reaches the OVP threshold, the driver will be shut down. During detect process, output voltage will keep stepping up for 8 clock cycles. fi d SHUTDOWN The CTRL pin is used for enable device and PWM dimming. When the CTRL voltage is logic low for more than 2.5ms, the driver will be shut down. UNDER-VOLTAGE LOCKOUT o n When the input voltage is lower than the UVLO threshold (2.2V typ.), the driver will turn off. If the input voltage rises by under-voltage lockout hysteresis, the IC restarts. CURRENT PROGRAM C The LED current is programmed externally using a resistor in series with the LED string. The value of the R SET can be calculated by the following equation: ic ILED = Where: VFB RSET (1) in ILED = output current of LEDs VFB = regulated voltage of FB w RSET = current sense resistor PWM BRIGHTNESS DIMMING a When the CTRL pin is constantly high, the FB voltage is regulated to 200mV typically. However, the CTRL pin allows a PWM signal to reduce this regulation voltage, it achieves LED brightness dimming. The relationship between the duty cycle and the FB voltage is given by the following equation: VFB = Duty x 200mV (2) Where: Duty = duty cycle of the PWM signal 200mV = internal reference voltage www.awinic.com.cn 12 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 l As shown in the FIGURE 15, the IC chops up the internal 200mV reference voltage at the duty cycle of the PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is used for brightness dimming, only the WLED DC current is modulated, which is often referred as analog dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog dimming, AW9962E regulation voltage is independent of the PWM logic voltage level which often has large variations. ti a Reference 200mV CTRL n EA out e Err or Amplifier Figure15 fi d FB Block Diagram of Programmable FB Voltage Using PWM Signal n THERMAL SHUTDOWN a w in ic C o An internal thermal shutdown turns off the device when the typical junction temperature exceed 165°C. The device will restart when the junction temperature decreases by 15°C. www.awinic.com.cn 13 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 APPLICATION INFORMATION INDUCTOR SELECTION The inductor DC current can be calculated as: IIN _ DC  VOUT  Iout VIN  η (3) L × Fs × ( VOUT 1 1 1 + ) + VF - VIN VIN IP  IIN_DC  fi d Therefore, the peak current IP seen by the inductor is calculated as (4) e IPP = n The inductor current peak to peak ripple can be calculated as IPP 2 ti a l Because the selection of inductor affects power supply’s steady state operation, transient behavior, loop stability and the boost converter efficiency, the inductor is one of the most important components in switching power regulator design. There are three important inductor specifications, inductor value, DC resistance and saturation current. (5) C o n The inductor saturation current rating should be considered to cover the inductor peak current. Smaller size and better efficiency are the major concerns for portable devices. The inductor should have low core loss at 1100kHz and low DCR for better efficiency. For these reasons, a 4.7μH to 10μH inductor value range is recommended. A 10μH inductor optimized the efficiency for most application while maintaining low inductor peak to peak ripple. TABLE 2 lists the recommended inductor for the AW9962E. When recommending inductor value, the factory has considered –40% and +20% tolerance from its nominal value. Table 2 Recommended Inductors for AW9962E DCR Max (Ω) Saturation Current (mA) Size (L x W x H mm) Vendor MRSC252A10-100M-N 10 0.5 900 2.5 x 2 x 1 Chilisin LQH3NPN100NM0 10 0.3 750 3 x 3 x 1.5 Murata CDH3809/SLD 10 0.3 570 4 x 4 x 1.0 Sumida LPS4018-472ML 4.7 0.125 1900 4 x 4 x 1.8 Coilcraft ic L (μH) w in Part Number a SCHOTTKY DIODE SELECTION To optimize the efficiency, a high-speed and low reverse-recovery current Schottky diode are recommended. Make sure the diode’s average and peak current ratings exceed the output average LED current and the peak inductor current. In addition, the diode’s break-down voltage rating must exceed the maximum voltage across the diode. Usually, unexpected high-frequency voltage spikes can be seen across the diode when the diode turns off. Therefore, leaving some voltage rating margin is always needed to guarantee normal long-term operation when selecting a diode. The MBR0540 and the NSR05F40 are recommended for AW9962E. www.awinic.com.cn 14 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 INPUT AND OUTPUT CAPCCITORS SELECTION The output capacitor keeps the output voltage ripple small and ensures feedback loop stability. This ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming ESR of a capacitor is zero, the minimum capacitance needed for a given ripple can be calculated by ： COUT  ( VOUT - VIN )  Iout VOUT  FS  Vripple (6) Vripple _ ESR  Iout  RESR ti a l Where, Vripple represents peak-to-peak output ripple. The additional output ripple caused by ESR can be calculated as: (7) Vripple_ESR can be neglected for ceramic capacitors due to its low ESR, but must be considered if tantalum or electrolytic capacitors are used. e n Note that the ceramic capacitance is dependent on the voltage rating. With a DC bias voltage, the capacitance can lose as much as 50% of its value at its rated voltage rating. Leave a large enough voltage rating margin when selecting the component. Therefore, leave enough margin on the voltage rating to ensure adequate capacitance at the required output voltage. fi d An X5R or X7R capacitor of 10μF is recommended for input side. The output requires a X5R or X7R capacitor in the range of 0.47μF to 4.7μF. A 100nF capacitor and a 33 pF capacitor are recommended to use in parallel with the input capacitor and the output capacitor to suppress high frequency noise. The output capacitor affects the loop stability of the boost regulator. If the output capacitor is below the range, the boost regulator can potentially become unstable. o n Note that capacitor degradation increases the ripple much. Select the capacitor with 50V rated voltage to reduce the degradation at the output voltage. If the output ripple is too large, change a capacitor with less degradation effect or with higher rated voltage could be helpful. C POWER DISSIPATION ic The maximum IC junction temperature should not be exceed 125°C under normal operating conditions. This restriction limits the power dissipation of the AW9962E. It is recommended to keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined by using the following equation: PD(max)  TJ max - TA θ ja in Where, TJmax is the Maximum Junction Temperature, TA is the maximum ambient temperature for the application. θja is the thermal resistance junction-to-ambient given in Power Dissipation Table. a w The θja of the DFN package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered directly to the analog ground on the PCB. After soldering, the PCB can be used as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane, or alternatively, can be attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). Using thermal vias underneath the thermal pad as illustrated in the layout example. www.awinic.com.cn 15 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 PCB LAYOUT CONSIDERATION ti a l PCB layout is an important design step for those high frequency, high current switching power regulators in order to minimize noise and keep loop stable. To reduce switching losses, it is better to make the SW pin rise and fall times as short as possible. Minimizing the length and area of all traces connected to the SW pin and using a ground plane under the switching regulator are strongly recommended to minimize inter-plane coupling. The input capacitor should be very close to the IC to get the best decoupling. The path of the inductor, schottky diode and output capacitor should be kept as short as possible to minimize noise and ringing. FB is a sensitive node and it should be kept separate from the SW pin in the PCB layout. a w in ic C o n fi d e n Connect the exposed paddle to the PCB ground plane using at least two vias. The input and the output bypass capacitors should be placed as close to the IC as possible. Minimize trace lengths between the IC and the inductor, the diode and the output capacitor; keep these traces short, direct, and wide. www.awinic.com.cn 16 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 TAPE AND REEL INFORMATION TAPE DIMENSIONS REEL DIMENSIONS P1 P0 P2 K0 ti a B0 D1 Cavity l W A0 e n A0：Dimension designed to accommodate the component width B0：Dimension designed to accommodate the component length K0：Dimension designed to accommodate the component thickness W：Overall width of the carrier tape P0：Pitch between successive cavity centers and sprocket hole P1：Pitch between successive cavity centers P2：Pitch between sprocket hole D0：Reel width D1：Reel diameter fi d D0 Q2 Q3 Q4 Q1 Q2 Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 Q3 Q4 C Q1 o n QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed a w in ic Pocket Quadrants www.awinic.com.cn 17 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 PACKAGE DESCRIPTION ti a l 2.0±0.1 e n 2.0±0.1 fi d TOP VIEW n SIDE VIEW 6X(0.25±0.05) SYMM ℄ 3 C 6X(0.3±0.05) o 1.0±0.1 0.75±0.05 0.00~0.05 4 0.65BSC 1.6±0.1 1 6 SYMM ℄ 0.25±0.1 BOTTOM VIEW 0.2REF SIDE VIEW Dimensions are all in millimeters a w in ic 0.2REF www.awinic.com.cn 18 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 LAND PATTERN DATA 4X0.65 6 4 SYMM 1.00 1.50 ℄ e n Via layout may vary depending on layout constraints ti a l 1.60 6X0.35 ℄ SOLDER MASK OPENING C METAL 0.05 MIN All AROUND o 0.05 MAX All AROUND 6X0.30 n SYMM fi d 3 1 METAL UNDER SOLDER MASK SOLDER MASK DEFINED ic NON SOLDER MASK DEFINED SOLDER MASK OPENING a w in Dimensions are all in millimeters www.awinic.com.cn 19 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 REVISION HISTORY Date Change Record V1.0 Nov 2017 Datasheet V1.0 Released V1.1 Jun 2018 Correct some mistake of description. V1.2 Jan 2019 Correct some mistake of description. a w in ic C o n fi d e n ti a l Vision www.awinic.com.cn 20 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD AW9962E Jan 2019 V1.2 DISCLAIMER Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. ti a l AWINIC Technology reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. Customers shall obtain the latest relevant information before placing orders and shall verify that such information is current and complete. This document supersedes and replaces all information supplied prior to the publication hereof. e n AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an AWINIC Technology product can reasonably be expected to result in personal injury, death or severe property or environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC Technology products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. fi d Applications that are described herein for any of these products are for illustrative purposes only. AWINIC Technology makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. All products are sold subject to the general terms and conditions of commercial sale supplied at the time of order acknowledgement. o n Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. C Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. a w in ic Resale of AWINIC components or services with statements different from or beyond the parameters stated by AWINIC for that component or service voids all express and any implied warranties for the associated AWINIC component or service and is an unfair and deceptive business practice. AWINIC is not responsible or liable for any such statements. www.awinic.com.cn 21 Copyright © 2017 SHANGHAI AWINIC TECHNOLOGY CO., LTD