74HC165M/TR

74HC165 8-BIT PARALLEL-LOAD SHIFT REGISTERS FEATURES DESCRIPTION • • • • • • • • • • The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. 1 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V Low Input Current of 1 μA Max Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a lowto-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. SN54HC165 . . . FK PACKAGE (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 7 8 11 10 9 VCC CLK INH D C B A SER QH E F NC G H 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D C NC B A QH GND NC QH SER SH/LD CLK E F G H QH GND CLK SH/LD NC VCC CLK INH SN54HC165 . . . J or W PACKAGE SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection http://www.hgsemi.com.cn 1 2018 AUG 74HC165 FUNCTION TABLE INPUTS SH/LD (1) CLK CLK INH FUNCTION L X X Parallel load H H X No change H X H No change H L ↑ Shift (1) H ↑ L Shift (1) Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register. LOGIC DIAGRAM (POSITIVE LOGIC) A SH/LD CLK INH CLK SER 1 B 11 C 12 D 13 E 14 F G 4 3 H 5 6 9 15 QH 2 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R 7 Pin numbers shown are for theD, DB, J, N, NS, PW, and W packages. http://www.hgsemi.com.cn 2 2018 AUG QH 74HC165 TYPICAL SHIFT, LOAD, AND INHIBIT SEQUENCE CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load http://www.hgsemi.com.cn 3 2018 AUG 74HC165 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNITS −0.5 to 7 V ±20 mA VCC Supply voltage range IIK Input clamp current VI < 0 or VI > VCC (2) IOK Output clamp current VO < 0 or VO > VCC (2) ±20 mA IO Continuous output current VO = 0 to VCC ±25 mA ±50 mA D package 73 °C/W DB Package 82 °C/W N package 67 °C/W NS package 64 °C/W 108 °C/W –65 to 150 °C Continuous current through V θJA (3) CC or GND Package thermal impedance PW package Tstg (1) (2) (3) Storage temperature range Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range (unless otherwise noted) SN54HC165 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V NOM MAX 2 5 6 Low level input voltage MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 2 V VIL SN74HC165 MIN VCC = 4.5 V VCC = 6 V UNIT V V 0.5 0.5 1.35 1.35 1.8 1.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 2 V Δt/Δv (2) TA (1) (2) Input transition rise/fall time 1000 1000 VCC = 4.5 V 500 500 VCC = 6 V 400 400 −55 Operating free-air temperature 125 −40 125 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. http://www.hgsemi.com.cn 4 2018 AUG 74HC165 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 μA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA VOL ICC VI = VCC or 0, MIN TYP 2V 1.9 1.998 1.9 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 4.4 6V 5.9 5.999 5.9 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 3.7 6V 5.48 5.2 5.34 5.8 MIN MAX MIN MAX Recommended SN74HC165 –40°C TO 125°C MIN UNIT MAX V 5.2 0.002 0.1 0.1 0.1 0.1 IOL = 20 μA 4.5 V 0.001 0.1 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.1 IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33 0.4 6V 0.15 0.26 0.4 0.33 0.4 6V ±0.1 ±100 ±1000 ±1000 ±1000 nA 8 160 80 160 μA 10 10 10 10 pF IOL = 5.2 mA VI = VCC or 0 MAX SN74HC165 –40°C TO 85°C 2V VI = VIH or VIL II SN54HC165 –55°C TO 125°C TA = 25°C VCC IO = 0 Ci http://www.hgsemi.com.cn 6V 2 V to 6 V 3 5 V 2018 AUG 74HC165 TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) VCC MIN fclock Clock frequency SH/LD low tw Pulse duration CLK high or low SH/LD high before CLK↑ SER before CLK↑ tsu Setup time CLK INH low before CLK↑ CLK INH high before CLK↑ Data before SH/LD↓ SER data after CLK↑ th Hold time PAR data after SH/LD↓ http://www.hgsemi.com.cn SN54HC165 –55°C TO 125°C TA = 25°C MAX MIN MAX Recommended SN74HC165 –40°C TO 125°C SN74HC165 –40°C TO 85°C MIN MAX MIN MAX 2V 6 4.2 5 4.2 4.5 V 31 21 25 21 6V 36 25 29 25 2V 80 120 100 120 4.5 V 16 24 20 24 6V 14 20 17 20 2V 80 120 100 120 4.5 V 16 24 20 24 6V 14 20 17 20 2V 80 120 100 120 4.5 V 16 24 20 24 6V 14 20 17 20 2V 40 60 50 60 4.5 V 8 12 10 12 6V 7 10 9 10 2V 100 150 125 150 4.5 V 20 30 25 30 6V 17 25 21 25 2V 40 60 50 60 4.5 V 8 12 10 12 6V 7 10 9 10 2V 100 150 125 150 4.5 V 20 30 25 30 6V 17 26 21 26 2V 5 5 5 5 4.5 V 5 5 5 5 6V 5 5 5 5 2V 5 5 5 5 4.5 V 5 5 5 5 6V 5 5 5 5 6 UNIT MHz ns ns ns 2018 AUG 74HC165 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SH/LD tpd CLK H tt QH or QH QH or QH QH or QH Any SN54HC165 –55°C TO 125°C TA = 25°C VCC MAX MIN SN74HC165 –40°C TO 85°C MAX MIN MAX Recommended SN74HC165 –40°C TO 125°C MIN TYP 2V 6 13 4.2 5 MIN 4.2 4.5 V 31 50 21 25 21 6V 36 62 25 29 25 UNIT MAX MHz 2V 80 150 225 190 225 4.5 V 20 30 45 38 45 6V 16 26 38 32 38 2V 75 150 225 190 225 4.5 V 15 30 45 38 45 6V 13 26 38 32 38 2V 75 150 225 190 225 4.5 V 15 30 45 38 45 6V 13 26 38 32 38 2V 38 75 110 95 110 4.5 V 8 15 22 19 22 6V 6 13 19 16 19 ns ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance http://www.hgsemi.com.cn No load 7 TYP 75 UNIT pF 2018 AUG 74HC165 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS VCC Input 50% 50% 0V tPLH VCC Reference Input In-Phase Output 50% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% tPLH 50% 10% tf tf VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms http://www.hgsemi.com.cn 8 2018 AUG