NY8A054ES8

NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Table of Contents 1. 概述 .............................................................................................................................................5 1.1 功能 .................................................................................................................................................5 1.2 NY8A054E 與 NY8A054D 的主要差異...........................................................................................7 1. General Description.................................................................................................................8 to r 1.1 Features ........................................................................................................................................ 8 1.2 Major Differences Table Between NY8A054E and NY8A054D .......................................................10 1.2 Block Diagram ...............................................................................................................................11 uc 1.3 Pin Assignment ..............................................................................................................................11 nd 1.4 Pin Description...............................................................................................................................12 2. Memory Organization ..............................................................................................................13 co 2.1 Program Memory ...........................................................................................................................13 2.2 Data Memory .................................................................................................................................14 mi 3. Function Description...............................................................................................................18 3.1.1 Se 3.1 R-page Special Function Register ..................................................................................................18 INDF (Indirect Addressing Register).................................................................................................... 1 8 TMR0 (Timer0 Register)...................................................................................................................... 18 3.1.3 PCL (Low Byte of PC[10:0]) ............................................................................................................... 18 3.1.4 STATUS (Status Register) ................................................................................................................... 19 3.1.5 FSR (Register File Selection Register) ............................................................................................... 19 3.1.6 PortA (PortA Data Register) ................................................................................................................ 20 JS MI CR O 3.1.2 3.1.7 PortB (PortB Data Register) ................................................................................................................ 20 3.1.8 PCON (Power Control Register) ......................................................................................................... 20 3.1.9 BWUCON (PortB Wake-up Control Register) ..................................................................................... 21 3.1.10 PCHBUF (High Byte of PC)................................................................................................................. 21 3.1.11 ABPLCON (PortA/PortB Pull-Low Resistor Control Register)............................................................. 21 3.1.12 BPHCON (PortB Pull-High Resistor Control Register)........................................................................ 22 3.1.13 INTE (Interrupt Enable Register) ......................................................................................................... 22 3.1.14 INTF (Interrupt Flag Register) ............................................................................................................. 23 3.1.15 AWUCON (PortA Wake-up Control Register) ..................................................................................... 23 3.1.16 INTEDG (Interrupt Edge Register) ...................................................................................................... 24 3.1.17 TMRH (Timer High Byte Register) ...................................................................................................... 24 www.jsmsemi.com 第１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.18 RFC (RFC Register) ............................................................................................................................ 24 3.1.19 TM34RH (Timer3 High Byte Register) ................................................................................................ 25 3.1.20 INTE2 (Interrupt Enable and Flag 2nd. Register)................................................................................ 25 3.2 T0MD Register.............................................................................................................................26 3.3 F-page Special Function Register ..................................................................................................27 IOSTA (PortA I/O Control Register) ..................................................................................................... 27 3.3.2 IOSTB (PortB I/O Control Register) .................................................................................................... 27 3.3.3 APHCON (PortA Pull-High Resistor Control Register)........................................................................ 27 to r 3.3.1 PS0CV (Prescaler0 Counter Value Register)...................................................................................... 28 3.3.5 BODCON (PortB Open-Drain Control Register).................................................................................. 28 3.3.6 CMPCR (Comparator voltage select Control Register)....................................................................... 28 3.3.7 PCON1 (Power Control Register1) ..................................................................................................... 29 uc 3.3.4 nd 3.4 S-page Special Function Register ..................................................................................................30 TMR1 (Timer1 Register)...................................................................................................................... 30 3.4.2 T1CR1 (Timer1 Control Register1) ..................................................................................................... 30 3.4.3 T1CR2 (Timer1 Control Register2) ..................................................................................................... 31 3.4.4 PWM1DUTY (PWM1 Duty Register) ................................................................................................... 32 3.4.5 PS1CV (Prescaler1 Counter Value Register)...................................................................................... 32 3.4.6 BZ1CR (Buzzer1 Control Register) ..................................................................................................... 32 3.4.7 IRCR (IR Control Register).................................................................................................................. 33 3.4.8 TBHP (Table Access High Byte Address Pointer Register)................................................................. 34 3.4.9 TBHD (Table Access High Byte Data Register) .................................................................................. 34 CR O Se mi co 3.4.1 3.4.10 P2CR1 (PWM2 Control Register1)...................................................................................................... 34 3.4.11 PWM2DUTY (PWM2 Duty Register) ................................................................................................... 35 JS MI 3.4.12 OSCCR (Oscillation Control Register) ................................................................................................ 35 3.4.13 TMR3 (Timer3 Register)...................................................................................................................... 35 3.4.14 T3CR1 (Timer3 Control Register1) ..................................................................................................... 36 3.4.15 T3CR2 (Timer3 Control Register2) ..................................................................................................... 37 3.4.16 PWM3DUTY (PWM3 Duty Register) ................................................................................................... 37 3.4.17 PS3CV (Prescaler3 Counter Value Register)...................................................................................... 38 3.4.18 P4CR1 (PWM4 Control Register1)..................................................................................................... 38 3.4.19 PWM4DUTY (PWM4 Duty Register) .................................................................................................. 38 3.4.20 P5CR1 (PWM5 Control Register1)..................................................................................................... 38 3.4.21 PWM5DUTY (PWM5 Duty Register) ................................................................................................... 39 3.4.22 PWM5RH (PWM5 High Byte Register) ............................................................................................... 39 www.jsmsemi.com 第２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.5 I/O Port .........................................................................................................................................39 3.5.1 Block Diagram of IO Pins .................................................................................................................... 41 3.6 Timer0............................................................................................................................................51 3.7 Timer1 / PWM1 / Buzzer1 ..............................................................................................................52 3.8 PWM2............................................................................................................................................55 3.9 Timer3 / PWM3 ..............................................................................................................................55 to r 3.10 PWM4...........................................................................................................................................58 3.11 PWM5...........................................................................................................................................58 3.12 RFC Mode ....................................................................................................................................59 uc 3.13 IR Carrier .......................................................................................................................................60 3.14 Low Voltage Detector (LVD) ...........................................................................................................60 Comparator Reference Voltage (Vref) ...................................................................................63 co 3.15.1 nd 3.15 Voltage Comparator .......................................................................................................................62 3.16 Watch-Dog Timer (WDT)................................................................................................................64 mi 3.17 Interrupt .........................................................................................................................................65 3.17.1 Timer0 Overflow Interrupt.................................................................................................................... 66 Se 3.17.2 Timer1 Underflow Interrupt.................................................................................................................. 66 3.17.3 Timer3 Underflow Interrupt.................................................................................................................. 66 3.17.4 WDT Timeout Interrupt ........................................................................................................................ 66 CR O 3.17.5 PA/PB Input Change Interrupt ............................................................................................................. 66 3.17.6 External 0 Interrupt .............................................................................................................................. 66 3.17.7 External 1 Interrupt .............................................................................................................................. 67 JS MI 3.17.8 LVD Interrupt ....................................................................................................................................... 67 3.18 Oscillation Configuration ................................................................................................................67 3.19 Operating Mode .............................................................................................................................69 3.19.1 Normal Mode ....................................................................................................................................... 71 3.19.2 Slow Mode ........................................................................................................................................... 71 3.19.3 Standby Mode...................................................................................................................................... 72 3.19.4 Halt Mode ............................................................................................................................................ 72 3.19.5 Wake-up Stable Time .......................................................................................................................... 73 3.19.6 Summary of Operating Mode .............................................................................................................. 73 3.20 Reset Process ...............................................................................................................................74 4. Instruction Set ........................................................................................................................76 www.jsmsemi.com 第３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 5. Configuration Words ...............................................................................................................92 6. Electrical Characteristics........................................................................................................93 6.1 Absolute Maximum Rating .............................................................................................................93 6.2 DC Characteristics .........................................................................................................................93 6.3 OSC Characteristics ......................................................................................................................95 6.4 Comparator / LVD Characteristics ..................................................................................................95 to r 6.5 Characteristic Graph ......................................................................................................................95 Frequency vs. VDD of I_HRC ............................................................................................................... 95 6.5.2 Frequency vs. Temperature of I_HRC................................................................................................. 96 6.5.3 Frequency vs. VDD of I_LRC ................................................................................................................ 96 6.5.4 Frequency vs. Temperature of I_LRC .................................................................................................96 uc 6.5.1 nd 6.6 Recommended Operating Voltage .................................................................................................97 co 6.7 LVR vs. Temperature......................................................................................................................97 7. Die Pad Diagram .....................................................................................................................98 mi 8. Package Dimension................................................................................................................99 8.1 8-Pin Plastic SOP (150 mil)..........................................................................................................99 Se 8.2 16-Pin Plastic SOP (150 mil)........................................................................................................99 JS MI CR O 9. Ordering Information............................................................................................................100 www.jsmsemi.com 第４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 1. 概述 NY8A054E 是以EPROM作為記憶體的 8 位元微控制器，專為多組PWM的應用設計。例如燈控，遙控車應用。採用 CMOS製程並同時提供客戶低成本、高性能、及高性價比等顯著優勢。NY8A054E 核心建立在RISC精簡指令集架構 可以很容易地做編輯和控制，共有 55 條指令。除了少數指令需要 2 個時序，大多數指令都是 1 個時序即能完成，可 以讓使用者輕鬆地以程式控制完成不同的應用。因此非常適合各種中低記憶容量但又複雜的應用。 在I/O的資源方面，NY8A054E 有 14 根彈性的雙向I/O腳，每個I/O腳都有單獨的暫存器控制為輸入或輸出腳。而且每 to r 一個I/O腳位都有附加的程式控制功能如上拉或下拉電阻或開漏極(Open-Drain) 輸出。此外針對紅外線搖控的產品方 面，NY8A054E內建了可選擇頻率的紅外載波發射口。 NY8A054E 有三組計時器，可用系統頻率當作一般的計時的應用或者從外部訊號觸發來計數。另外NY8A054E 提供 uc 5 組 10 位元解析度的PWM輸出，1 組蜂鳴器輸出可用來驅動馬達、LED、或蜂鳴器等等。 NY8A054E 採用雙時鐘機制，高速振盪或者低速振盪都可以分別選擇內部RC振盪或外部Crystal輸入。在雙時鐘機制 nd 下，NY8A054E 可選擇多種工作模式如正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby mode) 與睡 眠模式(Halt mode)可節省電力消耗延長電池壽命。並且微控制器在使用內部RC高速振盪時，低速振盪可以同時使用 co 外部精準的Crystal計時。可以維持高速處理同時又能精準計算真實時間。 在省電的模式下如待機模式(Standby mode) 與睡眠模式(Halt mode)中，有多種事件可以觸發中斷喚醒NY8A054E  寬廣的工作電壓： Se 功能 2.0V ~ 5.5V @系統頻率 ≦8MHz。  2.2V ~ 5.5V @系統頻率 > 8MHz。 CR O   寬廣的工作温度：-40°C ~ 85°C。  2Kx14 bits EPROM。 JS MI 1.1 mi 進入正常操作模式(Normal) 或 慢速模式(Slow mode) 來處理突發事件。  128 bytes SRAM。  14 根可分別單獨控制輸入輸出方向的I/O腳(GPIO)、PA[7:0]、PB[5:0]。  PA[5:0] 及 PB[3:0] 可選擇輸入時使用內建下拉電阻。  PA[7: 0] 及 PB[5:0] 可選擇輸入時使用上拉電阻。  PB[5:0] 可選擇開漏極輸出(Open-Drain)。  PA[5] 可選擇當作輸入或開漏極輸出(Open-Drain)。  8 層程式堆棧(Stack)。  存取資料有直接或間接定址模式。  一組 8 位元上數計時器(Timer0)包含可程式化的頻率預除線路。 www.jsmsemi.com 第５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU  二組 10 位元下數計時器(Timer1, 3)可選重複載入或連續下數計時。  五個 10 位元脈衝寬度調變(PWM1, 2, 3, 4, 5)，PWM1/2 共用Timer1; PWM3/4/5 共用Timer3。  一個蜂鳴器輸出(BZ1)。  38/57KHz紅外線載波頻率可供選擇，同時載波之極性也可以根據數據作選擇。  內建準確的低電壓偵測電路(LVD)。  內建準確的電壓比較器(Voltage Comparator)。 to r  內建上電復位電路(POR)。  內建低壓復位功能(LVR)。  內建電阻頻率轉換器(RFC)功能。  高速振盪：E_HXT (超過 6MHz外部高速石英振盪) co E_XT (455K~6MHz外部石英振盪) nd  雙時鐘機制，系統可以隨時切換高速振盪或者低速振盪。 uc  內建看門狗計時(WDT)，可由程式韌體控制開關。 I_HRC (1~20MHz內部高速RC振盪) 低速振盪：E_LXT (32KHz外部低速石英振盪) mi  I_LRC (內部 32KHz低速RC振盪) Se  四種工作模式可隨系統需求調整電流消耗：正常模式(Normal)、慢速模式(Slow mode)、待機模式(Standby mode) 與 睡眠模式(Halt mode)。  八種硬體中斷： Timer0 溢位中斷。  Timer1 借位中斷。  Timer3 借位中斷。  WDT 中斷。 JS MI CR O   PA/PB 輸入狀態改變中斷。  兩組外部中斷輸入。  低電壓偵測中斷。  NY8A054E在待機模式(Standby mode)下的八種喚醒中斷：  Timer0 溢位中斷。  Timer1 借位中斷。  Timer3 借位中斷。  WDT 中斷。  PA/PB 輸入狀態改變中斷。  兩組外部中斷輸入。  低電壓偵測中斷。 www.jsmsemi.com 第６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU  NY8A054E在睡眠模式(Halt mode)下的四種喚醒中斷： WDT 中斷。  PA/PB 輸入狀態改變中斷。  兩組外部中斷輸入。 NY8A054E 與 NY8A054D 的主要差異 Item Function NY8A054E NY8A054D PA[7:6], PA[4:0] PortA input pull-high resistor PA[7:0] 2 PortA input pull-low resistor PA[5:0] 3 Low Voltage Detector(LVD) voltage level 16 voltage levels 4 Comparator structure shared with LVD rail-to-rail comparator 5 PortA, PortB wake-up default status default: disable default: enable 6 Input Voltage Schmitt Trigger Enable/Disable --- 7 Recommended Operating Voltage PA[5], PA[3:0] 8 voltage levels co nd uc to r 1 CR O Se mi NY8A054E LVR default and recommended voltage are lower than NY8A054D. JS MI 1.2  www.jsmsemi.com 第７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 1. General Description NY8A054E is an EPROM based 8-bit MCU tailored for I/O based applications like light control and remote car application. NY8A054E adopts advanced CMOS technology to provide customers remarkable solution with low cost, high performance. RISC architecture is applied to NY8A054E and it provides 55 instructions. All instructions are executed in single instruction cycle except program branch and skip instructions which will take two instruction cycles. Therefore, NY8A054E is very suitable for those applications that are sophisticated but compact program size is required. to r As NY8A054E address I/O type applications, it can provide 14 I/O pins for applications which require abundant input and output functionality. Moreover, each I/O pin may have additional features, like Pull-High/Pull-Low resistor and open-drain output type through programming. Moreover, NY8A054E has built-in infrared (IR) carrier generator with uc selectable IR carrier frequency and polarity for applications which demand remote control feature. NY8A054E also provides 3 sets of timers which can be used as regular timer based on system oscillation or event nd counter with external trigger clock. Moreover, NY8A054E provides 5 sets of 10-bit resolution Pulse Width Modulation (PWM) output and 1 set of buzzer output in order to drive motor/LED and buzzer. co NY8A054E employs dual-clock oscillation mechanism, either high oscillation or low oscillation can be derived from internal resistor/capacitor oscillator or external crystal oscillator. Moreover, based on dual-clock mechanism, mi NY8A054E provides kinds of operation mode like Normal mode, Slow mode, Standby mode and Halt mode in order to save power consumption and lengthen battery operation life. Moreover, it is possible to use internal Se high-frequency oscillator as CPU operating clock source and external 32KHz crystal oscillator as timer clock input, so as to accurate count real time and maintain CPU working power. While NY8A054E operates in Standby mode and Halt mode, kinds of event will issue interrupt requests and can Features JS MI 1.1 CR O wake-up NY8A054E to enter Normal mode and Slow mode in order to process urgent events.  Wide operating voltage range:  2.0V ~ 5.5V @system clock ≦8MHz.  2.2V ~ 5.5V @system clock > 8MHz.  Wide operating temperature: -40°C ~ 85°C.  2K x 14 bits EPROM.  128 bytes SRAM.  14 general purpose I/O pins (GPIO), PA[7:0], PB[5:0], with independent direction control.  PA[5:0] and PB[3:0] have features of Pull-Low resistor for input pin.  PA[7: 0] and PB[5:0] have features of Pull-High resistor.  PB[5:0] has features of Open-Drain output. www.jsmsemi.com 第８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU  PA[5] has feature of input or open-drain output.  8-level hardware Stack.  Direct and indirect addressing modes for data access.  One 8-bit up-count timer (Timer0) with programmable prescaler.  Five 10-bit reload or continuous down-count timers (Timer1, 3).  Five 10-bit resolution PWM (PWM1, 2, 3, 4, 5) output. PWM1/2 use Timer1, PWM3/4/5 use Timer3. to r  One buzzer (BZ1) output.  Selectable 38/57KHz IR carrier frequency and high/low polarity according to data value.  Built-in high-precision Low-Voltage Detector (LVD). uc  Built-in high-precision Voltage Comparator. nd  Built-in Power-On Reset (POR).  Built-in Low-Voltage Reset (LVR). co  Built-in Watch-Dog Timer (WDT) enabled/disabled by firmware control.  Built-in Resistance to Frequency Converter (RFC) function.  mi  Dual-clock oscillation: System clock can switch between high oscillation and low oscillation. High oscillation: E_HXT (External High Crystal Oscillator, above 6MHz) Se E_XT (External Crystal Oscillator, 455K~6MHz) I_HRC (Internal High Resistor/Capacitor Oscillator ranging from 1M~20MHz)  Low oscillation: E_LXT (External Low Crystal Oscillator, about 32KHz) CR O I_LRC (Internal 32KHz oscillator)  Four kinds of operation mode to reduce system power consumption:  Normal mode, Slow mode, Standby mode and Halt mode. JS MI  Eight hardware interrupt events:  Timer0 overflow interrupt.  Timer1 underflow interrupt.  Timer3 underflow interrupt.  WDT timeout interrupt.  PA/PB input change interrupt.  2 set External interrupt.  LVD interrupt. www.jsmsemi.com 第９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU  Timer0 overflow interrupt.  Timer1 underflow interrupt.  Timer3 underflow interrupt.  WDT timeout interrupt.  PA/PB input change interrupt.  2 set External interrupt.  LVD interrupt. to r  Eight interrupt events to wake-up NY8A054E from Standby mode:  Four interrupt events to wake-up NY8A054E from Halt mode:  PA/PB input change interrupt.  2 set External interrupt. nd uc WDT timeout interrupt. Major Differences Table Between NY8A054E and NY8A054D NY8A054E co Item Function PortA input pull-high resistor PA[7:0] PA[7:6], PA[4:0] 2 PortA input pull-low resistor PA[5:0] PA[5], PA[3:0] 3 Low Voltage Detector(LVD) voltage level 16 voltage levels 8 voltage levels 4 Comparator structure shared with LVD rail-to-rail comparator 5 PortA, PortB wake-up default status default: disable default: enable 6 Input Voltage Schmitt Trigger Enable/Disable --- 7 Recommended Operating Voltage NY8A054E LVR default and recommended voltage are lower than NY8A054D. CR O Se mi 1 NY8A054D JS MI 1.2  www.jsmsemi.com 第１０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Block Diagram 1.3 Pin Assignment Se mi co nd uc to r 1.2 JS MI CR O NY8A054E provides two kinds of package type which are SOP16 and SOP8 package. Figure 1 Package pin assignment www.jsmsemi.com 第１１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Pin Description I/O PA0/ PWM2 I/O PA0 is bidirectional I/O pin, and can be comparator analog input pins. PA0 can be the output of PWM2. PA1/ PWM5/ EX_CKI1 I/O PA1 is bidirectional I/O pin, and can be comparator analog input pins. PA1 can be the output of PWM5. Moreover, it can be Timer3 clock source EX_CKI1. PA2/ PWM4/ INT1/ SDI I/O PA2 is a bidirectional I/O pin, and can be comparator analog input pin. PA2 can be the output of PWM4. PA2 can be the input pin of external interrupt INT1. PA2 can be programming pad SDI. PA3/ PWM3/ SDO I/O PA3 is a bidirectional I/O pin, and can be comparator analog input pin. PA3 can be the output of PWM3 PA3 can be programming pad SDO. I/O PA4 is a bidirectional I/O pin. PA4 can be the output of PWM1 PA4 can be the Timer0,1 clock source EX_CKI0. PA4 can be programming pad SCK. PA5/ RSTb/ Vpp I/O PA5 is an input pin or open-drain output pin. PA5 can be the reset pin RSTb. If this pin is more than 7.75V, it also can make NY8A054E enter EPROM programming mode. PA6/ Xin I/O PA6 is a bidirectional I/O pin. PA6 can be the input pin of crystal oscillator Xin. PA7/ Xout I/O PA7 is a bidirectional I/O pin. PA7 can be the output pin of crystal oscillator Xout. PA7 also can be output of instruction clock. PB0/ PWM5/ INT0 I/O PB0 is a bidirectional I/O pin. PB0 can be the output of PWM5. PB0 can be the input pin of external interrupt INT0. PB1/ IR/ INT1 I/O PB1 is a bidirectional I/O pin. If IR mode is enabled, this pin is IR carrier output. PB1 can be the input pin of external interrupt INT1. PB2/ PWM2 I/O PB2 is a bidirectional I/O pin. PB2 can be the output of PWM2. PB3/ PWM1/ BZ1/ SDO I/O PB3 is a bidirectional I/O pin. PB3 can be the output of Buzzer1 or PWM1 PB3 can be programming pad SDO. PB4/ PWM3 I/O PB4 is bidirectional I/O pin. PB4 can be the output of PWM3. PB5/ PWM4 I/O PB5 is bidirectional I/O pin. PB5 can be the output of PWM4. VDD P Positive power supply. VSS P Ground. uc nd co mi Se CR O PA4/ PWM1/ EX_CKI0/ SCK Description to r Pin Name JS MI 1.4 www.jsmsemi.com 第１２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 2. Memory Organization NY8A054E memory is divided into two categories: one is program memory and the other is data memory. Program Memory The program memory space of NY8A054E is 2K words. Therefore, the Program Counter (PC) is 11-bit wide in order to address any location of program memory. to r Some locations of program memory are reserved as interrupt entrance. Power-On Reset vector is located at 0x000. Software interrupt vector is located at 0x001. Internal and external hardware interrupt vector is located at 0x008. uc NY8A054E provides instruction CALL, GOTOA, CALLA to address 256 location of program space. NY8A054E provides instruction GOTO to address 512 location of program space. NY8A054E also provides instructions nd LCALL and LGOTO to address any location of program space. When a call or interrupt is happening, next ROM address is written to top of the stack, when RET, RETIA or co RETIE instruction is executed, the top of stack data is read and load to PC. NY8A054E program ROM address 0x7FE~0x7FF are reserved space, if user tries to write code in these mi addresses will get unexpected false functions. NY8A054E program ROM address 0x00E~0x00F are preset rolling code can be released and used as normal CR O Se program space. JS MI 2.1 Figure 2 Program Memory Address Mapping www.jsmsemi.com 第１３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Data Memory According to instructions used to access data memory, the data memory can be divided into three kinds of categories: one is R-page Special-function register (SFR) + General Purpose Register (GPR), another is F-page SFR and the other is S-page SFR. GPR are made of SRAM and user can use them to store variables or intermediate results. R-page data memory is divided into 4 banks and can be accessed directly or indirectly through a SFR register which is File Select Register (FSR). STATUS [7:6] are used as Bank register BK[1:0] to select one bank out of to r the 4 banks. R-page register can be divided into addressing mode: direct addressing mode and indirect addressing mode. uc The indirect addressing mode of data memory access is described in the following graph. This indirect addressing mode is implied by accessing register INDF. The bank selection is determined by STATUS[7:6] and CR O Se mi co nd the location selection is from FSR[6:0]. Figure 3 Indirect Addressing Mode of Data Memory Access The direct addressing mode of data memory access is described below. The bank selection is determined by STATUS [7:6] and the location selection is from instruction op-code[6:0] immediately. JS MI 2.2 Figure 4 Direct Addressing Mode of Data Memory Access www.jsmsemi.com 第１４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU R-page SFR can be accessed by general instructions like arithmetic instructions and data movement instructions. The R-page SFR occupies address from 0x0 to 0x1F of Bank 0. However, the same address range of Bank 1, Bank 2 and Bank 3 are mapped back to Bank 0. In other words, R-page SFR physically existed at Bank 0. The GPR physically occupy address from 0x20 to 0x7F of Bank 0 and 0x20 to 0x3F of Bank 1. Other bank in address from 0x20 to 0x7F are mapped back as the Table 1 shows. The NY8A054E register name and address mapping of R-page SFR are described in the following table. 01 (Bank 1) INDF 0x1 TMR0 0x2 PCL 0x3 STATUS 0x4 FSR 0x5 PORTA 0x6 PORTB 0x7 - 0x8 PCON 0x9 BWUCON 0xA PCHBUF 0xB ABPLCON 0xC BPHCON 0xD - 0xF nd co Se JS MI 0x10 The same mapping as Bank 0 CR O 0xE 11 (Bank 3) uc 0x0 10 (Bank 2) to r 00 (Bank 0) mi Status [7:6] Address INTE INTF - 0x11 - 0x12 - 0x13 - 0x14 - 0x15 AWUCON 0x16 - 0x17 - 0x18 INTEDG 0x19 TMRH 0x1A - www.jsmsemi.com 第１５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Status [7:6] 00 (Bank 0) Address 01 (Bank 1) 10 (Bank 2) 11 (Bank 3) 0x1B RFC 0x1C TM34RH 0x1D ~ 0x1E - - 0x1F INTE2 The same mapping as Bank 0 0x20 ~ 0x3F General Purpose Register General Purpose Register Mapped to bank0 Mapped to Bank1 0x40 ~ 0x7F General Purpose Register Mapped to bank0 Mapped to bank0 Mapped to bank0 R-page SFR Address Mapping uc Table 1 to r The same mapping as Bank 0 F-page SFR can be accessed only by instructions IOST and IOSTR. S-page SFR can be accessed only by nd instructions SFUN and SFUNR. STATUS[7:6] bank select bits are ignored while F-page and S-page register is accessed. The register name and address mapping of F-page and S-page are depicted in the following table. 0x0 - 0x1 - 0x2 - 0x3 - S-page SFR co F-page SFR TMR1 mi SFR Category T1CR1 T1CR2 PWM1DUTY 0x5 Se Address IOSTA BZ1CR 0x6 IOSTB IRCR 0x7 - TBHP 0x8 - TBHD 0x9 APHCON - 0xA PS0CV 0xB - P2CR1 - 0xC BODCON PWM2DUTY 0xD - - 0xE CMPCR - 0xF PCON1 OSCCR 0x10 - TMR3 0x11 - T3CR1 0x12 - T3CR2 0x13 - PWM3DUTY 0x14 - PS3CV 0x15 - - 0x16 - P4CR1 JS MI CR O 0x4 - PS1CV www.jsmsemi.com 第１６页，共１００页 Address SFR Category F-page SFR S-page SFR - 0x18 - PWM4DUTY 0x19 - - 0x1A - - 0x1B - P5CR1 0x1C - - 0x1D - PWM5DUTY 0x1E - - 0x1F - PWM5RH 0x17 F-page and S-page SFR Address Mapping JS MI CR O Se mi co nd uc Table 2 to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU www.jsmsemi.com 第１７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3. Function Description This chapter will describe the detailed operations of NY8A054E. R-page Special Function Register 3.1.1 INDF (Indirect Addressing Register) Name SFR Type Addr. INDF R 0x0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INDF[7:0] R/W Property R/W Initial Value Xxxxxxxx to r 3.1 The register INDF is not physically existed and it is used as indirect addressing mode. Any instruction Name SFR Type Addr. TMR0 R 0x1 Bit7 R/W Property Bit5 mi Initial Value Bit6 nd TMR0 (Timer0 Register) co 3.1.2 uc accessing INDF actually accesses the register pointed by register FSR Bit4 Bit3 Bit2 Bit1 Bit0 TMR0[7:0] R/W Xxxxxxxx When read the register TMR0, it actually read the current running value of Timer0. Se Write the register TMR0 will change the current value of Timer0. Timer0 clock source can be from instruction clock FINST, or from external pin EX_CKI0, or from Low Oscillator 3.1.3 CR O Frequency according to T0MD and configuration word setting. PCL (Low Byte of PC[10:0]) SFR Type JS MI Name PCL R Addr. Bit7 Bit6 Bit5 0x2 Bit4 Bit3 Bit2 Bit1 Bit0 PCL[7:0] R/W Property R/W Initial Value 0x00 The register PCL is the least significant byte (LSB) of 11-bit PC. PCL will be increased by one after one instruction is executed except some instructions which will change PC directly. The high byte of PC, i.e. PC[10:8], is not directly accessible. Update of PC[10:8] must be done through register PCHBUF. For GOTO instruction, PC[8:0] is from instruction word and PC[10:9] is loaded from PCHBUF[2:1]. For CALL instruction, PC[7:0] is from instruction word and PC[10:8] is loaded from PCHBUF[2:0]. Moreover the next PC address, i.e. PC+1, will push onto top of Stack. For LGOTO instruction, PC[10:0] is from instruction word. For LCALL instruction, PC[10:0] is from instruction word. Moreover the next PC address, i.e. PC+1, will push onto top of Stack. www.jsmsemi.com 第１８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.4 STATUS (Status Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 STATUS R 0x3 BK[1] BK[0] GP5 /TO /PD Z DC C R/W Property R/W R/W R/W R/W(*2) R/W(*1) R/W R/W R/W Initial Value 0 0 0 1 1 X X X The register STATUS contains result of arithmetic instructions and reasons to cause reset. C: Carry/Borrow bit to r C=1, carry is occurred for addition instruction or borrow is not occurred for subtraction instruction. C=0, carry is not occurred for addition instruction or borrow is occurred for subtraction instruction. DC: Half Carry/half Borrow bit uc DC=1, carry from the 4th LSB is occurred for addition instruction or borrow from the 4th LSB is not occurred for subtraction instruction. nd DC=0, carry from the 4th LSB is not occurred for addition instruction or borrow from the 4th LSB is occurred for subtraction instruction. co Z: Zero bit Z=1, result of logical operation is zero. mi Z=0, result of logical operation is not zero. /PD: Power down flag bit Se /PD=1, after power-up or after instruction CLRWDT is executed. /PD=0, after instruction SLEEP is executed. /TO: Time overflow flag bit CR O /TO=1, after power-up or after instruction CLRWDT or SLEEP is executed. /TO=0, WDT timeout is occurred. GP5: General purpose read/write register bit. JS MI BK[1:0]: Bank register is used to select one specific bank of data memory. BK[1:0]=00b, Bank 0 is selected. BK[1:0]=01b, Bank 1 is selected. BK[1:0]=10b, Bank 2 is selected. BK[1:0]=11b, Bank 3 is selected. (*1) can be cleared by sleep instruction. (*2) can be set by clrwdt instruction. 3.1.5 FSR (Register File Selection Register) Name SFR Type Addr. Bit7 FSR R 0x4 GP7 Bit6 Bit5 Bit4 Bit2 Bit1 Bit0 X X X FSR[6:0] R/W Property Initial Value Bit3 R/W 0 X X X X FSR[6:0]: Select one register out of 128 registers of specific Bank. GP7: general register. www.jsmsemi.com 第１９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.6 PortA (PortA Data Register) Name SFR Type PortA R Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x5 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R/W Property R/W Initial Value Data latch value is xxxxxxxx, read value is xxxxxxxx port value(PA7~PA0) While reading PortA, it will get the status of the specific pin if that pin is configured as input pin. However, if that pin is configured as output pin, whether it will get the status of the pin or the value of the corresponding to r output data latch is depend on the configuration option RD_OPT. While writing to PortA, data is written to PA’s output data latch. uc PortB (PortB Data Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PortB R 0x6 GP7 GP6 PB5 PB4 PB3 PB2 PB1 PB0 nd 3.1.7 R/W Property R/W Data latch value is xxxxxxxx, read value is xxxxxxxx port value(PB5~PB0) co Initial Value While reading PortB, it will get the status of the specific pin if that pin is configured as input pin. However, if mi that pin is configured as output pin, whether it will get the status of the pin or the value of the corresponding output data latch is depend on the configuration option RD_OPT. While writing to PortB, data is written to Se PB’s output data latch. GP7~6 : general purpose registers. PCON (Power Control Register) CR O 3.1.8 Name SFR Type PCON R Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0x8 WDTEN /PLPA4 LVDEN /PHPA5 LVREN CMPEN GP1 GP0 1 0 0 0 JS MI R/W Property Initial Value R/W 1 1 0 1 GP1, GP0: General read/write register bits. CMPEN: Enable/disable Comparator. CMPEN=1, enable comparator. CMPEN=0, disable comparator. LVREN: Enable/disable LVR. LVREN=1, enable LVR. LVREN=0, disable LVR. /PHPA5: Disable/Enable PA5 pull-high resistor /PHPA5=1, Disable PA5 pull-high resistor /PHPA5=0, Enable PA5 pull-high resistor LVDEN: Enable/disable LVD. www.jsmsemi.com 第２０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU LVDEN=1, enable LVD. LVDEN=0, disable LVD. /PLPA4: Disable/Enable PA4 pull-low resistor /PLPA4=1, Disable PA4 pull-low resistor /PLPA4=0, Enable PA4 pull-low resistor WDTEN: Enable/disable WDT. WDTEN=1, enable WDT. BWUCON (PortB Wake-up Control Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 BWUCON R 0x9 - - Bit2 Bit1 Bit0 R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 0 0 0 0 0 0 uc WUPB5 WUPB4 WUPB3 WUPB2 WUPB1 WUPB0 nd 3.1.9 to r WDTEN=0, disable WDT. WUPBx: Enable/disable PBx wake-up function, 0 ≤ x ≤ 5. co WUPBx=1, enable PBx wake-up function. 3.1.10 PCHBUF (High Byte of PC) mi WUPBx=0, disable PBx wake-up function. SFR Type Addr. Bit7 Bit6 PCHBUF R 0xA - XSPD_STP - PCHBUF[2:0] - W - W X 0 X 0 R/W Property Se Name Bit4 Bit3 Bit2 Bit1 Bit0 CR O Initial Value Bit5 PCHBUF[2:0]: Buffer of the 10th ~ 8th bit of PC. XSPD_STP: Write 1 to stop crystal 32.768K speed-up function, write-only. JS MI 3.1.11 ABPLCON (PortA/PortB Pull-Low Resistor Control Register) Name ABPLCON SFR Addr. Type R 0xB Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 /PLPB3 /PLPB2 /PLPB1 /PLPB0 /PLPA3 /PLPA2 /PLPA1 /PLPA0 1 1 1 R/W Property Initial Value R/W 1 1 1 1 1 /PLPAx: Disable/enable PAx Pull-Low resistor, 0 ≤ x ≤ 3. /PLPAx=1, disable PAx Pull-Low resistor. /PLPAx=0, enable PAx Pull-Low resistor. /PLPBx: Disable/enable PBx Pull-Low resistor, 0 ≤ x ≤ 3. /PLPBx=1, disable PBx Pull-Low resistor. /PLPBx=0, enable PBx Pull-Low resistor. www.jsmsemi.com 第２１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.12 BPHCON (PortB Pull-High Resistor Control Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 BPHCON R 0xC - - R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 1 1 1 1 1 1 /PHPB5 /PHPB4 /PHPB3 /PHPB2 /PHPB1 /PHPB0 /PHPBx: Disable/enable PBx Pull-High resistor, 0 ≤ x ≤ 5. to r /PHPBx=1, disable PBx Pull-High resistor. /PHPBx=0, enable PBx Pull-High resistor. uc 3.1.13 INTE (Interrupt Enable Register) SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTE R 0xE INT1IE WDTIE - LVDIE T1IE INT0IE PABIE T0IE R/W Property R/W R/W - R/W R/W R/W R/W R/W Initial Value 0 0 X 0 0 0 0 0 co T0IE: Timer0 overflow interrupt enable bit. nd Name mi T0IE=1, enable Timer0 overflow interrupt. T0IE=0, disable Timer0 overflow interrupt. Se PABIE: PortA/PortB input change interrupt enable bit. PABIE=1, enable PortA/PortB input change interrupt. PABIE=0, disable PortA/PortB input change interrupt. CR O INT0IE: External interrupt 0 enable bit. INT0IE=1, enable external interrupt 0. INT0IE=0, disable external interrupt 0. JS MI T1IE: Timer1 underflow interrupt enable bit. T1IE=1, enable Timer1 underflow interrupt. T1IE=0, disable Timer1 underflow interrupt. LVDIE: Low-voltage detector interrupt enable bit. LVDIE=1, enable low-voltage detector interrupt. LVDIE=0, disable low-voltage detector interrupt. WDTIE: WDT timeout interrupt enable bit. WDTIE=1, enable WDT timeout interrupt. WDTIE=0, disable WDT timeout interrupt. INT1IE: External interrupt 1 enable bit. INT1IE=1, enable external interrupt 1. INT1IE=0, disable external interrupt 1. www.jsmsemi.com 第２２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.14 INTF (Interrupt Flag Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTF R 0xF INT1IF WDTIF - LVDIF T1IF INT0IF PABIF T0IF R/W Property R/W R/W - R/W R/W R/W R/W R/W Initial Value(note*) 0 0 X 0 0 0 0 0 T0IF: Timer0 overflow interrupt flag bit. to r T0IF=1, Timer0 overflow interrupt is occurred. T0IF must be clear by firmware. PABIF: PortA/PortB input change interrupt flag bit. PABIF=1, PortA/PortB input change interrupt is occurred. uc PABIF must be clear by firmware. INT0IF: External interrupt 0 flag bit. nd INT0IF=1, external interrupt 0 is occurred. INT0IF must be clear by firmware. co T1IF: Timer1 underflow interrupt flag bit. T1IF must be clear by firmware. mi T1IF=1, Timer1 underflow interrupt is occurred. LVDIF: Low-voltage detector interrupt flag bit. Se LVDIF=1, Low-voltage detector interrupt is occurred. LVDIF must be clear by firmware. WDTIF: WDT timeout interrupt flag bit. CR O WDTIF=1, WDT timeout interrupt is occurred. WDTIF must be clear by firmware. INT1IF: External interrupt 1 flag bit. JS MI INT1IF=1, external interrupt 1 is occurred. INT1IF must be clear by firmware. Note: When corresponding INTE bit is not enabled, the read interrupt flag is 0. 3.1.15 AWUCON (PortA Wake-up Control Register) Name AWUCON SFR Addr. Type R 0x15 Bit7 Bit6 WUPA7 WUPA6 Bit5 Bit4 WUPA5 WUPA4 Bit3 Bit2 WUPA3 WUPA2 Bit1 Bit0 WUPA1 WUPA0 R/W Property R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 WUPAx: Enable/disable PAx wake-up function, 0 ≤ x ≤ 7. WUPAx=1, enable PAx wake-up function. WUPAx=0, disable PAx wake-up function. www.jsmsemi.com 第２３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.1.16 INTEDG (Interrupt Edge Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTEDG R 0x18 - - EIS1 EIS0 INT1G1 INT1G0 INT0G1 INT0G0 R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 0 0 0 1 0 1 EIS1: External interrupt 1 select bit EIS1=1, PB1/PA2 is external interrupt 1. to r EIS1=0, PB1/PA2 is GPIO. EIS0: External interrupt 0 select bit EIS0=1, PB0 is external interrupt 0. uc EIS0=0, PB0 is GPIO. INT1G1~0: INT1 edge trigger select bit. nd 00: reserved, 01: rising edge, 10: falling edge, 11: rising/falling edge. INT0G1~0: INT0 edge trigger select bit. co 00: reserved, 01: rising edge, 10: falling edge, 11: rising/falling edge. SFR Type Addr. TMRH R 0x19 R/W Property Bit7 Bit6 Se Name mi 3.1.17 TMRH (Timer High Byte Register) Bit4 Bit3 Bit2 Bit1 Bit0 - - TMR19 TMR18 PWM2 DUTY9 PWM2 DUTY8 PWM1 DUTY9 PWM1 DUTY8 - - R/W R/W R/W R/W R/W R/W X X X X X X X X CR O Initial Value Bit5 TMR19~8: Timer1 MSB 2 bits. Write these 2 bits will overwrite the 10-bit Timer1 load value of bit 9 and 8. Read these 2 bits will get the Timer1 bit9-8 current value. JS MI PWM2DUTY9~8: PWM2 duty data MSB 2 bits. PWM1DUTY9~8: PWM1 duty data MSB 2 bits. 3.1.18 RFC (RFC Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 RFC R 0x1B RFCEN - - - PSEL[3:0] R/W Property R/W - - - R/W Initial Value 0 X X X 0 Bit0 RFCEN: Enable/disable RFC function. RFCEN=1, enable RFC function. RFCEN=0, disable RFC function. www.jsmsemi.com 第２４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU PA0 0001 PA1 0010 PA2 0011 PA3 0100 PA4 0101 PA5 0110 PA6 0111 PA7 1000 PB0 1001 PB1 1010 PB2 1011 PB3 1100 PB4 1101 PB5 Table 3 uc 0000 nd RFC PAD RFC pad select SFR Type Addr. TM34RH R 0x1C R/W Property Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - TMR39 TMR38 PWM4 DUTY9 PWM4 DUTY8 PWM3 DUTY9 PWM3 DUTY8 - - R/W R/W R/W R/W R/W R/W X X X X X X X X CR O Initial Value Bit7 Se Name mi 3.1.19 TM34RH (Timer3 High Byte Register) co PSEL[3:0] to r PSEL[3:0]: Select RFC pad. TMR39~8: Timer3 MSB 2 bits. Write these 2 bits will overwrite the 10-bit Timer3 load value of bit 9 and 8.Read these 2 bits will get the Timer3 bit9-8 current value. JS MI PWM3DUTY9~8: PWM3 duty data MSB 2 bits. PWM4DUTY9~8: PWM4 duty data MSB 2 bits. 3.1.20 INTE2 (Interrupt Enable and Flag 2nd. Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INTE2 R 0x1F - - - T3IF - - - T3IE R/W Property - - - R/W - - - R/W Initial Value - - - 0 - - - 0 T3IF: Timer3 underflow interrupt flag bit. T3IF=1, Timer3 underflow interrupt is occurred. T3IF must be clear by firmware. www.jsmsemi.com 第２５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU T3IE: Timer3 underflow interrupt enable bit. T3IE=1, enable Timer3 underflow interrupt. T3IE=0, disable Timer3 underflow interrupt. T0MD Register T0MD is a readable/writeable register which is only accessed by instruction T0MD / T0MDR. Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 T0MD - - LCKTM0 GP6 T0CS T0CE PS0WDT PS0SEL[2:0] 1 111 R/W Initial Value(note*) 0 0 1 1 Bit1 to r R/W Property Bit2 Bit0 uc PS0SEL[2:0]: Prescaler0 dividing rate selection. The rate depends on Prescaler0 is assigned to Timer0 or WDT. When Prescaler0 is assigned to WDT, the dividing rate is dependent on which timeout nd mechanism is selected. Dividing Rate PS0SEL[2:0] PS0WDT=0 (Timer0) 000 1:2 001 1:4 PS0WDT=1 (WDT Interrupt) 1:1 1:2 1:2 1:4 1:8 1:4 1:8 1:16 1:8 1:16 1:32 1:16 1:32 1:64 1:32 1:64 110 1:128 1:64 1:128 111 1:256 1:128 1:256 100 mi CR O 101 Se 010 011 co PS0WDT=1 (WDT Reset) Table 4 Prescaler0 Dividing Rate PS0WDT: Prescaler0 assignment. JS MI 3.2 PS0WDT=1, Prescaler0 is assigned to WDT. PS0WDT=0, Prescaler0 is assigned to Timer0. Note: Always set PS0WDT and PS0SEL[2:0] before enabling watchdog or timer interrupt, or reset or interrupt may be falsely triggered. T0CE: Timer0 external clock edge selection. T0CE=1, Timer0 will increase one while high-to-low transition occurs on pin EX_CKI0. T0CE=0, Timer0 will increase one while low-to-high transition occurs on pin EX_CKI0. Note: T0CE is also applied to Low Oscillator Frequency as Timer0 clock source condition. T0CS: Timer0 clock source selection. T0CS=1, External clock on pin EX_CKI0 or Low Oscillator Frequency (I_LRC or E_LXT) is selected. T0CS=0, Instruction clock FINST is selected. www.jsmsemi.com 第２６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU GP6: General register. LCKTM0: When T0CS=1, timer 0 clock source can be optionally selected to be low-frequency oscillator. T0CS=0, Instruction clock FINST is selected as Timer0 clock source. T0CS=1, LCKTM0=0, external clock on pin EX_CKI0 is selected as Timer0 clock source. T0CS=1, LCKTM0=1, Low Oscillator Frequency (I_LRC or E_LXT, depends on configuration word Low Oscillator Frequency) output replaces pin EX_CKI0 as Timer0 clock source. F-page Special Function Register IOSTA (PortA I/O Control Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOSTA F 0x5 IOPA7 IOPA6 IOPA5 IOPA4 IOPA3 IOPA2 IOPA1 IOPA0 R/W Property R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 co IOPAx: PAx I/O mode selection, 0 ≤ x ≤ 7. Se IOSTB (PortB I/O Control Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 IOSTB F 0x6 - - IOPB5 IOPB4 IOPB3 IOPB2 IOPB1 IOPB0 R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 1 1 1 1 1 1 Bit4 Bit3 Bit2 Bit1 Bit0 CR O 3.3.2 mi IOPAx=1, PAx is input mode. IOPAx=0, PAx is output mode. uc 3.3.1 nd 3.3 to r Note: For more detail descriptions of Timer0 clock source select, please see Timer0 section. IOPBx: PBx I/O mode selection, 0 ≤ x ≤ 5. JS MI IOPBx=1, PBx is input mode. IOPBx=0, PBx is output mode. 3.3.3 APHCON (PortA Pull-High Resistor Control Register) Name SFR Type Addr. APHCON F 0x9 Bit7 Bit6 Bit5 /PHPA7 /PHPA6 /PLPA5 /PHPA4 /PHPA3 /PHPA2 /PHPA1 /PHPA0 R/W Property Initial Value R/W 1 1 1 1 1 1 1 1 /PHPAx: Enable/disable Pull-High resistor of PAx, x=0~4, 6~7. /PHPAx=1, disable Pull-High resistor of PAx. /PHPAx=0, enable Pull-High resistor of PAx. www.jsmsemi.com 第２７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU /PLPA5: Enable/disable Pull-Low resistor of PA5. /PLPA5=1, disable Pull-Low resistor of PA5. /PLPA5=0, enable Pull-Low resistor of PA5. Note: When PA6 and PA7 are used as crystal oscillator pads, the Pull-High resistor should not enable. Or the oscillation may fail. PS0CV (Prescaler0 Counter Value Register) Name SFR Type Addr. PS0CV F 0xA Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 to r 3.3.4 PS0CV[7:0] R/W Property R 1 1 1 1 1 1 1 1 Bit2 Bit1 Bit0 ODPB2 ODPB1 ODPB0 uc Initial Value BODCON (PortB Open-Drain Control Register) SFR Type Addr. Bit7 Bit6 Bit5 Bit4 BODCON F 0xC - - R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 0 0 0 0 0 0 co Name Bit3 ODPB5 ODPB4 ODPB3 mi 3.3.5 nd While reading PS0CV, it will get current value of Prescaler0 counter. Se ODPBx: Enable/disable open-drain of PBx, 0 ≤ x ≤ 5. ODPBx=1, enable open-drain of PBx. ODPBx=0, disable open-drain of PBx. CMPCR (Comparator voltage select Control Register) CR O 3.3.6 Name CMPCR SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 F 0xE GP7 RBIAS_H RBIAS_L CMPF_INV PS1 PS0 NS1 NS0 1 1 0 0 JS MI R/W Property Initial Value R/W 0 0 0 0 NS[1:0]: Comparator inverting input select. NS[1:0] Inverting input 00 PA1 01 PA3 10 Bandgap (0.6V) 11 Vref PS[1:0]: Comparator non-inverting input select www.jsmsemi.com 第２８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU PS[1:0] Non-inverting input 00 PA0 01 PA2 10 Vref 11 --- CMPF_INV: Comparator output inverse control bit. CMPF_INV = 1, Inverse comparator output. to r CMPF_INV = 0, Non-inverse comparator output. RBIAS_L, RBIAS_H: Set corresponding voltage reference levels PCON1 (Power Control Register1) SFR Type Addr. Bit7 PCON1 F 0xF GIE Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 LVDS2 LVDS1 LVDS0 GP1 T0EN nd Name LVDOUT LVDS3 R/W Property R/W (1*) R R/W R/W R/W R/W R/W R/W Initial Value 0 X 1 1 1 1 0 1 co 3.3.7 uc (please refer to chapter 3.15.1) T0EN=1, enable Timer0. Se T0EN=0, disable Timer0. mi T0EN: Enable/disable Timer0. LVDS[3:0] Voltage 0000 1.9V 0001 CR O LVDS3~0: Select one of the 16 LVD voltage. 0010 0011 2.2V 2.4V JS MI 0100 2.0V 2.6V 0101 2.8V 0110 2.9V 0111 3.0V 1000 3.15V 1001 3.30V 1010 3.45V 1011 3.60V 1100 3.75V 1101 3.90V 1110 4.05V 1111 4.15V Table 7 LVD voltage select www.jsmsemi.com 第２９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU LVDOUT: Low voltage detector output, read-only. GIE: Global interrupt enable bit. GIE=1, enable all unmasked interrupts. GIE=0, disable all interrupts. GP5, GP1: General purpose read/write register. (1*) : set by instruction ENI, clear by instruction DISI, read by instruction IOSTR. 3.4.1 to r S-page Special Function Register TMR1 (Timer1 Register) Name SFR Type Addr. TMR1 S 0x0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR1[7:0] uc 3.4 R/W Property R/W XXXXXXXX nd Initial Value When reading register TMR1, it will obtain current value of 10-bit down-count Timer1 at TMR1[9:0]. When co writing register TMR1, it will write data from TMRH[5:4] and Timer1 reload register to TMR1[9:0] current T1CR1 (Timer1 Control Register1) Name SFR Type Addr. T1CR1 S 0x1 Se 3.4.2 mi content. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM1OEN PWM1OAL - - - T1OS T1RL T1EN R/W R/W - - - R/W R/W R/W 0 0 X X X 0 0 0 CR O R/W Property Initial Value This register is used to configure Timer1 functionality. JS MI T1EN: Enable/disable Timer1. T1EN=1, enable Timer1. T1EN=0, disable Timer1. T1RL: Configure Timer1 down-count mechanism while Non-Stop mode is selected (T1OS=0). T1RL=1, initial value is reloaded from reload register TMR1[9:0]. T1RL=0, continuous down-count from 0x3FF when underflow is occurred. T1OS: Configure Timer1 operating mode while underflow is reached. T1OS=1, One-Shot mode. Timer1 will count once from the initial value to 0x00. T1OS=0, Non-Stop mode. Timer1 will keep down-count after underflow. T1OS T1RL 0 0 Timer1 Down-Count Functionality Timer1 will count from reload value down to 0x00. When underflow is reached, 0x3FF is reloaded and continues down-count. www.jsmsemi.com 第３０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU T1OS T1RL Timer1 Down-Count Functionality 0 1 Timer1 will count from reload value down to 0x00. When underflow is reached, reload value is reloaded and continues to down-count. 1 x Timer1 will count from initial value down to 0x00. When underflow is reached, Timer1 will stop down-count. Table 8 Timer1 Functionality PWM1OAL: Define PWM1 output active state. to r PWM1OAL=1, PWM1 output is active low. PWM1OAL=0, PWM1 output is active high. PWM1OEN: Enable/disable PWM1 output. uc PWM1OEN=1, PWM1 output will be present on PB3 or PA4. T1CR2 (Timer1 Control Register2) SFR Type Addr. Bit7 Bit6 T1CR2 S 0x2 - R/W Property - Initial Value X Bit5 Bit4 Bit3 - T1CS T1CE /PS1EN - R/W R/W R/W R/W R/W R/W X 1 1 1 1 1 1 co Name mi 3.4.3 nd PWM1OEN=0, PB3 or PA4 is GPIO. Bit2 Bit1 Bit0 PS1SEL[2:0] This register is used to configure Timer1 functionality. Se PS1SEL[2:0]: Prescaler1 dividing rate selection. Dividing Rate 000 1:2 001 1:4 010 011 100 JS MI 101 CR O PS1SEL[2:0] 1:8 1:16 1:32 1:64 110 1:128 111 1:256 Table 9 Prescaler1 Dividing Rate Note: Always set PS1SEL[2:0] at /PS1EN=1, or interrupt may be falsely triggered. /PS1EN: Disable/enable Prescaler1. /PS1EN=1, disable Prescaler1. /PS1EN=0, enable Prescaler1. T1CE: Timer1 external clock edge selection. T1CE=1, Timer1 will decrease one while high-to-low transition occurs on pin EX_CKI0. T1CE=0, Timer1 will decrease one while low-to-high transition occurs on pin EX_CKI0. www.jsmsemi.com 第３１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU T1CS: Timer1 clock source selection. T1CS=1, External clock on pin EX_CKI0 is selected. T1CS=0, Instruction clock is selected. PWM1DUTY (PWM1 Duty Register) Name SFR Type Addr. PWM1DUTY S 0x3 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM1DUTY[7:0] R/W Property W Initial Value XXXXXXXX to r 3.4.4 The reload value of 10-bit Timer1 stored on registers TMRH[5:4] and TMR1[7:0] is used to define the PWM1 PS1CV (Prescaler1 Counter Value Register) Name SFR Type Addr. PS1CV S 0x4 Bit7 Bit6 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 Bit2 Bit1 PS1CV[7:0] co R/W Property 1 1 1 R 1 1 mi Initial Value Bit5 nd 3.4.5 uc frame rate, and registers TMRH[1:0] and PWM1DUTY[7:0] is used to define the duty cycle of PWM1. While reading PS1CV, it will get current value of Prescaler1 counter. Se BZ1CR (Buzzer1 Control Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 BZ1CR S 0x5 BZ1EN - - - BZ1FSEL[3:0] R/W Property W - - - W Initial Value 0 X X X CR O 3.4.6 Bit3 1 1 1 Bit0 1 BZ1FSEL[3:0]: Frequency selection of BZ1 output. BZ1 Frequency Selection JS MI BZ1FSEL[3:0] Clock Source Dividing Rate 0000 1:2 0001 1:4 0010 1:8 0011 0100 Prescaler1 output 1:16 1:32 0101 1:64 0110 1:128 0111 1:256 1000 1001 Timer1 output Timer1 bit 0 Timer1 bit 1 www.jsmsemi.com 第３２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU BZ1 Frequency Selection Clock Source Dividing Rate 1010 Timer1 bit 2 1011 Timer1 bit 3 1100 Timer1 bit 4 1101 Timer1 bit 5 1110 Timer1 bit 6 1111 Timer1 bit 7 Table 10 to r BZ1FSEL[3:0] Buzzer1 Output Frequency Selection uc BZ1EN: Enable/Disable BZ1 output. BZ1EN=1, enable Buzzer1. Name SFR Type Addr. Bit7 IRCR S 0x6 IROSC358M W Initial Value 0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - - - IRCSEL IRF57K IREN - - - - W W W X X X X 0 0 0 mi R/W Property co IRCR (IR Control Register) Se 3.4.7 nd BZ1EN=0, disable Buzzer1. IREN: Enable/Disable IR carrier output. IREN=1, enable IR carrier output. CR O IREN=0, disable IR carrier output. IRF57K: Selection of IR carrier frequency. IRF57K=1, IR carrier frequency is 57KHz. JS MI IRF57K=0, IR carrier frequency is 38KHz. IRCSEL: Polarity selection of IR carrier. IRCSEL=0, IR carrier will be generated when I/O pin data is 1. IRCSEL=1, IR carrier will be generated when I/O pin data is 0. IROSC358M: When external crystal is used, this bit is determined according to what kind of crystal is used. This bit is ignored if internal high frequency oscillation is used. IROSC358M=1, crystal frequency is 3.58MHz. IROSC358M=0, crystal frequency is 455KHz. Note: 1. Only high oscillation (FHOSC) (See section 3.18) can be used as IR clock source. 2. Division ratio for different oscillation type. www.jsmsemi.com 第３３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU OSC. Type 57KHz 38KHz High IRC(4MHz) 64 96 Xtal 3.58MHz 64 96 Xtal mode & IROSC358M=1 Xtal 455KHz 8 12 Xtal mode & IROSC358M=0 what system clock is) Division ratio for different oscillation type TBHP (Table Access High Byte Address Pointer Register) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 TBHP S 0x7 - - - - - R/W Property - - - - - Initial Value X X X X Bit2 Bit1 Bit0 TBHP2 TBHP1 TBHP0 R/W R/W R/W X X X uc 3.4.8 HIRC mode (the input to IR module is set to 4MHz no matter to r Table 11 Conditions X nd When instruction CALLA, GOTOA or TABLEA is executed, the target address is constituted by TBHP[2:0] TBHD (Table Access High Byte Data Register) Name SFR Type Addr. Bit7 TBHD S 0x8 - Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - TBHD5 TBHD4 TBHD3 TBHD2 TBHD1 TBHD0 - R R R R R R X X X X X X X Se R/W Property Bit6 mi 3.4.9 co and ACC. ACC is the Low Byte of PC[10:0] and TBHP[2:0] is the high byte of PC[10:0]. Initial Value X When instruction TABLEA is executed, high byte of content of addressed ROM is loaded into TBHD[5:0] CR O register. The Low Byte of content of addressed ROM is loaded to ACC. 3.4.10 P2CR1 (PWM2 Control Register1) SFR Type Addr. P2CR1 S 0xA JS MI Name Bit7 Bit6 PWM2OEN PWM2OAL Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 - - - - - - R/W Property R/W R/W - - - - - - Initial Value 0 0 X X X X X X PWM2OAL: Define PWM2 output active state. PWM2OAL=1, PWM2 output is active low. PWM2OAL=0, PWM2 output is active high. PWM2OEN: Enable/disable PWM2 output. PWM2OEN=1, PWM2 output will be present on PB2 or PA0. PWM2OEN=0, PB2 or PA0 is GPIO. www.jsmsemi.com 第３４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.4.11 PWM2DUTY (PWM2 Duty Register) Name SFR Type Addr. PWM2DUTY S 0xC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM2DUTY[7:0] R/W Property W Initial Value XXXXXXXX The reload value of 10-bit Timer1 stored on registers TMRH[5:4] and TMR1[7:0] is used to define the PWM2 to r frame rate, and registers TMRH[3:2] and PWM2DUTY[7:0] is used to define the duty cycle of PWM2. 3.4.12 OSCCR (Oscillation Control Register) Bit7 Bit6 Bit5 Bit4 - - - - R/W Property - - - - R/W R/W R/W Initial Value X X X X 00 0 1 OSCCR S 0xF Bit3 Bit2 OPMD[1:0] Bit1 Bit0 STPHOSC SELHOSC uc SFR Type Addr. nd Name SELHOSC: Selection of system oscillation (FOSC). co SELHOSC=1, FOSC is high-frequency oscillation (FHOSC). SELHOSC=0, FOSC is low-frequency oscillation (FLOSC). mi STPHOSC: Disable/enable high-frequency oscillation (FHOSC). STPHOSC=1, FHOSC will stop oscillation and be disabled. Se STPHOSC=0, FHOSC keep oscillation. OPMD[1:0]: Selection of operating mode. Operating Mode 00 Normal mode 01 10 Halt mode Standby mode reserved JS MI 11 CR O OPMD[1:0] Table 12 Selection of Operating Mode by OPMD[1:0] Note: STPHOSC cannot be changed with SELHOSC or OPMD at the same time. STPHOSC cannot be changed with OPMD at the same time during SELHOSC=1. 3.4.13 TMR3 (Timer3 Register) Name SFR Type Addr. TMR3 S 0x10 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TMR3[7:0] R/W Property R/W Initial Value XXXXXXXX www.jsmsemi.com 第３５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU When reading register TMR3, it will obtain current value of 10-bit down-count Timer3 at TMR3[7:0]. When writing register TMR3, it will write data from TM34RH[5:4] and Timer3 reload register to Timer3[9:0] current content. 3.4.14 T3CR1 (Timer3 Control Register1) SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CR1 S 0x11 PWM3OEN PWM3OAL - - - T3OS T3RL T3EN R/W Property R/W R/W - - - R/W R/W R/W Initial Value 0 0 X X X 0 0 0 This register is used to configure Timer3 functionality. uc T3EN: Enable/disable Timer3. to r Name T3EN=1, enable Timer3. nd T3EN=0, disable Timer3. T3RL: Configure Timer3 down-count mechanism while Non-Stop mode is selected (T3OS=0). co T3RL=1, initial value is reloaded from reload register TMR3. T3RL=0, continuous down-count from 0x3FF when underflow is occurred. mi T3OS: Configure Timer3 operating mode while underflow is reached. T3OS=1, One-Shot mode. Timer3 will count once from the initial value to 0x00. T3OS T3RL 0 0 Timer3 will count from reload value down to 0x00. When underflow is reached, 0x3FF is reloaded and continues down-count. 1 Timer3 will count from reload value down to 0x00. When underflow is reached, reload value is reloaded and continues to down-count. x Timer3 will count from initial value down to 0x00. When underflow is reached, Timer3 will stop down-count. JS MI 1 Timer3 Down-Count Functionality CR O 0 Se T3OS=0, Non-Stop mode. Timer3 will keep down-count after underflow. Table 13 Timer3 Functionality PWM3OAL: Define PWM3 output active state. PWM3OAL=1, PWM3 output is active low. PWM3OAL=0, PWM3 output is active high. PWM3OEN: Enable/disable PWM3 output. PWM3OEN=1, PWM3 output will be present on PA3 or PB4. PWM3OEN=0, PA3 or PB4 is GPIO. www.jsmsemi.com 第３６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.4.15 T3CR2 (Timer3 Control Register2) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 T3CR2 S 0x12 - - T3CS T3CE /PS3EN R/W Property - - R/W R/W R/W R/W R/W R/W Initial Value X X 1 1 1 1 1 1 PS3SEL[2:0] This register is used to configure Timer3 functionality. Dividing Rate 000 1:2 001 1:4 010 1:8 011 1:16 100 1:32 101 1:64 110 1:128 111 1:256 nd co Prescaler3 Dividing Rate mi Table 14 uc PS3SEL[2:0] to r PS3SEL[2:0]: Prescaler3 dividing rate selection. Note: Always set PS3SEL[2:0] at /PS3EN=1, or interrupt may be falsely triggered. Se /PS3EN: Disable/enable Prescaler3. /PS3EN=1, disable Prescaler3. /PS3EN=0, enable Prescaler3. CR O T3CE: Timer3 external clock edge selection. T3CE=1, Timer3 will decrease one while high-to-low transition occurs on pin EX_CKI1. T3CE=0, Timer3 will decrease one while low-to-high transition occurs on pin EX_CKI1. JS MI T3CS: Timer3 clock source selection. T3CS=1, External clock on pin EX_CKI1 is selected. T3CS=0, Instruction clock is selected. 3.4.16 PWM3DUTY (PWM3 Duty Register) Name SFR Type Addr. PWM3DUTY S 0x13 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM3DUTY[7:0] R/W Property W Initial Value XXXXXXXX The reload value of 10-bit Timer3 stored on registers TM34RH[5:4] and TMR3[7:0] is used to define the PWM3 frame rate, and registers TM34RH[1:0] and PWM3DUTY[7:0] is used to define the duty cycle of PWM3. www.jsmsemi.com 第３７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.4.17 PS3CV (Prescaler3 Counter Value Register) Name SFR Type Addr. PS3CV S 0x14 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 PS3CV[7:0] R/W Property R Initial Value 1 1 1 1 1 While reading PS3CV, it will get current value of Prescaler3 counter. 3.4.18 P4CR1 (PWM4 Control Register1) Addr. Bit7 Bit6 Bit5 P4CR1 S 0x16 PWM4OEN PWM4OAL - R/W Property R/W R/W - - Initial Value 0 0 X X Bit3 Bit2 Bit1 Bit0 - - - - - - - - X X X X Bit3 Bit2 Bit1 nd PWM4OAL: Define PWM4 output active state. PWM4OAL=1, PWM4 output is active low. Bit4 to r SFR Type uc Name PWM4OEN: Enable/disable PWM4 output. co PWM4OAL=0, PWM4 output is active high. PWM4OEN=1, PWM4 output will be present on PA2 or PB5. mi PWM4OEN=0, PA2 or PB5 is GPIO. Se 3.4.19 PWM4DUTY (PWM4 Duty Register) Name SFR Type Addr. PWM4DUTY S 0x18 Bit7 Bit6 Bit5 Bit4 Bit0 PWM4DUTY[7:0] W Initial Value XXXXXXXX CR O R/W Property The reload value of 10-bit Timer3 stored on registers TM34RH[5:4] and TMR3[7:0] is used to define the JS MI PWM4 frame rate, and registers TM34RH[3:2] and PWM4DUTY[7:0] is used to define the duty cycle of PWM4. 3.4.20 P5CR1 (PWM5 Control Register1) Name SFR Type Addr. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P5CR1 S 0x1B PWM5OEN PWM5OAL - - - - - - R/W Property R/W R/W - - - - - - Initial Value 0 0 X X X X X X PWM5OAL: Define PWM5 output active state. PWM5OAL=1, PWM5 output is active low. PWM5OAL=0, PWM5 output is active high. PWM5OEN: Enable/disable PWM5 output. www.jsmsemi.com 第３８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU PWM5OEN=1, PWM5 output will be present on PB0 or PA1. PWM5OEN=0, PB0 or PA1 is GPIO. 3.4.21 PWM5DUTY (PWM5 Duty Register) Name SFR Type Addr. PWM5DUTY S 0x1D Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PWM5DUTY[7:0] W Initial Value XXXXXXXX to r R/W Property The reload value of 10-bit Timer3 stored on registers TM34RH[5:4] and TMR3[7:0] is used to define the PWM5 frame rate, and registers PWM5RH[1:0] and PWM5DUTY[7:0] is used to define the duty cycle of uc PWM5. SFR Type Addr. Bit7 Bit6 PWM5RH S 0x1F - - - Initial Value X Bit4 Bit3 Bit2 - - - - - - - - X X X X mi R/W Property Bit5 co Name nd 3.4.22 PWM5RH (PWM5 High Byte Register) Bit1 Bit0 - PWM5 DUTY9 R/W PWM5D UTY8 R/W X X X I/O Port NY8A054E provides 14 I/O pins which are PA[7:0] and PB[5:0]. User can read/write these I/O pins through CR O registers PORTA and PORTB respectively. Each I/O pin has a corresponding register bit to define it is input pin or output pin. Register IOSTA[7:0] define the input/output direction of PA[7:0]. Register IOSTB[5:0] define the input/output direction of PB[5:0]. When an I/O pin is configured as input pin, it may have Pull-High resistor or Pull-Low resistor which is enabled JS MI 3.5 Se PWM5DUTY9~8: PWM5 duty data MSB 2 bits. or disabled through registers. Register APHCON[7:6, 4:0] and PCON[4] are used to enable or disable Pull-High resistor of PA[7:0]. Register APHCON[5], PCON[6] and ABPLCON[3:0] are used to enable or disable Pull-Low resistor of PA[5:0]. Register BPHCON[5:0] are used to enable or disable Pull-High resistor of PB[5:0]. Register ABPLCON[7:4] are used to enable or disable Pull-Low resistor of PB[3:0]. When an PortB I/O pin is configured as output pin, there is a corresponding and individual register to select as Open-Drain output pin. Register BODCON[5:0] determine PB[5:0] is Open-Drain or not. The summary of Pad I/O feature is listed in the table below. Feature Input PA[4:0] PA[7:6] PA[5] PB[3:0] PB[5:4] Pull-High Resistor V V V V V Pull-Low Resistor V X V V X www.jsmsemi.com 第３９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Feature Output PA[4:0] PA[7:6] PA[5] PB[3:0] PB[5:4] X X always V V Open-Drain Table 15 Summary of Pad I/O Feature The level change on each I/O pin of PA and PB may generate interrupt request. Register AWUCON[7:0] and BWUCON[5:0] will select which I/O pin of PA and PB may generate this interrupt. As long as any pin of PA and PB is selected by corresponding bit of AWUCON and BWUCON, the register bit PABIF (INTF[1]) will set to 1 if there is a level change occurred on any selected pin. An interrupt request will occur and interrupt service routine to r will be executed if register bit PABIE (INTE[1]) and GIE (PCON1[7]) are both set to 1. There is two external interrupt provided by NY8A054E. When register bit EIS0 (INTEDG[4]) is set to 1, PB0 is used as input pin for external interrupt 0. When register bit EIS1 (INTEDG[5]) is set to 1, PB1 is used as input uc pin for external interrupt 1. Note: When PB0 or PB1 is both set as level change operation and external interrupt, the external PB5~PB2 level change function are not affected. nd interrupt will have higher priority, and the PB0 or PB1 level change operation will be disabled. But co NY8A054E provides IR carrier generation output. It is depended both on register bit IREN (IRCR[0]) and carrier output will be present on PB1 pad. When IREN=1, the IR sink current=20mA. When IREN=0, the IR carrier will mi not be generated. PA5 can be used as external reset input determined by a configuration word. When an active-low signal is Se applied to PA5, it will cause NY8A054E to enter reset process. When external crystal (E_HXT, E_XT or E_LXT) is adopted for high oscillation or low oscillation according to pin (Xout). CR O setting of configuration words, PA6 will be used as crystal input pin (Xin) and PA7 will be used as crystal output When I_HRC or I_LRC mode is selected as system oscillation and E_HXT, E_XT or E_LXT is not adopted, JS MI instruction clock is observable on PA7 if a configuration word is enabled. Moreover, PA4 can be timer 0 external clock source EX_CKI0 if T0MD T0CS=1 and LCK_TM0=0. PA4 can be timer 1 external clock source EX_CKI0 if T1CS=1. PA1 can be Timer3 external clock source EX_CKI1 if T3CS =1. Moreover, PB3 or PA4 can be PWM1 output If T1CR1[7] PWM1OEN=1. PB3 can be Buzzer1 output if BZ1CR[7] BZ1EN=1. The output priority of PB3 is PWM1 output > Buzzer1 output. PB2 or PA0 can be PWM2 output If P2CR1[7] PWM2OEN=1. www.jsmsemi.com 第４０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.5.1 Block Diagram of IO Pins IO_SEL: set pad attribute as input or output WRITE_EN: write data to pad. READ_EN: read pad. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. VPEN: enable pad to comparator non-inverting input. to r VNEN: enable pad to comparator inverting input. CMPVP, CMPVN: comparator non-inverting and inverting input. CR O Se mi co nd uc RD_TYPE: select read pin or read latch. Block Diagram of PA[3:2]&PA0 JS MI Figure 5 www.jsmsemi.com 第４１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. VPEN: enable pad to comparator non-inverting input. VNEN: enable pad to comparator inverting input. to r CMPVP, CMPVN: comparator non-inverting and inverting input. RD_TYPE: select read pin or read latch. JS MI CR O Se mi co nd uc EX_CKI1: external clock for Timer 3. Figure 6 Block Diagram of PA1 www.jsmsemi.com 第４２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. RD_TYPE: select read pin or read latch. Se mi co nd uc to r EX_CKI0: external clock for Timer0, 1. Block Diagram of PA4 JS MI CR O Figure 7 www.jsmsemi.com 第４３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU RSTPAD_EN: enable PA5 as reset pin. RSTB_IN: reset signal input. IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. Figure 8 Block Diagram of PA5 JS MI CR O Se mi co nd uc to r RD_TYPE: select read pin or read latch. www.jsmsemi.com 第４４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU XTL_EN: enable crystal oscillation mode. IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. PULLUP_ENB: enable Pull-High. mi co nd uc to r RD_TYPE: select read pin or read latch. Block Diagram of PA6, PA7 JS MI CR O Se Figure 9 www.jsmsemi.com 第４５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. OD_EN: enable open-Drain. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. RD_TYPE: select read pin or read latch. to r EIS0: external interrupt function enable. INTEDG[1:0]: external interrupt edge select. uc EX_INT0: external interrupt signal. WUB: port B wake-up enable. JS MI CR O Se mi co nd SET_PBIF: port B wake-up flag. Figure 10 Block Diagram of PB0 www.jsmsemi.com 第４６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. OD_EN: enable open-Drain. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. RD_TYPE: select read pin or read latch. to r EIS1: external interrupt function enable. INTEDG[3:2]: external interrupt edge select. uc EX_INT1: external interrupt signal. WUB: port B wake-up enable. JS MI CR O Se mi co nd SET_PBIF: port B wake-up flag. Figure 11 Block Diagram of PB1 www.jsmsemi.com 第４７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. OD_EN: enable open-Drain. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. RD_TYPE: select read pin or read latch. to r WUB: port B wake-up enable. JS MI CR O Se mi co nd uc SET_PBIF: port B wake-up flag. Figure 12 Block Diagram of PB2 www.jsmsemi.com 第４８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. OD_EN: enable open-Drain. PULLUP_ENB: enable Pull-High. PULLDOWN_EN: enable Pull-Low. RD_TYPE: select read pin or read latch. to r WUB: port B wake-up enable. JS MI CR O Se mi co nd uc SET_PBIF: port B wake-up flag. Figure 13 Block Diagram of PB3 www.jsmsemi.com 第４９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IO_SEL: set pad attribute as input or output. WRITE_EN: write data to pad. READ_EN: read pad. OD_EN: enable open-Drain. PULLUP_ENB: enable Pull-High. RD_TYPE: select read pin or read latch. WUB: port B wake-up enable. JS MI CR O Se mi co nd uc to r SET_PBIF: port B wake-up flag. Figure 14 Block Diagram of PB4, PB5 www.jsmsemi.com 第５０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Timer0 Timer0 is an 8-bit up-count timer and its operation is enabled by register bit T0EN (PCON1[0]). Writing to Timer0 will set its initial value. Reading from Timer0 will show its current count value. The clock source to Timer0 can be from instruction clock, external pin EX_CKI0 or low speed clock Low Oscillator Frequency according to register bit T0CS and LCK_TM0 (T0MD[5] and T0MD[7]). When T0CS is 0, instruction clock is selected as Timer0 clock source. When T0CS is 1 and LCK_TM0 is 0, EX_CKI0 is selected as Timer0 clock source. When T0CS is 1 and LCK_TM0 is 1 (and Timer0 source must set to 1), Low Oscillator below. (Also check Table 15) T0CS LCKTM0 Timer0 source Instruction clock 0 X X EX_CKI0 1 0 X E_LXT 1 1 I_LRC 1 1 nd 0 X X 1 1 1 0 mi co X Table 16 Low Oscillator Frequency uc Timer0 clock source to r Frequency (I_LRC or E_LXT, depends on configuration word) output is selected. Summarized table is shown Summary of Timer0 clock source control Se Moreover the active edge of EX_CKI0 or Low Oscillator Frequency to increase Timer0 can be selected by register bit T0CE (T0MD[4]). When T0CE is 1, high-to-low transition on EX_CKI0 or Low Oscillator Frequency will increase Timer0. When T0CE is 0, low-to-high transition on EX_CKI0 or Low Oscillator Frequency will CR O increase Timer0. When using Low Oscillator Frequency as Timer0 clock source, it is suggested to use prescaler0 (see below descriptions) and the ratio set to more than 4, or missing count may happen. Before Timer0 clock source is supplied to Timer0, it can be divided by Prescaler0 if register bit PS0WDT (T0MD[3]) is clear to 0. When writing 0 to PS0WDT by instruction, Prescaler0 is assigned to Timer0 and JS MI 3.6 Prescaler0 will be clear after this instruction is executed. The dividing rate of Prescaler0 is determined by register bits PS0SEL[2:0] which is from 1:2 to 1:256. When Timer0 is overflow, the register bit T0IF (INTF[0]) will be set to 1 to indicate Timer0 overflow event is occurred. If register bit T0IE (INTE[0]) and GIE are both set to 1, interrupt request will occur and interrupt service routine will be executed. T0IF will not be clear until firmware writes 0 to T0IF. The block diagram of Timer0 and WDT is shown in the figure below. www.jsmsemi.com 第５１页，共１００页 co Timer1 / PWM1 / Buzzer1 Timer1 is an 10-bit down-count timer with Prescaler1 whose dividing rate is programmable. The output of mi Timer1 can be used to generate PWM1 output and Buzzer1 output. Timer1 builds in auto-reload function and Timer1 reload register stores reload data with double buffers. When user write Timer1 reload register, write Se Timer1 MSB 2 bits(TMRH[5:4]) first and write TMR1 second, Timer1 reload register will be updated to Timer1 counter after Timer1 overflow occurs when T1EN=1. If T1EN=0, Timer1 reload register will be updated to Timer1 counter after write TMR1 immediately. A read to the Timer1 will show the content of the Timer1 current count CR O value. The block diagram of Timer1 is shown in the figure below. JS MI 3.7 Block Diagram of Timer0 and WDT nd Figure 15 uc to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Figure 16 Block Diagram of Timer1 www.jsmsemi.com 第５２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU The operation of Timer1 can be enabled or disabled by register bit T1EN (T1CR1[0]). After Timer1 is enabled, its clock source can be instruction clock or pin EX_CKI0 which is determined by register bit T1CS (T1CR2[5]). When T1CS is 1, EX_CKI0 is selected as clock source. When T1CS is 0, instruction clock is selected as clock source. When EX_CKI0 is selected, the active edge to decrease Timer1 is determined by register bit T1CE (T1CR2[4]). When T1CE is 1, high-to-low transition on EX_CKI0 will decrease Timer1. When T1CE is 0, low-to-high transition on EX_CKI0 will decrease Timer1. The selected clock source can be divided further by Prescaler1 before it is applied to Timer1. Prescaler1 is enabled by writing 0 to register bit /PS1EN (T1CR2[3]) and the dividing rate is from 1:2 to 1:256 determined by register bits PS1SEL[2:0] (T1CR2[2:0]). Current value of to r Prescaler1 can be obtained by reading register PS1CV. Timer1 provides two kinds of operating mode: one is One-Shot mode and the other is Non-Stop mode. When uc register bit T1OS (T1CR1[2]) is 1, One-Shot mode is selected. Timer1 will count down once from initial value stored on register TMR1[9:0] to 0x00, i.e. underflow is occurred. When register bit T1OS (T1CR1[2]) is 0, nd Non-Stop mode is selected. When underflow is occurred, there are two selections to start next down-count which is determined by register bit T1RL (T1CR1[1]). When T1RL is 1, the initial value stored on register TMR1[9:0] will be restored and start next down-count from this initial value. When T1RL is 0, Timer1 will start co next down-count from 0x3FF. mi When Timer1 is underflow, the register bit T1IF (INTF[3]) will be set to 1 to indicate Timer1 underflow event is occurred. If register bit T1IE (INTE[3]) and GIE are both set to 1, interrupt request will occur and interrupt service Se routine will be executed. T1IF will not be clear until firmware writes 0 to T1IF. JS MI CR O The timing chart of Timer1 is shown in the following figure. Figure 17 Timer1 Timing Chart The PWM1 output can be available on I/O pin PB3 or PA4 when register bit PWM1OEN (T1CR1[7]) is set to 1. Moreover, PB3 or PA4 will become output pin automatically. The active state of PWM1 output is determined by register bit PWM1OAL (T1CR1[6]). When PWM1OAL is 1, PWM1 output is active low. When PWM1OAL is 0, PWM1 output is active high. Moreover, the duty cycle and frame rate of PWM1 are both programmable. The www.jsmsemi.com 第５３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU duty cycle is determined by registers TMRH[1:0] and PWM1DUTY[7:0]. When PWM1DUTY is 0, PWM1 output will be never active. When PWM1DUTY is 0x3FF, PWM1 output will be active for 1023 Timer1 input clocks. The frame rate is determined by TMRH[5:4] + TMR1[7:0] initial value. Therefore, PWM1DUTY value must be less than or equal to TMRH[5:4] + TMR1[7:0]. When user write PWM1DUTY, write PWM1DUTY[9:8] MSB 2 bits(TMRH[1:0]) first and write PWM1DUTY[7:0] second, PWM1 duty register will be updated after Timer1 PWM1 Block Diagram mi Figure 18 co nd uc to r overflow occurs. The block diagram of PWM1 is illustrated in the following figure. Se The Buzzer1 output (BZ1) can be available on I/O pin PB3 when register bit BZ1EN (BZ1CR[7]) is set to 1. Moreover, PB3 will become output pin automatically. The frequency of BZ1 can be derived from Timer1 output or Prescaler1 output and dividing rate is determined by register bits BZ1FSEL[3:0] (BZ1CR[3:0]). When BZ1FSEL[3] is 0, Prescaler1 output is selected to generate BZ1 output. When BZ1FSEL[3] is 1, Timer1 output is CR O selected to generate BZ1 output. The dividing rate can be from 1:2 to 1:256 in order to generate all kinds of JS MI frequency. The block diagram of Buzzer1 is illustrated in the following figure. Figure 19 Buzzer1 Block Diagram Note: When PWM1 and Buzzer1 are both enabled, PWM1 will have the higher priority for PB3 output. www.jsmsemi.com 第５４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.8 PWM2 The PWM2 output can be available on I/O pin PB2 or PA0 when register bit PWM2OEN (P2CR1[7]) is set to 1. Moreover, PB2 or PA0 will become output pin automatically. The active state of PWM2 output is determined by register bit PWM2OAL (P2CR1[6]). When PWM2OAL is 1, PWM2 output is active low. When PWM2OAL is 0, PWM2 output is active high. Moreover, the duty cycle and frame rate of PWM2 are both programmable. The duty cycle is determined by register TMRH[3:2],PWM2DUTY[7:0]. When PWM2DUTY is 0, PWM2 output will be never active. When PWM2DUTY is 0x3FF, PWM2 output will be active for 1023 Timer1 input clocks. The frame to r rate is determined by TMRH[5:4],TMR1[7:0] initial value. Therefore, PWM2DUTY value must be less than or equal to TMR1[9:0]. Besides, user needs to set P2CR1 (T1EN, T1RL, T1OS data is as the same as T1CR1) because PWM2 and PWM1 are both shared with Timer1. When user write PWM2DUTY, write PWM2DUTY[9:8] uc MSB 2 bits(TMRH[3:2]) first and write PWM2DUTY[7:0] second, PWM2 duty register will be updated after CR O Se mi co nd Timer1 overflow occurs. The block diagram of PWM2 is illustrated in the following figure. Figure 20 Timer3 / PWM3 JS MI 3.9 PWM2 Block Diagram Timer3 is an 10-bit down-count timer with Prescaler3 whose dividing rate is programmable. The output of Timer3 can be used to generate PWM3 output. Timer3 builds in auto-reload function and Timer3 reload register stores reload data with double buffers. When users write Timer3 reload register, write Timer3 MSB 2 bits(TM34RH[5:4]) first and write TMR3 second, Timer3 reload register will be updated to Timer3 counter after Timer3 overflow occurs when T3EN=1. If T3EN=0, Timer3 reload register will be updated to Timer3 counter after write TMR3 immediately. A read to the Timer3 will show the content of the Timer3 current count value. The block diagram of Timer3 is shown in the figure below. www.jsmsemi.com 第５５页，共１００页 Block Diagram of Timer3 uc Figure 21 to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU The operation of Timer3 can be enabled or disabled by register bit T3EN (T3CR1[0]). After Timer3 is enabled, its nd clock source can be instruction clock or pin EX_CKI1 which is determined by register bit T3CS (T3CR2[5]). When T3CS is 1, EX_CKI1 is selected as clock source. When T3CS is 0, instruction clock is selected as clock co source. When EX_CKI1 is selected, the active edge to decrease Timer3 is determined by register bit T3CE (T3CR2[4]). When T3CE is 1, high-to-low transition on EX_CKI1 will decrease Timer3. When T3CE is 0, mi low-to-high transition on EX_CKI1 will decrease Timer3. The selected clock source can be divided further by Prescaler3 before it is applied to Timer3. Prescaler3 is Se enabled by writing 0 to register bit /PS3EN (T3CR2[3]) and the dividing rate is from 1:2 to 1:256 determined by register bits PS3SEL[2:0] (T3CR2[2:0]). Current value of Prescaler3 can be obtained by reading register PS3CV. CR O Timer3 provides two kinds of operating mode: one is One-Shot mode and the other is Non-Stop mode. When register bit T3OS (T3CR1[2]) is 1, One-Shot mode is selected. Timer3 will count down once from initial value stored on register TMR3[9:0] to 0x00, i.e. underflow is occurred. When register bit T3OS (T3CR1[2]) is 0, JS MI Non-Stop mode is selected. When underflow is occurred, there are two selections to start next down-count which is determined by register bit T3RL (T3CR1[1]). When T3RL is 1, the initial value stored on register TMR3[9:0] will be restored and start next down-count from this initial value. When T3RL is 0, Timer3 will start next down-count from 0x3FF. When Timer3 is underflow, the register bit T3IF (INTE2[4]) will be set to 1 to indicate Timer3 underflow event is occurred. If register bit T3IE (INTE2[0]) and GIE are both set to 1, interrupt request will occur and interrupt service routine will be executed. T3IF will not be clear until firmware writes 0 to T3IF. The timing chart of Timer3 is shown in the following figure. www.jsmsemi.com 第５６页，共１００页 Timer3 Timing Chart nd Figure 22 uc to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU co The PWM3 output can be available on I/O pin PA3 or PB4 when register bit PWM3OEN (T3CR1[7]) is set to 1. Moreover, PA3 or PB4 will become output pin automatically. The active state of PWM3 output is determined by register bit PWM3OAL (T3CR1[6]). When PWM3OAL is 1, PWM3 output is active low. When PWM3OAL is 0, mi PWM3 output is active high. Moreover, the duty cycle and frame rate of PWM3 are both programmable. The duty cycle is determined by register TM34RH[1:0], PWM3DUTY[7:0]. When PWM3DUTY is 0, PWM3 output will Se be never active. When PWM3DUTY is 0x3FF, PWM3 output will be active for 1023 Timer3 input clocks. The frame rate is determined by TM34RH[5:4],TMR3[7:0] initial value. Therefore, PWM3DUTY value must be less than or equal to TMR3[9:0]. When user write PWM3DUTY, write PWM3DUTY[9:8] MSB 2 bits(TM34RH[1:0]) CR O first and write PWM3DUTY[7:0] second, PWM3 duty register will be updated after Timer3 overflow occurs. The JS MI block diagram of PWM3 is illustrated in the following figure. Figure 23 PWM3 Block Diagram www.jsmsemi.com 第５７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.10 PWM4 The PWM4 output can be available on I/O pin PB5 or PA2 when register bit PWM4OEN (P4CR1[7]) is set to 1. Moreover, PB5 or PA2 will become output pin automatically. The active state of PWM4 output is determined by register bit PWM4OAL (P4CR1[6]). When PWM4OAL is 1, PWM4 output is active low. When PWM4OAL is 0, PWM4 output is active high. Moreover, the duty cycle and frame rate of PWM4 are both programmable. The duty cycle is determined by register TM34RH[3:2],PWM4DUTY[7:0]. When PWM4DUTY is 0, PWM4 output will be never active. When PWM4DUTY is 0x3FF, PWM4 output will be active for 1023 Timer3 input clocks. The to r frame rate is determined by TM34RH[5:4],TMR3[7:0] initial value. Therefore, PWM4DUTY value must be less than or equal to TMR3[9:0]. Besides, user needs to set P4CR1 (T3EN, T3RL, T3OS data is as the same as T3CR1) because PWM4 and PWM3 are both shared with Timer3. When user write PWM4DUTY, write uc PWM4DUTY[9:8] MSB 2 bits(TM34RH[3:2]) first and write PWM4DUTY[7:0] second, PWM4 duty register will be CR O Se mi co nd updated after Timer3 overflow occurs. The block diagram of PWM4 is illustrated in the following figure. Figure 24 JS MI 3.11 PWM5 PWM4 Block Diagram The PWM5 output can be available on I/O pin PA1 or PB0 when register bit PWM5OEN (P5CR1[7]) is set to 1. Moreover, PA1 or PB0 will become output pin automatically. The active state of PWM5 output is determined by register bit PWM5OAL (P5CR1[6]). When PWM5OAL is 1, PWM5 output is active low. When PWM5OAL is 0, PWM5 output is active high. Moreover, the duty cycle and frame rate of PWM5 are both programmable. The duty cycle is determined by register PWM5RH[1:0],PWM5DUTY[7:0]. When PWM5DUTY is 0, PWM5 output will be never active. When PWM5DUTY is 0x3FF, PWM5 output will be active for 1023 Timer3 input clocks. The frame rate is determined by TM34RH[5:4],TMR3[7:0] initial value. Therefore, PWM5DUTY value must be less than or equal to TMR3[9:0]. Besides, user needs to set P5CR1 (T3EN, T3RL, T3OS data is as the same as T3CR1) because PWM5 and PWM3 are both shared with Timer3. When user write PWM5DUTY, write PWM5DUTY[9:8] MSB 2 bits(PWM5RH[1:0]) first and write PWM5DUTY[7:0] second, PWM5 duty register will be updated after Timer3 overflow occurs. The block diagram of PWM5 is illustrated in the following figure. www.jsmsemi.com 第５８页，共１００页 PWM5 Block Diagram uc Figure 25 to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU nd 3.12 RFC Mode NY8A054E has built-in RFC mode. Once RFC mode is enabled, the selected input pad state will take control of co the Timer1 counting. When the selected input pad is recognized as 0 state (The input pad voltage is smaller than VIL), Timer1 keeps counting. When this selected pad is recognized as 1 (The input pad voltage is larger mi than VIH), Timer1 stops counting. The following figure shows how RFC mode operates: PSEL3~0 is used to select one RFC input pad out of 14 NY8A054E pads. RFCEN is used to switch the Timer1 enable signal Se between the normal enable signal T1EN and RFC selected input state. One application of RFC mode is to measure the capacitor-resistor charging time, As the figure shows, when PSEL3~0=0x01, PA1 is selected as RFC input pad. At first the PA1 is set as output low (the voltage of PA1 is CR O discharged to 0). Next step, clear Timer1 content, set PA1 as input and enable RFC mode. Then Timer1 will start counting, and the RC circuit will start charging PA1. As PA1 is charged to the VIH voltage, the Timer1 counting is stopped because PA1 input is high. The Timer1 content will show the RC circuit charging time. JS MI (Note: Timer1 is down-count.) Figure 26 RFC Block Diagram www.jsmsemi.com 第５９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.13 IR Carrier The IR carrier will be generated after register bit IREN (IRCR[0]) is set to 1. Moreover, PB1 will become output pin automatically. When IREN is clear to 0, PB1 will become general I/O pin as it was configured. The IR carrier frequency is selectable by register bit IRF57K (IRCR[1]). When IRF57K is 1, IR carrier frequency is 57KHz. When IRF57K is 0, IR carrier frequency is 38KHz. Because IR carrier frequency is derived from high frequency system oscillation FHOSC, it is necessary to specify what frequency is used as system oscillation when external crystal is used. Register bit IROSC358M (IRCR[7]) is used to provide NY8A054E this information. to r When IROSC358M is 1, frequency of external crystal is 3.58MHz and when IROSC358M is 0, frequency of external crystal is 455KHz. When internal high frequency oscillation is adopted, this register will be ignored, and it will provide 4MHz clock to IR module. uc The active state (polarity) of IR carrier is selectable according to PB1 output data. When register bit IRCSEL (IRCR[2]) is 1, IR carrier will be present on pin PB1 when its output data is 0. When register bit IRCSEL nd (IRCR[2]) is 0, IR carrier will be present on pin PB1 when its output data is 1. The polarity of IR carrier is shown Se mi co in the following figure. Figure 27 Polarity of IR Carrier vs. Output Data CR O 3.14 Low Voltage Detector (LVD) NY8A054E low voltage detector (LVD) built-in precise band-gap reference for accurately detecting VDD level. If LVDEN (register PCON[5]) =1 and VDD voltage value falls below LVD voltage which is selected by LVDS[3:0] as JS MI table shown below, the LVD output will become low. If the LVD interrupt is enabled, the LVD interrupt flag will be high and if GIE=1 it will force the program to execute interrupt service routine. Moreover, LVD real-state output can be polled by register PCON1[6]. The following is LVD block diagram: PCON[5] LVDS + LVD output Bandgap PCON1[6] - D INV Figure 28 LVDIF C LVD block diagram www.jsmsemi.com 第６０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 0001 2.0V 0010 2.2V 0011 2.4V 0100 2.6V 0101 2.8V 0110 2.9V 0111 3.0V 1000 3.15V 1001 3.30V 1010 3.45V 1011 3.60V 1100 3.75V 1101 3.90V 1110 4.05V 1111 4.15V Table 17 LVD voltage select Se Note: uc 1.9V nd 0000 co Voltage mi LVDS[3:0] to r The following table is LVD voltage select table. The hysteresis voltage (from low to high) of LVD is about 0.1V. In battery charging applications (detected voltage is from low to high), CR O the LVD voltage select table should be as followed: LVDS[3:0] Voltage 0000 (1.9+0.1) V JS MI 0001 (2.0+0.1) V 0010 (2.2+0.1) V 0011 (2.4+0.1) V 0100 (2.6+0.1) V 0101 (2.8+0.1) V 0110 (2.9+0.1) V 0111 (3.0+0.1) V 1000 (3.15+0.1) V 1001 (3.30+0.1) V 1010 (3.45+0.1) V 1011 (3.60+0.1) V 1100 (3.75+0.1) V 1101 (3.90+0.1) V www.jsmsemi.com 第６１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU LVDS[3:0] Voltage 1110 (4.05+0.1) V 1111 (4.15+0.1) V The LVD control flow is as the following: Step1: Select LVD voltage by LVDS[3:0] Step2: Set CMPCR = 0x0A Step3: Set PCOM[5]=1 Step4: Check LVD status by PCON1[6] to r (enable LVD) Note: If LVD voltage LVDS[3:0] is changed, user must wait at least 50us(@FHOSC=1MHz) to get correct uc LVD status by PCON1[6] nd 3.15 Voltage Comparator NY8A054E provides voltage comparator and internal reference voltage with various analog comparing mode. co The comparator non-inverting and inverting input can share with GPIO. CMPEN (register PCON[2]) is used to enable and disable comparator. When CMPEN=0(default), comparator is mi disabled. When CMPEN=1, the comparator is enabled. In halt mode the comparator is disabled automatically. Se The structure of comparator is shown in the following figure: PS[1:0] 00 PA2 01 Vref 10 CR O PA0 JS MI x PCON[2] + 11 PA1 00 PA3 01 Bandgap 10 Vref 11 PCON1[6] - NS[1:0] Figure 29 Comparator block diagram www.jsmsemi.com 第６２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.15.1 Comparator Reference Voltage (Vref) The internal reference voltage Vref is built by series resistance to provide different level of reference voltage. RBIAS_H and RBIAS_L are used to select the maximum and minimum values of Vref, and LVDS[3:0] are used to select one of 16 voltage levels. VDD R1 R2 R15 R16 to r R0 RBIAS_H MUX nd LVDS[3:0] uc RBIAS_L Vref hardware connection mi Figure 30 co Vref Se The Vref is determined by RBIAS_H, RBIAS_L and LVDS[3:0]. The LVDS[3:0] is used to select one out of 16 reference voltages, the table shown below. RBIAS_H=1 RBIAS_L=0 RBIAS_H=0 RBIAS_L=1 RBIAS_H=1 RBIAS_L=1 0000 65/128 VDD 31/128 VDD 54/128 VDD 0001 62/128 VDD 29/128 VDD 50/128 VDD 0010 56/128 VDD 25/128 VDD 43/128 VDD 0011 51/128 VDD 22/128 VDD 38/128 VDD 0100 48/128 VDD 19/128 VDD 33/128 VDD 0101 44/128 VDD 17/128 VDD 29/128 VDD 0110 43/128 VDD 16/128 VDD 28/128 VDD 0111 41/128 VDD 15/128 VDD 26/128 VDD 1000 39/128 VDD 14/128 VDD 23/128 VDD 1001 37/128 VDD 12/128 VDD 21/128 VDD 1010 36/128 VDD 11/128 VDD 19/128 VDD 1011 34/128 VDD 10/128 VDD 18/128 VDD 1100 33/128 VDD 9/128 VDD 16/128 VDD JS MI CR O LVDS[3:0] www.jsmsemi.com 第６３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 1101 31/128 VDD 8/128 VDD 14/128 VDD 1110 31/128 VDD 8/128 VDD 13/128 VDD 1111 30/128 VDD 7/128 VDD 12/128 VDD Table 18 The reference voltage Vref selection table Note: The deviation of Vref is ±0.1V. to r The non-inverting input of the comparator is determined by PS[1:0] (register CMPCR[3:2]). 00 PA0 01 PA2 10 Vref 11 --- nd Non-inverting input co PS[1:0] uc The table is shown below mi Table 19 Non-inverting input select The table is shown below Se The inverting input of the comparator is determined by NS[1:0] (register CMPCR[1:0]). Inverting input 00 PA1 CR O NS[1:0] PA3 10 Bandgap (0.6V) 11 Vref JS MI 01 Table 20 Inverting input select Comparator output can be polled by PCON1[6]. 3.16 Watch-Dog Timer (WDT) There is an on-chip free-running oscillator in NY8A054E which is used by WDT. As this oscillator is independent of other oscillation circuits, WDT may still keep working during Standby mode and Halt mode. WDT can be enabled or disabled by a configuration word. When WDT is enabled by configuration word, its operation still can be controlled by register bit WDTEN (PCON[7]) during program execution. Moreover, the www.jsmsemi.com 第６４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU mechanism after WDT time-out can reset NY8A054E or issue an interrupt request which is determined by another configuration word. At the same time, register bit /TO (STATUS[4]) will be clear to 0 after WDT time-out. The baseline of WDT time-out period can be 3.5 ms, 15 ms, 60 ms or 250 ms which is determined by two configuration words. The time-out period can be lengthened if Prescaler0 is assigned to WDT. Prescaler0 will be assigned to WDT by writing 1 to register bit PS0WDT. The dividing rate of Prescaler0 for WDT is determined by register bits PS0SEL[2:0] and depends on WDT time-out mechanism. The dividing rate is from 1:1 to 1:128 if WDT time-out will reset NY8A054E and dividing rate is from 1:2 to 1:256 if WDT time-out will interrupt to r NY8A054E. When Prescaler0 is assigned to WDT, the execution of instruction CLRWDT will clear WDT, Prescaler0 and set /TO flag to 1. uc If user selects interrupt for WDT time-out mechanism, register bit WDTIF (INTF[6]) will set to 1 after WDT is expired. It may generate an interrupt request if register bit WDTIE (INTE[6]) and GIE both set to 1. WDTIF will nd not be clear until firmware writes 0 to WDTIF. co 3.17 Interrupt NY8A054E provides two kinds of interrupt: one is software interrupt and the other is hardware interrupt. Software interrupt is caused by execution of instruction INT. There are 8 hardware interrupts: mi  Timer0 overflow interrupt.  Timer3 underflow interrupt.  WDT timeout interrupt.  PA/PB input change interrupt. Se  Timer1 underflow interrupt. CR O  External 0 interrupt.  External 1 interrupt  LVD interrupt. JS MI GIE is global interrupt enable flag. It has to be 1 to enable hardware interrupt functions. GIE can be set by ENI instruction and clear to 0 by DISI instruction. After instruction INT is executed, no matter GIE is set or clear, the next instruction will be fetched from address 0x001. At the same time, GIE will be clear to 0 by NY8A054E automatically. This will prevent nested interrupt from happening. The last instruction of interrupt service routine of software interrupt has to be RETIE. Execution of this instruction will set GIE to 1 and return to original execution sequence. While any of hardware interrupts is occurred, the corresponding bit of interrupt flag will be set to 1. This bit will not be clear until firmware writes 0 to this bit. Therefore user can obtain information of which event causes hardware interrupt by polling the corresponding bit of interrupt flag. Note that only when the corresponding interrupt enable bit is set to 1, will the corresponding interrupt flag be read. And if the corresponding interrupt enable bit is set to 1 and GIE is also 1, hardware interrupt will occur and next instruction will be fetched from 0x008. At the same time, the register bit GIE will be clear by NY8A054E automatically. If user wants to www.jsmsemi.com 第６５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU implement nested interrupt, instruction ENI can be used as the first instruction of interrupt service routine which will set GIE to 1 again and allow other interrupt events to interrupt NY8A054E again. Instruction RETIE has to be the last instruction of interrupt service routine which will set GIE to 1 and return to original execution sequence. It should be noted that ENI instruction cannot be placed right before RETIE instruction because ENI instruction in interrupt service routine will trigger nested interrupt, but RETIE will clear internal interrupt processing after jump out of ISR, so it is possible for interrupt flag to be falsely cleared. to r 3.17.1 Timer0 Overflow Interrupt Timer0 overflow (from 0x00 to 0xFF) will set register bit T0IF. This interrupt request will be serviced if T0IE uc and GIE are set to 1. 3.17.2 Timer1 Underflow Interrupt nd Timer1 underflow (from 0x3FF to 0x00) will set register bit T1IF. This interrupt request will be serviced if T1IE co and GIE are set to 1. 3.17.3 Timer3 Underflow Interrupt mi Timer3 underflow (from 0x3FF to 0x00) will set register bit T3IF. This interrupt request will be serviced if T3IE 3.17.4 WDT Timeout Interrupt Se and GIE are set to 1. When WDT is timeout and the configuration word selects WDT timeout will generate interrupt request, it will CR O set register bit WDTIF. This interrupt request will be serviced if WDTIE and GIE are set to 1. 3.17.5 PA/PB Input Change Interrupt JS MI When PAx, 0 ≤ x ≤ 7, PBy, 0 ≤ y ≤ 5 is configured as input pin and corresponding register bit WUPAx, WUPBx is set to 1, a level change on these selected I/O pin(s) will set register bit PABIF. This interrupt request will be serviced if PABIE and GIE are set to 1. Note when PB0 or PB1 is both set as level change interrupt and external interrupt, the external interrupt enable EIS0 or EIS1=1 will disable PB0 or PB1 level change operation. 3.17.6 External 0 Interrupt According to the configuration of EIS0=1 and INTEDG, the selected active edge on I/O pin PB0 will set register bit INT0IF and this interrupt request will be served if INT0IE and GIE are set to 1. www.jsmsemi.com 第６６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.17.7 External 1 Interrupt According to the configuration of EIS1=1 and INTEDG, the selected active edge on I/O pin PB1 will set register bit INT1IF and this interrupt request will be served if INT1IE and GIE are set to 1. 3.17.8 LVD Interrupt When VDD level falls below LVD voltage, LVD flag will go from high to low, and set the register bit LVDIF=1. to r This interrupt request will be serviced if LVDIE and GIE are set to 1. 3.18 Oscillation Configuration uc Because NY8A054E is a dual-clock IC, there are high oscillation (FHOSC) and low oscillation (FLOSC) that can be selected as system oscillation (FOSC). The oscillators which could be used as FHOSC are internal high RC oscillator nd (I_HRC), external high crystal oscillator (E_HXT) and external crystal oscillator (E_XT). The oscillators which could JS MI CR O Se mi co be used as FLOSC are internal low RC oscillator (I_LRC) and external low crystal oscillator (E_LXT). Figure 31 Oscillation Configuration of NY8A054E There are two configuration words to determine which oscillator will be used as FHOSC. When I_HRC is selected as FHOSC, I_HRC output frequency is determined by three configuration words and it can be 1M, 2M, 4M, 8M, 16M or 20MHz. Moreover, external crystal oscillator pads PA6 and PA7 can be used as I/O pins. On the other www.jsmsemi.com 第６７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU hand, PA7 can be the output pin of instruction clock according to a configuration word’s setting. If FHOSC required external crystal whose frequency ranges from 8MHz to 20MHz, E_HXT is recommended. If FHOSC required external crystal whose frequency ranges from 455KHz to 6MHz, E_XT is recommended. When E_HXT or E_XT is adopted, PA6/PA7 cannot be used as I/O pins. They must be used as crystal output pin and input pin. PA7 is crystal output pin (Xout) and PA6 is crystal input pin (Xin). There is one configuration word to determine which oscillator will be used as FLOSC. When I_LRC is selected, its frequency is centered on 32768Hz. If FLOSC required external crystal, E_LXT is selected and only 32768Hz to r crystal is allowed. When E_LXT is adopted, PA6/PA7 cannot be used as I/O pins. They must be used as crystal output pin and input pin. PA7 is crystal output pin (Xout) and PA6 is crystal input pin (Xin). The dual-clock FHOSC FLOSC 1 I_HRC I_LRC 2 E_HXT or E_XT I_LRC 3 I_HRC E_LXT Dual-clock combinations co Table 21 nd No. uc combinations of FHOSC and FLOSC are listed below. When E_HXT, E_XT or E_LXT is used as one of oscillations, the crystal or resonator is connected to Xin and mi Xout to provide oscillation. Moreover, a resistor and two capacitors are recommended to connect as following figure in order to provide reliable oscillation, refer to the specification of crystal or resonator to adopt appropriate E_HXT JS MI E_XT E_LXT Table 22 Crystal Frequency (Hz) C1, C2 (pF) 16M 5 ~ 10 10M 5 ~ 30 8M 5 ~ 20 4M 5 ~ 30 1M 5 ~ 30 455K 10 ~ 100 32768 5 ~ 30 CR O Oscillation Mode Se C1 or C2 value. The recommended value of C1 and C2 are listed in the table below. Recommended C1 and C2 Value for Different Kinds of Crystal Oscillation For 20MHZ resonator in 2 clock CPU cycle mode, an 18pF C2 capacitor is a must. To get precise and stable 32.768k frequency, choosing the right C1 and C2 value is important. You need to match the C1 / C2 capacitance to the specific crystal you chose. Every crystal datasheet lists something called the Load Capacitance (CL), C1 and C2 value is chosen with the following formula: C1=C2=2*CL-Cbt Where Cbt is the NY8A054E crystal pad built-in capacitance, which is about 5pF. For example, for crystal CL=12.5P, C1=C2=20pF is recommended. www.jsmsemi.com 第６８页，共１００页 Figure 32 to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Connection for External Crystal Oscillation uc Either FHOSC or FLOSC can be selected as system oscillation FOSC according to the value of register bit SELHOSC (OSCCR[0]). When SELHOSC is 1, FHOSC is selected as FOSC. When SELHOSC is 0, FLOSC is selected as FOSC. nd Once FOSC is determined, the instruction clock FINST can be FOSC/2 or FOSC/4 according to value of a co configuration word. mi 3.19 Operating Mode NY8A054E provides four kinds of operating mode to tailor all kinds of application and save power consumptions. These operating modes are Normal mode, Slow mode, Standby mode and Halt mode. Normal mode is Se designated for high-speed operating mode. Slow mode is designated for low-speed mode in order to save power consumption. At Standby mode, NY8A054E will stop almost all operations except Timer0/Timer1/ Timer3 WDT in order to wake-up periodically. At Halt mode, NY8A054E will sleep until external event or WDT trigger IC JS MI CR O to wake-up. The block diagram of four operating modes is described in the following figure. www.jsmsemi.com 第６９页，共１００页 JS MI CR O Se mi co nd uc to r NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Figure 33 Four Operating Modes www.jsmsemi.com 第７０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.19.1 Normal Mode After any Reset Event is occurred and Reset Process is completed, NY8A054E will begin to execute program under Normal mode or Slow mode. Which mode is selected after Reset Process is determined by the Startup Clock configuration word. If Startup Clock=fast, NY8A054E will enter Normal mode, if Startup Clock=Slow, NY8A054E will enter Slow mode. At Normal mode, FHOSC is selected as system oscillation in order to provide highest performance and its power consumption will be the largest among four operating modes. After power on or any reset trigger is released, NY8A054E will enter Normal mode after reset  to r process is completed. Instruction execution is based on FHOSC and all peripheral modules may be active according to corresponding module enable bit. The FLOSC is still active and running.  IC can switch to Slow mode by writing 0 to register bit SELHOSC (OSCCR[0]).  IC can switch to Standby mode or Halt mode by programming register bits OPMD[1:0] (OSCCR[3:2]).  For real time clock applications, the NY8A054E can run in normal mode, at the same time the co nd uc  low-frequency clock Low Oscillator Frequency connects to Timer0 clock. This is made possible by mi setting LCKTM0 to 1 and corresponding configuration word Timer0 source setting to 1. Se 3.19.2 Slow Mode NY8A054E will enter Slow mode by writing 0 to register bit SELHOSC. At Slow mode, FLOSC is selected as system oscillation in order to save power consumption but still keep IC running. However, FHOSC will not be disabled automatically by NY8A054E. Therefore user can write 0 to register bit STPHOSC (OSCCR[1]) in slow CR O mode to reduce power consumption further. But it is noted that it is forbidden to enter slow mode and stop FHOSC at the same time, one must enter slow mode first, then disable FHOSC, or the program may hang on.  Instruction execution is based on FLOSC and all peripheral modules may be active according to JS MI corresponding module enable bit.  FHOSC can be disabled by writing 1 to register bit STPHOSC.  IC can switch to Standby mode or Halt mode by programming register bits OPMD[1:0].  IC can switch to Normal mode by writing 1 to SELHOSC. www.jsmsemi.com 第７１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.19.3 Standby Mode NY8A054E will enter Standby mode by writing 10b to register bits OPMD[1:0]. At Standby mode, however, FHOSC will not be disabled automatically by NY8A054E and user has to enter slow mode and write 1 to register bit STPHOSC in order to stop FHOSC oscillation. Most of NY8A054E peripheral modules are disabled but Timer can be still active if register bit T0EN/T1EN/T3EN is set to 1. Therefore NY8A054E can wake-up after Timer0/Timer1/Timer3 is expired. The expiration period is determined by the register  to r TMR0/TMR1[9:0]/TMR3[9:0], FINST and other configurations for Timer0/Timer1/Timer3. Instruction execution is stop and some peripheral modules may be active according to corresponding module enable bit. F HOSC can be disabled by writing 1 to register bit STPHOSC.  The FLOSC is still active and running.  IC can wake-up from Standby mode if any of the following conditions: nd uc  (a) Timer0/Timer1/Timer3 (overflow/underflow) interrupt co (b) WDT timeout interrupt (c) PA/PB input change interrupt mi (d) INT0/INT1 external interrupt is happened.  After wake-up from Standby mode, IC will return to Normal mode if SELHOSC=1, IC will return to Slow mode if SELHOSC=0. It is not recommended to change oscillator mode (normal to slow / slow to normal) and enter standby CR O  Se (e) LVD interrupt mode at the same time. JS MI 3.19.4 Halt Mode NY8A054E will enter Halt mode by executing instruction SLEEP or writing 01b to register bits OPMD[1:0]. After entering Halt mode, register bit /PD (STATUS[3]) will be clear to 0, register bit /TO (STATUS[4]) will be set to 1 and WDT will be clear but keep running. At Halt mode, all of peripheral modules are disabled, instruction execution is stop and NY8A054E can only wake-up by some specific events. Therefore, Halt mode is the most power saving mode provided by NY8A054E.  Instruction execution is stop and all peripheral modules are disabled.  FHOSC and FLOSC are both disabled automatically.  IC can wake-up from Halt mode if any of the following conditions: (a) WDT timeout interrupt (b) PA/PB input change interrupt www.jsmsemi.com 第７２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU (c) INT0/INT1 external interrupt is happened.  After wake-up from Halt mode, IC will return to Normal mode if SELHOSC=1, IC will return to Slow mode if SELHOSC=0. Note: Users can change STPHOSC and enter Halt mode in the same instruction.  It is not recommended to change oscillator mode (normal to slow or slow to normal) and enter halt mode at the same time. to r 3.19.5 Wake-up Stable Time The wake-up stable time of Halt mode is determined by Configuration word: High Oscillator Frequency or Low Oscillator Frequency. If one of E_HXT, E_XT and E_LXT is selected, the wake-up period would be uc 512*FOSC. And if no XT mode are selected, 16*Fosc would be set as wake up period. On the other hand, there is no need of wake-up stable time for Standby mode because either FHOSC or FLOSC is still running at nd Standby mode. Before NY8A054E enter Standby mode or Halt mode, user may execute instruction ENI. At this condition, co NY8A054E will branch to address 0x008 in order to execute interrupt service routine after wake-up. If instruction DISI is executed before entering Standby mode or Halt mode, the next instruction will be executed mi after wake-up. Se 3.19.6 Summary of Operating Mode The summary of four operating modes is described in the following table. Normal Slow Standby Halt FHOSC Enabled STPHOSC STPHOSC Disabled FLOSC Enabled Enabled Enabled Disabled Instruction Execution Executing Executing Stop Stop Timer0/1/3 TxEN TxEN TxEN Disabled WDT Option and WDTEN Option and WDTEN Option and WDTEN Option and WDTEN Module enable bit All disabled JS MI CR O Mode Other Modules Wake-up Source Module enable bit Module enable bit - - Table 23 - Timer0/1/3 overflow - WDT timeout - WDT timeout - PA/PB input change - PA/PB input change - INT0/1 - INT0/1 - LVD interrupt Summary of Operating Modes www.jsmsemi.com 第７３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 3.20 Reset Process NY8A054E will enter Reset State and start Reset Process when one of following Reset Event is occurred:  Power-On Reset (POR) is occurred when VDD rising is detected.  Low-Voltage Reset (LVR) is occurred when operating VDD is below pre-defined voltage.  Pin RSTb is low state.  WDT timeout reset. to r Moreover, value of all registers will be initialized to their initial value or unchanged if its initial value is unknown. The status bits /TO and /PD could be initialized according to which event causes reset. The /TO and /PD value /PD 1 1 unchanged unchanged RSTb reset from Halt mode 1 WDT reset from non-Halt mode 0 WDT reset from Halt mode 0 SLEEP executed 1 CLRWDT executed 1 POR, LVR 1 0 0 1 Summary of /TO & /PD Value and its Associated Event Se Table 24 1 mi RSTb reset from non-Halt mode co Event uc /TO nd and its associated event is summarized in the table below. After Reset Event is released, NY8A054E will start Reset Process. It will wait certain amount of period for oscillation stable no matter what kind of oscillator is adopted. This period is called power-up reset time and is determined by three-bit configuration words which can be 140us, 4.5ms, 18ms, 72ms or 288ms. After power-up CR O reset time, NY8A054E will wait for further oscillator start-up time (OST) before it starts to execute program. OST=1 clock cycle of FOSC if the previous power-up time is 140us, OST=16 clock cycles of FOSC if the previous JS MI power-up time is 4.5ms, 18ms, 72ms or 288ms. Figure 34 Block diagram of on-chip reset circuit www.jsmsemi.com 第７４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU For slow VDD power-up, it is recommended to use RSTb reset, as the following figure.  It is recommended the R value should be not greater than 40KΩ.  The R1 value=100Ω to 1KΩ will prevent high current, ESD or Electrical overstress flowing into reset pin. Block Diagram of Reset Application JS MI CR O Se mi co nd Figure 35 uc to r  The diode helps discharge quickly when power down. www.jsmsemi.com 第７５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 4. Instruction Set NY8A054E provides 55 powerful instructions for all kinds of applications. Inst. OP 1 Operation 2 Cyc. Flag Arithmetic Instructions Inst. OP 1 Operation 2 Cyc. Flag Arithmetic Instructions R d dest = ACC & R 1 Z ADDAR R d dest = R + ACC 1 Z, DC, C IORAR R d dest = ACC | R 1 Z SUBAR R d dest = R + (~ACC) 1 Z, DC, C XORAR R d dest = ACC ⊕ R 1 Z ADCAR R d dest = R + ACC + C 1 Z, DC, C ANDIA i ACC = ACC & i 1 Z SBCAR R d dest = R + (~ACC) + C 1 Z, DC, C IORIA i ACC = ACC | i 1 Z ADDIA i ACC = I + ACC 1 Z, DC, C XORIA i ACC = ACC ⊕ i 1 Z SUBIA i ACC = i + (~ACC) 1 Z, DC, C RRR R d Rotate right R 1 C ADCIA i ACC = i + ACC + C 1 Z, DC, C RLR R d Rotate left R 1 C SBCIA i ACC = i + (~ACC) + C 1 Z, DC, C BSR R bit Set bit in R 1 - DAA Decimal adjust for ACC 1 C BCR R bit Clear bit in R 1 - CMPAR Compare R with ACC 1 Z, C INCR R d Increase R 1 Z CLRA Clear ACC 1 Z DECR R d Decrease R 1 Z CLRR Clear R 1 Z COMR R d dest = ~R 1 NOP No operation 1 - uc nd co R mi Se Conditional Instructions Z to r ANDAR Other Instructions R bit Test bit in R, skip if clear 1 or 2 - SLEEP Go into Halt mode 1 /TO, /PD BTRSS R bit Test bit in R, skip if set 1 or 2 - CLRWDT Clear Watch-Dog Timer 1 /TO, /PD INCRSZ R d Increase R, skip if 0 1 or 2 - ENI Enable interrupt 1 - DECRSZ R d Decrease R, skip if 0 1 or 2 - DISI Disable interrupt 1 - INT Software Interrupt 3 - RET Return from subroutine 2 - 2 - 2 - CR O BTRSC Data Transfer Instructions R Move ACC to R 1 - MOVR R Move R 1 Z MOVIA i Move immediate to ACC 1 - SWAPR R Swap halves R 1 - IOST F Load ACC to F-page SFR 1 - IOSTR F Move F-page SFR to ACC 1 - CALLA Call subroutine by ACC 2 - SFUN S Load ACC to S-page SFR 1 - GOTOA unconditional branch by ACC 2 - SFUNR S Move S-page SFR to ACC 1 - CALL adr Call subroutine 2 - T0MD Load ACC to T0MD 1 - GOTO adr unconditional branch 2 - T0MDR Move T0MD to ACC 1 - LCALL adr Call subroutine 2 - TABLEA Read ROM 2 - LGOTO adr unconditional branch 2 - d JS MI MOVAR d Table 25 Return from interrupt and RETIE RETIA enable interrupt i Return, place immediate in ACC Instruction Set www.jsmsemi.com 第７６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU ACC: Accumulator. adr: immediate address. bit: bit address within an 8-bit register R. C: Carry/Borrow bit C=1, carry is occurred for addition instruction or borrow is not occurred for subtraction instruction. C=0, carry is not occurred for addition instruction or borrow is occurred for subtraction instruction. d: Destination to r If d is “0”, the result is stored in the ACC. If d is “1”, the result is stored back in register R. DC: Digital carry flag. uc dest: Destination. F: F-page SFR, F is 0x5 ~ 0XF. nd i: 8-bit immediate data. PC: Program Counter. co PCHBUF: High Byte Buffer of Program Counter. /PD: Power down flag bit mi /PD=1, after power-up or after instruction CLRWDT is executed. /PD=0, after instruction SLEEP is executed. R: R-page SFR, R is 0x0 ~0x7F. S: S-page SFR, S is 0x0 ~ 0x1F. Se Prescaler: Prescaler0 dividing rate. CR O T0MD: T0MD register. TBHP: The high-Byte at target address in ROM. TBHD: Store the high-Byte data at target address in ROM. /TO: Time overflow flag bit JS MI /TO=1, after power-up or after instruction CLRWDT or SLEEP is executed. /TO=0, WDT timeout is occurred. WDT: Watchdog Timer Counter. Z: Zero flag . www.jsmsemi.com 第７７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU ADCAR Add ACC and R with Carry ADDAR Add ACC and R Syntax: ADCAR Syntax: ADDAR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: R + ACC + C → dest Operation: ACC + R → dest Status affected: Z, DC, C Status affected: Z, DC, C Description: Add the contents of ACC and register R with Carry. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. 1 Description: Add the contents of ACC and R. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: ADDAR R, d before executing instruction: ACC=0x12, R=0x34,C=1, d=1, after executing instruction: R=0x46, ACC=0x12, C=0. Syntax: Add ACC and Immediate with Carry ADCIA i Operand: 0 ≤ I ＜ 255 Operation: to r ADCIA uc ADCAR R, d before executing instruction: ACC=0x12, R=0x34, C=1, d=1, after executing instruction: R=0x47, ACC=0x12, C=0. R, d nd Example: co Cycle R, d Add ACC and Immediate Syntax: ADDIA Operand: 0 ≤ i ＜ 255 ACC + i + C → ACC Operation: ACC + i → ACC Status affected: Z, DC, C Status affected: Z, DC, C Description: Add the contents of ACC and the 8-bit immediate data i with Carry. The result is placed in ACC. 1 Description: Add the contents of ACC with the 8-bit immediate data i. The result is placed in ACC. Cycle: 1 Example: ADDIA i before executing instruction: ACC=0x12, i=0x34, C=1, after executing instruction: ACC=0x46, C=0. Example: Se CR O JS MI Cycle: mi ADDIA ADCIA i before executing instruction: ACC=0x12, i=0x34, C=1, after executing instruction: ACC=0x47, C=0. www.jsmsemi.com i 第７８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU ANDAR AND ACC and R Clear Bit in R Syntax: BCR R, bit ANDAR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operand: 0 ≤ R ≤ 127 0 ≤ bit ≤ 7 Operation: ACC & R → dest Operation: 0 → R[bit] Status affected: Z Status affected: -- Description: The content of ACC is AND’ed with R. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Description: Clear the bitth position in R. Cycle: 1 Example: BCR R, B2 before executing instruction: R=0x5A, B2=0x3, after executing instruction: R=0x52. 1 Example: ANDAR R, d before executing instruction: ACC=0x5A, R=0XaF, d=1. after executing instruction: R=0x0A, ACC=0x5A, Z=0. co nd Cycle: to r Syntax: uc R, d BCR AND Immediate with ACC Syntax: ANDIA Operand: 0 ≤ i ＜ 255 Operation: ACC & i → ACC Status affected: Z Description: The content of ACC register is BSR Set Bit in R Syntax: BSR R, bit Operand: 0 ≤ R ≤ 127 0 ≤ bit ≤ 7 Operation: 1 → R[bit] Status affected: -- Description: Set the bitth position in R. Cycle: 1 Example: BSR R, B2 before executing instruction: R=0x5A, B2=0x2, after executing instruction: R=0x5E. mi ANDIA CR O Se i AND’ed with the 8-bit immediate data i. The result is placed in JS MI ACC. Cycle: 1 Example: ANDIA i before executing instruction: ACC=0x5A, i=0XaF, after executing instruction: ACC=0x0A, Z=0. www.jsmsemi.com 第７９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU BTRSC Test Bit in R and Skip if Clear CALL Call Subroutine Syntax: BTRSC Syntax: CALL Operand: 0 ≤ R ≤ 127 0 ≤ bit ≤ 7 Operand: 0 ≤ adr ＜ 255 Operation: Skip next instruction, if R[bit] = 0. -- Operation: PC + 1 → Top of Stack {PCHBUF, adr} → PC Status affected: -- If R[bit] = 0, the next instruction which is already fetched is discarded and a NOP is executed instead. Therefore it makes this instruction a two-cycle instruction. 1 or 2(skip) Description: The return address (PC + 1) is pushed onto top of Stack. The 8-bit immediate address adr is loaded into PC[7:0] and PCHBUF[2:0] is loaded into PC[10:8]. 2 Example: BTRSC R, B2 Instruction1 Instruction2 before executing instruction: R=0x5A, B2=0x2, after executing instruction: because R[B2]=0, instruction1 will not be executed, the program will start execute instruction from instruction2. Example: BTRSS Test Bit in R and Skip if Set CALLA Call Subroutine Syntax: BTRSS Syntax: CALLA Operand: 0 ≤ R ≤ 127 0 ≤ bit ≤ 7 Operand: -- Operation: PC + 1 → Top of Stack {TBHP, ACC} → PC Status affected: -- Description: The return address (PC + 1) is pushed onto top of Stack. The contents of TBHP[2:0] is loaded into PC[10:8] and ACC is loaded into PC[7:0]. Cycle: 2 Example: CALLA before executing instruction: TBHP=0x02, ACC=0x34. PC=A0. Stack pointer=1. after executing instruction: PC=0x234, Stack[1]=A0+1, Stack pointer=2 Operation: Status affected: R, bit Skip next instruction, if R[bit] = 1. -If R[bit] = 1, the next instruction which is already fetched is discarded and a NOP is executed instead. Therefore it makes this instruction a two-cycle instruction. 1 or 2(skip) JS MI Description: Cycle: Example: BTRSS R, B2 Instruction2 Instruction3 before executing instruction: R=0x5A, B2=0x3, after executing instruction: because R[B2]=1, instruction2 will not be executed, the program will start execute instruction from instruction3. to r adr CALL SUB before executing instruction: PC=A0. Stack pointer=1 after executing instruction: PC=address of SUB, Stack[1] = A0+1, Stack pointer=2. co nd uc Cycle: mi Cycle: Se Description: CR O Status affected: R, bit www.jsmsemi.com 第８０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Clear ACC CLRWDT Clear Watch-Dog Timer Syntax: CLRA Syntax: CLRWDT Operand: -- Operand: -- Operation: 00h → ACC 1→ Z Operation: Status affected: Z Description: ACC is clear and Z is set to 1. 00h → WDT, 00h → WDT prescaler 1 → /TO 1 → /PD Cycle: 1 Status affected: /TO, /PD Example: CLRA before executing instruction: ACC=0x55, Z=0. after executing instruction: ACC=0x00, Z=1. Description: Executing CLRWDT will reset WDT, Prescaler0 if it is assigned to WDT. Moreover, status bits /TO and /PD will be set to 1. Cycle: 1 Example: CLRWDT before executing instruction: /TO=0 after executing instruction: /TO=1 co nd uc to r CLRA Clear R Syntax: CLRR Operand: 0 ≤ R ≤ 127 Operation: 00h → R 1→Z Status affected: Description: Z CR O Se R The content of R is clear and Z is set to 1. Cycle: 1 Example: CLRR R before executing instruction: R=0x55, Z=0. after executing instruction: R=0x00, Z=1. JS MI COMR Complement R Syntax: COMR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: ~R → dest Status affected: Z Description: The content of R is complemented. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: COMR, d before executing instruction: R=0XA6, d=1, Z=0. after executing instruction: R=0x59, Z=0. mi CLRR www.jsmsemi.com R, d 第８１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU CMPAR Compare ACC and R DECR Decrease R Syntax: CMPAR Syntax: DECR Operand: 0 ≤ R ≤ 127 Operand: Operation: R–- ACC → (No restore) 0 ≤ R ≤ 127 d = 0, 1. Status affected: Z, C Operation: R–- 1 → dest Description: Compare ACC and R by subtracting ACC from R with 2’s complement representation. The content of ACC and R is not changed. Status affected: Z Description: Decrease R. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: DECR R, d before executing instruction: R=0x01, d=1, Z=0. after executing instruction: R=0x00, Z=1. Example: CMPAR R before executing instruction: R=0x34, ACC=12, Z=0, C=0. after executing instruction: R=0x34, ACC=12, Z=0, C=1. DAA Syntax: Convert ACC Data Format from Hexadecimal to Decimal DAA Operand: -- Operation: ACC(hex) → ACC(dec) Status affected: C Description: Convert ACC data format from hexadecimal to decimal after addition operation and restore result to ACC. DAA instruction must be placed immediately after addition operation if decimal format is required. Please note that interrupt should be disabled before addition instruction and enabled after DAA instruction to avoid unexpected result. 1 to r 1 Example: DECRSZ Decrease R, Skip if 0 Syntax: DECRSZ Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: R–- 1 → dest, Skip if result = 0 Status affected: -- Description: Decrease R first. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. If result is 0, the next instruction which is already fetched is discarded and a NOP is executed instead. Therefore it makes this instruction a two-cycle instruction. 1 or 2(skip) mi Se CR O JS MI Cycle: co nd Cycle: R, d uc R DISI ADDAR R,d DAA ENI before executing instruction: ACC=0x28, R=0x25, d=0. after executing instruction: ACC=0x53, C=0. Cycle: Example: www.jsmsemi.com R, d DECRSZ R, d instruction2 instruction3 before executing instruction: R=0x1, d=1, Z=0. after executing instruction: R=0x0, Z=1, and instruction will skip instruction2 execution because the operation result is zero. 第８２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU DISI Disable Interrupt Globally GOTO Unconditional Branch Syntax: DISI Syntax: GOTO Operand: -- Operand: 0 ≤ adr ＜ 511 Operation: Disable Interrupt, 0 → GIE Status affected: -- Operation: {PCHBUF, adr} → PC Description: GIE is clear to 0 in order to disable all interrupt requests. Status affected: -- Description: Cycle: 1 Example: DISI before executing instruction: GIE=1, After executing instruction: GIE=0. GOTO is an unconditional branch instruction. The 9-bit immediate address adr is loaded into PC[8:0] and PCHBUF[2:1] is loaded into PC[10:9]. Cycle: 2 Example: GOTO Level before executing instruction: PC=A0. after executing instruction: PC=address of Level. Syntax: ENI Operand: -- Operation: Enable Interrupt, 1 → GIE Status affected: Description: -- GIE is set to 1 in order to enable all interrupt requests. 1 Example: ENI before executing instruction: GIE=0, After executing instruction: GIE=1. Unconditional Branch Syntax: GOTOA Operand: -- Operation: {TBHP, ACC} → PC Status affected: -- Description: GOTOA is an unconditional branch instruction. The content of TBHP[2:0] is loaded into PC[10:8] and ACC is loaded into PC[7:0]. 2 Cycle: Example: JS MI CR O Cycle: GOTOA mi Enable Interrupt Globally Se ENI co nd uc to r adr www.jsmsemi.com GOTOA before executing instruction: PC=A0. TBHP=0x02, ACC=0x34. after executing instruction: PC=0x234 第８３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Increase R INT Software Interrupt Syntax: INCR Syntax: INT Operand: 0 ≤ R ≤ 127 d = 0, 1. Operand: -- Operation: R + 1 → dest. Operation: PC + 1 → Top of Stack, 001h → PC Status affected: Z Status affected: -- Description: Increase R. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Description: Cycle: 1 Software interrupt. First, return address (PC + 1) is pushed onto the Stack. The address 0x001 is loaded into PC[10:0]. Example: INCR R, d before executing instruction: R=0XfF, d=1, Z=0. after executing instruction: R=0x00, Z=1. Cycle: 3 Example: INT before executing instruction: PC=address of INT code after executing instruction: PC=0x01 INCRSZ Increase R, Skip if 0 Syntax: INCRSZ Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: R + 1 → dest, Skip if result = 0 Se -- OR ACC with R Syntax: IORAR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: ACC | R → dest Status affected: Z Description: OR ACC with R. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: IORAR R, d before executing instruction: R=0x50, ACC=0XaA, d=1, Z=0. after executing instruction: R=0XfA, ACC=0XaA, Z=0. mi R, d IORAR CR O Increase R first. If d is 0, the result is stored in ACC. If d is 1, the result is stored back to R. If result is 0, the next instruction which is already fetched is discarded and a NOP is executed instead. Therefore it makes this instruction a two-cycle instruction. JS MI Status affected: Description: co nd uc R, d to r INCR Cycle: 1 or 2(skip) Example: INCRSZ R, d instruction2, instruction3. before executing instruction: R=0XfF, d=1, Z=0. after executing instruction: R=0x00, Z=1. And the program will skip instruction2 execution because the operation result is zero. www.jsmsemi.com R, d 第８４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU IORIA OR Immediate with ACC IOSTR Move F-page SFR to ACC Syntax: IORIA Syntax: IOSTR Operand: 0 ≤ i ＜ 255 Operand: 5 ≤ F ≤ 15 Operation: ACC | i → ACC Operation: F-page SFR → ACC Status affected: Z Status affected: -- Description: OR ACC with 8-bit immediate data i. The result is stored in ACC. 1 Description: Move F-page SFR F to ACC. Cycle: 1 Example: IOSTR F before executing instruction: F=0x55, ACC=0XaA. after executing instruction: F=0x55, ACC=0x55. Cycle: i IORIA i before executing instruction: i=0x50, ACC=0XaA, Z=0. after executing instruction: ACC=0XfA, Z=0. IOST Load F-page SFR from ACC Syntax: IOST Operand: 5 ≤ F ≤ 15 Operation: ACC → F-page SFR Status affected: -- Description: F-page SFR F is loaded by content of ACC. Cycle: 1 Example: IOST F before executing instruction: F=0x55, ACC=0XaA. after executing instruction: F=0XaA, ACC=0XaA. Se CR O JS MI LCALL Call Subroutine Syntax: LCALL Operand: 0 ≤ adr ≤ 2047 Operation: PC + 1 → Top of Stack, adr → PC[10:0] Status affected: -- Description: The return address (PC + 1) is pushed onto top of Stack. The 11-bit immediate address adr is loaded into PC[10:0]. Cycle: 2 Example: LCALL SUB before executing instruction: PC=A0. Stack level=1 after executing instruction: PC=address of SUB, Stack[1]= A0+1, Stack pointer =2. mi F co nd uc to r Example: F www.jsmsemi.com adr 第８５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU LGOTO Unconditional Branch MOVIA Move Immediate to ACC Syntax: LGOTO Syntax: MOVIA Operand: 0 ≤ adr ≤ 2047 Operand: 0 ≤ i ＜ 255 Operation: adr → PC[10:0]. Operation: i → ACC Status affected: Description: -- Status affected: -- Description: The content of ACC is loaded with 8-bit immediate data i. Cycle: 1 Example: MOVIA i before executing instruction: i=0x55, ACC=0XaA. after executing instruction: ACC=0x55. LGOTO Level before executing instruction: PC=A0. after executing instruction: PC=address of Level. MOVAR Move ACC to R Syntax: MOVAR Operand: 0 ≤ R ≤ 127 Operation: ACC → R Status affected: Description: -- Move content of ACC to R. Cycle: 1 Example: MOVAR R before executing instruction: R=0x55, ACC=0XaA. after executing instruction: R=0XaA, ACC=0XaA. co nd Example: to r LGOTO is an unconditional branch instruction. The 11-bit immediate address adr is loaded into PC[10:0]. 2 i uc Cycle: adr Se CR O JS MI Move R to ACC or R Syntax: MOVR Operand: Operation: 0 ≤ R ≤ 127 d = 0, 1. R → dest Status affected: Z Description: The content of R is move to destination. If d is 0, destination is ACC. If d is 1, destination is R and it can be used to check whether R is zero according to status flag Z after execution. Cycle: 1 Example: MOVR R, d before executing instruction: R=0x0, ACC=0XaA, Z=0, d=0. after executing instruction: R=0x0, ACC=0x00, Z=1. mi R MOVR www.jsmsemi.com R, d 第８６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU NOP No Operation RETIA Return with Data in ACC Syntax: NOP Syntax: RETIA Operand: -- Operand: 0 ≤ i ＜ 255 Operation: No operation. Operation: Status affected: -- i → ACC, Top of Stack → PC Description: No operation. Status affected: -- Cycle: 1 Description: ACC is loaded with 8-bit immediate data i and PC is loaded from top of Stack as return address. Cycle: 2 Example: RETIA i before executing instruction: GIE=0, Stack pointer =2. i=0x55, ACC=0XaA. after executing instruction: GIE=1, PC=Stack[2], Stack pointer =1. ACC=0x55. mi co nd uc NOP before executing instruction: PC=A0 after executing instruction: PC=A0+1 to r Example: i Return from Subroutine Syntax: RET Operand: -- Operand: -- Operation: Top of Stack → PC 1 → GIE -- Operation: Top of Stack → PC Status affected: -- Description: PC is loaded from top of Stack as return address. Cycle: 2 Example: RET before executing instruction: Stack level=2. after executing instruction: PC=Stack[2], Stack level=1. Description: CR O Status affected: Se RET Syntax: Return from Interrupt and Enable Interrupt Globally RETIE RETIE The PC is loaded from top of Stack as return address and GIE is set to 1. 2 Example: RETIE before executing instruction: GIE=0, Stack level=2. after executing instruction: GIE=1, PC=Stack[2], Stack pointer=1. JS MI Cycle: www.jsmsemi.com 第８７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU RLR Rotate Left R Through Carry SBCAR Subtract ACC and Carry from R Syntax: RLR Syntax: SBCAR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: C → dest[0], R[7] → C, R[6:0] → dest[7:1] Operation: R + (~ACC) + C → dest Status affected: Z, DC, C Description: Subtract ACC and Carry from R with 2’s complement representation. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: SBCAR R, d C R Status affected: Description: b6 b5 b4 b3 b2 b1 b0 C The content of R is rotated one bit to the left through flag Carry. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. 1 Example: RLR R, d before executing instruction: R=0XA5, d=1, C=0. after executing instruction: R=0x4A, C=1. RRR Rotate Right R Through Carry Syntax: RRR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: C → dest[7], R[7:1] R[0] → C co mi → dest[6:0], (b) before executing instruction: R=0x05, ACC=0x06, d=1, C=1, after executing instruction: R=0XfF, C=0. (-1)I) before executing instruction: R=0x06, ACC=0x05, d=1, C=0, after executing instruction: R=0x00, C=1. (-0), Z=1. (d) before executing instruction: R=0x06, ACC=0x05, d=1, C=1, after executing instruction: R=0x1, C=1. (+1) R b6 b5 b4 JS MI b7 Status affected: Description: Se R, d CR O C nd Cycle: (a) before executing instruction: R=0x05, ACC=0x06, d=1, C=0, after executing instruction: R=0XfE, C=0. (-2) uc b7 R, d to r R, d b3 b2 b1 b0 C The content of R is rotated one bit to the right through flag Carry. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. Cycle: 1 Example: RRR R, d before executing instruction: R=0XA5, d=1, C=0. after executing instruction: R=0x52, C=1. www.jsmsemi.com 第８８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU SFUNR Move S-page SFR to ACC Syntax: Subtract ACC and Carry from Immediate SBCIA i Syntax: SFUNR Operand: 0 ≤ i ＜ 255 Operand: 0 ≤ S ≤ 31 Operation: i + (~ACC) + C → dest Operation: S-page SFR → ACC Status affected: Z, DC, C Status affected: -- Description: Subtract ACC and Carry from 8-bit immediate data i with 2’s complement representation. The result is placed in ACC. Description: Move S-page SFR S to ACC. Cycle: 1 Example: SFUNR S before executing instruction: S=0x55, ACC=0xAA. after executing instruction: S=0x55, ACC=0x55. SBCIA i (a) before executing instruction: i=0x05, ACC=0x06, C=0, after executing instruction: ACC=0xFE, C=0. (-2) (b) before executing instruction: i=0x05, ACC=0x06, C=1, after executing instruction: ACC=0xFF, C=0. (-1) mi (c) before executing instruction: i=0x06, ACC=0x05, C=0, after executing instruction: ACC=0x00, C=1. (-0), Z=1. to r Example: uc 1 nd Cycle: CR O Se (d) before executing instruction: i=0x06, ACC=0x05, C=1, after executing instruction: ACC=0x1, C=1. (+1) S co SBCIA SLEEP Enter Halt Mode Syntax: SLEEP Operand: -- Operation: 00h → WDT, 00h → WDT prescaler 1 → /TO 0 → /PD Status affected: /TO, /PD Description: WDT and Prescaler0 are clear to 0. /TO is set to 1 and /PD is clear to 0. IC enter Halt mode. Load S-page SFR from ACC Syntax: SFUN Operand: 0 ≤ S ≤ 31 Operation: ACC → S-page SFR Status affected: -- Cycle: 1 Description: S-page SFR S is loaded by content of ACC. Example: Cycle: 1 Example: SFUN S before executing instruction: S=0x55, ACC=0xAA. after executing instruction: S=0xAA, ACC=0xAA. SLEEP before executing instruction: /PD=1, /TO=0. after executing instruction: /PD=0, /TO=1. JS MI SFUN S www.jsmsemi.com 第８９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU SUBAR Subtract ACC from R SWAPR Swap High/Low Nibble in R Syntax: SUBAR Syntax: SWAPR Operand: 0 ≤ R ≤ 127 d = 0, 1. Operand: 0 ≤ R ≤ 127 d = 0, 1. Operation: R – ACC → dest Operation: Status affected: Description: Z, DC, C R[3:0] → dest[7:4]. R[7:4] → dest[3:0] Status affected: -- Description: Cycle: 1 The high nibble and low nibble of R is exchanged. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. Example: SBCAR R, d Subtract ACC from R with 2’s complement representation. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. Cycle: SWAPR R, d before executing instruction: R=0xA5, d=1. after executing instruction: R=0x5A. nd uc Example: mi (b) before executing instruction: R=0x06, ACC=0x05, d=1, after executing instruction: R=0x01, C=1. (+1) 1 co (a) before executing instruction: R=0x05, ACC=0x06, d=1, after executing instruction: R=0xFF, C=0. (-1) R, d to r R, d Subtract ACC from Immediate TABLEA Read ROM data Syntax: SUBIA Syntax: TABLEA Operand: 0 ≤ i ＜ 255 Operand: -- Operation: i – ACC → ACC Status affected: Description: Z, DC, C Operation: ROM data{ TBHP, ACC } [7:0] → ACC ROM data{TBHP, ACC} [13:8] → TBHD. Status affected: -- Description: The 8 least significant bits of ROM pointed by {TBHP[2:0], ACC} is placed to ACC. The 6 most significant bits of ROM pointed by {TBHP[2:0], ACC} is placed to TBHD[5:0]. Cycle: 2 Example: TABLEA before executing instruction: TBHP=0x02, ACC=0x34. TBHD=0x01. ROM data[0x234]= 0x35AA after executing instruction: TBHD=0x35, ACC=0xAA. CR O i Se SUBIA JS MI Subtract ACC from 8-bit immediate data i with 2’s complement representation. The result is placed in ACC. Cycle: 1 Example: SUBIA i (a) before executing instruction: i=0x05, ACC=0x06. after executing instruction: ACC=0xFF, C=0. (-1) (b) before executing instruction: i=0x06, ACC=0x05, d=1, after executing instruction: ACC=0x01, C=1. (+1) www.jsmsemi.com 第９０页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU T0MD Load ACC to T0MD XORAR Exclusive-OR ACC with R Syntax: T0MD Syntax: XORAR Operand: -- Operand: Operation: ACC → T0MD Status affected: -- Operation: 0 ≤ R ≤ 127 d = 0, 1. ACC ⊕ R → dest Description: The content of T0MD is loaded by ACC. Status affected: Z Description: Cycle: 1 Example: T0MD before executing instruction: T0MD=0x55, ACC=0xAA. after executing instruction: t0MD=0xAA. Exclusive-OR ACC with R. If d is 0, the result is placed in ACC. If d is 1, the result is stored back to R. 1 to r Cycle: R, d XORAR R, d before executing instruction: R=0xA5, ACC=0xF0, d=1. after executing instruction: R=0x55. Syntax: T0MDR Operand: -- Operation: Status affected: T0MD → ACC -- Syntax: Exclusive-OR with ACC XORIA i Operand: 0 ≤ i ＜ 255 Operation: ACC ⊕ i → ACC Status affected: Z Description: Exclusive-OR ACC with 8-bit immediate data i. The result is stored in ACC. Cycle: 1 Example: XORIA i before executing instruction: i=0xA5, ACC=0xF0. after executing instruction: ACC=0x55. XORIA mi Move T0MD to ACC Se T0MDR co nd uc Example: Move the content of T0MD to ACC. Cycle: 1 Example: T0MDR before executing instruction T0MD=0x55, ACC=0xAA. after executing instruction ACC=0x55. JS MI CR O Description: www.jsmsemi.com Immediate 第９１页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 5. Configuration Words Item Name 1 High Oscillator Frequency 1. I_HRC 2. E_HXT 2 Low Oscillator Frequency 1. I_LRC 2. E_LXT 3 High IRC Frequency 1. 4. 1MHz 8MHz 2. 5. 2MHz 16MHz E_XT 3. 6. 4MHz 20MHz 1. 6MHz＜ FHOSC ≦8MHz 2. 8MHz＜ FHOSC ≦10MHz 3. 10MHz＜ FHOSC ≦12MHz 4. 12MHz＜ FHOSC ≦16MHz 5. 16MHz＜ FHOSC ≦20MHz 1. 2 oscillator period to r High Crystal Oscillator 3. 5 Instruction Clock 6 WDT 7 WDT Event 1. Watchdog Reset 2. Watchdog Interrupt 8 Timer0 Source 1. EX_CKI0 2. 9 PA.5 1. PA.5 is I/O 10 PA.7 1. PA.7 is I/O 11 Startup Time 1. 140us 12 WDT Time Base 1. 3.5ms 13 LVR Setting 1. Register Control 14 LVR Voltage 1. 6. 1.6V 2.7V 2. 7. 1.8V 3.0V 3. 8. 2.0V 3.3V 15 VDD Voltage 1. 3.0V 2. 4.5V 3. 5.0V 16 Analog Input pin select 1. Enable 2. Disable 17 Read Output Data 1. I/O Port 2. Register 18 E_LXT Backup Control 1. Auto Off 2. Register Off JS MI 4 Options 2. 4 oscillator period 19 EX_CKI0 to Inst. Clock 1. Sync 2. Async 20 Startup Clock 1. Fast (I_HRC/E_HXT/E_XT) 2. Slow (I_LRC/E_LXT) 21 PWM1 Output Pin 1. PB3 2. PA4 22 PWM2 Output Pin 1. PB2 2. PA0 23 PWM3 Output Pin 1. PB4 2. PA3 24 PWM4 Output Pin 1. PB5 2. PA2 25 PWM5 Output Pin 1. PB0 2. PA1 26 Input Schmitt Trigger 1 Enable 2. Disable (1/2 VDD) 27 Input High Voltage (VIH) 1. 0.7VDD 2. 0.5VDD 28 Input Low Voltage (VIL) 1. 0.3VDD 2. 0.2VDD 29 INT1 pad select 1. PB1 2. PA2 1. Watchdog Enable (Software control) CR O nd Low Oscillator (I_LRC/E_LXT) PA.5 is reset 2. PA.7 is instruction clock output co 2. 2. 4.5ms 3. 18ms 4. 72ms 2. 15ms 3. 60ms 4. 250ms mi Se Table 26 uc 2. Watchdog Disable (Always disable) 2. 5. 288ms LVR Always On 4. 9. 2.2V 3.6V 5. 2.4V 10. 4.2V Configuration Words www.jsmsemi.com 第９２页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 6. Electrical Characteristics Absolute Maximum Rating Symbol VDD - VSS Rated Value Unit -0.5 ~ +6.0 V VSS-0.3V ~ VDD+0.3 V Supply voltage Input voltage TOP Operating Temperature -40 ~ +85 °C TST Storage Temperature -40 ~ +125 °C to r VIN DC Characteristics (All refer FINST=FHOSC/4, FHOSC=16MHz@I_HRC, WDT enabled, ambient temperature TA=25°C unless otherwise specified.) Parameter VDD Min. Typ. Max. Unit uc Symbol FINST=20MHz @ I_HRC/4 nd 2.0 2.4 1.8 VDD Operating voltage -- 1.8 1.8 FINST=16MHz @ E_HXT/2 -- 5.5 V mi 1.8 VIL Input low voltage IOH Output high current IOL Output low current IIR IR sink current FINST=8MHz @ I_HRC/4 & I_HRC/2 FINST=8MHz @ E_HXT/4 & E_HXT/2 FINST=4MHz @ I_HRC/4 & I_HRC/2 FINST=4MHz @ E_XT/4 & E_XT/2 1.8 FINST=32KHz @ I_LRC/4 & I_LRC/2 1.8 FINST=32KHz @ E_LXT/4 & E_LXT/2 Se Input high voltage FINST=16MHz @ E_HXT/4 1.8 5V 4.0 -- -- 3V 2.4 -- -- 5V 3.5 -- -- 3V 2.1 -- -- 5V 2.5 -- -- 3V 1.5 -- -- 5V -- -- 1.0 3V -- -- 0.6 5V -- -- 1.5 3V -- -- 0.9 5V -- -- 1.0 3V -- -- 0.6 5V -- 18 -- 3V -- 10 -- 5V -- 41 -- 3V -- 26 -- 5V -- 43 -- 3V -- 27 -- CR O VIH Condition FINST=20MHz @ I_HRC/2 3.0 JS MI 6.2 Parameter co 6.1 www.jsmsemi.com V RSTb (0.8 VDD) V All other I/O pins, EX_CKI, INT CMOS option (0.7 VDD) V All other I/O pins, EX_CKI TTL option (0.5 VDD) V RSTb (0.2 VDD) V All other I/O pins, EX_CKI, INT CMOS option (0.3 VDD) V All other I/O pins, EX_CKI TTL option (0.2 VDD) mA VOH=4.0V VOH=2.0V mA VOL=1.0V mA VOL=1.0V, IR 第９３页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Symbol Parameter VDD Min. Typ. Max. Unit Condition Normal Mode -- 1.4 -- 5V -- 2.1 -- 3V -- 0.9 -- 5V -- 2.6 -- 3V -- 1.1 -- 5V -- 1.8 -- 3V -- 0.8 -- 5V -- 1.6 -- 3V -- 0.7 -- 5V -- 1.2 -- 3V -- 0.5 -- 5V -- 1.2 -- 3V -- 0.5 -- 5V -- 1.0 -- 3V -- 0.4 -- 5V -- 0.9 -- 3V -- 0.4 -- -- 0.8 -- -- 0.3 -- 5V Se 3V 5V -- 6.9 -- 3V -- 3.0 -- 5V -- 7.9 -- 3V -- 3.2 -- 5V -- 4.8 -- 3V -- 2.0 -- 5V -- 5.8 -- 3V -- 2.2 -- 5V -- 3.2 -- 3V -- 1.2 -- 5V -- -- 0.5 3V -- -- 0.2 5V -- -- 5.0 3V -- -- 2.0 5V -- 50 -- 3V -- 100 -- 5V -- 50 -- 3V -- 100 -- CR O JS MI ISTB IHALT Standby current Halt current RPH Pull-High resistor RPL Pull-Low resistor mA FHOSC=20MHz @ I_HRC/2 & E_HXT/2 mA FHOSC=20MHz @ I_HRC/4 & E_HXT/4 mA FHOSC=16MHz @ I_HRC/2 & E_HXT/2 mA FHOSC=16MHz @ I_HRC/4 & E_HXT/4 mA FHOSC=8MHz @ I_HRC/2 & E_HXT/2 to r 3V uc -- mA FHOSC=8MHz @ I_HRC/4 & E_HXT/4 mA FHOSC=4MHz @ I_HRC/2 & E_XT/2 mA FHOSC=4MHz @ I_HRC/4 & E_XT/4 nd 3.1 co Operating current -- mi IOP 5V www.jsmsemi.com mA FHOSC=1MHz @ I_HRC/2 & E_XT/2 mA FHOSC=1MHz @ I_HRC/4 & E_XT/4 Slow Mode uA FHOSC disabled, FLOSC=32KHz @ I_LRC/2 uA FHOSC disabled, FLOSC=32KHz @ E_LXT/2. uA FHOSC disabled, FLOSC=32KHz @ I_LRC/4 uA FHOSC disabled, FLOSC=32KHz @ E_LXT/4. uA Standby mode, FHOSC disabled, FLOSC=32KHz @ I_LRC/4 uA Halt mode, WDT disabled. uA Halt mode, WDT enabled. KΩ Pull-High resistor KΩ Pull-Low resistor 第９４页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 6.3 OSC Characteristics (Measurement conditions VDD Voltage, TA Temperature are equal to programming conditions.) 6.4 Min. Typ. Max. Unit Condition I_HRC deviation by socket ±1 % Socket installed directly on writer. I_HRC deviation by handler ±3 % Handler condition with correct setup. I_LRC deviation by handler ±5 % Comparator / LVD Characteristics (VDD=5V, VSS=0V, TA=25°C unless otherwise specified.) Typ. Max. Unit 5 V Condition Comparator input voltage range 0 -- TENO Comparator enable to output valid -- 20 -- us FHOSC=1MHz ICO Operating current of comparator -- 135 -- uA FHOSC=1MHz, P2V mode ILVD Operating current of LVD -- 150 -- uA FHOSC=1MHz, LVD=4.3V ELVD LVD voltage error -- -- 3 % FHOSC=1MHz, LVD=4.3V mi co nd VIVR Characteristic Graph FHOSC=1MHz Frequency vs. VDD of I_HRC JS MI CR O 6.5.1 Min. Se 6.5 Parameter uc Symbol to r Parameter www.jsmsemi.com 第９５页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU Frequency vs. Temperature of I_HRC 6.5.3 Frequency vs. VDD of I_LRC 6.5.4 Frequency vs. Temperature of I_LRC JS MI CR O Se mi co nd uc to r 6.5.2 www.jsmsemi.com 第９６页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 6.6 Recommended Operating Voltage Recommended Operating Voltage (Temperature range: -40°C ~ +85°C) LVR: Recommended Frequency Min. Voltage Max. Voltage LVR: default (25°C) 20M/2T 3.0V 5.5V 3.3V 3.6V 16M/2T 2.4V 5.5V 2.7V 3.0V 20M/4T 2.0V 5.5V 2.2V 2.4V 16M/4T 1.8V 5.5V 2.0V 2.2V 8M(2T or 4T) 1.8V 5.5V 2.0V ≦6M(2T or 4T) 1.8V 5.5V 2.0V to r (-40°C ~ +85°C) 2.2V uc 2.2V JS MI CR O Se mi co nd 6.7 LVR vs. Temperature www.jsmsemi.com 第９７页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU JS MI CR O Se mi co nd uc to r 7. Die Pad Diagram www.jsmsemi.com 第９８页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 8. Package Dimension 8-Pin Plastic SOP (150 mil) CR O 16-Pin Plastic SOP (150 mil) JS MI 8.2 Se mi Note: For 8-pin SOP, 100 units per tube. co nd uc to r 8.1 Note: For 16-pin SOP, 50 units per tube. www.jsmsemi.com 第９９页，共１００页 NY8A054E 14 I/O + 5-channel PWM 8-bit EPROM-Based MCU 9. Ordering Information P/N Package Type Pin Count Package Width Shipping NY8A054E Die -- -- -- NY8A054ES8 SOP 8 150 mil NY8A054ES16 SOP 16 150 mil Tape & Reel: 2.5K pcs per Reel Tube: 100 pcs per Tube Tape & Reel: 2.5K pcs per Reel JS MI CR O Se mi co nd uc to r Tube: 50 pcs per Tube www.jsmsemi.com 第１００页，共１００页