GD32F405VGH6

GD32F405xx GigaDevice Semiconductor Inc. GD32F405xx ARM® Cortex®-M4 32-bit MCU Datasheet 0 / 60 GD32F405xx Table of Contents List of Figures ............................................................................................................................. 3 List of Tables ............................................................................................................................... 4 1 Introduction ...................................................................................................................... 5 2 Device overview ............................................................................................................... 6 2.1 Device information .............................................................................................................................. 6 2.2 Block diagram ...................................................................................................................................... 7 2.3 Pinouts and pin assignment .............................................................................................................. 8 2.4 Memory map ...................................................................................................................................... 12 2.5 Clock tree ........................................................................................................................................... 15 2.6 Pin definitions .................................................................................................................................... 16 Functional description .................................................................................................. 32 3 3.1 ARM® Cortex®-M4 core .................................................................................................................... 32 3.2 On-chip memory................................................................................................................................ 32 3.3 Clock, reset and supply management ........................................................................................... 33 3.4 Boot modes ........................................................................................................................................ 34 3.5 Power saving modes ........................................................................................................................ 34 3.6 Analog to digital converter (ADC) ................................................................................................... 35 3.7 Digital to analog converter (DAC) ................................................................................................... 35 3.8 DMA .................................................................................................................................................... 36 3.9 General-purpose inputs/outputs (GPIOs) ...................................................................................... 36 3.10 Timers and PWM generation........................................................................................................... 37 3.11 Real time clock (RTC) and backup registers ................................................................................ 38 3.12 Inter-integrated circuit (I2C) ............................................................................................................. 38 3.13 Serial peripheral interface (SPI)...................................................................................................... 39 3.14 Universal synchronous/asynchronous receiver transmitter (USART/UART) ........................... 39 3.15 Inter-IC sound (I2S) .......................................................................................................................... 39 3.16 Universal serial bus on-the-go full-speed (USB OTG FS) .......................................................... 40 3.17 Universal serial bus on-the-go high-speed (USB OTG HS) ....................................................... 40 3.18 Controller area network (CAN) ........................................................................................................ 40 3.19 Secure digital input and output card interface (SDIO) ................................................................. 41 3.20 Digital camera interface (DCI) ......................................................................................................... 41 3.21 Debug mode ...................................................................................................................................... 41 3.22 Package and operation temperature.............................................................................................. 41 Electrical characteristics .............................................................................................. 42 4 4.1 Absolute maximum ratings .............................................................................................................. 42 4.2 Recommended DC characteristics ................................................................................................. 42 4.3 Power consumption .......................................................................................................................... 43 4.4 EMC characteristics .......................................................................................................................... 44 1 / 60 GD32F405xx 4.5 Power supply supervisor characteristics ....................................................................................... 45 4.6 Electrical sensitivity........................................................................................................................... 45 4.7 External clock characteristics .......................................................................................................... 46 4.8 Internal clock characteristics ........................................................................................................... 47 4.9 PLL characteristics ........................................................................................................................... 48 4.10 Memory characteristics .................................................................................................................... 49 4.11 GPIO characteristics......................................................................................................................... 50 4.12 ADC characteristics .......................................................................................................................... 51 4.13 DAC characteristics .......................................................................................................................... 53 4.14 SPI characteristics ............................................................................................................................ 54 4.15 I2C characteristics ............................................................................................................................ 54 4.16 USART characteristics ..................................................................................................................... 54 Package information ..................................................................................................... 55 5 5.1 LQFP package outline dimensions ................................................................................................ 55 5.2 BGA package outline dimensions .................................................................................................. 57 6 Ordering information ..................................................................................................... 58 7 Revision history ............................................................................................................. 59 2 / 60 GD32F405xx List of Figures Figure 1. GD32F405xx block diagram ...................................................................................................................... 7 Figure 2. GD32F405Vx BGA100 pinouts ................................................................................................................. 8 Figure 3. GD32F405Zx LQFP144 pinouts ............................................................................................................... 9 Figure 4. GD32F405Vx LQFP100 pinouts ............................................................................................................. 10 Figure 5. GD32F405Rx LQFP64 pinouts ............................................................................................................... 11 Figure 6. GD32F405xx memory map ..................................................................................................................... 12 Figure 7. GD32F405xx clock tree............................................................................................................................ 15 Figure 8. LQFP package outline .............................................................................................................................. 55 Figure 9. BGA package outline ................................................................................................................................ 57 3 / 60 GD32F405xx List of Tables Table 1. GD32F405xx devices features and peripheral list................................................................................... 6 Table 2. GD32F405xx pin definitions ...................................................................................................................... 16 Table 3. Port A alternate functions summary ......................................................................................................... 25 Table 4. Port B alternate functions summary ......................................................................................................... 26 Table 5. Port C alternate functions summary......................................................................................................... 27 Table 6. Port D alternate functions summary......................................................................................................... 28 Table 7. Port E alternate functions summary ......................................................................................................... 29 Table 8. Port F alternate functions summary ......................................................................................................... 30 Table 9. Port G alternate functions summary ........................................................................................................ 31 Table 12. Absolute maximum ratings ...................................................................................................................... 42 Table 13. DC operating conditions .......................................................................................................................... 42 Table 14. Power consumption characteristics ....................................................................................................... 43 Table 15. EMS characteristics ................................................................................................................................. 44 Table 16. EMI characteristics................................................................................................................................... 44 Table 17. Power supply supervisor characteristics .............................................................................................. 45 Table 18. ESD characteristics.................................................................................................................................. 45 Table 19. Static latch-up characteristics ................................................................................................................ 45 Table 20. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ................. 46 Table 21. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics ................... 46 Table 22. High speed internal clock (IRC16M) characteristics ........................................................................... 47 Table 23. High speed internal clock (IRC48M) characteristics ........................................................................... 47 Table 24. Low speed internal clock (IRC32K) characteristics ............................................................................. 48 Table 25. PLL characteristics ................................................................................................................................... 48 Table 26. PLL spread spectrum clock generation (SSCG) characteristics ....................................................... 48 Table 27. Flash memory characteristics ................................................................................................................. 49 Table 28. I/O port characteristics ............................................................................................................................. 50 Table 29. ADC characteristics .................................................................................................................................. 51 Table 30. ADC RAIN max for fADC=40MHz ................................................................................................................. 51 Table 31. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 52 Table 32. ADC dynamic accuracy at fADC = 30 MHz ............................................................................................. 52 Table 33. ADC dynamic accuracy at fADC = 36 MHz ............................................................................................. 52 Table 34. ADC dynamic accuracy at fADC = 40 MHz ............................................................................................. 52 Table 35. ADC static accuracy at fADC = 15 MHz .................................................................................................. 52 Table 36. DAC characteristics ................................................................................................................................. 53 Table 37. SPI characteristics .................................................................................................................................... 54 Table 38. I2C characteristics .................................................................................................................................... 54 Table 39. USART characteristics ............................................................................................................................ 54 Table 40. LQFP package dimensions ..................................................................................................................... 56 Table 41. BGA package dimensions ....................................................................................................................... 57 Table 42. Part ordering code for GD32F405xx devices ....................................................................................... 58 Table 43. Revision history......................................................................................................................................... 59 4 / 60 GD32F405xx 1 Introduction The GD32F405xx device belongs to the connectivity line of GD32 MCU Family. It is a new 32-bit general-purpose microcontroller based on the ARM® Cortex®-M4 RISC core with best cost-performance ratio in terms of enhanced processing capacity, reduced power consumption and peripheral set. The Cortex®-M4 core features a Floating Point Unit (FPU) that accelerates single precision floating point math operations and supports all ARM® single precision instructions and data types. It implements a full set of DSP instructions to address digital signal control markets that demand an efficient, easy-to-use blend of control and signal processing capabilities. It also provides a Memory Protection Unit (MPU) and powerful trace technology for enhanced application security and advanced debug support. The GD32F405xx device incorporates the ARM® Cortex®-M4 32-bit processor core operating at 168 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 3072 KB on-chip Flash memory and 192 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to three 12-bit 2.6M SPS ADCs, two 12-bit DACs, up to eight general-purpose 16-bit timers, two 16-bit PWM advanced-control timers , two 32-bit general-purpose timers, and two 16-bit basic timers, as well as standard and advanced communication interfaces: up to three SPIs, three I2Cs, four USARTs and two UARTs, two I2Ss, two CANs, a SDIO, USB device/host/OTG FS and HS. Additional peripherals as Digital camera interface (DCI) is included. The device operates from a 2.6 to 3.6V power supply and available in –40 to +85 °C temperature range. Three power saving modes provide the flexibility for maximum optimization of power consumption, an especially important consideration in low power applications. The above features make GD32F405xx devices suitable for a wide range of interconnection and advanced applications, especially in areas such as industrial control, consumer and handheld equipment, embedded modules, human machine interface, security and alarm systems, graphic display, automotive navigation, drone, IoT and so on. 5 / 60 GD32F405xx 2 Device overview 2.1 Device information Table 1. GD32F405xx devices features and peripheral list GD32F405xx Part Number RG RK VG VK VG VK ZG ZK Code Area (KB) 512 512 512 512 512 512 512 512 512 Data Area (KB) 0 512 2560 512 2560 512 2560 512 2560 Total (KB) 512 1024 3072 1024 3072 1024 3072 1024 3072 192 192 192 192 192 192 192 192 192 16-bit GPTM 8 8 8 8 8 8 8 8 8 32-bit GPTM 2 2 2 2 2 2 2 2 2 Adv. 16-bit TM 2 2 2 2 2 2 2 2 2 Basic TM 2 2 2 2 2 2 2 2 2 SysTick 1 1 1 1 1 1 1 1 1 Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 USART+UART 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2 4+2 I2C 3 3 3 3 3 3 3 3 3 SPI/I2S 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 3/2 SDIO 1 1 1 1 1 1 1 1 1 CAN 2.0B 2 2 2 2 2 2 2 2 2 USB OTG FS+HS FS+HS FS+HS FS+HS Digital Camera 1 1 1 1 1 1 1 1 1 GPIO 51 51 51 82 82 82 82 114 114 ADC Unit (CHs) 3(16) 3(16) 3(16) 3(16) 3(16) 3(16) 3(16) 3(24) 3(24) DAC 2 2 2 2 2 2 2 2 2 Flash RE Connectivity Timers SRAM (KB) Package FS+HS FS+HS LQFP64 FS+HS FS+HS FS+HS LQFP100 BGA100 LQFP144 6 / 60 GD32F405xx Block diagram Figure 1. GD32F405xx block diagram Powered By LDO (1.2V) Flash Memory IBUS TPIU SW/JTA G master slave FMC SBUS master M master P master M master P master DMA0 DMA1 USBHS Powered By V DDA master master AHB Interconnect Matrix (Fmax=168MHz) DBUS ARM Cortex-M4 Processor Fmax: 168MHz slave slave TCMSRAM slave SRAM0 slave SRAM1 DAC BKP SRAM CRC LVD PLLs IRC16M IRC32K GPIO RCU slave AHB1 Per ipheral s TRNG DCI USBFS slave AHB2 Per ipheral s slave AHB Interconnect Matrix (Fmax=168MHz) slave 2.2 SDIO SPI0 CTC DAC IVREF CAN1 TIMER9 TIMER13 CAN0 TIMER8 TIMER12 TIMER7 TIMER11 TIMER0 TIMER6 USART5 TIMER5 UART3 USART0 TIMER4 USART2 TIMER3 TIMER2 TIMER1 WWDG T SAR ADC Powered By V DDA POR/ PDR USART1 I2C2 I2C1 I2C0 I2S2_add SPI2/I2S2 SPI1/I2S1 LDO FWDG T HXTAL UART4 APB1 (Fmax=42MHz) ADC0~2 APB2 (Fmax=84MHz) EXTI SYS CFG TIMER10 I2S1_add PMU Powered By V DD LXTAL RTC Powered By V B AT 7 / 60 GD32F405xx 2.3 Pinouts and pin assignment Figure 2. GD32F405Vx BGA100 pinouts 1 2 A PE3 PE1 B PE4 C 3 4 5 6 7 8 9 10 PB8 BOOT0 PD7 PD5 PB4 PB3 PA15 PA14 PE2 PB9 PB7 PB6 PD6 PD4 PD3 PD1 PC12 PC10 PA11 PC13 PE5 PE0 VDD PB5 PD2 PD0 PC11 NC PA10 D PC14 PE6 VSS PA9 PA8 PC9 E PC15 VBAT NC PC8 PC7 PC6 F PH0 VSS VSS VSS G PH1 VDD VDD VDD H PC0 NRST PDR_ ON PD15 PD14 PD13 PD12 PD11 PD10 PB15 PB14 PB13 GigaDevice GD32F405Vx BGA100 J VSSA PC1 PC2 K VREF- PC3 PA2 PA5 PC4 L VREF+ PA0 PA3 PA6 PC5 PB2 PE8 M VDDA PA1 PA4 PA7 PB0 PB1 PE7 PD9 PB11 PE10 PE12 PB10 PE9 11 12 PA13 PA12 NC PB12 PE11 PE13 PE14 PE15 8 / 60 GD32F405xx Figure 3. GD32F405Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS VDD PD6 PD7 PG9 PG11 PG10 PG12 PG13 PG14 VDD VSS PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VDD PDR_ON 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 PE3 PE4 2 107 VSS 3 106 NC PE5 PE6 4 105 PA13 5 104 PA12 VBAT 6 103 PA11 PC13-TAMPER-RTC PC14-OSC32_IN 7 102 PA10 8 101 PA9 PC15-OSC32_OUT 9 100 PA8 PF0 10 99 PC9 PC8 VDD PF1 11 98 PF2 12 97 PC7 PF3 PF4 13 96 PC6 14 95 VDD PF5 15 94 VSS VSS 16 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 VDD 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 87 PG2 PH0-OSC_IN 23 86 PD15 PH0-OSC_OUT 24 85 PD14 NRST 25 84 VDD PC0 26 83 VSS PC1 27 82 PD13 PC2 28 81 PD12 PC3 VDD 29 80 PD11 30 79 PD10 VSSA VREF+ 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 GigaDevice GD32F405Zx LQFP144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC VDD PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD PE10 VSS PE9 PE7 PE8 PG1 PG0 PF15 PF13 PF14 VSS VDD PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VSS VDD PA3 9 / 60 GD32F405xx Figure 4. GD32F405Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS VDD PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32_IN 7 70 69 PA10 8 68 PA9 PC15-OSC32_OUT 9 67 PA8 VSS 10 66 PC9 65 PC8 64 PC7 63 PC6 VDD PA11 VDD 11 PH0-OSC_IN 12 PH1-OSC_OUT 13 NRST PC0 14 62 PD15 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VDD 19 57 PD10 VSSA VREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 GigaDevice GD32F405Vx LQFP100 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD PB11 NC PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PB2 PE7 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VSS VDD PA3 10 / 60 GD32F405xx Figure 5. GD32F405Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PD2 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS VDD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 PC13-TAMPER-RTC 2 47 PC14-OSC32_IN 3 46 PA13 PC15-OSC32_OUT PH0-OSC_IN 4 45 PA12 5 44 PA11 PH1-OSC_OUT 6 43 PA10 NRST PC0 7 42 PA9 PC1 9 PC2 PC3 VSSA GigaDevice GD32F405Rx LQFP64 VDD_2 NC 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD NC PB11 PB10 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 VDD PA4 VSS PA3 11 / 60 GD32F405xx 2.4 Memory map Figure 6. GD32F405xx memory map Pre-defined Regions Bus Address Peripherals 0xC000 0000 - 0xDFFF FFFF EXMC - SDRAM 0xA000 1000 - 0xBFFF FFFF Reserved AHB 0xA000 0000 - 0xA000 0FFF Reserved matrix 0x9000 0000 - 0x9FFF FFFF Reserved 0x7000 0000 - 0x8FFF FFFF Reserved 0x6000 0000 - 0x6FFF FFFF Reserved 0x5006 0C00 - 0x5FFF FFFF Reserved 0x5006 0800 - 0x5006 0BFF TRNG 0x5005 0400 - 0x5006 07FF Reserved 0x5005 0000 - 0x5005 03FF DCI 0x5004 0000 - 0x5004 FFFF Reserved 0x5000 0000 - 0x5003 FFFF USBFS 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF USBHS 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF DMA1 0x4002 6000 - 0x4002 63FF DMA0 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF FMC 0x4002 3800 - 0x4002 3BFF RCU 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2400 - 0x4002 2FFF Reserved 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE 0x4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA External Device External RAM AHB2 Peripheral AHB1 12 / 60 GD32F405xx Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 6C00 - 0x4001 FFFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5800 - 0x4001 67FF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF TIMER10 0x4001 4400 - 0x4001 47FF TIMER9 0x4001 4000 - 0x4001 43FF TIMER8 0x4001 3C00 - 0x4001 3FFF EXTI 0x4001 3800 - 0x4001 3BFF SYSCFG 0x4001 3400 - 0x4001 37FF Reserved 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF SDIO 0x4001 2400 - 0x4001 2BFF Reserved 0x4001 2000 - 0x4001 23FF ADC 0x4001 1800 - 0x4001 1FFF Reserved 0x4001 1400 - 0x4001 17FF USART5 0x4001 1000 - 0x4001 13FF USART0 0x4001 0800 - 0x4001 0FFF Reserved 0x4001 0400 - 0x4001 07FF TIMER7 0x4001 0000 - 0x4001 03FF TIMER0 0x4000 C800 - 0x4000 FFFF Reserved 0x4000 C400 - 0x4000 C7FF IVREF 0x4000 8000 - 0x4000 C3FF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 0x4000 6C00 - 0x4000 6FFF CTC 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF CAN0 0x4000 6000 - 0x4000 63FF Reserved 0x4000 5C00 - 0x4000 5FFF I2C2 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 13 / 60 GD32F405xx Pre-defined Regions SRAM Code Bus AHB matrix AHB matrix Address Peripherals 0x4000 4000 - 0x4000 43FF I2S2_add 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF I2S1_add 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF TIMER13 0x4000 1C00 - 0x4000 1FFF TIMER12 0x4000 1800 - 0x4000 1BFF TIMER11 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2003 0000 - 0x2006 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF SRAM1(16KB) 0x2000 0000 - 0x2001 BFFF SRAM0(112KB) 0x1FFF C010 - 0x1FFF FFFF Reserved 0x1FFF C000 - 0x1FFF C00F Option bytes(Bank 0) 0x1FFF 7A10 - 0x1FFF BFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F OTP(528B) 0x1FFF 0000 - 0x1FFF 77FF Boot loader(30KB) 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Option bytes(Bank 1) 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF TCMSRAM(64KB) 0x0830 0000 - 0x0FFF FFFF Reserved 0x0800 0000 - 0x082F FFFF Main Flash(3072KB) 0x0000 0000 - 0x07FF FFFF Aliased to the boot device 14 / 60 GD32F405xx 2.5 Clock tree Figure 7. GD32F405xx clock tree CK_HXTAL /2 to /31 11 32.768 KHz LXTAL OSC CK_RTC 01 (to RTC) 10 RTCSRC[1:0] CK_FWDGT 32 KHz IRC32K (to FWDGT) CK_OUT1 00 01 10 11 CKOUT1DIV ÷1,2,3,4,5 CK_SYS CK_PLLI2SR CK_HXTAL CK_PLLP CKOUT1SEL[1:0] HCLK (to AHB bus,CortexM4,SRAM,DMA,peripherals) AHB enable CK_OUT0 00 01 10 11 CKOUT0DIV ÷1,2,3,4,5 CK_IRC16M CK_LXTAL CK_HXTAL CK_CST ÷8 (to Cortex-M4 SysTick) FCLK CK_PLLP (free running clock) APB1 Prescaler ÷1,2,4,8,16 CKOUT0SEL[1:0] SCS[1:0] CK_IRC16M 16 MHz IRC16M 01 CK_SYS 200 MHz max AHB Prescaler ÷1,2...512 CK_AHB APB2 Prescaler ÷1,2,4,8,16 10 Clock Monitor 200 MHz max CK_TIMERx TIMERx enable to TIMER1,2,3,4, 5,6,11,12,13 CK_APB2 PCLK2 to APB2 peripherals 100 MHz max Peripheral enable TIMER0,7,8, 9,10 CK_APB2 x1 x2 or x4 PLLSEL CTC 0 TIMER1,2,3,4,5,6, 11,12,13 CK_APB1 x1 x2 or x4 200 MHz max CK_PLLP /PSC PCLK1 to APB1 peripherals Peripheral enable 00 CK_HXTAL 4-32 MHz HXTAL CK_APB1 50 MHz max 200 MHz max CK_TIMERx TIMERx enable to TIMER0,7, 8,9,10 1 VCO /P /Q xN /R PLL CK_CTC 48 MHz IRC48M ADC Prescaler CK_ADCX to ADC0,1,2 40 MHz max CK48MSEL PLL48MSEL 0 VCO I2SSEL /P /Q xN PLLI2S VCO 1 CK48M 0 Peripheral enable 1 to USBFS USBHS TRNG SDIO 1 /R CK_I2Sx 0 Peripheral enable I2S_CKIN to I2S /P /Q xN /R /DIV PLLSAI CK_TLI Peripheral enable ENET_TX_CLK /2 or /20 0 1 Peripheral enable ENET_PHY_SEL 1 ENET_RX_CLK to TLI CK_ENETTX to ENET TX CK_ENETRX 0 EMBPHY Peripheral enable to ENET RX USB HS PHY clock 24Mhz to 60Mhz 0 CK48M 1 CK_USBHS_ULPI Peripheral enable to USBHS ULPI Legend: HXTAL: High speed crystal oscillator LXTAL: Low speed crystal oscillator IRC16M: Internal 16M RC oscillators IRC48M: Internal 48M RC oscillators IRC32K: Internal 32K RC oscillator 15 / 60 GD32F405xx 2.6 Pin definitions BGA100 LQFP144 LQFP100 LQFP64 Pin Type(1) Pins I/O(2) Level Table 2. GD32F405xx pin definitions PE2 B2 1 1 - I/O 5VT PE3 A1 2 2 - I/O 5VT PE4 B1 3 3 - I/O 5VT PE5 C2 4 4 - I/O 5VT PE6 D2 5 5 - I/O 5VT VBAT E2 6 6 1 C1 7 7 2 Pin Name P - PC13TAMPER- OSC32IN PC15OSC32OUT Default: PE2 Alternate: TRACECLK, EVENTOUT Default: PE3 Alternate:TRACED0, EVENTOUT Default: PE4 Alternate:TRACED1, DCI_D4, EVENTOUT Default: PE5 Alternate:TRACED2,TIMER8_CH0, DCI_D6, EVENTOUT Default: PE6 Alternate:TRACED3,TIMER8_CH1, DCI_D7, EVENTOUT Default: VBAT Default: PC13 I/O 5VT Alternate: EVENTOUT RTC PC14- Functions description Additional: RTC_TAMP0, RTC_OUT, RTC_TS Default: PC14 D1 8 8 3 I/O 5VT Alternate: EVENTOUT Additional: OSC32IN Default: PC15 E1 9 9 4 I/O 5VT Alternate: EVENTOUT Additional: OSC32OUT PF0 - 10 - - I/O 5VT PF1 - 11 - - I/O 5VT PF2 - 12 - - I/O 5VT Default: PF0 Alternate:I2C1_SDA, EVENTOUT, CTC_SYNC Default: PF1 Alternate: I2C1_SCL, EVENTOUT Default: PF2 Alternate: I2C1_SMBA, EVENTOUT Default: PF3 PF3 - 13 - - I/O 5VT Alternate: EVENTOUT, I2C1_TXFRAME Additional: ADC2_IN9 Default: PF4 PF4 - 14 - - I/O 5VT Alternate: EVENTOUT Additional: ADC2_IN14 Default: PF5 PF5 - 15 - - I/O 5VT Alternate: EVENTOUT Additional: ADC2_IN15 16 / 60 GD32F405xx BGA100 LQFP144 LQFP100 LQFP64 Pin Type(1) I/O(2) Level Pins Functions description VSS F2 16 10 - P - Default: VSS VDD G2 17 11 - P - Default: VDD Pin Name Default: PF6 PF6 - 18 - - I/O 5VT Alternate:TIMER9_CH0, EVENTOUT Additional: ADC2_IN4 Default: PF7 PF7 - 19 - - I/O 5VT Alternate:TIMER10_CH0, EVENTOUT Additional: ADC2_IN5 Default: PF8 PF8 - 20 - - I/O 5VT Alternate: TIMER12_CH0, EVENTOUT Additional: ADC2_IN6 Default: PF9 PF9 - 21 - - I/O 5VT Alternate: TIMER13_CH0, EVENTOUT Additional: ADC2_IN7 Default: PF10 PF10 - 22 - - I/O 5VT Alternate: DCI_D11, EVENTOUT Additional: ADC2_IN8 Default: PH0, OSCIN PH0 F1 23 12 5 I/O 5VT Alternate: EVENTOUT Additional: OSCIN Default: PH1, OSCOUT PH1 G1 24 13 6 I/O 5VT Alternate: EVENTOUT Additional: OSCOUT NRST H2 25 14 7 - - Default: NRST Default: PC0 PC0 H1 26 15 8 I/O 5VT Alternate: USBHS_ULPI_STP, EVENTOUT Additional: ADC012_IN10 Default: PC1 PC1 J2 27 16 9 I/O 5VT Alternate:SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, EVENTOUT Additional: ADC012_IN11 Default: PC2 PC2 J3 28 17 10 I/O 5VT Alternate:SPI1_MISO,I2S1_ADD_SD,USBHS_ULPI_DIR, EVENTOUT Additional: ADC012_IN12 Default: PC3 PC3 K2 29 18 11 I/O 5VT Alternate:SPI1_MOSI,I2S1_SD,USBHS_ULPI_NXT, EVENTOUT Additional: ADC012_IN13 VDD - 30 19 VSSA J1 31 20 12 VREFN K1 - - - - P - Default: VDD P - Default: VSSA P - Default: VREF17 / 60 GD32F405xx Pin Type(1) I/O(2) Level P - Default: VREF+ P - Default: VDDA LQFP100 - LQFP144 Functions description BGA100 LQFP64 Pins VREFP L1 32 21 VDDA M1 33 22 13 Pin Name Default: PA0 PA0-WKUP L2 34 23 14 I/O 5VT Alternate:TIMER1_CH0,TIMER1_ETI,TIMER4_CH0, TIMER7_ETI,USART1_CTS, UART3_TX, EVENTOUT Additional: ADC012_IN0, WKUP Default: PA1 PA1 M2 35 24 15 I/O 5VT Alternate:TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, EVENTOUT Additional: ADC012_IN1 Default: PA2 PA2 K3 36 25 16 I/O 5VT Alternate:TIMER1_CH2,TIMER4_CH2,TIMER8_CH0, I2S_CKIN, USART1_TX, EVENTOUT Additional: ADC012_IN2 Default: PA3 PA3 L3 37 26 17 I/O 5VT Alternate:TIMER1_CH3,TIMER4_CH3,TIMER8_CH1, I2S1_MCK,USART1_RX,USBHS_ULPI_D0, EVENTOUT Additional: ADC012_IN3 VSS - 38 NC E3 - VDD - 39 27 18 - - 28 19 P - Default: VSS - - - P - Default: VDD Default: PA4 PA4 M3 40 29 20 I/O TTa Alternate:SPI0_NSS,SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, EVENTOUT Additional: ADC01_IN4, DAC_OUT0 Default: PA5 PA5 K4 41 30 21 I/O TTa Alternate:TIMER1_CH0,TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT Additional: ADC01_IN5, DAC_OUT1 Default: PA6 PA6 L4 42 31 22 I/O 5VT Alternate:TIMER0_BRKIN,TIMER2_CH0,TIMER7_BRKIN,SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT Additional: ADC01_IN6 Default: PA7 PA7 M4 43 32 23 I/O 5VT Alternate:TIMER0_CH0_ON,TIMER2_CH1, TIMER7_CH0_ON,SPI0_MOSI,TIMER13_CH0, EVENTOUT Additional: ADC01_IN7 PC4 K5 44 33 24 I/O 5VT Default: PC4 Alternate: EVENTOUT 18 / 60 I/O(2) Level LQFP64 LQFP100 LQFP144 Pin Name BGA100 Pins Pin Type(1) GD32F405xx Functions description Additional: ADC01_IN14 Default: PC5 PC5 L5 45 34 25 I/O 5VT Alternate:USART2_RX, EVENTOUT Additional: ADC01_IN15 Default: PB0 PB0 M5 46 35 26 I/O 5VT Alternate:TIMER0_CH1_ON,TIMER2_CH2,TIMER7_CH1_ON,SPI2_MO SI,I2S2_SD,USBHS_ULPI_D1, SDIO_D1, EVENTOUT Additional: ADC01_IN8, IREF Default: PB1 PB1 M6 47 36 27 I/O 5VT Alternate:TIMER0_CH2_ON,TIMER2_CH3,TIMER7_CH2_ON,USBHS_ ULPI_D2, SDIO_D2, EVENTOUT Additional: ADC01_IN9 Default: PB2, BOOT1 PB2 L6 48 37 28 I/O 5VT Alternate:TIMER1_CH3,SPI2_MOSI,I2S2_SD,USBHS_ULPI_D4, SDIO_CK, EVENTOUT Default: PF11 PF11 - 49 - - I/O 5VT PF12 - 50 - - I/O 5VT VSS - 51 - - P - Default: VSS VDD - 52 - - P - Default: VDD PF13 - 53 - - I/O 5VT PF14 - 54 - - I/O 5VT PF15 - 55 - - I/O 5VT PG0 - 56 - - I/O 5VT PG1 - 57 - - I/O 5VT PE7 M7 58 38 - I/O 5VT PE8 L7 59 39 - I/O 5VT PE9 M8 60 40 - I/O 5VT VSS - 61 - - P - Default: VSS VDD - 62 - - P - Default: VDD Alternate: DCI_D12, EVENTOUT Default: PF12 Alternate: EVENTOUT Default: PF13 Alternate: EVENTOUT Default: PF14 Alternate: EVENTOUT Default: PF15 Alternate: EVENTOUT Default: PG0 Alternate: EVENTOUT Default: PG1 Alternate: EVENTOUT Default: PE7 Alternate: TIMER0_ETI, EVENTOUT Default: PE8 Alternate: TIMER0_CH0_ON, EVENTOUT Default: PE9 Alternate: TIMER0_CH0, EVENTOUT 19 / 60 BGA100 LQFP144 LQFP100 LQFP64 Pin Type(1) Pins I/O(2) Level GD32F405xx PE10 L8 63 41 - I/O 5VT PE11 M9 64 42 - I/O 5VT PE12 L9 65 43 - I/O 5VT PE13 M10 66 44 - I/O 5VT PE14 M11 67 45 - I/O 5VT PE15 M12 68 46 - I/O 5VT Pin Name Functions description Default: PE10 Alternate: TIMER0_CH1_ON, EVENTOUT Default: PE11 Alternate:TIMER0_CH1, EVENTOUT Default: PE12 Alternate:TIMER0_CH2_ON, EVENTOUT Default: PE13 Alternate:TIMER0_CH2, EVENTOUT Default: PE14 Alternate:TIMER0_CH3, EVENTOUT Default: PE15 Alternate: TIMER0_BRKIN, EVENTOUT Default: PB10 PB10 L10 69 47 29 I/O 5VT Alternate:TIMER1_CH2,I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK,USART2_TX,USBHS_ULPI_D3, SDIO_D7, EVENTOUT Default: PB11 PB11 K9 70 48 30 I/O 5VT Alternate:TIMER1_CH3,I2C1_SDA,I2S_CKIN,USART2_RX,USBHS_UL PI_D4, EVENTOUT NC L11 71 VSS F12 - VDD G12 72 49 31 - - 50 32 P - Default: VCORE P - Default: VSS P - Default: VDD Default: PB12 PB12 L12 73 51 33 I/O 5VT Alternate:TIMER0_BRKIN,I2C1_SMBA,SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, USBHS_ID, EVENTOUT Default: PB13 Alternate:TIMER0_CH0_ON,SPI1_SCK,I2S1_CK, PB13 K12 74 52 34 I/O 5VT USART2_CTS,CAN1_TX,USBHS_ULPI_D6, EVENTOUT, I2C1_TXFRAME Additional: USBHS_VBUS Default: PB14 PB14 K11 75 53 35 I/O 5VT Alternate:TIMER0_CH1_ON,TIMER7_CH1_ON,SPI1_MISO,I2S1_ADD_ SD,USART2_RTS,TIMER11_CH0,USBHS_DM, EVENTOUT Default: PB15 PB15 K10 76 54 36 I/O 5VT Alternate:RTC_REFIN,TIMER0_CH2_ON,TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT PD8 - 77 55 - I/O 5VT PD9 K8 78 56 - I/O 5VT Default: PD8 Alternate: USART2_TX, EVENTOUT Default: PD9 Alternate: USART2_RX, EVENTOUT 20 / 60 LQFP100 LQFP64 Pin Type(1) PD10 J12 79 57 - I/O 5VT PD11 J11 80 58 - I/O 5VT PD12 J10 81 59 - I/O 5VT PD13 H12 82 60 - I/O 5VT Pin Name BGA100 LQFP144 Pins I/O(2) Level GD32F405xx Functions description Default: PD10 Alternate: USART2_CK, EVENTOUT Default: PD11 Alternate: USART2_CTS, EVENTOUT Default: PD12 Alternate:TIMER3_CH0,USART2_RTS , EVENTOUT Default: PD13 Alternate: TIMER3_CH1, EVENTOUT VSS - 83 - - P - Default: VSS VDD - 84 - - P - Default: VDD PD14 H11 85 61 - I/O 5VT PD15 H10 86 62 - I/O 5VT Default: PD14 Alternate: TIMER3_CH2, EVENTOUT Default: PD15 Alternate:TIMER3_CH3, EVENTOUT, CTC_SYNC Default: PG2 PG2 - 87 - - I/O 5VT PG3 - 88 - - I/O 5VT PG4 - 89 - - I/O 5VT PG5 - 90 - - I/O 5VT PG6 - 91 - - I/O 5VT PG7 - 92 - - I/O 5VT PG8 - 93 - - I/O 5VT VSS - 94 - - P - Default: VSS VDD - 95 - - P - Default: VDD Alternate: EVENTOUT Default: PG3 Alternate: EVENTOUT Default: PG4 Alternate: EVENTOUT Default: PG5 Alternate: EVENTOUT Default: PG6 Alternate: DCI_D12, EVENTOUT Default: PG7 Alternate:USART5_CK, DCI_D13, EVENTOUT Default: PG8 Alternate:USART5_RTS, EVENTOUT Default: PC6 PC6 E12 96 63 37 I/O 5VT Alternate:TIMER2_CH0,TIMER7_CH0,I2S1_MCK,USART5_TX, SDIO_D6, DCI_D0, EVENTOUT Default: PC7 PC7 E11 97 64 38 I/O 5VT Alternate:TIMER2_CH1,TIMER7_CH1,SPI1_SCK,I2S1_CK,I2S2_MCK, USART5_RX,SDIO_D7,DCI_D1,EVENTOUT Default: PC8 PC8 E10 98 65 39 I/O 5VT Alternate:TRACED0,TIMER2_CH2,TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT 21 / 60 I/O(2) Level LQFP64 LQFP100 LQFP144 Pin Name BGA100 Pins Pin Type(1) GD32F405xx Functions description Default: PC9 PC9 D12 99 66 40 I/O 5VT Alternate:CK_OUT1,TIMER2_CH3,TIMER7_CH3,I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT Default: PA8 PA8 D11 100 67 41 I/O 5VT Alternate:CK_OUT0,TIMER0_CH0,I2C2_SCL,USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC Default: PA9 PA9 D10 101 68 42 I/O 5VT Alternate:TIMER0_CH1,I2C2_SMBA,SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT Additional: USBFS_VBUS Default: PA10 PA10 C12 102 69 43 I/O 5VT Alternate:TIMER0_CH2,USART0_RX,USBFS_ID,DCI_D1, EVENTOUT, I2C2_TXFRAME Default: PA11 PA11 B12 103 70 44 I/O 5VT Alternate:TIMER0_CH3,USART0_CTS,USART5_TX,CAN0_RX, USBFS_DM, EVENTOUT Default: PA12 PA12 A12 104 71 45 I/O 5VT Alternate:TIMER0_ETI,USART0_RTS,USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT PA13 A11 105 72 46 I/O 5VT Default: JTMS, SWDIO, PA13 Alternate: EVENTOUT NC C11 106 73 47 - - - VSS F11 107 74 P - Default: VSS VDD G11 108 75 48 P - Default: VDD PA14 - A10 109 76 49 I/O 5VT Default: JTCK, SWCLK, PA14 Alternate: EVENTOUT Default: JTDI, PA15 PA15 A9 110 77 50 I/O 5VT Alternate:TIMER1_CH0,TIMER1_ETI,SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT Default: PC10 PC10 B11 111 78 51 I/O 5VT Alternate:SPI2_SCK,I2S2_CK,USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT Default: PC11 PC11 C10 112 79 52 I/O 5VT Alternate:I2S2_ADD_SD,SPI2_MISO,USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT Default: PC12 PC12 B10 113 80 53 I/O 5VT Alternate:I2C1_SDA,SPI2_MOSI,I2S2_SD,USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT PD0 C9 114 81 - I/O 5VT Default: PD0 22 / 60 I/O(2) Level LQFP64 LQFP100 LQFP144 Pin Name BGA100 Pins Pin Type(1) GD32F405xx Functions description Alternate:SPI2_MOSI, I2S2_SD, CAN0_RX, EVENTOUT PD1 B9 115 82 - I/O 5VT PD2 C8 116 83 54 I/O 5VT Default: PD1 Alternate: SPI1_NSS, I2S1_WS, CAN0_TX, EVENTOUT Default: PD2 Alternate:TIMER2_ETI,UART4_RX,SDIO_CMD,DCI_D11, EVENTOUT Default: PD3 PD3 B8 117 84 - I/O 5VT Alternate:TRACED1,SPI1_SCK,I2S1_CK, USART1_CTS, DCI_D5,EVENTOUT PD4 B7 118 85 - I/O 5VT PD5 A6 119 86 - I/O 5VT Default: PD4 Alternate: USART1_RTS, EVENTOUT Default: PD5 Alternate: USART1_TX, EVENTOUT VSS - 120 - - P - Default: VSS VDD - 121 - - P - Default: VDD PD6 B6 122 87 - I/O 5VT PD7 A5 123 88 - I/O 5VT Default: PD6 Alternate:SPI2_MOSI,I2S2_SD,USART1_RX, DCI_D10, EVENTOUT Default: PD7 Alternate:USART1_CK, EVENTOUT Default: PG9 PG9 - 124 - - I/O 5VT PG10 - 125 - - I/O 5VT PG11 - 126 - - I/O 5VT PG12 - 127 - - I/O 5VT PG13 - 128 - - I/O 5VT PG14 - 129 - - I/O 5VT VSS - 130 - - P - Default: VSS VDD - 131 - - P - Default: VDD PG15 - 132 - - I/O 5VT Alternate:USART5_RX, DCI_VSYNC, EVENTOUT Default: PG10 Alternate: DCI_D2,EVENTOUT Default: PG11 Alternate: DCI_D3, EVENTOUT Default: PG12 Alternate: USART5_RTS, EVENTOUT Default: PG13 Alternate:TRACED2, USART5_CTS, EVENTOUT Default: PG14 Alternate:TRACED3, USART5_TX, EVENTOUT Default: PG15 Alternate:USART5_CTS,DCI_D13, EVENTOUT Default: JTDO, PB3 PB3 A8 133 89 55 I/O 5VT Alternate:TRACESWO,TIMER1_CH1,SPI0_SCK,SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT PB4 A7 134 90 56 I/O 5VT Default: NJTRST, PB4 Alternate:TIMER2_CH0,SPI0_MISO,SPI2_MISO, 23 / 60 I/O(2) Level LQFP64 LQFP100 LQFP144 Pin Name BGA100 Pins Pin Type(1) GD32F405xx Functions description I2S2_ADD_SD,I2C2_SDA,SDIO_D0,EVENTOUT, I2C0_TXFRAME Default: PB5 PB5 C5 135 91 57 I/O 5VT Alternate:TIMER2_CH1,I2C0_SMBA,SPI0_MOSI,SPI2_MOSI,I2S2_SD, CAN1_RX,USBHS_ULPI_D7,ETH_PPS_OUT, DCI_D10, EVENTOUT Default: PB6 PB6 B5 136 92 58 I/O 5VT Alternate:TIMER3_CH0,I2C0_SCL,USART0_TX,CAN1_TX, DCI_D5, EVENTOUT Default: PB7 PB7 B4 137 93 59 I/O 5VT Alternate:TIMER3_CH1,I2C0_SDA,USART0_RX, DCI_VSYNC, EVENTOUT BOOT0 A4 138 94 60 I/O 5VT Default: BOOT0 Default: PB8 PB8 A3 139 95 61 I/O 5VT Alternate:TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, SDIO_D4, DCI_D6, EVENTOUT Default: PB9 PB9 B3 140 96 62 I/O 5VT Alternate:TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT PE0 C3 141 97 - I/O 5VT PE1 A2 142 98 - I/O 5VT VSS D3 PDR_ON VDD - H3 143 99 63 - - C4 144 100 64 Default: PE0 Alternate:TIMER3_ETI, DCI_D2, EVENTOUT Default: PE1 Alternate:TIMER0_CH1_ON, DCI_D3, EVENTOUT P - Default: VSS P - Default: PDR_ON P - Default: VDD Notes: 1. Type: I = input, O = output, P = power. 2. I/O Level: 5VT = 5 V tolerant. 24 / 60 GD32F405xx Table 3. Port A alternate functions summary Pin Name PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 USART1_ UART3_TX CTS USART1_ UART3_R RTS X I2S_CKI USART1_T N X I2S1_M USART1_ CK RX SPI0_N SPI2_NSS/I2 USART1_ SS S2_WS CK TIMER1_CH0 TIMER7_C SPI0_S /TIMER1_ETI H0_ON CK TIMER0_BR TIMER2_CH TIMER7_B SPI0_MI I2S1_MCK KIN 0 RKIN SO TIMER0_CH0 TIMER2_CH TIMER7_C SPI0_M _ON 1 H0_ON OSI USART0_ CK_OUT0 TIMER0_CH0 I2C2_SCL CK SPI1_S I2C2_SMB USART0_T TIMER0_CH1 CK/I2S1 A X _CK I2C2_TXF USART0_ TIMER0_CH2 RAME RX USART0_ USART5_T TIMER0_CH3 CTS X USART0_ USART5_ TIMER0_ETI RTS RX JTMS/SWD IO JTCK/SWC LK TIMER1_CH0 SPI0_N SPI2_NSS/I2 USART0_T JTDI /TIMER1_ETI SS S2_WS X AF9 TIMER1_CH0 TIMER4_CH TIMER7_E /TIMER1_ETI 0 TI TIMER4_CH TIMER1_CH1 1 TIMER4_CH TIMER8_C TIMER1_CH2 2 H0 TIMER4_CH TIMER8_C TIMER1_CH3 3 H1 AF10 AF11 AF12 AF13 AF14 AF15 EVENTOUT EVENTOUT EVENTOUT USBHS_U LPI_D0 EVENTOUT USBHS_ DCI_HSYN SOF C USBHS_U LPI_CK TIMER12_ CH0 TIMER13_ CH0 CTC_SYN USBFS_S C OF EVENTOUT SDIO_C DCI_PIXC MD LK USBFS_D M USBFS_D CAN0_TX P CAN0_RX EVENTOUT EVENTOUT SDIO_D1 SDIO_D2 USBFS_ID EVENTOUT EVENTOUT DCI_D0 EVENTOUT DCI_D1 EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT 25 / 60 GD32F405xx Table 4. Port B alternate functions summary Pin Name PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 TIMER0_C TIMER2_C TIMER7_C SPI2_MOSI H1_ON H2 H1_ON /I2S2_SD TIMER0_C TIMER2_C TIMER7_C H2_ON H3 H2_ON TIMER1_C SPI2_MOSI H3 /I2S2_SD JTDO/TRA TIMER1_C SPI2_SCK USART0_R SPI0_SCK CESWO H1 /I2S2_CK X TIMER2_C I2C0_TXF SPI0_MIS SPI2_MIS I2S2_ADD_ NJTRST H0 RAME O O SD SPI2_MO I2C0_SMB SPI0_MO TIMER2_C SI/I2S2_S A SI H1 D TIMER3_C USART0_T I2C0_SCL H0 X TIMER3_C USART0_R I2C0_SDA H1 X TIMER1_C TIMER3_C TIMER9_C H0/TIMER I2C0_SCL H2 H0 1_ETI TIMER1_C TIMER3_C TIMER10_ SPI1_NSS I2C0_SDA H1 H3 CH0 /I2S1_WS TIMER1_C SPI1_SCK USART2_T I2C1_SCL I2S2_MCK H2 /I2S1_CK X TIMER1_C USART2_R I2C1_SDA I2S_CKIN H3 X TIMER0_B I2C1_SMB SPI1_NSS USART2_C RKIN A /I2S1_WS K TIMER0_C I2C1_TXF SPI1_SCK USART2_C H0_ON RAME /I2S1_CK TS TIMER0_C TIMER7_C SPI1_MIS I2S1_ADD USART2_R H1_ON H1_ON O _SD TS SPI1_MO TIMER7_C RTC_REFI TIMER0_C SI/I2S1_S H2_ON N H2_ON D AF8 AF9 AF10 USBHS_U LPI_D1 USBHS_U LPI_D2 USBHS_U LPI_D4 AF11 AF12 AF13 SDIO_D 1 SDIO_D 2 SDIO_C K AF15 EVENTOUT EVENTOUT EVENTOUT I2C1_SDA EVENTOUT SDIO_D 0 I2C2_SDA CAN1_RX AF14 USBHS_U LPI_D7 CAN1_TX CAN0_RX CAN0_TX SDIO_D 4 SDIO_D 5 SDIO_D 7 EVENTOUT DCI_D10 EVENTOUT DCI_D5 EVENTOUT DCI_VSY NC EVENTOUT DCI_D6 EVENTOUT DCI_D7 EVENTOUT USBHS_U LPI_D3 USBHS_U LPI_D4 USBHS_U CAN1_RX LPI_D5 USBHS_U CAN1_TX LPI_D6 TIMER11_ CH0 USBHS_ ID USBHS_ DM EVENTOUT TIMER11_ CH1 USBHS_ DP EVENTOUT EVENTOUT EVENTOUT EVENTOUT EVENTOUT 26 / 60 GD32F405xx Table 5. Port C alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 USBHS_U LPI_STP PC0 PC1 SPI2_MOSI/I2S 2_SD PC2 SPI1_MISO PC3 SPI1_MOSI/I2S 1_SD EVENTOUT USBHS_U LPI_DIR USBHS_U LPI_NXT EVENTOUT EVENTOUT PC4 EVENTOUT USART2_ RX PC5 PC6 PC7 PC8 TRACED0 PC9 CK_OUT1 PC10 PC11 PC12 AF15 EVENTOUT SPI1_MOS I/I2S1_SD I2S1_ADD _SD AF14 TIMER2_ CH0 TIMER2_ CH1 TIMER2_ CH2 TIMER2_ CH3 TIMER7_ I2S1_MCK USART5_TX CH0 TIMER7_ SPI1_SCK/I2S1 I2S2_MC USART5_RX CH1 _CK K TIMER7_ USART5_CK CH2 TIMER7_ I2C2_SD I2S_CKIN CH3 A SPI2_SC USART2_T UART3_TX K/I2S2_C X K SPI2_MIS USART2_ I2S2_ADD_SD UART3_RX O RX SPI2_MO I2C1_SD USART2_ UART4_TX SI/I2S2_S A CK D EVENTOUT SDIO_D6 DCI_D0 EVENTOUT SDIO_D7 DCI_D1 EVENTOUT SDIO_D0 DCI_D2 EVENTOUT SDIO_D1 DCI_D3 EVENTOUT SDIO_D2 DCI_D8 EVENTOUT SDIO_D3 DCI_D4 EVENTOUT SDIO_CK DCI_D9 EVENTOUT PC13 EVENTOUT PC14 EVENTOUT PC15 EVENTOUT 27 / 60 GD32F405xx Table 6. Port D alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 PD0 AF7 AF8 SPI1_NSS /I2S1_WS PD1 PD2 PD3 AF6 SPI2_MOS I/I2S2_SD TIMER2_ETI UART4_RX SPI1_SCK/ I2S1_CK TRACED1 USART1_ CTS AF9 AF10 AF11 AF12 AF13 AF14 AF15 CAN0_R X EVENTOUT CAN0_T X EVENTOUT SDIO_CMD DCI_D11 EVENTOUT DCI_D5 EVENTOUT PD4 USART1_ RTS EVENTOUT PD5 USART1_ TX EVENTOUT SPI2_MOSI /I2S2_SD PD6 USART1_ RX DCI_D10 EVENTOUT PD7 USART1_ CK EVENTOUT PD8 USART2_ TX EVENTOUT PD9 USART2_ RX EVENTOUT PD10 USART2_ CK EVENTOUT PD11 USART2_ CTS EVENTOUT USART2_ RTS EVENTOUT PD12 TIMER3_CH0 PD13 TIMER3_CH1 EVENTOUT PD14 TIMER3_CH2 EVENTOUT TIMER3_CH3 EVENTOUT PD15 CTC_SYN C 28 / 60 GD32F405xx Table 7. Port E alternate functions summary Pin Name AF0 AF1 AF2 AF3 TIMER 3_ETI PE0 TIMER0_CH1 _ON PE1 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 DCI_D2 EVENTOUT DCI_D3 EVENTOUT PE2 TRACECLK EVENTOUT PE3 TRACED0 EVENTOUT PE4 TRACED1 PE5 TRACED2 PE6 TRACED3 DCI_D4 EVENTOUT TIMER8_CH0 DCI_D6 EVENTOUT TIMER8_CH1 DCI_D7 EVENTOUT PE7 TIMER0_ETI EVENTOUT PE8 TIMER0_CH0 _ON EVENTOUT PE9 TIMER0_CH0 EVENTOUT PE10 TIMER0_CH1 _ON EVENTOUT PE11 TIMER0_CH1 EVENTOUT PE12 TIMER0_CH2 _ON EVENTOUT PE13 TIMER0_CH2 EVENTOUT PE14 TIMER0_CH3 EVENTOUT PE15 TIMER0_BR KIN EVENTOUT 29 / 60 GD32F405xx Table 8. Port F alternate functions summary Pin Name AF0 PF0 CTC_SYN C AF1 AF2 AF3 PF1 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 PF3 EVENTOUT I2C1_SCL EVENTOUT EVENTOUT EVENTOUT PF4 EVENTOUT PF5 PF6 PF7 PF8 PF9 AF15 I2C1_SDA I2C1_SMB A I2C1_TXF RAME PF2 AF14 EVENTOUT TIMER9_C H0 TIMER10_ CH0 EVENTOUT EVENTOUT TIMER12_ CH0 TIMER13_ CH0 EVENTOUT EVENTOUT PF10 DCI_D11 EVENTOUT PF11 DCI_D12 EVENTOUT PF12 EVENTOUT PF13 EVENTOUT PF14 EVENTOUT PF15 EVENTOUT 30 / 60 GD32F405xx Table 9. Port G alternate functions summary Pin Name AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 PG0 EVENTOUT PG1 EVENTOUT PG2 EVENTOUT PG3 EVENTOUT PG4 EVENTOUT PG5 EVENTOUT PG6 USART5_ CK USART5_ RTS USART5_ RX PG7 PG8 PG9 PG10 PG11 PG12 PG13 TRACED2 PG14 TRACED3 PG15 USART5_ RTS USART5_ CTS USART5_ TX USART5_ CTS DCI_D12 EVENTOUT DCI_D13 EVENTOUT EVENTOUT DCI_VSY NC EVENTOUT DCI_D2 EVENTOUT DCI_D3 EVENTOUT EVENTOUT EVENTOUT EVENTOUT DCI_D13 EVENTOUT 31 / 60 GD32F405xx 3 Functional description 3.1 ARM® Cortex®-M4 core The ARM® Cortex®-M4 processor is a high performance embedded processor with DSP instructions which allow efficient signal processing and complex algorithm execution. It brings an efficient, easy-to-use blend of control and signal processing capabilities to meet the digital signal control markets demand. The processor is highly configurable enabling a wide range of implementations from those requiring floating point operations, memory protection and powerful trace technology to cost sensitive devices requiring minimal area, while delivering outstanding computational performance and an advanced system response to interrupts. 32-bit ARM® Cortex®-M4 processor core  Up to 168 MHz operation frequency  Single-cycle multiplication and hardware divider  Floating Point Unit (FPU)  Integrated DSP instructions  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex®-M4 processor is based on the ARMv7-M architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex®-M4:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 3072 Kbytes of Flash memory, including code Flash and data Flash  512B of OTP (one-time programmable) memory  192 KB of SRAM The ARM® Cortex®-M4 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 3072 Kbytes of inner Flash at most, which includes code Flash and data Flash is available for storing programs and data, and 32 / 60 GD32F405xx accessed (R/W) at CPU clock speed with zero wait states. Up to 192 Kbytes of inner SRAM is composed of SRAM0 (112KB) and SRAM1 (16KB) that can be accessed at same time, and including 64 KB of TCM (tightly-coupled memory) data RAM that can be accessed only by the data bus of the Cortex®-M4 core. The additional 4KB of backup SRAM (BKP SRAM) is implemented in the backup domain, which can keep its content even when the VDD power supply is down. The Figure of GD32F405xx memory map shows the memory map of the GD32F405xx series of devices, including Flash, SRAM, peripheral, and other pre-defined regions. 3.3 Clock, reset and supply management  Internal 16 MHz factory-trimmed RC and external 4 to 32 MHz crystal oscillator  Internal 48 MHz RC oscillator  Internal 32 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the frequency configuration of the AHB and two APB domains. The maximum frequency of the two AHB domains are 168 MHz. The maximum frequency of the two APB domains including APB1 is 42 MHz and APB2 is 84 MHz. See Figure 6 for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from 2.4 V and down to 1.8V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. 33 / 60 GD32F405xx 3.4 Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main Flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal 30KB of information blocks for the boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0, USART2, and USB Device FS in device mode. It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 2 of Flash memory by setting a bit in option bytes. 3.5 Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are Sleep mode, Deep-sleep mode, and Standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In Deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC16M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the Deep-sleep mode including the 23 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the Deep-sleep mode, the IRC16M is selected as the system clock.  Standby mode In Standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC16M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup Registers) are lost. There are four wakeup sources for the Standby mode, including the external reset from NRST pin, the RTC, the FWDG reset, and the rising edge on WKUP pin. 34 / 60 GD32F405xx 3.6 Analog to digital converter (ADC)  12-bit SAR ADC's conversion rate is up to 2.6MSPS  12-bit, 10-bit, 8-bit or 6-bit configurable resolution  Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit  Input voltage range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Up to three 12-bit 2.6MSPS multi-channel ADCs are integrated in the device. It has a total of 19 multiplexed channels: 16 external channels, 1 channel for internal temperature sensor (VSENSE), 1 channel for internal reference voltage (VREFINT) and 1 channel for external battery power supply (VBAT). The input voltage range is between 2.6 V and 3.6 V. An on-chip hardware oversampling scheme improves performance while off-loading the related computational burden from the CPU. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced use. The ADC can be triggered from the events generated by the general-purpose level 0 timers (TMx) and the advanced-control timers (TM0 and TM7) with internal connection. The temperature sensor can be used to generate a voltage that varies linearly with temperature. It is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage in a digital value. 3.7 Digital to analog converter (DAC)  Two 12-bit DAC converter of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The 12-bit buffered DAC channel is used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. The maximum output value of the DAC is VREF+. 35 / 60 GD32F405xx 3.8 DMA  16 channels DMA controller and each channel are configurable (8 for DMA0 and 8 for DMA1)  Support independent 8, 16, 32-bit memory and peripheral transfer  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S, SDIO and DCI The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Three types of access method are supported: peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9 General-purpose inputs/outputs (GPIOs)  Up to 114 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 140 general purpose I/O pins (GPIO) in GD32F405xx, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~ PH15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except for analog inputs. 36 / 60 GD32F405xx 3.10 Timers and PWM generation  Two 16-bit advanced-control timer (TM0 & TM7), eight 16-bit general-purpose timers (TM2, TM3, TM8 ~ TM13), two 32-bit general-purpose timers (TM1 & TM4) and two 16bit basic timer (TM5 & TM6)  Up to 4 independent channels of PWM, output compare or input capture for each generalpurpose timer (GPTM) and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Free watchdog and window watchdog) The advanced-control timer (TM0 & TM7) can be used as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable dead-time generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for input capture, output compare, PWM generation (edge- or center-aligned counting modes) and single pulse mode output. If configured as a general-purpose 16-bit timer, it has the same functions as the TMx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM), can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. TM1 & TM4 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TM2 & TM3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. TM9 ~ TM13 is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TM5 & TM6, are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F405xx have two watchdog peripherals, free watchdog and window watchdog. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and a 8-bit prescaler, It is clocked from an independent 32 kHz internal RC and as it operates independently of the main clock, it can operate in deep sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog is based on a 7-bit down counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 37 / 60 GD32F405xx The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.11  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC) and backup registers  Independent binary-coded decimal (BCD) format timer/counter with twenty 32-bit backup registers.  Calendar with subsecond, seconds, minutes, hours, week day, date, year and month automatically correction  Alarm function with wake up from deep-sleep and standby mode capability  On-the-fly correction for synchronization with master clock. Digital calibration with 1 ppm resolution for compensation of quartz crystal inaccuracy. The real time clock is an independent timer which provides a set of continuously running counters in backup registers to provide a real calendar function, and provides an alarm interrupt or an expected interrupt. It is not reset by a system or power reset, or when the device wakes up from standby mode. A prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12 Inter-integrated circuit (I2C)  Up to three I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz (Fast mode)  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides two data transfer rates: 100 kHz of standard mode or 400 kHz of the fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 38 / 60 GD32F405xx 3.13 Serial peripheral interface (SPI)  Up to three SPI interfaces with a frequency of up to 30 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14 Universal synchronous/asynchronous receiver transmitter (USART/UART)  Up to four USARTs and two UARTs with operating frequency up to 9 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  ISO 7816-3 compliant smart card interface The USART (USART0, USART1, USART2, USART5) and UART (UART3, UART4) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART/UART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART/UART transmitter and receiver. The USART/UART also supports DMA function for high speed data communication. 3.15 Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz, multiplexed with SPI1 and SPI2  Support either master or slave mode Audio  Sampling frequencies from 8 kHz up to 192 kHz are supported. The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 4-wire serial lines. GD32F405xx contain an I2S-bus interface that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequencies from 8 kHz to 192 kHz is supported. 39 / 60 GD32F405xx 3.16 Universal serial bus on-the-go full-speed (USB OTG FS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal 48 MHz oscillator support crystal-less operation  Internal main PLL for USB CLK compliantly  Internal USB OTG FS PHY support The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers. Transaction formatting is performed by the hardware, including CRC generation and checking. It supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. The required precise 48 MHz clock which can be generated from the internal main PLL (the clock source must use an HXTAL crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode that allows crystal-less operation. 3.17 Universal serial bus on-the-go high-speed (USB OTG HS)  One USB device/host/OTG high-speed Interface with frequency up to 480 Mbit/s  An external PHY device connected to the ULPI is required when using in HS mode USB OTG HS supports both host and device modes, as well as OTG mode with Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). The controller provides ULPI interface for external USB PHY integration and it also contains a full-speed USB PHY internal. For full-speed or low-speed operation, no more external PHY chip is needed. It supports all the four types of transfer (control, bulk, Interrupt and isochronous) defined in USB 2.0 protocol. HUB connection is supported when USB HS operates at high-speed in host mode. There is also a DMA engine operating as an AHB bus master in USBHS to speed up the data transfer between USB HS and system. 3.18 Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for CAN CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 28 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 40 / 60 GD32F405xx 3.19 Secure digital input and output card interface (SDIO)  Support SD2.0/SDIO2.0/MMC4.2 host interface The Secure Digital Input and Output Card Interface (SDIO) provides access to external SD memory cards specifications version 2.0, SDIO card specification version 2.0 and multi-media card system specification version 4.2 with DMA supported. In addition, this interface is also compliant with CE-ATA digital protocol rev1.1. 3.20 Digital camera interface (DCI)  Digital video/picture capture  8/10/12/14 data width supported  High transfer efficiency with DMA interface  Video/picture crop supported  Various pixel formats supported including JPEG/YCrCb/RGB  Hard/embedded synchronous signals supported DCI is an 8-bit to 14-bit parallel interface that able to capture video or picture from a camera via Digital Camera Interface. It supports 8/10/12/14 bits data width through DMA operation. 3.21 Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.22 Package and operation temperature  BGA100 (GDF405VxH), LQFP144 (GD32F405Zx), LQFP100 (GD32F405Vx) and LQFP64 (GD32F405Rx)  Operation temperature range: -40°C to +85°C (industrial level) 41 / 60 GD32F405xx 4 Electrical characteristics 4.1 Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 10. Absolute maximum ratings Symbol Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V VIN IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C Storage temperature range -55 +150 °C Maximum junction temperature — 125 °C TSTG TJ 4.2 Parameter Recommended DC characteristics Table 11. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 42 / 60 GD32F405xx 4.3 Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 12. Power consumption characteristics Symbol Parameter Conditions VDD=VDDA=3.3V, HXTAL=25MHz, System Min Typ Max Unit — 99.2 — mA — 60.1 — mA -— 56.3 — mA — 35.2 — mA — 67.9 — mA — 30 — mA — 1.57 — mA — 1.55 — mA — 5.36 — μA — 5.03 — μA — 4.45 — μA — 2.03 — μA — 1.73 — μA — 1.43 — μA — 1.43 — μA clock=168MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Supply current clock =168MHz, All peripherals disabled (Run mode) VDD=VDDA=3.3V, HXTAL =25MHz, System clock =108MHz, All peripherals enabled VDD=VDDA=3.3V, HXTAL =25MHz, System Clock =108MHz, All peripherals disabled VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=168MHz, All Supply current peripherals enabled (Sleep mode) VDD=VDDA=3.3V, HXTAL =25MHz, CPU clock off, System clock=168MHz, All IDD peripherals disabled VDD=VDDA=3.3V, Regulator in run mode, Supply current (Deep-Sleep mode) IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, Regulator in low power mode, IRC32K on, RTC on, All GPIOs analog mode VDD=VDDA=3.3V, LXTAL off, IRC32K on, RTC on Supply current VDD=VDDA=3.3V, LXTAL off, IRC32K on, (Standby mode) RTC off VDD=VDDA=3.3V, LXTAL off, IRC32K off, RTC off VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Higher IBAT Battery supply current driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Higher driving VDD not available, VBAT=3.6 V, LXTAL on with external crystal, RTC on, Lower driving 43 / 60 GD32F405xx Symbol Parameter Conditions Min Typ — 1.15 — μA — 0.83 — μA VDD not available, VBAT=3.3 V, LXTAL on with external crystal, RTC on, Lower driving VDD not available, VBAT=2.6 V, LXTAL on with external crystal, RTC on, Lower driving 4.4 Max Unit EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the following table, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 13. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and VSS pins Level/Class 3B VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the following table, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 14. EMI characteristics Symbol Parameter Conditions VDD = 5.0 V, SEMI Peak level TA = +25 °C, compliant with IEC 61967-2 Tested frequency band Conditions Unit 24M 48M 0.1 to 2 MHz