WB32F103RBT6

WB32F103xx Medium-density performance line ARM-based 32-bit MCU with up to 128KB Flash, up to 28KB SRAM, USB, 7 timers, 10/12-bit ADC, 11 communication interfaces. Features   Core: ARM 32-bit Cortex™-M3 CPU  72 MHz maximum frequency, 1.25 Comparator  2 independent comparators  Each with 4 positive and 4 negative DMIPS/MHz (Dhrystone 2.1) performance  input channels  64 Byte cache for instruction and data LED driver unit  bus support 0 wait state memory access    Seven-segment LEDs   hardware division external interrupt vectors Memories  64, 96 or 128Kbytes of Flash memory  20 or 28 Kbytes of SRAM   Clock, reset and supply management 26/37/51 I/Os, all mappable on 16 Debug mode  Serial wire debug (SWD) interface 7 timers  Three 20-bit timers, each with up to 4  2.0 to 3.6 V application supply and I/Os IC/OC/PWM or pulse counter and  POR, PDR, and programmable voltage quadrature (incremental) encoder input  20-bit, motor control PWM timer with  4-to-16 MHz crystal oscillator dead-time generation and emergency  Internal 8 MHz factory-trimmed RC stop  Internal 48 MHz factory-trimmed RC  Internal 32 kHz RC  PLL for CPU clock  32 kHz oscillator for RTC with  2 watchdog timers (Independent and Window)   calibration  Up to 51 fast I/O ports Single-cycle multiplication and detector (PVD)  Capable of drive 56 LEDs or 8 Low power SysTick timer: a 24-bit downcounter Up to 11 communication interfaces  2 x I2C interfaces (SMBus/PMBus)  3 UARTs (IrDA capability, modem  Sleep, Stop and Standby modes  VBAT supply for RTC and backup  3 SPI interfaces, 1 QSPI interface registers  I2S interface  Run mode: 150uA/MHz  USB 2.0 full-speed interface  Stop mode: 28uA @3.3V  Standby mode: 4uA @3.3V  VBAT with RTC: 0.5uA @3.3V 10/12-bit mode ADC  Max convert rate: 1Msps  Up to 16 A/D channels  Support 4 channel sample simultaneously in 10-bit mode  Flexible sample and converter modes.  Temperature sensor control)  2 DMA controller, triggered by Timers, ADC, SPIs, I2Cs, UARTs  CRC calculation unit, 96-bit unique ID  RNG generate Random number  Packages are ECOPACK ® Contents 1 Introduction 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Package 2.1 LQFP64 package . . . . . . 2.2 LQFP48 package . . . . . . 2.3 LQFP32 package . . . . . . 2.4 QFN36 package . . . . . . 2.5 QFN32 package . . . . . . 2.6 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block Diagram 4 4 4 7 7 8 8 9 9 10 13 4 System description 4.1 Device Overview . . . . . . . . . . . . . . . . . . . . . 4.2 ARM Cortex™-M3 core . . . . . . . . . . . . . . . . . 4.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . 4.4 System reset . . . . . . . . . . . . . . . . . . . . . . . 4.5 NVIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 EXTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . 4.8 Boot mode . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Power supply schemes . . . . . . . . . . . . . . . . . 4.10 DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11 RTC (real-time clock) and backup registers . . . . . . 4.12 Independent watchdog . . . . . . . . . . . . . . . . . . 4.13 Window watchdog . . . . . . . . . . . . . . . . . . . . 4.14 System Tick . . . . . . . . . . . . . . . . . . . . . . . . 4.15 General-purpose timers . . . . . . . . . . . . . . . . . 4.16 I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . 4.17 Universal asynchronous receiver transmitters (UART) 4.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . 4.19 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20 GPIOs (general-purpose inputs/outputs) . . . . . . . . 4.21 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22 Comparators . . . . . . . . . . . . . . . . . . . . . . . 4.23 Random number generator . . . . . . . . . . . . . . . 4.24 LED Driver . . . . . . . . . . . . . . . . . . . . . . . . 4.25 CRC (cyclic redundancy check) calculation unit . . . . 4.26 Embedded SRAM and Flash memory . . . . . . . . . 4.27 Power supply supervisor . . . . . . . . . . . . . . . . 4.28 Low-power modes . . . . . . . . . . . . . . . . . . . . 4.29 SWD Debug Port . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 16 16 18 18 18 18 18 19 19 19 19 19 20 20 20 20 20 21 21 21 21 21 21 21 22 22 22 22 WB32F103xx datasheet 5 Electrical characteristics 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . 5.1.1 Voltage characteristics . . . . . . . . . . . . . . . . . . . . 5.1.2 Current characteristics . . . . . . . . . . . . . . . . . . . . 5.1.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . 5.2 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 General operating conditions . . . . . . . . . . . . . . . . 5.2.2 Embedded reset and power control block characteristics . 5.2.3 Supply current characteristics . . . . . . . . . . . . . . . . 5.2.4 External clock source characteristics . . . . . . . . . . . . 5.2.5 Internal clock source characteristics . . . . . . . . . . . . 5.2.6 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . 5.2.7 Memory characteristics . . . . . . . . . . . . . . . . . . . 5.2.8 Absolute maximum ratings (electrical sensitivity) . . . . . 5.2.9 EFT Characteristics . . . . . . . . . . . . . . . . . . . . . 5.2.10 IO characteristics . . . . . . . . . . . . . . . . . . . . . . . 5.2.11 TIM characteristics . . . . . . . . . . . . . . . . . . . . . . 5.2.12 USB DC electrical characteristics . . . . . . . . . . . . . . 5.2.13 CMP characteristics . . . . . . . . . . . . . . . . . . . . . 5.2.14 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 24 24 24 25 26 26 27 28 29 29 30 31 32 32 33 33 6 Package characteristics 6.1 LQFP64 10x10mm . 6.2 LQFP64 7X7mm . . 6.3 LQFP48 7X7mm . . 6.4 LQFP32 7X7mm . . 6.5 QFN36 6X6mm . . . 6.6 QFN32 4x4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 37 38 39 40 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Product selection 42 8 Ordering information 44 9 Revision History 46 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 3/46 Chapter 1 Introduction 1.1 Description The WB32F103xx performance line family incorporates the high-performance ARM ®Cortex™-M3 32 bit RISC core operating at 72 MHz maximum frequency, Memory up to 128KB FLASH, 28KB SRAM, One advanced-control timer, Three general-purpose timers, Two watchdog timers (Independent and Window), Three SPI and one QSPI interfaces, Two I2C interfaces, Three UART interfaces, One I2S interface, One USB2.0 Full Speed interface, One 12-bit SAR ADC converter, One LED driver, Two comparators, One RTC. 1.2 Features • Supply Management – Main supply voltage (VDD): 2.0V - 3.6V – Battery supply voltage (VBAT): 1.8V - 3.6V – VBAT for RTC and 84 Byte backup registers • Low Power – Sleep, Stop and Standby modes – Run mode: 105uA/MHz – Stop mode: 18.5uA @3.3V – Standby mode: 4.5uA @3.3V – VBAT with RTC: 1.1uA @3.3V • Operation temperature – Industrial temperature range (-40°C ∼ +85°C) – Commercial temperature range (0°C ∼ 85°C) • Reset – NRST reset – Power On reset – Software reset – Watchdog (IWDT and WWDT) reset – Low power mode reset • Programmable Voltage Detector (PVD) – Adjustable 8 detect levels 4 WB32F103xx datasheet – Configurable rising/falling detect edges • Clock – 4 -16 MHz crystal oscillator, typical 8MHz (HSE) – 32 kHz oscillator for RTC with calibration (LSE) – Internal 8 MHz factory-trimmed RC (MHSI) – Internal 48 MHz factory-trimmed RC (FHSI) – Internal 32 kHz RC (LSI) – PLL for CPU clock • High performance 32-bit ARM CPU Core – Up to 72 MHz ARM Cortex™-M3 Core – 64 Byte cache for instruction and data bus, support 0 wait state memory access – Configurable system clock frequency – Nestable interrupt vector controller – Single-cycle multiplication and hardware division – 24-bit System Tick down-counter • Flash – 64KB ∼ 128KB Flash • SRAM – 20KB ∼ 28KB SRAM • 12-bit SAR A/D converter – Up to 16 A/D input channels – Max convert rate: 1Msps – Continuous sample and converter mode. – Software or Hardware triggered A/D converter mode. – Temperature sensor connect to A/D channel 16. • Comparator – 2 independent comparators – 4 positive and 4 negative input channels for each comparator • Debug Port – Serial wire debug (SWD) – Cortex-M3 Instrumentation Trace Macrocell (ITM) • Communication interfaces – Up to 3 UART interfaces – 3 SPI interfaces, 1 QSPI interface – 2 I2C interfaces, support SMBus 2.0/PMBus • Timers – Three 20-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 20-bit PWM counter – Trigger A/D convertor ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 5/46 WB32F103xx datasheet • General purpose IOs – 64-pin production has 51 GPIOs, 48-pin production has 37 GPIOs, 36-pin production has 26 GPIOs, 32-pin production has 25 GPIOs – All GPIO mappable on 16 external interrupt vectors – Up to 16mA drive current • Mulit-channel DMA controller, can be triggered by Timers, ADC, SPIs, I2Cs, UARTs • CRC calculation unit,support 8/ 16/ 32 bit CRC algorithms. • RNG Unit, generate Random number • LED driver unit, support up to 56 LEDs or 8 Seven-segment LEDs. • Real-time clock counter (RTC) • Support software second development • Support LQFP64, LQFP48, QFN36, QFN32 packages ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 6/46 Chapter 2 Package 2.1 LQFP64 package PB3 PD2 PC12 PC11 PC10 PA15 PA14 PB6 PB5 PB4 PB8 BOOT0 PB7 VDD_3 VSS_3 PB9 Figure 2.1: LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD_2 PC13-TAMPER-RTC PC14-OSC32_IN 2 47 46 VSS_2 PA13 45 PA12 44 43 PA11 PA10 42 PA9 41 40 PA8 PC9 PB15 14 15 16 35 PB14 34 PB13 33 PB12 7 VSS_1 VDD_1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB2 PA2 PC6 36 PB10 PA11 PA1 PC7 37 PB0 PB1 VDDA PA0-WKUP PC8 38 PC5 VSSA 39 11 12 13 PC4 PC3 LQFP64 PA6 PA7 PC2 7 8 9 10 PA5 PC0 PC1 6 PA4 NRST 5 PA3 PD0-OSC_IN PD1-OSC_OUT VSS_4 VDD_4 PC15-OSC32_OUT 3 4 WB32F103xx datasheet 2.2 LQFP48 package PB3 PA1 PA14 PB6 PB5 PB4 PB8 BOOT0 PB7 VDD_3 VSS_3 PB9 Figure 2.2: LQFP48 pinout 48 47 46 45 44 43 42 41 40 39 38 37 VBAT 1 36 VDD_2 PC13-TAMPER-RTC PC14-OSC32_IN 2 35 34 VSS_2 PA13 33 PA12 32 31 PA11 PA10 30 PA9 29 28 PA8 PB15 27 PB14 26 PB13 25 PB12 PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WUKUP PA1 PA2 3 4 5 6 LQFP48 7 8 9 10 11 12 VDD_1 PB11 VSS_1 PB10 PB2 PB0 PB1 PA7 PA6 PA3 PA4 PA5 13 14 15 16 17 18 19 20 21 22 23 24 2.3 LQFP32 package PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 VSS_3 Figure 2.3: LQFP32 pinout 32 31 30 29 28 27 26 25 VDD 1 24 PA14 OSC_IN/PD0 2 23 PA13 OSC_OUT/PD1 3 22 PA12 NRST 4 21 PA11 VDDA 5 20 PA10 PA0-WKUP 6 19 PA9 PA1 7 18 PA8 PA2 8 17 VDD_1 LQFP32 VSS_1 PB1 PB0 PA7 PA6 PA5 10 11 12 13 14 15 16 PA4 PA3 9 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 8/46 WB32F103xx datasheet 2.4 QFN36 package PA14 PA15 PB3 PB4 PB5 PB6 PB7 VSS_3 BOOT0 Figure 2.4: QFN36 pinout VDD 1 36 35 34 33 32 31 30 29 28 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 VDDA 5 23 PA11 VSSA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 19 10 11 12 13 14 15 16 17 18 VDD_1 VSS_1 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 QFN36 2.5 QFN32 package PA15 PB3 PB4 PB5 PB6 PB7 BOOT0 VSS_3 Figure 2.5: QFN32 pinout VDD 1 32 31 30 29 28 27 26 25 24 PA14 OSC_IN/PD0 2 23 PA13 OSC_OUT/PD1 3 22 PA12 NRST 4 21 PA11 VDDA 5 20 PA10 PA0-WKUP 6 19 PA9 PA1 7 18 PA8 PA2 8 VDD_1 VSS_1 PB1 PB0 PA7 PA4 PA6 17 10 11 12 13 14 15 16 PA5 9 PA3 QFN32 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 9/46 WB32F103xx datasheet 2.6 Pinouts and pin description Table 2.1: Pinout description QFN32 QFN36 LQFP48 LQFP64 Pin No. Pin Name 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 23 24 25 - 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 25 26 27 28 29 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 34 35 36 37 38 - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 46 47 48 49 50 51 52 53 54 VBAT PC13 PC14 PC15 PD0 PD1 NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0 PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA13 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 PD2 Type S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S I/O I/O I/O I/O I/O I/O Main Function Alternate Function Analog Function VBAT TAMPER/RTC PC13 OSC32_IN PC14 OSC32_OUT PC15 OSC_IN PD0 OSC_OUT PD1 NRST SPIM2_NSS0/SPIS2_NSS ADC_IN10 PC0 SPIM2_SCK/SPIS2_SCK ADC_IN11 PC1 SPIM2_MI/SPIS2_SO ADC_IN12 PC2 SPIM2_MO/SPIS2_SI ADC_IN13 PC3 VSSA VDDA TIM2_CH1_ETR/UART2_CTS/WKUP ADC_IN0 PA0/WKUP TIM2_CH2/UART2_RTS ADC_IN1 PA1 TIM2_CH3/UART2_TX ADC_IN2 PA2 TIM2_CH4/UART2_RX ADC_IN3 PA3 VSS_4 VDD_4 QSPI_NSS0/SPIS1_NSS/UART2_CK ADC_IN4 PA4 QSPI_SCK/SPIS1_SCK ADC_IN5 PA5 TIM3_CH1/QSPI_MI_IO1/SPIS1_SO ADC_IN6 PA6 TIM3_CH2/QSPI_MO_IO0/SPIS1_SI ADC_IN7 PA7 TRACECK ADC_IN14 PC4 SPIM2_NSS2/TRACED0 ADC_IN15 PC5 TIM3_CH3/QSPI_IO2 ADC_IN8 PB0 TIM3_CH4/QSPI_IO3 ADC_IN9 PB1 PB2/BOOT1 TIM2_CH3/TIM4_CH1/I2C2_SCL/QSPI_NSS2/UART3_TX PB10 TIM2_CH4/I2C2_SDA/SPIM2_NSS1/UART3_RX PB11 VSS_1 VDD_1 LED4/SPIM2_NSS0/SPIS2_NSS/UART3_CK PB12 LED5/SPIM2_SCK/SPIS2_SCK/UART3_CTS PB13 LED6/SPIM2_MI/SPIS2_SO/UART3_RTS PB14 LED7/SPIM2_MO/SPIS2_SI PB15 TIM3_CH1/LED0 PC6 TIM3_CH2/LED1 PC7 TIM3_CH3/LED2 PC8 TIM3_CH4/LED3/TRACED1 PC9 LED0/UART1_CK/MCO CMPA_P0 PA8 LED1/UART1_TX CMPA_N0 PA9 LED2/UART1_RX PA10 QSPI_NSS1 CMPA_P3 SWDIO VSS_2 VDD_2 QSPI_NSS2 CMPA_N3 SWDCLK TIM2_CH1_ETR/I2C1_SMBAI/QSPI_NSS0/SPIS1_NSS CMPB_P3 PA15 LED4/UART3_TX/TRACED2 CMPB_P1 PC10 LED5/UART3_RXTRACED3 CMPB_P2 PC11 TIM4_ETR/LED6/UART3_CK CMPB_N0 PC12 TIM3_ETR/LED7 CMPB_P0 PD2 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 10/46 WB32F103xx datasheet QFN32 QFN36 LQFP48 LQFP64 Pin No. Pin Name 26 27 28 29 30 31 32 1 30 31 32 33 34 5 36 1 39 40 41 42 43 44 45 46 47 48 55 56 57 58 59 60 61 62 63 64 PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 Type Main Function I/O I/O I/O I/O I/O I I/O I/O S S PB3 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 Alternate Function Analog Function SWO/TIM2_CH2/QSPI_SCK/SPIS1_SCK TIM3_CH1/QSPI_MI_IO1/SPIS1_SO TIM3_CH2/I2C1_SMBAI/QSPI_MO_IO0/SPIS1_SI TIM4_CH1/I2C1_SCL/QSPI_NSS1/UART1_TX TIM4_CH2/I2C1_SDA/SPIM2_NSS1/UART1_RX CMPB_N3 CMPA_P1 CMPA_P2 CMPA_N1 CMPA_N2 TIM4_CH3/I2C1_SCL/SPIM2_NSS2/UART1_CTS TIM4_CH4/I2C1_SDA/UART1_RTS CMPB_N1 CMPB_N2 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 11/46 WB32F103xx datasheet WB32F103xx performance line GPIO function selection: Table 2.2: Pin func selection AFR[3:0] 0 1 PORT TIM2_CH1_ETR WKUP PA0 A TIM2_CH2 PA1 TIM2_CH3 PA2 TIM2_CH4 PA3 PA4 PA5 PA6 PA7 PA8 MCO PA9 PA10 PA11 PA12 PA13 SWD_DIO PA14 SWD_CLK TIM2_CH1_ETR PA15 PORT PB0 B PB1 BOOT1 PB2 TIM2_CH2 PB3 SWO PB4 PB5 PB6 PB7 PB8 PB9 TIM2_CH3 PB10 TIM2_CH4 PB11 PB12 PB13 PB14 PB15 PORT PC0 C PC1 PC2 PC3 PC4 TRACECK PC5 TRACED0 PC6 PC7 PC8 PC9 TRACED1 PC10 TRACED2 PC11 TRACED3 PC12 PC13 TAMPER_RTC PC14 OSC32_IN PC15 OSC32_OUT PORT OSC_IN PD0 D PD1 OSC_OUT PD2 2 3 4 5 6 7 UART2_CTS TIM3_CH1 TIM3_CH2 LED0 LED1 LED2 LED3 I2C1_SMBAI UART2_RTS UART2_TX UART2_RX QSPI_NSS0 SPIS1_NSS UART2_CK QSPI_SCK SPIS1_SCK QSPI_MI_IO1 SPIS1_SO QSPI_MO_IO0 SPIS1_SI UART1_CK UART1_TX UART1_RX UART1_CTS UART1_RTS QSPI_NSS1 QSPI_NSS2 QSPI_NSS0 SPIS1_NSS TIM3_CH3 QSPI_IO2 TIM3_CH4 QSPI_IO3 TIM3_CH1 TIM3_CH2 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_CH4 TIM4_CH1 QSPI_SCK SPIS1_SCK QSPI_MI_IO1 SPIS1_SO I2C1_SMBAI QSPI_MO_IO0 SPIS1_SI UART1_TX I2C1_SCL QSPI_NSS1 UART1_RX I2C1_SDA SPIM2_NSS1 I2C1_SCL SPIM2_NSS2 UART1_CTS I2C1_SDA UART1_RTS UART3_TX I2C2_SCL QSPI_NSS2 UART3_RX I2C2_SDA SPIM2_NSS1 SPIM2_NSS0 SPIS2_NSS UART3_CK LED4 SPIM2_SCK SPIS2_SCK UART3_CTS LED5 SPIM2_MI SPIS2_SO UART3_RTS LED6 SPIS2_SI SPIM2_MO LED7 SPIM2_NSS0 SPIS2_NSS SPIM2_SCK SPIS2_SCK SPIM2_MI SPIS2_SO SPIS2_SI SPIM2_MO SPIM2_NSS2 TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 TIM4_ETR LED0 LED1 LED2 LED3 LED4 LED5 LED6 TIM3_ETR LED7 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 UART3_TX UART3_RX UART3_CK 12/46 Chapter 3 Block Diagram WB32F103xx performance line block diagram: Figure 3.1: WB32F103xx block diagram SWD SWCLK SWDIO IS FMC DS Cortex-M3 IBUS AHB BUS Matrix MAIN SS NVIC NRST, OSC_IN, OSC_OUT WKUP RCC PWR 36KB SRAM BKP SFM AHB2APB CMP RTC ISO IWDG CRC CMP_CH0~ CMP_CH15 256KB Flash CACHE USB AHB2APB TAMPIN OSC32_IN OSC32_OUT ISOCLK ISODA USBDP USBDM FIFO AHB BUS Matrix MAIN DMA 1 DMA 2 RC 8Mhz AHB BUS Matrix 1 4 Channels， 3 compl.Channels, Brk input AHB BUS Matrix 2 RC 48Mhz TIM1 RCC RC 32Khz WWDG LED LED00~ LED07 RNG SPIM2 NSSx,SCK, MI,MO 4 Channels TIM2 4 Channels TIM3 AFIO SPIS2 NSS,SCK, SI,SO 4 Channels TIM4 GPIOA I2C1 SMBAI, SDA,SCL RX,TX,CK, RTS,CTS UART1 GPIOB I2C2 SDA,SCL NSSx,SCK, MIO0~MIO3 QSPI GPIOC UART2 RX,TX,CK, RTS,CTS NSS,SCK, SI,SO SPIS1 GPIOD UART3 RX,TX,CK, RTS,CTS ADC EXTI I2S CH0~CH15 51 PORTs PD[2:0] PC[15:0] PB[15:0] PA[15:0] 13 MCLK,SCLK, WS,SD0,SD1 Chapter 4 System description 4.1 Device Overview Table below show WB32F103xx device features and peripherals: 14 WB32F103xx datasheet Communication Timers Table 4.1: WB32F103xx device features and peripheral counts Peripheral WB32F103Kx Flash(KB) 64 64 128 64 96 128 SRAM(KB) 20 20 28 20 28 28 General-purpose 3 3 3 3 3 3 Advanced-Control 1 1 1 1 1 1 QSPI(Master) 1 1 1 1 1 1 SPIM 0 1 1 1 1 1 SPIS 1 2 2 2 2 2 I2 C 1 2 2 2 2 2 UART 2 3 3 3 3 3 USB 1 1 1 1 1 1 I2 S 0 0 1 0 0 1 25 37 37 51 51 51 12-bit ADC 1 1 1 1 1 1 ADC channels 10 10 10 16 16 16 Number 2 2 2 2 2 2 CMP channel 10 12 12 16 16 16 Comparators ADC GPIOs WB32F103Cx WB32F103Rx CPU frequency 72 MHz Operating voltage 2.0V ∼ 3.6V Operating temperatures Packages Industrial temperature�-40°C ∼ +85°C QFN32 Junction temperature�-40°C ∼ +125°C LQFP48 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 LQFP64 15/46 WB32F103xx datasheet 4.2 ARM Cortex™-M3 core Cortex™ M3 is a 32-bit RISC processor core with three levels pipeline. It includes the AMBA-Lite interface and is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), which is a low cost but high performance MCU platform. It has optional hardware debugging function, can execute Thumb-2 instruction, and is compatible with other Cortex-M series. WB32F103xx performance line family incorporates the ARM ®Cortex™-M3 processor core, so it is compatible with all ARM tools and software. 4.3 Memory map Program memory, data memory, system memory and AHB/APB peripherals are organized within the same linear 4-GB address space. The addressable memory space is divided into 8 main blocks, each of 512 MB. AHB peripheral address space is 64KB, can support up to 64 peripherals. APB peripheral address space is 64KB, each peripheral can use up to 1KB address space. APB peripheral only support word access, byte and half-word accesses are not supported. System memory address space is 4KB and reserved for ISP program. The WB32F103xx memory map is organized below: ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 16/46 WB32F103xx datasheet Figure 4.1: WB32F103xx memory map 0xFFFF_FFFF 7 0xE010_0000 0xE000_0000 Cortex-M3 Internal Peripherials 6 0xC000_0000 5 0xA000_0000 0x2008_13FF Data Memory 2 0x2008_1000 4 Reserved 0x2000_9000 Data Memory 1 0x8000_0000 0x2000_1000 Data Memory 0 3 0x2000_0000 0x1FFF_FFFF Option Byte 0x1FFF_F000 0x6000_0000 System Memory 0x1FFF_E000 2 Reserved Peripherials 0x0804_0000 0x4000_0000 Flash memory (256KB) 1 0x0800_0000 SRAM Reserved 0x2000_0000 0x0004_0000 0 Aliased Flash memory 0x0000_1000 Aliased to Flash or system memory depending on BOOT pins 0x0000_0000 0x0000_0000 ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 0x4001_FC00 RESERVED 0x4001_8000 RESERVED 0x4001_7C00 RESERVED 0x4001_7800 FMC 0x4001_7400 RESERVED 0x4001_6800 RESERVED 0x4001_6400 SYS 0x4001_6000 ISO 0x4001_5C00 BKP 0x4001_5800 RTC 0x4001_5400 CACHE 0x4001_5000 RESERVED 0x4001_4C00 SFM 0x4001_4800 CRC 0x4001_4400 RESERVED 0x4001_4000 USB 0x4001_3C00 RESERVED 0x4001_1000 RESERVED 0x4001_0C00 RCC 0x4001_0800 IWDG 0x4001_0400 ANCTL 0x4001_0000 PWR 0x4000_FC00 DMA 2 0x4000_F800 RESERVED 0x4000_C000 RESERVED 0x4000_BC00 LED 0x4000_B800 RNG 0x4000_B400 I2S 0x4000_B000 RESERVED 0x4000_9C00 RESERVED 0x4000_9800 WWDG 0x4000_9400 SPIS2 0x4000_9000 SPIM2 0x4000_8C00 I2C2 0x4000_8800 I2C1 0x4000_8400 UART3 0x4000_8000 UART2 0x4000_7C00 DMA 1 0x4000_7800 RESERVED 0x4000_4000 RESERVED 0x4000_3C00 ADC 0x4000_3800 UART1 0x4000_3400 SPIS1 0x4000_3000 QSPI 0x4000_2C00 RESERVED 0x4000_2800 TIM4 0x4000_2400 TIM3 0x4000_2000 TIM2 0x4000_1C00 TIM1 0x4000_1800 EXTI 0x4000_1400 AFIO 0x4000_1000 RESERVED 0x4000_0C00 GPIOD 0x4000_0800 GPIOC 0x4000_0400 GPIOB 0x4000_0000 GPIOA 17/46 WB32F103xx datasheet 4.4 System reset System reset can be triggered by the sources below: • POR reset (POR) • NRST • WDG reset (IWDG and WWDG) • CPU Software reset • Exiting standby mode Any source above can trigger the sysrem reset. When the working voltage is proper, the MHSI will be turned on and keep active. When NRST is asserted to high level, the oscillator will start running, and the flash controller will finish the device initilization. 4.5 NVIC Cortex™-M3 is tightly coupled with the Nested Vectored Interrupt Controller (NVIC). This hardware block provides flexible interrupt management features with minimal interrupt latency. The main feature includes: • low latency interrupt processing • handle the system exceptions/faults and peripheral interrupts/events • support up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) • four programmable levels for the interrupt priority • generate the software interrupt • configurable Non Maskable Interrupt (NMI). 4.6 EXTI The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. 4.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock, internal RC 48 MHz oscillator or clock output from PLL can be selected as system clock. When An external 4-16 MHz clock is used, it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC 8 MHz oscillator. A software interrupt is generated if enabled. Several prescalers allow the configuration frequency of the AHB, APB1 and APB2 domains. The maximum frequency of the AHB, APB1 and APB2 is 72 MHz, and the frequency of them can be configured independently. 4.8 Boot mode At startup, boot pins are used to select one of three boot options: ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 18/46 WB32F103xx datasheet • Boot from user Flash • Boot from system memory • Boot from embedded SRAM 4.9 Power supply schemes • VDD = 2.0∼3.6V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VDDA = 2.4∼3.6V: external analog power supplies for ADC, and the minimum voltage should be 2.4 V when the ADC is used. • VBAT = 1.8∼3.6V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Note: VDDA must be the same potential as VDD. It is recommended to power VDD and VDDA from the same source. 4.10 DMAC Two general-purpose DMACs, each have 3 channels and up to 16 hardware DMA requests (16 requests for DMAC0 and 12 requests for DMAC1) are able to manage memory-to-memory, peripheral-to-memory and memoryto-peripheral transfers. The two DMA controllers have internal arbitor to arbitrate the priority of DMA requests. Each channel can be configured with to hardware DMA requests, or also support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, UART, TIMx and ADC. 4.11 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. 4.12 Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 4.13 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. ©2022 WestBerryTech Co.Ltd All Rights Reserved. Doc ID 10103 Rev03 19/46 WB32F103xx datasheet 4.14 System Tick This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Clock source is fixed to 1/8 of CPU frequency 4.15 General-purpose timers There are up to 3 synchronizable general-purpose timers (TIM2, TIM3 and TIM4) embedded in the WB32F103xx performance line devices. These timers are based on a 20-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one- pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. 4.16 I2C bus Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support standard (