BY25Q40ALUIG(R)

Boya Microelectronics Memory Series BY25Q40AL 4M BIT SPI NOR FLASH Features ● Serial Peripheral Interface (SPI) - Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD - Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD - Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3 - Software Reset ● Read - Normal Read Data: 33MHz clock rate - others Read Data: 85MHz clock rate ● Program - Serial-input Page Program up to 256bytes - Dual-input Page Program up to 256bytes - Quad-input Page Program up to 256bytes - Program Suspend and Resume ● Erase - Page erase (256-byte) - Block erase (64/32 KB) - Sector erase (4 KB) - Chip erase - Erase Suspend and Resume ● Program/Erase Speed - Page Program time: 2ms typical - Page Erase time: 8ms typical - Sector/Block Erase time: 8ms typical - Chip Erase time: 8ms typical ● Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte ● Low Power Consumption - 3mA maximum active current - 0.6uA maximum power down current ● Software/Hardware Write Protection - 3x512-Byte Security Registers with OTP Lock - Enable/Disable protection with WP Pin - Write protect all/portion of memory via software protect - Top or Bottom, Sector or Block selection ● Single Supply Voltage - Full voltage range: 1.65~2.0V ● Temperature Range - Commercial (0℃ to +70℃) - Industrial (-40℃ to +85℃) ● Cycling Endurance/Data Retention - Typical 100k Program-Erase cycles on any sector - Typical 20-year data retention August 2019 Rev 1.4 1 / 75 BY25Q40AL Contents Contents 1. Description ................................................................................. 4 2. Signal Description ...................................................................... 6 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Input/Output Summary ................................................................................. 6 Chip Select (/CS) .......................................................................................... 6 Serial Clock (SCLK) ..................................................................................... 6 Serial Input (SI)/IO0 ..................................................................................... 6 Serial Data Output (SO)/IO1......................................................................... 7 Write Protect (/WP)/IO2 ............................................................................... 7 HOLD (/HOLD)/IO3 .................................................................................... 7 VCC Power Supply ....................................................................................... 7 VSS Ground .................................................................................................. 7 3. Block/Sector Addresses ............................................................. 8 4. Function Descriptions ................................................................. 9 4.1 4.2 4.3 Standard SPI Instructions .............................................................................. 9 Dual SPI Instructions .................................................................................... 9 Quad SPI Instructions ................................................................................... 9 5. Operation Features .................................................................. 10 5.1 Supply Voltage ............................................................................................ 10 5.1.1 Operating Supply Voltage ............................................................... 10 5.1.2 Power-up Conditions ....................................................................... 10 5.1.3 Device Reset .................................................................................... 10 5.1.4 Power-down ...................................................................................... 10 5.2 Active Power and Standby Power Modes ................................................... 10 5.3 Hold Condition............................................................................................ 10 5.4 Status Register............................................................................................. 12 5.4.1 The Status and Control Bits ........................................................... 12 5.4.2 Status Register Memory Protection .............................................. 14 6. Device Identification ................................................................. 16 7. Instructions Description ............................................................ 17 7.1 Configuration and Status Instructions ......................................................... 20 7.1.1 Write Enable (06H) .......................................................................... 20 7.1.2 Write Enable for Volatile Status Register (50h) ........................... 20 7.1.3 Write Disable (04h) .......................................................................... 21 7.1.4 Read Status Register-1 (05h), Status Register-2 (35h)............. 22 7.1.5 Active Status Interrupt (25h) .......................................................... 23 7.1.6 Write Status Register (01h) ............................................................ 24 7.2 Read Instructions......................................................................................... 25 7.2.1 Normal Read Data (03H) ................................................................ 25 7.2.2 Fast Read (0BH) .............................................................................. 26 7.2.3 Fast Read Dual Output (3Bh) ........................................................ 27 7.2.4 Fast Read Quad Output (6Bh) ....................................................... 28 7.2.5 Fast Read Dual I/O (BBh)............................................................... 29 7.2.6 Fast Read Quad I/O (EBh) ............................................................. 31 7.2.7 Set Burst with Wrap (77h) .............................................................. 33 7.3 ID and Power Instructions........................................................................... 34 7.3.1 Deep Power-down (B9h) ................................................................ 34 7.3.2 Release Power-down / Device ID (ABh) ...................................... 35 7.3.3 Read Manufacturer / Device ID (90h) ........................................... 36 7.3.4 Read Manufacturer / Device ID Dual I/O (92h) ........................... 37 August 2019 Rev 1.4 2 / 75 BY25Q40AL Contents 7.3.5 Read Manufacturer / Device ID Quad I/O (94h) ......................... 38 7.3.6 Read JEDEC ID (9Fh)..................................................................... 39 7.3.7 Read Unique ID Number (4Bh).......................................................... 40 7.4 Program / Erase and Security Instructions .................................................. 41 7.4.1 Page Program (02h) ........................................................................ 41 7.4.2 Dual Page Program (A2h) .............................................................. 42 7.4.3 Quad Page Program (32h) ............................................................. 43 7.4.4 Page Erase (81h/DBh) .................................................................... 44 7.4.5 Sector Erase (20h)........................................................................... 45 7.4.6 32KB Block Erase (52h) ................................................................. 46 7.4.7 64KB Block Erase (D8h) ................................................................. 47 7.4.8 Chip Erase (C7h / 60h) ................................................................... 48 7.4.9 Program/Erase Suspend (75h) ...................................................... 49 7.4.10 Program/Erase Resume (7Ah) ............................................... 51 7.4.11 Erase Security Registers (44h) ............................................... 52 7.4.12 Program Security Registers (42h) .......................................... 53 7.4.13 Read Security Registers (48h)................................................ 54 7.4.14 Enable Reset (66h) and Reset Device (99h)........................ 55 7.4.15 Read Serial Flash Discoverable Parameter (5AH) .............. 56 8. Electrical Characteristics .......................................................... 61 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 Absolute Maximum Ratings ....................................................................... 61 Operating Ranges ........................................................................................ 61 Power-up Timing......................................................................................... 62 DC Electrical Characteristics ...................................................................... 63 AC Measurement Conditions ...................................................................... 64 AC Electrical Characteristics ...................................................................... 65 AC Electrical Characteristics (cont’d) ........................................................ 66 Serial Output Timing ................................................................................... 67 Serial Input Timing ..................................................................................... 67 /HOLD Timing ............................................................................................ 67 /WP Timing ................................................................................................. 67 9. Package Information ................................................................ 68 9.1 9.2 9.3 9.4 9.5 Package 8-Pin SOP 150-mil ........................................................................ 68 Package 8-Pin SOP 208-mil ........................................................................ 69 Package 8-Pin TSSOP 173-mil ................................................................... 70 Package USON8 (2*3-0.50mm) ................................................................. 71 Package USON8 (2*3-0.55mm) ................................................................. 72 10. Order Information ..................................................................... 73 10.1 10.2 Valid part Numbers and Top Side Marking................................................. 74 Minimum Packing Quantity (MPQ) ........................................................... 74 11. Document Change History ....................................................... 75 August 2019 Rev 1.4 3 / 75 Description BY25Q40AL 1. Description The BY25Q40AL is 4M-bit Serial Peripheral Interface (SPI) Flash memory, designed for using in a wide variety of high-volume consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the device, with its page erase granularity it is ideal for data storage as well, eliminating the need for additional data storage devices. The erase block sizes of the device have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device density. The device uses a single low voltage power supply, ranging from 1.65 Volt to 2.0 Volt, and supports JEDEC standard manufacturer and device ID, a 128-bit Unique Serial Number and three 512-bytes Security Registers. August 2019 Rev 1.4 4 / 75 Description BY25Q40AL Figure 1. Logic diagram VCC SCLK SO SI /CS BY25QXX /WP /HOLD VSS Figure 2. Pin Configuration SOP8/TSSOP8 Top View /CS 1 SO 2 8 VCC 7 HOLD SOP8/TSSOP8 /WP 3 6 SCLK VSS 4 5 SI Figure 3. Pin Configuration DFN 2*3mm /CS 1 8 VCC SO 2 7 /HOLD Top View August 2019 /WP 3 6 SCLK VSS 4 5 SI Rev 1.4 5 / 75 BY25Q40AL Signal Description 2. Signal Description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, see Section 8.4, DC Electrical Characteristics). These signals are described next. 2.1 Input/Output Summary Table 1. Signal Names Pin Name I/O /CS I SO (IO1) I/O /WP (IO2) I/O VSS Chip Select Serial Output for Standard SPI mode IO1 for Dual or Quad SPI mode Write Protect in Standard SPI mode or Dual SPI mode IO2 in Quad SPI mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad SPI mode. Ground SI (IO0) I/O SCLK I /HOLD (IO3) I/O VCC Description Serial Input for Standard SPI mode. IO0 for Dual or Quad SPI mode. Serial Clock Hold (pause) serial transfer in Standard SPI mode or Dual SPI mode. IO3 in Quad SPI mode. The signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad SPI mode. Core and I/O Power Supply 2.2 Chip Select (/CS) The chip select signal indicates when an instruction for the device is in process and the other signals are relevant for the memory device. When the /CS signal is at the logic high state, the device is not selected and all input signals are ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers embedded operation is in progress, the device will be in the Standby Power mode. Driving the /CS input to logic low state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction. 2.3 Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. 2.4 Serial Input (SI)/IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 an input and output during Dual and Quad SPI mode for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). August 2019 Rev 1.4 6 / 75 BY25Q40AL Signal Description 2.5 Serial Data Output (SO)/IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. SO becomes IO1 an input and output during Dual and Quad SPI mode for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). 2.6 Write Protect (/WP)/IO2 When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protected by the Block Protect, BP4, BP3 bits in the status registers, are also hardware protected against data modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1). The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for Quad mode. 2.7 HOLD (/HOLD)/IO3 The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). When QE=0, the IO3 pin can be configured either as a /HOLD pin. When QE=1, the /HOLD function is not available. The HOLD function is replaced by IO3 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). 2.8 VCC Power Supply VCC is the supply voltage. It is the single voltage used for all device functions including read, program, and erase. 2.9 VSS Ground VSS is the reference for the VCC supply voltage. August 2019 Rev 1.4 7 / 75 Block/Sector Addresses BY25Q40AL 3. Block/Sector Addresses Table 2. Block/Sector Addresses of BY25Q40AL Memory Density Block(64k byte) Block(32k byte) Sector 0 Sector Size(KB) 4 000000h-000FFFh ： ： ： Sector 7 4 007000h-007FFFh Sector 8 4 008000h-008FFFh ： 4 ： Sector 15 4 00F000h-00FFFFh Sector 16 4 010000h-010FFFh ： ： ： Sector 23 4 017000h-017FFFh Sector 24 4 018000h-018FFFh ： ： ： Sector 31 4 01F000h-01FFFFh ： ： ： Sector 96 4 060000h-060FFFh ： ： ： Sector 103 4 067000h-067FFFh Sector 104 4 068000h-068FFFh ： 4 ： Sector 111 4 06F000h-06FFFFh Sector 112 4 070000h-070FFFh ： ： ： Sector 119 4 077000h-077FFFh Sector 120 4 078000h-078FFFh ： ： ： Sector 127 4 07F000h-07FFFFh Sector No. Half block 0 Block 0 Half block 1 Half block 2 Block 1 Half block 3 4Mbit ： ： Half block 12 Block 6 Half block 13 Half block 14 Block 7 Half block 15 Address range Notes: 1. Block = Uniform Block, and the size is 64K bytes. 2. Half block = Half Uniform Block, and the size is 32k bytes. 3. Sector = Uniform Sector, and the size is 4K bytes. August 2019 Rev 1.4 8 / 75 Function Descriptions BY25Q40AL 4. Function Descriptions 4.1 Standard SPI Instructions The BY25Q40AL features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. 4.2 Dual SPI Instructions The BY25Q40AL supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3Bh and BBh) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1 4.3 Quad SPI Instructions The BY25Q40AL supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read”, (6Bh, EBh,) instructions. These instructions allow data to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set to 1. All of the above three SPI mode (Standard SPI, Dual SPI and Quad SPI) have input bits (including instructions, addresses, data, M7~M0, W6~W4 etc.) latched on the rising edge of SCLK and output bits shifted out on the falling edge of SCLK. August 2019 Rev 1.4 9 / 75 Operation Features BY25Q40AL 5. Operation Features 5.1 Supply Voltage 5.1.1 Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see operating ranges). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle. 5.1.2 Power-up Conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor. In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation. 5.1.3 Device Reset In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a power on reset (POR) circuit is included. At Power-up, the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in operating ranges). When VCC has passed the POR threshold, the device is reset. 5.1.4 Power-down At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating voltage to below the power on reset threshold voltage, the device stops responding to any instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should be no internal Write cycle in progress). 5.2 Active Power and Standby Power Modes When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device consumes ICC. When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in progress, the device then goes in to the Standby Power mode, and the device consumption drops. to ICC1. 5.3 Hold Condition The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write status register, programming, or erasing in progress. The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being August 2019 Rev 1.4 10 / 75 Operation Features BY25Q40AL low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if /CS drives high during HOLD operation, it will reset the internal logic of the device to Standby Mode. To re-start communication with chip, the /HOLD must be at high and the /CS must be at low. Figure 5.1. Hold condition activation /CS SCLK /HOLD HOLD HOLD August 2019 Rev 1.4 11 / 75 Status Register BY25Q40AL 5.4 Status Register 5.4.1 The Status and Control Bits SR2 Default value Note1 S15 S14 S13 S12 S11 S10 S9 S8 SUS1 CMP LB3 LB2 LB1 SUS2 QE SRP1 n/a 0 0 0 0 n/a 0 0 SR1 Default value Note1 S7 S6 S5 S4 S3 S2 S1 S0 SRP0 BP4 BP3 BP2 BP1 BP0 WEL WIP 0 0 0 0 0 0 n/a n/a Notes: 1. The default value is set by Manufacturer during wafer sort, Marked as Default in following text The status and control bits of the Status Register are as follows: 5.4.1.1 WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program / erase / write status register progress. When WIP bit is set to 1, means that the device is busy in program / erase / write status register progress, when WIP bit is cleared to 0, means that the device is not in program / erase / write status register progress. 5.4.1.2 WEL bit The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When WEL bit is set to 1 the internal Write Enable Latch is set, when WEL bit is cleared to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. 5.4.1.3 BP4, BP3, BP2, BP1, BP0 bits The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory (as defined in Table 4 and Table 5) are became protected against Page Program, Page Erase, Sector Erase and Block Erase instructions. The Block Protect (BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase instruction is executed. If the Block Protect (BP2, BP1, and BP0) bits are 0 and CMP=0 or the Block Protect (BP2, BP1 and BP0) bits are 1and CMP=1. August 2019 Rev 1.4 12 / 75 Status Register BY25Q40AL 5.4.1.4 SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock-down or one time programmable protection. Table 3. Status Register protect table SRP1 SRP0 /WP Status Register Software Protected Hardware Protected Hardware Unprotected 0 0 X 0 1 0 0 1 1 1 0 X Power Supply Lock-Down(1) 1 1 X One Time Program(2) Description The Status Register can be written to after a Write Enable instruction, WEL=1.(Default) /WP=0, the Status Register locked and cannot be written. /WP=1, the Status Register is unlocked and can be written to after a Write Enable instruction, WEL=1. Status Register is protected and cannot be written to again until the next Power-Down, Power-Up cycle. Status Register is permanently protected and cannot be written to. Notes: 1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state. 2. The One time Program feature is available upon special order. Please contact Boya Microelectronics for details. 5.4.1.5 QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad SPI operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE bit is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground). 5.4.1.6 LB3/LB2/LB1 bit The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S13-S11) that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently (LB3-1 corresponds to S13-11). 5.4.1.7 SUS1, SUS2 bit The SUS1 and SUS2 bit are read only bits in the status register2 (S15 and S10) that are set to 1 after executing a Program/Erase Suspend (75H) instruction (The Erase Suspend will set SUS1 to 1. The Program Suspend will set the SUS2 to 1). The SUS bits are cleared to 0 by Program/Erase Resume (7AH) instruction. Software reset (66H/99H) instruction as well as a power-down, power-up cycle. 5.4.1.8 Complement Protect (CMP) The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register. It is used in conjunction with BP4, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0. August 2019 Rev 1.4 13 / 75 Status Register 5.4.2 BY25Q40AL Status Register Memory Protection 5.4.2.1 Protect Table Table 4. BY25Q40AL Status Register Memory Protection (CMP = 0) STATUS REGISTER(1) BP4 BP3 BP2 BY25Q40AL (4M-BIT) MEMORY PROTECTION(3) BP1 BP0 PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION(2) X X 0 0 0 NONE NONE NONE NONE 0 0 0 0 1 7 070000h – 07FFFFh 64KB Upper 1/8 0 0 0 0 0 0 1 1 0 1 6 and 7 4 to 7 060000h – 07FFFFh 040000h – 07FFFFh 128KB 256KB Upper 1/4 Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/8 0 0 0 1 1 X 0 0 1 1 1 X 0 1 X 0 to 1 0 to 3 0 to 7 000000h – 01FFFFh 000000h – 03FFFFh 000000h – 07FFFFh 128KB 256KB 512KB Lower 1/4 Lower 1/2 ALL 1 0 0 0 1 7 07F000h – 07FFFFh 4KB U - 1/128 1 0 0 1 0 7 07E000h – 07FFFFh 8KB U - 1/64 1 0 0 1 1 7 07C000h – 07FFFFh 16KB U - 1/32 1 0 1 0 X 7 078000h – 07FFFFh 32KB U - 1/16 1 0 1 1 0 7 078000h – 07FFFFh 32KB U - 1/16 1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/128 1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/64 1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/32 1 1 1 0 X 0 000000h – 007FFFh 32KB L - 1/16 1 1 1 1 0 0 000000h – 007FFFh 32KB L - 1/16 1 X 1 1 1 0 to 7 000000h – 07FFFFh 512KB ALL Notes: 1. X = don’t care 2. L = Lower; U = Upper 3. If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will be ignored. August 2019 Rev 1.4 14 / 75 Status Register BY25Q40AL Table 5. Status Register Memory Protection (CMP = 1) STATUS REGISTER(1) BP4 BP3 BP2 BP1 BP0 BY25Q40AL (4M-BIT) MEMORY PROTECTION(3) PROTECTED BLOCK(S) PROTECTED ADDRESSES PROTECTED PROTECTED DENSITY PORTION(2) X X 0 0 0 0 to 7 000000h – 07FFFFh 512KB All 0 0 0 0 1 0 to 6 000000h – 06FFFFh 448KB Lower 7/8 0 0 0 1 0 0 and 5 000000h – 05FFFFh 384KB Lower 3/4 0 0 0 1 1 0 to 3 000000h – 03FFFFh 256KB Lower 1/2 0 1 0 0 1 1 to 7 010000h – 07FFFFh 448KB Upper 7/8 0 1 0 1 0 2 to 7 020000h – 07FFFFh 384KB Upper 3/4 0 1 0 1 1 4 to 7 040000h – 07FFFFh 256KB Upper 1/2 0 X 1 X X NONE NONE NONE NONE 1 0 0 0 1 0 to 7 000000h –07EFFFh 508KB L - 127/128 1 0 0 1 0 0 to 7 000000h – 07DFFFh 504KB L - 63/64 1 0 0 1 1 0 to 7 000000h – 07BFFFh 496KB L - 31/32 1 0 1 0 X 0 to 7 000000h – 077FFFh 480KB L - 15/16 1 0 1 1 0 0 to 7 000000h – 077FFFh 480KB L - 15/16 1 1 0 0 1 0 to 7 001000h – 07FFFFh 508KB U - 127/128 1 1 0 1 0 0 to 7 002000h – 07FFFFh 504KB U- 63/64 1 1 0 1 1 0 to 7 004000h – 07FFFFh 496KB U- 31/32 1 1 1 0 X 0 to 7 008000h – 07FFFFh 480KB U- 15/16 1 1 1 1 0 0 to 7 008000h – 07FFFFh 480KB U - 15/16 1 X 1 1 1 NONE NONE NONE NONE Notes: 1. X = don’t care 2. L = Lower; U = Upper 3.If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will be ignored. August 2019 Rev 1.4 15 / 75 Device Identification BY25Q40AL 6. Device Identification Three legacy Instructions (9Fh/90h/ABh) and two new Instructions (92h/94h) in Dual/Quad SPI mode are supported to access device identification that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. Table 6. BY25Q40AL ID Definition table Operation Code M7-M0 ID15-ID8 ID7-ID0 9Fh 68 68 60 13 12 12 90h / 92h /94h ABh August 2019 Rev 1.4 16 / 75 Instructions Description BY25Q40AL 7. Instructions Description All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 7, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. For the instruction of Read, Fast Read, Read Status Register-1, Read Status Register-2 or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Page Erase, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must drive high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. August 2019 Rev 1.4 17 / 75 Instructions Description BY25Q40AL Table 7. Instruction Set Table 1 (1) Instruction Name Byte 1 Write Enable 06h Volatile SR Write Enable 50h Write Disable 04h Read Status Register-1 05h (S7-S0)(2) Write Status Register(4) 01h S7-S0 Read Status Register-2 35h (S15-S8)(2) Active Status Interrupt 25h Chip Erase C7h/60h Program/Erase Suspend 75h Program/Erase Resume 7Ah Deep Power-down Release Power-down / ID Release Power-down B9h ABH Manufacturer/Device ID Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes (continuous) S15-S8 (continuous) (ID7-ID0)(2) Dummy Dummy Dummy 90h Dummy Dummy 00/01h Read JEDEC ID 9Fh (MF7-MF0) (ID15-ID8) (ID7-ID0)(2) Read Unique ID Number 4Bh Dummy Dummy Dummy Enable Reset 66h Reset Device 99h Read Serial Flash Discoverable Parameter 5Ah A23-A16 A15-A8 A7-A0 Dummy Normal Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) Fast Read 0Bh A23-A16 A15-A8 A7-A0 Dummy (D7-D0) (continuous) Dual Output Fast read 3Bh A23-A16 A7-A0 Dummy (D7-D0)(7) (continuous) BBh A23-A8(6) A15-A8 A7-A0 M7-M0(6) 6Bh Dummy A15-A8 A15-A8 Dual I/O Fast read Quad Output Fast read ABh Byte 2 Page Program 02h A23-A16 A23-A0 M7-M0(8) A23-A16 Dual Page Program A2h A23-A16 Quad I/O Fast read Quad Page Program Page Erase EBh 32h A15-A8 (continuous) (MF7-MF0)/ (ID7-ID0)(2)/ (continuous) (ID7-ID0) (MF7-MF0)(2) (continuous) Dummy (ID127-ID0) (D7-D0) (Next Byte) (continuous) (D7-D0) A7-A0 (D7-D0) (continuous) Dummy (D7-D0)(9) (10) A7-A0 (D7-D0) (Next Byte) A7-A0 (D7-D0)(3) (Next Byte) (3) (Next Byte) A15-A8 A7-A0 81h/DBh A23-A16 (D7-D0) A15-A8 A7-A0 Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0 Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0 Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0 Erase Security Registers 44h A23-A16(5) A15-A8(5) A7-A0(5) 42h A23-A16(5) A15-A8(5) A7-A0(5) D7-D0 Next Byte 48h A23-A16(5) A15-A8(5) A7-A0(5) Dummy D7-D0 Set Burst With Wrap 77h W6-W4 Mftr./Device ID Dual I/O 92h A23-A8(6) Mftr./Device ID Quad I/O 94h A23-A0 M7-M0(8) Program Security Registers Read Security Registers A7-A0(6) M7-M0 (M7-M0) (D7-D0)(10) (M7-M0) (D7-D0) (continuous) (continuous) (3) A23-A16 (continuous) (continuous) (continuous) Notes: 1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data output from the device. 2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. 3. At least one byte of data input is required for Page Program, Dual Page Program, Quad Page Program and Program Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. August 2019 Rev 1.4 18 / 75 Instructions Description BY25Q40AL 4. Write Status Register (01h) can also be used to write Status Register-1&2, see section 7.1.6. 5. Security Register Address: Security Register 1 A23-16 = 00h A15-9 = 0001000 A8-0 = byte address Security Register 2 A23-16 = 00h A15-9 = 0010000 A8-0 = byte address Security Register 3 A23-16 = 00h A15-9 = 0011000 A8-0 = byte address 6. Dual SPI address input format: IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1 7. Dual SPI data output format: IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 8. Quad SPI address input format: IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 9. Quad SPI data output format: IO0 = (D4, D0, …..) IO1 = (D5, D1, …..) IO2 = (D6, D2, …..) IO3 = (D7, D3, …..) 10. Fast Read Quad I/O data output format: IO0 = (x, x, x, x, D4, D0, D4, D0) IO1 = (x, x, x, x, D5, D1, D5, D1) IO2 = (x, x, x, x, D6, D2, D6, D2) IO3 = (x, x, x, x, D7, D3, D7, D3) August 2019 Rev 1.4 19 / 75 Instructions Description BY25Q40AL 7.1 Configuration and Status Instructions 7.1.1 Write Enable (06H) The Write Enable instruction (Figure 7.1.1) sets the Write Enable Latch (WEL) bit in the Status Register to a 1. The WEL bit must be set prior to every Page Program, Dual Page Program, Quad Page Program, Page Erase, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (SI) pin on the rising edge of SCLK, and then driving /CS high. Figure 7.1.1. Write Enable Instruction for SPI Mode /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Instruction SI 06H SO High_Z 7.1.2 Write Enable for Volatile Status Register (50h) The non-volatile Status Register bits described in section 5.4 can also be written to as volatile bits. This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status Register instruction (Figure 7.1.2) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status Register bit values. Figure 7.1.2. Write Enable for Volatile Status Register Instruction for SPI Mode /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Instruction SI 50H SO High_Z August 2019 Rev 1.4 20 / 75 Instructions Description 7.1.3 BY25Q40AL Write Disable (04h) The Write Disable instruction (Figure 7.1.3) resets the Write Enable Latch (WEL) bit in the Status Register to 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the SI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Erase/Program Security Registers, Page Program, Dual Page Program, Quad Page Program, Page Erase, Sector Erase, Block Erase, Chip Erase and Reset instructions. Figure 7.1.3. Write Disable Instruction for SPI Mode /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 Mode 3 Mode 0 Instruction SI 04H SO High_Z August 2019 Rev 1.4 21 / 75 Instructions Description 7.1.4 BY25Q40AL Read Status Register-1 (05h), Status Register-2 (35h) The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register -2 into the SI pin on the rising edge of SCLK. The status register bits are then shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 7.1.4, Refer to section 5.4 for Status Register descriptions. The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status Register cycle is in progress. This allows the WIP status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. The Status Register can be read continuously, as shown in Figure 7.1.4 The instruction is completed by driving /CS high. Figure 7.1.4. Read Status Register Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Instruction SI 05H or 35H SO High_Z Status Register-1/2 out August 2019 7 MSB 6 5 Rev 1.4 4 3 2 1 Status Register-1/2 out 0 7 6 5 4 3 2 1 0 MSB 22 / 75 7 Instructions Description 7.1.5 BY25Q40AL Active Status Interrupt (25h) To simplify the readout of the WIP bit, the Active Status Interrupt Instruction (25h) may be used. It is then not necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If the SO line is connected to an interrupt line on the host controller, the host controller may be in sleep mode until the SO line indicates that the device is ready for the next Instruction The WIP bit can be read at any time, including during an internally self-timed program or erase operation. To enable the Active Status Interrupt instruction, the /CS pin must first be asserted and the instruction code of 25h must be clocked into the device. The value of the SI line after the instruction code being clocked in is of no significance to the operation. The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the /CS pin remains asserted. Additional clocks on the SCK pin are not required. That is, whether the additional clock on the SCK pin exists is independent of the correct output of the value of WIP. (Figure 7.1.5 shows a case where additional clocks exist). If the WIP bit changes from 1 to 0 while the /CS pin is asserted, the SO line will change from 1 to 0. (The WIP bit cannot change from 0 to 1 during an operation, so if the SO line already is 0, it will not change.) De-asserting the /CS pin will terminate the Active Status Interrupt operation and put the SO pin into a high-impedance state. The sequence of issuing ASI instruction is: /CS goes low→ sending ASI instruction code→ WIP data out on SO Figure 7.1.5. Active Status Interrupt Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Instruction SI 25H SO High_Z August 2019 RDY/BSY Rev 1.4 23 / 75 Instructions Description 7.1.6 BY25Q40AL Write Status Register (01h) The Write Status Register instruction allows the Status Registers to be written. The writable Status Register bits include: SRP0, BP[4:0] in Status Register-1; CMP, LB[3:1], QE, SRP1 in Status Register- 2. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be cleared to 0. The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) or Write Enable For Volatile SR instruction must previously have been executed After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register instruction has no effect on S15(SUS1), S10(SUS2), S1(WEL) and S0(WIP) of the Status Register. /CS must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register (WRSR) command is not executed. If /CS is driven high after eighth bit of the data byte, the CMP and QE and SRP1 bits will be cleared to 0. As soon as /CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register instruction allows the user to change the values of the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table4 and Table5.The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status Register instruction is not executed once the Hardware Protected Mode is entered. The sequence of issuing WRSR instruction is: /CS goes low→ sending WRSR instruction code→ Status Register data on SI→/CS goes high. The /CS must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (/CS) goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The WIP is set 1 during the tW timing, and is set 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Figure 7.1.6. Write Status Register Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 01H 7 MSB 6 5 12 13 14 15 1 0 16 17 4 3 2 18 19 20 21 22 23 9 8 Mode 3 Mode 0 Status Register-2 in 15 14 13 12 11 10 MSB SO August 2019 11 Status Register-1 in Instruction SI 10 High_Z Rev 1.4 24 / 75 Instructions Description BY25Q40AL 7.2 Read Instructions 7.2.1 Normal Read Data (03H) The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a 24-bit address (A23-A0) into the SI pin. The code and address bits are latched on the rising edge of the SCLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first. The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in Figure 7.2.1. If a Read Data instruction is issued while an Erase, Program or other Write cycle is in progress (WIP=1) the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock frequency up to to a maximum of fR (see AC Electrical Characteristics). The Normal Read Data (03h) instruction is only supported in Standard SPI mode. Figure 7.2.1. Read Data Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 Instruction SI 03H 10 28 29 30 31 32 33 34 36 37 38 22 21 3 2 1 0 High_Z 7 6 5 Data Out 1 4 3 2 1 MSB August 2019 39 24-Bit Address 23 MSB SO 35 Rev 1.4 25 / 75 0 7 Instructions Description 7.2.2 BY25Q40AL Fast Read (0BH) The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest possible frequency of fC (see AC Electrical Characteristics). In standard SPI mode, this is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.2.2. The dummy clocks allow the devices internal circuits additional time for setting up the initial address. During the dummy clocks the data value on the SO pin is a “don’t care”. Figure 7.2.2. Fast Read Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 29 30 31 24-Bit Address Instruction 0BH SI 28 10 23 22 3 21 2 1 0 MSB High_Z SO /CS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy SI Clocks 0 SO High_Z 7 6 5 Data Out 1 4 3 2 MSB August 2019 1 0 7 6 5 Data Out 2 4 3 2 1 0 MSB Rev 1.4 26 / 75 7 Instructions Description 7.2.3 BY25Q40AL Fast Read Dual Output (3Bh) The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except that data is output on two pins; SI and SO. This allows data to be transferred at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-segments to RAM for execution. Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.2.3. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the SI pin should be high-impedance prior to the falling edge of the first data out clock. Figure 7.2.3. Fast Read Dual Output Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 Instruction SI 28 29 30 31 24-Bit Address 23 3BH 3 21 22 2 1 0 MSB High_Z SO /CS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCLK Dummy SI 6 0 SO IO0 switches from Input to Output Clocks High_Z 7 MSB August 2019 4 2 0 6 5 3 1 7 Data Out 1 Rev 1.4 MSB 4 2 0 6 5 3 1 7 Data Out 2 MSB 4 2 0 6 5 3 1 7 Data Out 3 MSB 4 2 0 6 5 3 1 7 Data Out 4 27 / 75 Instructions Description 7.2.4 BY25Q40AL Fast Read Quad Output (6Bh) The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction except that data is output on two pins, SI, SO, /WP, and /HOLD. The Quad Enable (QE) bit in Status Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices. The Fast Read Quad Output instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address as shown in Figure 7.2.4. The dummy clocks allow the device's internal circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. Figure 7.2.4. Fast Read Quad Output Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 Instruction SI (IO0) 28 29 30 31 24-Bit Address 23 6BH 3 21 22 2 1 0 MSB High_Z SO (IO1) /WP (IO2) /HOLD (IO3) High_Z High_Z /CS 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy SI (IO0) IO0 switches from Input to Output Clocks 0 SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 Byte1 August 2019 Rev 1.4 Byte2 Byte3 Byte4 28 / 75 Instructions Description 7.2.5 BY25Q40AL Fast Read Dual I/O (BBh) The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins, SI and SO. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual SPI in some applications. Fast Read Dual I/O with “Continuous Read Mode” The Fast Read Dual I/O instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23- 0), as shown in Figure 7.2.5a. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is raised and then lowered) does not require the BBh instruction code, as shown in Figure 7.2.5b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on SI for the next instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 7.2.5a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4≠10) /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 11 12 13 A23-16 Instruction SI 10 BBH SO 14 15 16 A15-8 17 18 19 20 22 21 23 M7-0 A7-0 22 20 18 16 14 12 10 8 6 4 2 0 6 4 2 0 23 21 19 17 15 13 11 9 7 5 3 1 7 5 3 1 MSB MSB /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK IOs IO0 switch from Input to Output SI 0 6 4 2 0 6 4 2 0 6 SO 1 7 5 3 1 7 5 3 1 7 MSB August 2019 Byte1 MSB Byte2 MSB 4 2 0 6 4 5 3 1 7 5 Byte3 Rev 1.4 MSB 2 0 6 3 1 7 Byte4 29 / 75 Instructions Description BY25Q40AL Figure 7.2.5b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10) /CS 0 1 SI 22 20 SO 23 21 SCLK Mode 3 Mode 0 2 3 4 5 18 16 14 12 10 8 6 4 19 17 15 13 11 9 7 5 A23-16 6 7 8 9 A15-8 10 11 12 13 A7-0 14 15 M7-0 2 0 6 4 2 0 3 1 7 5 3 1 30 31 MSB MSB /CS 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SCLK IOs IO0 switch from Input to Output SI 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 SO 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 MSB August 2019 Byte1 MSB Byte2 Rev 1.4 MSB Byte3 MSB Byte4 30 / 75 Instructions Description 7.2.6 BY25Q40AL Fast Read Quad I/O (EBh) The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that address and data bits are input and output through two pins SI, SO, /WP and /HOLD and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction. Fast Read Quad I/O with “Continuous Read Mode” The Fast Read Quad I/O instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 7.2.6a. The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered) does not require the EBh instruction code, as shown in Figure 7.2.6b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on SI for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation. Figure 7.2.6a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10) /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 10 A23-16 Instruction SI (IO0) 9 11 12 A15-8 13 A7-0 14 15 M7-0 16 17 Dummy 18 19 20 22 21 23 IOs switch from Input to Output Dummy 20 16 12 8 4 0 4 0 4 0 4 0 4 SO (IO1) 21 17 13 9 5 1 5 1 5 1 5 1 5 /WP (IO2) 22 18 14 10 6 2 6 2 6 2 6 2 6 /HOLD (IO3) 23 19 15 11 7 3 7 3 7 3 7 3 7 EBH Byte1 Byte2 Figure 7.2.6b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10 ) /CS SCLK Mode 3 Mode 0 0 1 A23-16 2 3 4 A15-8 5 A7-0 6 7 M7-0 8 9 Dummy 10 11 12 13 14 15 IOs switch from Input to Output Dummy SI (IO0) 20 16 12 8 4 0 4 0 4 0 4 0 4 SO (IO1) 21 17 13 9 5 1 5 1 5 1 5 1 5 /WP (IO2) 22 18 14 10 6 2 6 2 6 2 6 2 6 /HOLD (IO3) 23 19 15 11 7 3 7 3 7 3 7 3 Byte1 August 2019 Rev 1.4 Byte2 7 Byte3 31 / 75 Byte3 Instructions Description BY25Q40AL Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is enabled, the data being accessed can be limited to an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64- byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Refer to section 7.2.7 for detail descriptions. August 2019 Rev 1.4 32 / 75 Instructions Description 7.2.7 BY25Q40AL Set Burst with Wrap (77h) The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O (EBh)”, “instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Figure 7.2.8. Wrap bit W7 and the lower nibble W3-0 are not used. W4 = 0 W4 =1 (DEFAULT) W6, W5 Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 1 0 1 1 Yes Yes Yes 16-byte 32-byte 64-byte No No No N/A N/A N/A Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O (EBh)”, instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a software reset is 1. Figure 7.2.8. Set Burst with Wrap Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 8 9 don’t care X X Instruction SI (IO0) 7 77H 10 11 don’t care X X 12 13 14 15 don’t Wrap Bit care X w4 X X SO (IO1) X X X X X X w5 X /WP (IO2) X X X X X X w6 X /HOLD (IO3) X X X X X X X X August 2019 Rev 1.4 Mode 3 Mode 0 33 / 75 Instructions Description BY25Q40AL 7.3 ID and Power Instructions 7.3.1 Deep Power-down (B9h) Although the standby current during normal operation is relatively low, standby current can be further reduced with the Power-down instruction. The lower power consumption makes the Power-down instruction especially useful for battery powered applications (See ICC1 and ICC2 in DC Characteristics.)The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in Figure 7.3.1 The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down instruction will not be executed. After /CS is driven high, the power- down state will entered within the time duration of tDP (See AC Characteristics). While in the power-down state only the Release Power-down / Device ID (ABh) instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored. This includes the Read Status Register instruction, which is always available during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition for securing maximum write protection. The device always powers-up in the normal operation with the standby current of ICC1 Figure 7.3.1. Deep Power-down Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 tDP Mode 3 Mode 0 Instruction SI B9H Stand-by current August 2019 Rev 1.4 Power-down current 34 / 75 Instructions Description 7.3.2 BY25Q40AL Release Power-down / Device ID (ABh) The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the power-down state, or obtain the devices electronic identification (ID) number. To release the device from the power- down state, the instruction is issued by driving the /CS pin low, shifting the instruction code “ABh” and driving /CS high as shown in Figure 7.3.2a.Release from power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time duration. When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit (MSB) first. The Device ID value for the BY25Q40AL is listed in Manufacturer and Device Identification table. The Device ID can be read continuously. The instruction is completed by driving /CS high. When used to release the device from the power-down state and obtain the Device ID, the instruction is the same as previously described, and shown in Figure 7.3.2b, except that after /CS is driven high it must remain high for a time duration of tRES2 (See AC Characteristics) . After this time duration the device will resume normal operation and other instructions will be accepted. If the Release from Power- down / Device ID instruction is issued while an Erase, Program or Write cycle is in process (when WIP equals 1) the instruction is ignored and will not have any effects on the current cycle. Figure 7.3.2a. Release Power-down Instruction /CS 0 Mode 3 Mode 0 SCLK 1 2 3 4 5 6 tRES1 7 Mode 3 Mode 0 Instruction SI ABH Power-down current Stand-by current Figure 7.3.2b. Release Power-down / Device ID Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 9 23 22 Instruction SI SO ABH 29 30 31 1 0 32 33 34 35 36 37 38 39 tRES2 3 Dummy Bytes 2 Mode 3 Mode 0 MSB High_Z Device ID 7 MSB 6 5 4 3 2 1 0 Power-down current Stand-by current August 2019 Rev 1.4 35 / 75 Instructions Description 7.3.3 BY25Q40AL Read Manufacturer / Device ID (90h) The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer / Device ID instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0). After which, the Manufacturer ID for BoyaMicro (68h) and the Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 7.3.3. The Device ID values for the BY25Q40AL are listed in Manufacturer and Device Identification table. The address A23-A1 is an unrelated item and has no effect on the result of the instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then followed by the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then followed by the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 7.3.3. Read Manufacturer / Device ID Instruction /CS SCLK Mode 3 Mode 0 0 1 2 3 4 5 6 7 8 Instruction SI 90H 9 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 7 6 5 4 44 45 46 47 Address(000000h) 23 22 2 1 0 MSB SO High_Z 68H Manufacturer ID August 2019 Rev 1.4 MSB 3 2 1 0 Device ID 36 / 75 Mode 3 Mode 0 Instructions Description 7.3.4 BY25Q40AL Read Manufacturer / Device ID Dual I/O (92h) The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x speed. The Read Manufacturer / Device ID Dual I/O instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24-bit address (A23-A0) and four clock dummy cycles, but with the capability to input the Address bits two bits per clock. After which, the Manufacturer ID for BoyaMicro (68h) and the Device ID are shifted out 2 bits per clock on the falling edge of SCLK with most significant bits (MSB) first as shown in Figure 7.3.4. The Device ID values for the BY25Q40AL are listed in Manufacturer and Device Identification table. The address A23-A1 and M7-M0 is an unrelated item and has no effect on the result of the instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then followed by the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then followed by the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 7.3.4. Read Manufacturer / Device ID Dual I/O Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 Instruction SI 92H SO High_Z 9 10 11 12 A23-16 13 14 15 16 6 4 2 0 4 2 0 7 5 3 1 MSB 7 5 3 1 18 19 20 A7-0(00H) A15-8 6 17 6 4 2 0 7 5 3 1 MSB MSB 21 22 23 M7-0 6 4 2 0 7 5 3 1 MSB /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Mode 3 Mode 0 IOs switch from Input to Output SI SO 0 1 6 4 2 0 7 5 3 1 MSB 4 2 0 6 7 5 3 1 7 MSB MSB MFR ID August 2019 6 Device ID 4 2 0 5 3 1 MFR ID (repeat) Rev 1.4 6 4 2 0 7 5 3 1 MSB Device ID (repeat) 37 / 75 Instructions Description 7.3.5 BY25Q40AL Read Manufacturer / Device ID Quad I/O (94h) The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x speed. The Read Manufacturer / Device ID Quad I/O instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a 24-bit address (A23-A0) and six clock dummy cycles, but with the capability to input the Address bits four bits per clock. After which, the Manufacturer ID for BoyaMicro (68h) and the Device ID are shifted out four bits per clock on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 7.3.5. The Device ID values for the BY25Q40AL are listed in Manufacturer and Device Identification table. The address A23-A1 and M7-M0 is an unrelated item and has no effect on the result of the instruction. At the same time, if the A0 is initially set to 1 the Device ID will be read first and then followed by the Manufacturer ID. If the A0 is initially set to 0 the Manufacturer ID will be read first and then followed by the Device ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. Figure 7.3.5. Read Manufacturer / Device ID Quad I/O Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 Instruction SI (IO0) 94H SO (IO1) High_Z /WP (IO2) High_Z /HOLD (IO3) High_Z 8 9 A23-16 10 11 A15-8 12 13 A7-0 (00H) 14 15 M7-0 16 17 Dummy 18 19 20 21 22 23 IOs switch from Input to Output Dummy 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 MFR ID Device ID /CS 23 24 25 26 27 28 29 30 31 SCLK SI (IO0) 0 4 0 4 0 4 0 4 0 SO (IO1) 1 5 1 5 1 5 1 5 1 /WP (IO2) 2 6 2 6 2 6 2 6 2 /HOLD (IO3) 3 7 3 7 3 7 3 7 3 Mode 3 Mode 0 MFR ID Device ID MFR ID Device ID (repeat) (repeat) (repeat) (repeat) August 2019 Rev 1.4 38 / 75 Instructions Description 7.3.6 BY25Q40AL Read JEDEC ID (9Fh) The Read JEDEC ID instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics). For compatibility reasons, the BY25Q40AL provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for BoyaMicro (68h) and two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 7.3.6. For memory type and capacity values refer to Manufacturer and Device Identification table. Figure 7.3.6. Read JEDEC ID Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Instruction SI 9FH SO Manufacturer ID 68H High_Z /CS 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 Mode 3 Mode 0 30 SCLK SI SO August 2019 Memory Type ID15-8 7 MSB 6 5 4 3 2 Capacity ID7-0 1 Rev 1.4 0 7 MSB 6 5 4 3 2 1 0 39 / 75 Instructions Description 7.3.7 BY25Q40AL Read Unique ID Number (4Bh) The Read Unique ID Number instruction can operate at the highest possible frequency of fC (see AC Electrical Characteristics).The Read Unique ID Number instruction accesses a factory-set read-only 128-bit number that is unique to each BY25Q40AL device. The ID number can be used in conjunction with user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 128-bit ID is shifted out on the falling edge of SCLK as shown in Figure 7.3.7. Figure 7.3.7. Read Unique ID Sequence Diagram /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 Instruction SI 11 12 13 14 15 16 Dummy Byte 1 17 18 19 20 21 22 23 Dummy Byte 2 4BH SO High_Z /CS 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 101 102 103 SCLK Dummy Byte 3 Dummy Byte 4 SI SO High_Z 127 MSB August 2019 Rev 1.4 126 2 1 0 128-bit Unique Serial Number 40 / 75 Mode 3 Mode 0 Instructions Description BY25Q40AL 7.4 Program / Erase and Security Instructions 7.4.1 Page Program (02h) The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one data byte, into the SI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. The Page Program instruction sequence is shown in Figure 7.4.1. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been latched in; otherwise the Page Program instruction is not executed. As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tPP (See AC Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits Figure 7.4.1. Page Program Instruction /CS SCLK 0 Mode 3 Mode 0 1 2 3 4 5 6 7 8 9 10 Instruction SI 28 29 30 31 32 33 34 7 6 5 24-Bit Address 23 02H 36 37 38 39 Data Byte 1 3 21 22 35 2 MSB 1 0 4 3 2 1 0 MSB /CS 39 40 41 7 6 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079 SCLK Data Byte 2 SI 0 MSB August 2019 5 4 3 Data Byte 3 2 1 0 7 6 5 4 3 Data Byte 256 2 1 0 7 6 5 4 3 2 1 0 MSB MSB Rev 1.4 41 / 75 Mode 3 Mode 0 Instructions Description 7.4.2 BY25Q40AL Dual Page Program (A2h) The Dual Page Program instruction allows up to 256 bytes of data to be programmed at previously erased (FFh) memory locations using two pins: SI, SO. The Dual Page Program can improve performance for PROM Programmer and applications that have slow clock speeds