Boya Microelectronics
Memory Series
BY25D40/20
4/2M BIT SPI NOR FLASH
Features
● Serial Peripheral Interface (SPI)
- Standard SPI: SCLK, /CS, SI, SO, /WP
- Dual SPI: SCLK, /CS, IO0, IO1, /WP
● Read
- Normal Read (Serial): 55MHz clock rate
- Fast Read (Serial): 108MHz clock rate
- Dual Read: 108MHz clock rate
● Program
- Serial-input Page Program up to 256bytes
● Erase
- Block erase (64/32 KB)
- Sector erase (4 KB)
- Chip erase
● Program/Erase Speed
- Page Program time: 0.7ms typical
- Sector Erase time: 100ms typical
- Block Erase time: 0.3/0.5s typical
- Chip Erase time: 3/2s typical
● Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
● Low Power Consumption
- 20mA maximum active current
- 5uA maximum power down current
● Software/Hardware Write Protection
- Enable/Disable protection with WP Pin
- Write protect all/portion of memory via software
- Top or Bottom, Sector or Block selection
● Single Supply Voltage
- Full voltage range: 2.7~3.6V
● Temperature Range
SOP8 150-mil
SOP8 208-mil
USON8 3*2 mm
- Commercial (0℃ to +70℃)
- Industrial (-40℃ to +85℃)
● Cycling Endurance/Data Retention
- Typical 100k Program-Erase cycles on any sector
- Typical 20-year data retention at +55℃
May 2017
Rev 1.6
1 / 44
Contents
BY25D40/20
Contents
1.
2.
3.
4.
Description ................................................................................. 4
Signal Description ...................................................................... 6
Block/Sector Addresses ............................................................. 7
SPI Operation ............................................................................ 9
4.1
4.2
Standard SPI Instructions .............................................................................. 9
Dual SPI Instructions .................................................................................... 9
5. Operation Features .................................................................. 10
5.1
Supply Voltage ............................................................................................ 10
5.1.1 Operating Supply Voltage ............................................................... 10
5.1.2 Power-up Conditions ....................................................................... 10
5.1.3 Device Reset .................................................................................... 10
5.1.4 Power-down ...................................................................................... 10
5.2
Active Power and Standby Power Modes ................................................... 10
5.3
Status Register..............................................................................................11
5.3.1 Write Protect Features .................................................................... 12
5.4
Status Register Memory Protection ............................................................ 12
6. Device Identification ................................................................. 14
7. Instructions Description ............................................................ 15
7.1
Configuration and Status Instructions ......................................................... 17
7.1.1 Write Enable (06H) .......................................................................... 17
7.1.2 Write Disable (04H) ......................................................................... 17
7.1.3 Read Status Register (05H) ........................................................... 18
7.1.4 Write Status Register (01H) ........................................................... 18
7.2
Read Instructions......................................................................................... 19
7.2.1 Read Data (03H) .............................................................................. 19
7.2.2 Fast Read (0BH) .............................................................................. 20
7.2.3 Dual Output Fast Read (3BH) ........................................................ 21
7.3
ID and Security Instructions ....................................................................... 22
7.3.1 Read Manufacture ID/ Device ID (90H) ....................................... 22
7.3.2 JEDEC ID (9FH)............................................................................... 23
7.3.3 Read Unique ID Number (4Bh) ..................................................... 24
7.3.4 Deep Power-Down (B9H) ............................................................... 25
7.3.5 Release from Deep Power-Down/Read Device ID (ABH)......... 26
7.4
Program and Erase Instructions .................................................................. 27
7.4.1 Page Program (02H) ....................................................................... 27
7.4.2 Sector Erase (20H) .......................................................................... 28
7.4.3 32KB Block Erase (52H) ................................................................. 29
7.4.4 64KB Block Erase (D8H) ................................................................ 30
7.4.5 Chip Erase (60/C7H) ....................................................................... 31
8. Electrical Characteristics .......................................................... 32
8.1
8.2
8.3
8.4
May 2017
Absolute Maximum Ratings ....................................................................... 32
Operating Ranges ........................................................................................ 32
Data Retention and Endurance .................................................................... 32
Latch Up Characteristics ............................................................................. 33
Rev 1.6
2 / 44
Contents
8.5
8.6
8.7
8.8
BY25D40/20
Power-up Timing......................................................................................... 33
DC Electrical Characteristics ...................................................................... 34
AC Measurement Conditions ...................................................................... 35
AC Electrical Characteristics ...................................................................... 35
9. Package Information ................................................................ 38
9.1
9.2
9.3
9.4
9.5
Package 8-Pin SOP 150-mil ........................................................................ 38
Package 8-Pin SOP 208-mil ........................................................................ 39
Package 8-Pin TSSOP 173-mil ................................................................... 40
Package USON8 (3*2mm).......................................................................... 41
Package 8-Pin DIP8L .................................................................................. 42
10. Order Information ..................................................................... 43
11. Document Change History ....................................................... 44
May 2017
Rev 1.6
3 / 44
Description
BY25D40/20
1. Description
The BY25D40/20 is 4M/2M-bit Serial Peripheral Interface (SPI) Flash memory, and supports the
Dual SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO). The Dual Output data is
transferred with speed of 108Mbits/s. The device uses a single low voltage power supply, ranging
from 2.7 Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID.
In order to meet environmental requirements, Boya Microelectronics offers an 8-pin SOP 150-mil,
or 208mil, an 8-pin TSSOP 173-mil, an 8-pad USON 3x2-mm, and other special order packages,
please contacts Boya Microelectronics for ordering information.
Figure 1. Logic diagram
VCC
SCLK
SO
SI
/CS
BY25DXX
/WP
NC
VSS
Figure 2. Pin Configuration SOP8 150/208 mil, TSSOP 173mil
Top View
May 2017
/CS
1
8
SO
2
7
SOP8 150/208mil
TSSOP 173mil
/WP
3
6
SCLK
VSS
4
5
SI
Rev 1.6
VCC
NC
4 / 44
Description
BY25D40/20
Figure 3. Pin Configuration DIP8L
Top View
May 2017
/CS
1
8
VCC
SO
2
7
NC
/WP
3
6
SCLK
VSS
4
5
SI
Rev 1.6
5 / 44
Block/Sector Addresses
BY25D40/20
2. Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to
VCC(max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,
VIL or VOL, see Section 8.6, DC Electrical Characteristics on page 34). These signals are
described next.
Table 1. Signal Description
Pin Name
I/O
Description
/CS
I
Chip Select
SO (IO1)
I/O
/WP (IO2)
I
VSS
I/O
SCLK
I
VCC
May 2017
Write Protect in single bit
Ground
SI (IO0)
NC
Serial Output for single bit data Instructions. IO1 for Dual Instructions.
Serial Input for single bit data Instructions. IO0 for Dual Instructions.
Serial Clock
No Connection
Core and I/O Power Supply
Rev 1.6
6 / 44
Block/Sector Addresses
BY25D40/20
3. Block/Sector Addresses
Table 2. Block/Sector Addresses of BY25D40
Memory
Density
Block(64k
byte)
Block(32k
byte)
Half block
0
Block 0
Half block
1
Half block
2
Block 1
Half block
3
4Mbit
：
：
Half block
12
Block 6
Half block
13
Half block
14
Block 7
Half block
15
May 2017
Rev 1.6
Sector 0
Sector
Size(KB)
4
000000h-000FFFh
：
：
：
Sector 7
4
007000h-007FFFh
Sector 8
4
008000h-008FFFh
：
4
：
Sector 15
4
00F000h-00FFFFh
Sector 16
4
010000h-010FFFh
：
：
：
Sector 23
4
017000h-017FFFh
Sector 24
4
018000h-018FFFh
：
：
：
Sector 31
4
01F000h-01FFFFh
：
：
：
Sector 96
4
060000h-060FFFh
Sector No.
：
：
Address range
：
Sector 103
4
067000h-067FFFh
Sector 104
4
068000h-068FFFh
：
：
：
Sector 111
4
06F000h-06FFFFh
Sector 112
4
070000h-070FFFh
：
：
：
Sector 119
4
077000h-077FFFh
Sector 120
4
078000h-078FFFh
：
：
：
Sector 127
4
07F000h-07FFFFh
7 / 44
Block/Sector Addresses
BY25D40/20
Table 3. Block/Sector Addresses of BY25D20
Memory
Density
Block(64k
byte)
Block(32k
byte)
Half block
0
Block 0
Half block
1
Half block
2
Block 1
Half block
3
2Mbit
Half block
4
Block 2
Half block
5
Half block
6
Block 3
Half block
7
Sector No.
Sector
Size(KB)
Address range
Sector 0
4
000000h-000FFFh
：
：
：
Sector 7
4
007000h-007FFFh
Sector 8
4
008000h-008FFFh
：
4
：
Sector 15
4
00F000h-00FFFFh
Sector 16
4
010000h-010FFFh
：
：
：
Sector 23
4
017000h-017FFFh
Sector 24
4
018000h-018FFFh
：
：
：
Sector 31
4
01F000h-01FFFFh
Sector 32
4
020000h-020FFFh
：
：
：
Sector 39
4
027000h-027FFFh
Sector 40
4
028000h-028FFFh
：
：
：
Sector 47
4
02F000h-02FFFFh
Sector 48
4
030000h-030FFFh
：
：
：
Sector 55
4
037000h-037FFFh
Sector 56
4
038000h-038FFFh
：
：
：
Sector 63
4
03F000h-03FFFFh
Notes:
1. Block = Uniform Block, and the size is 64K bytes.
2. Half block = Half Uniform Block, and the size is 32k bytes.
3. Sector = Uniform Sector, and the size is 4K bytes.
May 2017
Rev 1.6
8 / 44
SPI Operation
BY25D40/20
4. SPI Operation
4.1 Standard SPI Instructions
The BY25D40/20 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge
of SCLK.
4.2 Dual SPI Instructions
The BY25D40/20 supports Dual SPI operation when using the “Dual Output Fast Read” (3BH)
instructions. These instructions allow data to be transferred to or from the device at two times the
rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
May 2017
Rev 1.6
9 / 44
SPI Operation
BY25D40/20
5. Operation Features
5.1 Supply Voltage
5.1.1
Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within
the specified [VCC(min), VCC(max)] range must be applied (see operating ranges of page 33). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and,
for a Write instruction, until the completion of the internal write cycle (tW).
5.1.2
Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time,
the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected until a
falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must
have been High, prior to going Low to start the first operation.
5.1.3
Device Reset
In order to prevent inadvertent Write operations during power-up (continuous rise of VCC), a
power on reset (POR) circuit is included. At Power-up, the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in operating ranges of page 33).
When VCC has passed the POR threshold, the device is reset.
5.1.4
Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage, the device stops responding to any
instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should
be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should
be no internal Write cycle in progress).
5.2 Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption drops
to ICC1.
May 2017
Rev 1.6
10 / 44
SPI Operation
BY25D40/20
5.3 Status Register
Table 4. Status Register
S7
SRP
S6
S5
Reserved Reserved
S4
BP2
S3
BP1
S2
BP0
S1
WEL
S0
WIP
The status and control bits of the Status Register are as follows:
WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write
status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write
status register progress, when WIP bit sets 0, means the device is not in program/erase/write
status register progress.
WEL bit
The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to
1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and
no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the Write
Status Register instruction. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant
memory area. Becomes protected against Page Program, Sector Erase and Block Erase
instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware
Protected mode has not been set.
SRP bits
The Status Register Protect (SRP) bit operates in conjunction with the Write Protect (WP#)
signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal set the device
to the Hardware Protected mode. When the Status Register Protect (SRP) bit is set to 1, and Write
Protect (WP#) is driven Low. In this mode, the non-volatile bits of the Status Register (SRP, BP2,
BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is not
execution. The default value of SRP is 0.
May 2017
Rev 1.6
11 / 44
SPI Operation
5.3.1
1.
BY25D40/20
Write Protect Features
Software Protection: The Block Protect (BP2, BP1, BP0) bits define the section of the memory
array that can be read but not change.
2.
Hardware Protection: /WP going low to protected the BP0~BP2 bits and SRP bits.
3.
Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the
Release from deep Power-Down Mode instruction.
4.
Write Enable: The Write Enable Latch (WEL) bit must be set prior to every Page Program,
Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program Security
Registers instruction.
5.4 Status Register Memory Protection
5.4.1.1 Protect Table
Table 5. BY25D40 Status Register Memory Protection
Status Register
Content
Memory Content
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
0
0
0
NONE
NONE
NONE
NONE
0
0
1
Sector 0 to 125
000000H-07DFFFH
504KB
Lower 126/128
0
1
0
Sector 0 to 123
000000H-07BFFFH
496KB
Lower 124/128
0
1
1
Sector 0 to 119
000000H-077FFFH
480KB
Lower 120/128
1
0
0
Sector 0 to 111
000000H-06FFFFH
448KB
Lower 112/128
1
0
1
Sector 0 to 95
000000H-05FFFFH
384KB
Lower 96/128
1
1
0
Sector 0 to 63
000000H-03FFFFH
256KB
Lower 64/128
1
1
1
ALL
000000H-07FFFFH
512KB
ALL
May 2017
Rev 1.6
12 / 44
SPI Operation
BY25D40/20
Table 6. BY25D20 Status Register Memory Protection
Status Register
Content
Memory Content
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
0
0
0
NONE
NONE
NONE
NONE
0
0
1
Sector 0 to 61
000000H-03DFFFH
248KB
Lower 62/64
0
1
0
Sector 0 to 59
000000H-03BFFFH
240KB
Lower 60/64
0
1
1
Sector 0 to 55
000000H-037FFFH
224KB
Lower 56/64
1
0
0
Sector 0 to 47
000000H-02FFFFH
192KB
Lower 48/64
1
0
1
Sector 0 to 31
000000H-01FFFFH
128KB
Lower 32/64
1
1
x
ALL
000000H-03FFFFH
256KB
ALL
May 2017
Rev 1.6
13 / 44
Device Identification
BY25D40/20
6. Device Identification
Three legacy Instructions are supported to access device identification that can indicate the
manufacturer, device type, and capacity (density). The returned data bytes provide the information
as shown in the below table.
BY25D40 ID Definition table
Operation Code
M7-M0
ID15-ID8
ID7-ID0
68
68
40
13
12
12
M7-M0
ID15-ID8
ID7-ID0
68
68
40
12
11
11
9FH
90H
ABH
BY25D20 ID Definition table
Operation Code
9FH
90H
ABH
May 2017
Rev 1.6
14 / 44
Instructions Description
BY25D40/20
7. Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction
code must be shifted in to the device, most significant bit first on SI, each bit being latched on the
rising edges of SCLK.
See Table 7, every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must
be driven high after the last bit of the instruction sequence has been shifted in. For the instruction
of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device
ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high
after any bit of the data-out sequence is being shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register,
Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a
byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must drive
high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For
Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not
be reset.
May 2017
Rev 1.6
15 / 44
Instructions Description
BY25D40/20
Table 7. Instruction Set Table
Instruction Name
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data
Fast Read
Dual Output Fast
Read
Page Program
Page Program
Sector Erase
Block Erase(32K)
Block Erase(64K)
Chip Erase
Deep Power-Down
Release From Deep
Power-Down, And
Read Device ID
Release From Deep
Power-Down
Manufacturer/ Device
ID
JEDEC ID
Byte 1
06H
04H
05H
01H
03H
0BH
3BH
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
(S7-S0)
(S7-S0)
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
(D7-D0)
dummy
dummy
Next byte
(D7-D0)
(D7-D0)(1)
02H
F2H
20H
52H
D8H
C7/60H
B9H
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
(D7-D0)
(D7-D0)
Next byte
Next byte
ABH
dummy
dummy
dummy
(ID7-ID0)
90H
dummy
dummy
00H
(M7-M0)
9FH
(M7-M0)
(ID15-ID8)
(ID7-ID0)
ABH
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
May 2017
Rev 1.6
16 / 44
(ID7-ID0)
Instructions Description
BY25D40/20
7.1 Configuration and Status Instructions
7.1.1
Write Enable (06H)
See Figure 4, the Write Enable instruction is for setting the Write Enable Latch bit. The Write
Enable Latch bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase
and Write Status Register instruction. The Write Enable instruction sequence: /CS goes low
sending the Write Enable instruction /CS goes high.
Figure 4. Write Enable Sequence Diagram
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
06H
High_Z
SO
7.1.2
Write Disable (04H)
See Figure 5, the Write Disable instruction is for resetting the Write Enable Latch bit. The Write
Disable instruction sequence: /CS goes low sending the Write Disable instruction /CS goes high.
The WEL bit is reset by following condition: Power-up and upon completion of the Write Status
Register, Page Program, Sector Erase, Block Erase and Chip Erase instructions.
Figure 5. Write Disable Sequence Diagram
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
04H
High_Z
SO
May 2017
Rev 1.6
17 / 44
Instructions Description
7.1.3
BY25D40/20
Read Status Register (05H)
See Figure 6 the Read Status Register (RDSR) instruction is for reading the Status Register. The
Status Register may be read at any time, even while a Program, Erase or Write Status Register
cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write
in Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the
Status Register continuously. For instruction code “05H”, the SO will output Status Register bits
S7~S0.
Figure 6. Read Status Register Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Instruction
SI
05H
S7-S0 out
SO
7.1.4
High_Z
7 6
MSB
5
4
3
S7-S0 out
2
1
0
7 6
MSB
5
4
3
2
1
0
Write Status Register (01H)
See Figure 7, the Write Status Register instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable instruction must previously have been
executed. After the Write Enable instruction has been decoded and executed, the device sets the
Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6
and S5 are always read as 0. /CS must be driven high after the eighth or sixteen bit of the data byte
has been latched in. If not, the Write Status Register instruction is not executed. As soon as Chip
Select (CS#) is driven High, the self-timed Write Status Register cycle (the duration is tW) is
initiated. While the Write Status Register cycle is in progress, reading Status Register to check the
Write In Progress (WIP) bit is achievable. The Write In Progress (WIP) bit is 1 during the self-timed
Write Status Register cycle, and turn to 0 on the completion of the Write Status Register. When the
cycle is completed, the Write Enable Latch (WEL) is reset to 0. The Write Status Register (WRSR)
instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, which
are utilized to define the size of the read-only area. The Write Status Register (WRSR) instruction
also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the
Write Protect (WP#) signal, by setting which the device can enter into Hardware Protected Mode
(HPM). The Write Status Register (WRSR) instruction is not executed once enter into the Hardware
Protected Mode (HPM).
May 2017
Rev 1.6
18 / 44
Instructions Description
BY25D40/20
Figure 7. Write Status Register Sequence Diagram
/CS
0
1
2
4
3
5
6
7
8
9
10 11 12 13 14 15
SCLK
Status Register in
Instruction
SI
01H
7
6
5
4
3
2
1
0
MSB
High_Z
SO
7.2 Read Instructions
7.2.1
Read Data (03H)
See Figure 8, the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0),
each bit being latched-in during the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, each bit being shifted out, at a Max frequency fR, during the falling
edge of SCLK. The address is automatically incremented to the next higher address after each
byte of data is shifted out allowing for a continuous stream of data. This means that the entire
memory can be accessed with a single command as long as the clock continues. The command is
completed by driving /CS high. The whole memory can be read with a single Read Data Bytes
(READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress. Normal
read mode running up to 50MHz.
Figure 8. Read Data Bytes Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
24-Bit Address
Instruction
SI
03H
23 22
21
3
2
1
0
Data Byte1
MSB
SO
May 2017
High_Z
7 6
MSB
Rev 1.6
5
4
3
High_Z
2
19 / 44
1
0
Instructions Description
7.2.2
BY25D40/20
Fast Read (0BH)
See Figure 9, the Read Data Bytes at Higher Speed (Fast Read) instruction is for quickly reading
data out. It is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO,
each bit being shifted out, at a Max frequency fc, during the falling edge of SCLK. The first byte
addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out.
Figure 9. Fast Read Sequence Diagram
/CS
0
1
2
3
4
5
6
7
9
8
28 29 30
10
31
SCLK
Instruction
24-Bit Address
23 22
0BH
SI
21
3
2
1
0
High_Z
SO
/CS
32 33 34 35 36
37 38 39 40 41 42 43 44
45 46 47
SCLK
Dummy Clocks
High_Z
SI
SO
May 2017
Data byte 1
High_Z
7
Rev 1.6
6
5
4
3
High_Z
2
1
0
20 / 44
Instructions Description
7.2.3
BY25D40/20
Dual Output Fast Read (3BH)
See Figure 10, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a
dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is
shifted out.
Figure 10. Dual Output Fast Read Sequence Diagram
/CS
0
1
2
3
4
5
6
7
9
8
28
10
29
30
31
SCLK
Instruction
24-Bit Address
3BH
SI
SO
23
22
21
41
42
43
3
2
1
0
High_Z
/CS
32
33
34
35
36
37
38
39
40
44
45
46
47
6
4
2
0
SCLK
SI
Dummy Clocks
6
4
2
0
Data Byte 2
Data Byte 1
SO
May 2017
High_Z
7
Rev 1.6
5
3
High_Z
1
7
5
3
High_Z
1
21 / 44
Instructions Description
BY25D40/20
7.3 ID and Security Instructions
7.3.1
Read Manufacture ID/ Device ID (90H)
See Figure 11, the Read Manufacturer/Device ID instruction is an alternative to the Release from
Power-Down/Device ID instruction that provides both the JEDEC assigned Manufacturer ID and
the specific Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H”
followed by a 24-bit address (A23-A0) of 000000H. If the 24-bit address is initially set to 000001H,
the Device ID will be read first.
Figure 11. Read Manufacture ID/ Device ID Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Instruction
SI
24-Bit Address
3 2
23 22 21
90H
High_Z
SO
1
0
/CS
32 33 34 35 36
37 38 39 40 41 42
43 44 45 46 47
SCLK
SI
SO
May 2017
7
6
Manufacturer ID
5 4
3 2
1
0
Rev 1.6
7
6
Device ID
3 2
5 4
1
0
22 / 44
Instructions Description
7.3.2
BY25D40/20
JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two
bytes of device identification. The device identification indicates the memory type in the first byte,
and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode.
See Figure 12, he device is first selected by driving /CS to low. Then, the 8-bit instruction code for
the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory,
being shifted out on Serial Data Output, each bit being shifted out during the falling edge of Serial
Clock. The JEDEC ID instruction is terminated by driving /CS to high at any time during data
output. When /CS is driven high, the device is put in the Standby Mode. Once in the Standby
Mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Figure 12. JEDEC ID Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
9FH
Instruction
SI
Manufacturer ID
7
MSB
SO
/CS
6
5
4
3
2
1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
Memory Type ID15-ID8
6 5 4 3 2 1
MSB
May 2017
0
7
Capacity ID7-ID0
6 5 4 3 2 1
0
MSB
Rev 1.6
23 / 44
0
Instructions Description
7.3.3
BY25D40/20
Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is
unique to each BY25D40&20 device. The ID number can be used in conjunction with user
software methods to help prevent copying or cloning of a system. The Read Unique ID instruction
is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four
bytes of dummy clocks. After which, the 64-bit ID is shifted out on the falling edge of SCLK as
shown in Figure 13.
Figure 13. JEDEC ID Sequence Diagram
/CS
SCLK
0
Mode 3
Mode 0
1
2
3
4
5
6
7
8
9
10
Instruction
SI
11
12
13
14
15
16
Dummy Byte 1
17
18
19
20
21
22
23
Dummy Byte 2
4BH
SO
High_Z
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
100 101 102 103
SCLK
Dummy Byte 3
Dummy Byte 4
SI
SO
May 2017
High_Z
63
MSB
Rev 1.6
62
2
1
0
64-bit Unique
Serial Number
24 / 44
Mode 3
Mode 0
Instructions Description
7.3.4
BY25D40/20
Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Deep Power-down instruction. The lower power consumption makes the
Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1
and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in Figure 14.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep
Power down instruction will not be executed. After /CS is driven high, the power-down state will
entered within the time duration of tDP. While in the power-down state only the Release from Deep
Power-down / Device ID instruction, which restores the device to normal operation, will be
recognized. All other Instructions are ignored. This includes the Read Status Register instruction,
which is always available during normal operation. Ignoring all but one instruction also makes the
Power Down state a useful condition for securing maximum write protection. The device always
powers-up in the normal operation with the standby current of ICC1.
Figure 14. Deep Power-Down Sequence Diagram
/CS
0
1
2
3 4
5
6
7
tDP
SCLK
Instruction
SI
B9H
Stand-by mode
May 2017
Rev 1.6
Power-down mode
25 / 44
Instructions Description
7.3.5
BY25D40/20
Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be
used to release the device from the Power-Down state or obtain the devices electronic
identification (ID) number.
See Figure 15a, to release the device from the Power-Down state, the instruction is issued by
driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release from
Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device will
resume normal operation and other instruction are accepted. The /CS pin must remain high during
the tRES1 time duration.
When used only to obtain the Device ID while not in the Power-Down state, the instruction is
initiated by driving the /CS pin low and shifting the instruction code “ABH” followed by 3-dummy
byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit
(MSB) first as shown in Figure 15b. The Device ID value for the BY25D40/20 is listed in
Manufacturer and Device Identification table. The Device ID can be read continuously. The
instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the
instruction is the same as previously described, and shown in Figure 15b, except that after /CS is
driven high it must remain high for a time duration of tRES2 (See AC Characteristics). After this
time duration the device will resume normal operation and other instruction will be accepted. If the
Release from Power-Down/Device ID instruction is issued while an Erase, Program or Write cycle
is in process (when WIP equal 1) the instruction is ignored and will not have any effects on the
current cycle.
Figure 15a. Release Power-Down Sequence Diagram
/CS
1
0
2
3 4
5
6
tRES1
7
SCLK
Instruction
SI
ABH
Power-down mode
Stand-by mode
Figure 15b. Release Power-Down/Read Device ID Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
29 30
31 32 33 34 35 36 37
38 39
SCLK
Instruction
SI
ABH
SO
High_Z
3 Dummy Bytes
23 22
2
1
MSB
tRES2
0
7
MSB
6
Device ID
3
4
5
2
1
0
Deep Power-down mode
May 2017
Rev 1.6
26 / 44
Stand-by mode
Instructions Description
BY25D40/20
7.4 Program and Erase Instructions
7.4.1
Page Program (02H)
The Page Program instruction is for programming the memory. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit before sending the Page Program
instruction.
See Figure 16, the Page Program instruction is entered by driving /CS Low, followed by the
instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant address
bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are
programmed from the start address of the same page (from the address whose 8 least significant
bits (A7-A0) are all zero). /CS must be driven low for the entire duration of the sequence. The
Page Program instruction sequence: /CS goes low sending Page Program instruction 3-byte
address on SI at least 1 byte data on SI /CS goes high. If more than 256 bytes are sent to the
device, previously latched data are discarded and the last 256 data bytes are guaranteed to be
programmed correctly within the same page. If less than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses without having any effects on the other
bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Page Program instruction is not executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is
initiated. While the Page Program cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch bit is reset.
A Page Program instruction applied to a page which is protected by the Block Protect (BP2, BP1,
BP0) bits is not executed.
Figure 16. Page Program Sequence Diagram
/CS
0
4
3
2
1
5
6
7
9
8
10
29 30
28
31 32 33 34 35 36 37 38 39
SCLK
2
3
1
0
2079
4
5
2078
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
7 6
MSB
2077
/CS
0
2074
2
2072
3
2073
02H
SI
Data Byte 1
1
2076
24-Bit Address
23 22 21
MSB
2075
Instruction
1
0
SCLK
Data Byte 2
SI
7
MSB
May 2017
6
5
4
3
2
1
0
7 6
MSB
Data Byte 3
4 3 2
5
Rev 1.6
1
0
7 6
MSB
Data Byte 256
3 2
5 4
27 / 44
Instructions Description
7.4.2
BY25D40/20
Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The Sector
Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-address
byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. /CS
must be driven low for the entire duration of the sequence.
See Figure 17, The Sector Erase instruction sequence: /CS goes low sending 64KB Block Erase
instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit of the
last address byte has been latched in; otherwise the Sector Erase instruction is not executed. As
soon as /CS is driven high, the self-timed Sector Erase cycle (whose duration is tSE) is initiated.
While the Sector Erase cycle is in progress, the Status Register may be read to check the value of
the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed,
the Write Enable Latch bit is reset. A Sector Erase instruction applied to a sector which is
protected by the Block Protect (BP2, BP1, BP0) bits is not executed.
Figure 17. Sector Erase Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Instruction
SI
May 2017
20H
Rev 1.6
24-Bit Address
23 22
2
1
0
28 / 44
Instructions Description
7.4.3
BY25D40/20
32KB Block Erase (52H)
The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The 32KB Block
Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte
address on SI. Any address inside the block is a valid address for the 32KB Block Erase
instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 18, the 32KB Block Erase instruction sequence: /CS goes low sending 32KB Block
Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the 32KB Block Erase instruction is not
executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE)
is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase instruction applied to a
block which is protected by the Block Protect (BP2, BP1, BP0) bits is not executed.
Figure 18. 32KB Block Erase Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Instruction
SI
May 2017
52H
Rev 1.6
24-Bit Address
23 22
2
1
0
29 / 44
Instructions Description
7.4.4
BY25D40/20
64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The 64KB Block
Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte
address on SI. Any address inside the block is a valid address for the 64KB Block Erase
instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 19, the 64KB Block Erase instruction sequence: /CS goes low sending 64KB Block
Erase instruction 3-byte address on SI /CS goes high. /CS must be driven high after the eighth bit
of the last address byte has been latched in; otherwise the 64KB Block Erase instruction is not
executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose duration is tBE)
is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch bit is reset. A 64KB Block Erase instruction applied to a
block which is protected by the Block Protect (BP2, BP1, BP0) bits is not executed.
Figure 19. 64KB Block Erase Sequence Diagram
/CS
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Instruction
SI
May 2017
D8H
Rev 1.6
24-Bit Address
23 22
2
1
0
30 / 44
Instructions Description
7.4.5
BY25D40/20
Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in
Figure 20.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase
instruction will commence for a time duration of tCE. While the Chip Erase cycle is in progress, the
Read Status Register instruction may still be accessed to check the status of the WIP bit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other Instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be
executed if any page is protected by the Block Protect (BP2, BP1, and BP0) bits.
Figure 20. Chip Erase Sequence Diagram
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
60/C7H
High_Z
SO
May 2017
Rev 1.6
31 / 44
Electrical Characteristics
BY25D40/20
8. Electrical Characteristics
8.1 Absolute Maximum Ratings
PARAMETERS
SYMBOL
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
Transient Voltage on any Pin
VIOT
Storage Temperature
TSTG
Electrostatic Discharge Voltage
VESD
CONDITIONS
RANGE
UNIT
–0.5 to 4
V
Relative to Ground
–0.5 to 4
V
工商网监
湘ICP备2023018690号
