P25Q32SH Datasheet
P25Q32SH
Ultra Low Power, 32M-bit
Serial Multi I/O Flash Memory Datasheet
Aug. 10, 2021
Performance Highlight
◆ Wide Supply Range from 2.3 to 3.6V for Read, Erase and Program
◆ Ultra Low Power consumption for Read, Erase and Program
◆ X1, X2 and X4 Multi I/O, QPI, DTR Support
◆ High reliability with 100K cycling and 20 Year-retention
Puya Semiconductor (Shanghai) Co., Ltd
Puya Semiconductor
Page 1 of 106
P25Q32SH Datasheet
Contents
1
2
3
Overview ........................................................................................................................................................4
Description .....................................................................................................................................................5
Pin Definition .................................................................................................................................................6
3.1
Pin Configurations .............................................................................................................................6
3.2
Pin Descriptions .................................................................................................................................6
4 Block Diagram ...............................................................................................................................................7
5 Electrical Specifications .................................................................................................................................8
5.1
Absolute Maximum Ratings ...............................................................................................................8
5.2
DC Characteristics .............................................................................................................................9
5.3
AC Characteristics .......................................................................................................................... 10
5.4
AC Characteristics for Program and Erase .................................................................................... 12
5.5
Operation Conditions ...................................................................................................................... 14
6 Data Protection ........................................................................................................................................... 16
7 Memory Address Mapping .......................................................................................................................... 19
8 Device Operation ........................................................................................................................................ 20
9 Hold Feature ............................................................................................................................................... 23
10 Commands ................................................................................................................................................. 24
10.1 Commands listing ........................................................................................................................... 24
10.2 Write Enable (WREN) ..................................................................................................................... 29
10.3 Write Disable (WRDI) ....................................................................................................................... 30
10.4 Write Enable for Volatile Status Register ....................................................................................... 31
10.5 Read Status Register (RDSR) .......................................................................................................... 32
10.6 Read Configure Register (RDCR) .................................................................................................... 34
10.7 Write Status Register (WRSR) ......................................................................................................... 36
10.8 Write Configure Register (WRCR) .................................................................................................... 37
10.9 Read Data Bytes (READ) ................................................................................................................. 38
10.10 Fast Read (FREAD) ......................................................................................................................... 39
10.11 DTR Fast Read(DTR_FREAD) ........................................................................................................ 40
10.12 Dual Read (DREAD) ........................................................................................................................ 41
10.13 2IO Read (2READ) .......................................................................................................................... 42
10.14 DTR 2IO Read (DTR_2READ) ......................................................................................................... 43
10.15 Quad Read (QREAD) ...................................................................................................................... 45
10.16 4IO Read (4READ) .......................................................................................................................... 46
10.17 Set Burst Read ................................................................................................................................ 48
10.18 DTR 4IO Read (DTR_4READ) ......................................................................................................... 49
10.19 4IO Word Read(E7h) ....................................................................................................................... 51
10.20 Set Read Parameters (C0h) ............................................................................................................. 53
10.21 Burst Read with Wrap (0Ch)............................................................................................................. 54
10.22 DTR Burst Read with Wrap (0Eh) .................................................................................................... 54
10.23 Data Learning Pattern..................................................................................................................... 55
10.24 Enable QPI (38H)............................................................................................................................. 58
10.25 Disable QPI (FFH) ........................................................................................................................... 58
10.26 Page Erase (PE) .............................................................................................................................. 59
10.27 Sector Erase (SE) ............................................................................................................................ 60
10.28 Block Erase (BE32K) ....................................................................................................................... 61
10.29 Block Erase (BE).............................................................................................................................. 62
10.30 Chip Erase (CE)............................................................................................................................... 63
10.31 Page Program (PP).......................................................................................................................... 63
10.32 Quad Page Program (QPP) ............................................................................................................. 65
10.33 Buffer Clear ..................................................................................................................................... 66
Puya Semiconductor
Page 2 of 106
P25Q32SH Datasheet
11
12
13
14
10.34 Buffer Load ...................................................................................................................................... 67
10.35 Buffer Read ..................................................................................................................................... 68
10.36 Buffer Write ...................................................................................................................................... 69
10.37 Buffer to Main Memory Page Program ............................................................................................. 70
10.38 Erase Security Registers (ERSCUR) ................................................................................................ 71
10.39 Program Security Registers (PRSCUR) ........................................................................................... 72
10.40 Read Security Registers (RDSCUR) ................................................................................................ 73
10.41 Deep Power-down (DP) ................................................................................................................... 74
10.42 Release form Deep Power-Down (RDP), Read Electronic Signature (RES) ...................................... 75
10.43 Read Electronic Manufacturer ID & Device ID (REMS) ..................................................................... 77
10.44 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS) .................................................... 78
10.45 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)................................................... 79
10.46 Read Identification (RDID)................................................................................................................ 80
10.47 Program/Erase Suspend/Resume .................................................................................................... 81
10.48 Erase Suspend to Program .............................................................................................................. 83
10.49 Program Resume and Erase Resume .............................................................................................. 84
10.50 No Operation (NOP) ........................................................................................................................ 84
10.51 Individual Block Lock (SBLK) ........................................................................................................... 85
10.52 Individual Block Unlock (SBULK)...................................................................................................... 86
10.53 Read Block Lock Status (RDBLK) .................................................................................................... 87
10.54 Global Block Lock (GBLK)................................................................................................................ 88
10.55 Global Block Unlock (GBULK) .......................................................................................................... 89
10.56 Software Reset (RSTEN/RST) ......................................................................................................... 90
10.57 RESET ............................................................................................................................................ 91
10.58 Read Unique ID (RUID) ................................................................................................................... 92
10.59 Read SFDP Mode (RDSFDP) .......................................................................................................... 93
Ordering Information................................................................................................................................... 98
Valid Part Numbers and Top Marking ......................................................................................................... 99
Package Information................................................................................................................................. 100
13.1 8-Lead SOP(150mil) ..................................................................................................................... 100
13.2 8-Lead SOP(208mil) ..................................................................................................................... 101
13.3 8-Lead TSSOP ............................................................................................................................. 102
13.4 8-Land USON(3x2x0.55mm) ........................................................................................................ 103
13.5 8-Land USON(3x4x0.55mm) ........................................................................................................ 104
13.6 8-Land WSON(6x5x0.75mm) ....................................................................................................... 105
Revision History........................................................................................................................................ 106
Puya Semiconductor
Page 3 of 106
P25Q32SH Datasheet
1 Overview
General
Single 2.3V to 3.60V supply
Industrial Temperature Range -40C to 85C
Serial Peripheral Interface (SPI) Compatible: Mode 0 and Mode 3
Single, Dual, Quad SPI, QPI, DTR
-
Standard SPI:
SCLK,CS#,SI,SO,WP#,HOLD#
-
Dual SPI:
SCLK,CS#,IO0,IO1,WP#, HOLD#
-
Quad SPI:
SCLK,CS#,IO0,IO1,IO2,IO3
-
QPI:
SCLK,CS#,IO0,IO1,IO2,IO3
-
DTR:
Double Transfer Rate Read
Flexible Architecture for Code and Data Storage
-
Uniform 256-byte
Page Program
-
Uniform 256/512/1024-byte
-
Uniform 4K-byte
-
Uniform 32K/64K-byte Block Erase
-
Full Chip Erase
Page Erase
Sector Erase
Hardware Controlled Locking of Protected Sectors by WP# Pin
One Time Programmable (OTP) Security Register
3*1024-Byte Security Registers With OTP Lock
128 bit unique ID for each device
Fast Program and Erase Speed
-
1.6ms
Single/Dual/Quad Page(s) program time
-
16ms
Page erase time
-
16ms
4K-byte sector erase time
-
16ms
32K/64K-byte block erase time
JEDEC Standard Manufacturer and Device ID Read Methodology
Ultra Low Power Consumption
-
0.3uA
Deep Power Down current
-
10.0uA
Standby current
-
7.5mA
Active Read current at 85MHz
-
3.0mA
Active Program or Erase current
High Reliability
-
100,000 Program / Erase Cycles
-
20-year Data Retention
Industry Standard Green Package Options
-
8-pin
SOP (150mil/208mil)
-
8-land
USON (3x2x0.55mm, 3x4x0.55mm)
-
8-land
WSON (6x5mm)
-
8-pin
TSSOP
-
WLCSP
-
KGD for SiP
Puya Semiconductor
Page 4 of 106
P25Q32SH Datasheet
2 Description
The P25Q32SH is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the device, with its page erase granularity it is
ideal for data storage as well, eliminating the need for additional data storage devices.
The erase block sizes of the device have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their own erase
regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash
memory devices can be greatly reduced. This increased memory space efficiency allows additional code
routines and data storage segments to be added while still maintaining the same overall device density.
The device also contains an additional 3*1024-byte security registers with OTP lock (One-Time
Programmable), can be used for purposes such as unique device serialization, system-level Electronic Serial
Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the device supports read, program, and erase
operations with a wide supply voltage range of 1.65V to 3.6V. No separate voltage is required for
programming and erasing.
Puya Semiconductor
Page 5 of 106
P25Q32SH Datasheet
3 Pin Definition
3.1 Pin Configurations
CS#
1
8
VCC
CS#
1
8
VCC
SO
2
7
HOLD#/RESET#
SO
2
7
HOLD#/RESET#
WP#
3
6
SCLK
WP#
3
6
SCLK
GND
4
5
SI
GND
4
5
SI
8-PIN SOP (150mil/208mil) and TSSOP
Top View
8-Land WSON (3x2/3x4/4x4/6x5mm)
Bottom View
VCC
CS#
CS#
VCC
HOLD#
SO
SO
HOLD#
SCLK
WP#
WP#
SCLK
SI
GND
GND
SI
8-Ball WLCSP Ball Assignment
3.2 Pin Descriptions
No.
Symbol
Extension
1
CS#
2
SO
SIO1
3
WP#
SIO2
4
GND
-
5
SI
SIO0
6
SCLK
-
7
HOLD#/RESET#
SIO3
8
VCC
-
Remarks
Chip select
Serial data output for 1 x I/O
Serial data input and output for 4 x I/O read mode
Write protection active low
Serial data input and output for 4 x I/O read mode
Ground of the device
Serial data input for 1x I/O
Serial data input and output for 4 x I/O read mode
Serial interface clock input
Hardware Reset Pin Active low or to pause the device
without deselecting the device
Serial data input and output for 4 x I/O read mode
Power supply of the device
Notes:
1.
SIO0 and SIO1 are used for Standard and Dual SPI instructions
2.
SIO0 – SIO3 are used for Quad SPI/QPI instructions, WP# & HOLD# (or RESET#) functions are only available for Standard/Dual
SPI.
Puya Semiconductor
Page 6 of 106
P25Q32SH Datasheet
4 Block Diagram
CS#
High Voltage Generator
Serial Bus
Control Logic
SCK
Data buffer
SI
SO
X -DECODER
Interface
Control &
Logic
Address Latch
WP#
Flash Memory Array
HOLD#
/Reset
Serial MUX &
I/O buffers
Control and
Protection logic
VCC
GND
Y-DECODER
Block Diagram
Flash Memory Array
Page (256/512/1024 bytes)
Buffer to
memory pgm
Buffer load
Buffer (256/512/1024 bytes)
Buffer write
&buffer clear
All erase
command
All read
command
All Program
command
Buffer read
I/O Interface
SI(IO0)
SO(IO1)
WP#(IO3) HOLD#(IO4)
Data Flow Diagram
Puya Semiconductor
Page 7 of 106
P25Q32SH Datasheet
5 Electrical Specifications
5.1 Absolute Maximum Ratings
NOTICE: Stresses above those listed under “Absolute
◼
Storage Temperature .......................-65°C to +150°C
◼
Operation Temperature ....................-40°C to +85°C
◼
Maximum Operation Voltage............. 4.0V
◼
Voltage on Any Pin with
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at those or any other conditions above those
indicated in the operational listings of this specification is
respect to Ground. ..........................-0.6V to + 4.1V
◼
not implied. Exposure to maximum rating conditions for
DC Output Current ............................5.0 mA
extended periods may affect device reliability.
Table 5-1 Pin Capacitance [1]
Symbol
Parameter
Max.
Units
Test Condition
COUT
Output Capacitance
8
pF
VOUT=GND
CIN
Input Capacitance
6
pF
VIN=GND
Note:
1.
Test Conditions: TA = 25°C, F = 1MHz, VCC = 3.0V.
Figure 5-1 Maximum Overshoot Waveform
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
VCC+1.0V
20ns
0V
VCC
20ns
-1.0V
Figure 5-2 Input Test Waveforms and Measurement Level
Input timing reference level
0.8VCC
Output timing reference level
0.7VCC
AC MeasurementLevel
0.5VCC
0.3VCC
0.2VCC
Note:Input pulse rise and fall time ara < 5ns
Figure 5-3 Output Loading
DEVICE
UNDER
TEST
25K ohm
VCC
CL
25K ohm
CL = 15/30pF Including jig capacitance
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Page 8 of 106
P25Q32SH Datasheet
5.2 DC Characteristics
Table 5-2 DC parameters (Ta=-40°C to +85°C)
Sym.
Parameter
IDPD
Deep power down current
ISB
Standby current
ICC1
Read current (STR)
(1, 2, 4 IO)
ICC2
Conditions
2.3V to 3.6V
Min.
Units
Typ.
Max.
0.3
5.0
uA
10.0
15.0
uA
f=85MHz; IOUT=0mA
7.5
10.0
mA
f=120MHz; IOUT=0mA
11.0
15.0
mA
Read current (DTR)
(1, 2, 4 IO)
f=50MHz; IOUT=0mA
7.0
9.0
mA
f=70MHz; IOUT=0mA
9.5
13.0
mA
ICC3
Program current
CS#=Vcc
3.0
4.0
mA
ICC4
Erase current
CS#=Vcc
3.0
4.0
mA
ILI
Input load current
All inputs at CMOS level
1.0
uA
ILO
Output leakage
All inputs at CMOS level
1.0
uA
VIL
Input low voltage
0.3Vcc
V
VIH
Input high voltage
VOL
Output low voltage
IOL=100uA
VOH
Output high voltage
IOH=-100uA
CS#=Vcc, all other inputs at 0V or
Vcc
CS#, HOLD#, WP#=VIH all inputs at
CMOS levels
0.7Vcc
V
0.2
Vcc-0.2
V
V
Note
1. Typical values measured at 3.0V @ 25°C for the 2.3V to 3.6V range.
Puya Semiconductor
Page 9 of 106
P25Q32SH Datasheet
5.3 AC Characteristics
Table 5-3-1 AC parameters(Ta=-40°C to +85°C)
Symbol
Alt.
fSCLK
fC
fRSCLK
fR
fT
fTSCLK
fQ
fD
fQPP
Parameter
2.3V~3.6V
min
typ
max
Unit
120
MHz
Clock Frequency for READ instructions
55
MHz
Clock Frequency for 2READ,DREAD instructions
120
MHz
120
MHz
66
MHz
120
MHz
Clock Frequency for the following instructions: FREAD, RDSFDP, PP, SE,
BE32K, BE, CE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR(7)
Clock Frequency for 4READ, QREAD, QPI 0Bh, QPI EBh, QPI 0Ch
instructions
Clock Frequency for DTR instructions
Clock Frequency for QPP (Quad page program)
tCH(1)
tCLH
Clock High Time
3.5
ns
tCL(1)
tCLL
Clock Low Time (fSCLK) 45% x (1fSCLK)
3.5
ns
tCLCH(7)
Clock Rise Time (peak to peak)
0.1
v/ns
tCHCL(7)
Clock Fall Time (peak to peak)
0.1
v/ns
CS# Active Setup Time (relative to SCLK)
5
ns
CS# Not Active Hold Time (relative to SCLK)
5
ns
tSLCH
tCSS
tCHSL
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
3
ns
tCHSH
CS# Active Hold Time (relative to SCLK)
5
ns
tSHCH
CS# Not Active Setup Time (relative to SCLK)
5
ns
CS# Deselect Time From Read to next Read
20
ns
CS# Deselect Time From Write,Erase,Program to Read Status Register
30
tSHSL
tCSH
tSHQZ(7)
tDIS
tCLQV
tV
tCLQX
tHO
ns
Output Disable Time
6
ns
Clock Low to Output Valid Loading 30pF
7
ns
6
ns
Clock Low to Output Valid Loading 15pF
Output Hold Time
0
ns
tHLCH
HOLD# Active Setup Time (relative to SCLK)
5
ns
tCHHH
HOLD# Active Hold Time (relative to SCLK)
5
ns
tHHCH
HOLD# Not Active Setup Time (relative to SCLK)
5
ns
tCHHL
HOLD# Not Active Hold Time (relative to SCLK)
5
ns
tHHQX
tLZ
HOLD# to Output Low-Z
tHLQZ
tHZ
HOLD# to Output High-Z
6
ns
6
ns
tWHSL(3)
Write Protect Setup Time
20
ns
tSHWL(3)
Write Protect Hold Time
100
ns
tDP
CS# High to Deep Power-down Mode
3
us
tRES1
CS# High To Standby Mode Without Electronic Signature Read
8
us
tRES2
CS# High To Standby Mode With Electronic Signature Read
8
us
12
ms
tW
tReady
tBL
tBC
Write Status Register Cycle Time
8
Reset recovery time(for erase/program operation except WRSR)
30
Reset recovery time(for WRSR operation)
12
us
8
ms
Load memory page data to buffer time(256Byte)
60
us
Load memory page data to buffer time(1024Byte)
240
us
Buffer clear to next instruction latency
Puya Semiconductor
200
ns
Page 10 of 106
P25Q32SH Datasheet
Table 5-3-2 SPI Read Command Performance Comparison (Unit: MHz)
Dummy Cycles (VCC=2.3V~3.6V)
Read command
4
6
8
10
FREAD
-
-
120
-
DTR_FREAD
-
66
-
-
DREAD
-
-
120
-
2READ
104(default)
-
120
-
66
-
-
-
QREAD
-
-
120
-
4READ
-
104(default)
-
120
DTR_4READ
-
-
66
-
DTR_2READ
Table 5-3-3 QPI Read Command Performance Comparison (Unit: MHz)
Dummy Cycles (VCC=2.3V~3.6V)
Read command
4
6
8
FREAD
80
104
120
DTR_FREAD
66
4READ
80
104
120
DTR_4READ
66
BURST READ
80
104
120
DTR_BURST READ
66
Puya Semiconductor
10
133(default)
133(default)
133(default)
-
Page 11 of 106
P25Q32SH Datasheet
5.4 AC Characteristics for Program and Erase
Table 5-4 AC parameters for program and erase (Ta=-40°C to +85°C)
Sym.
2.3V to 3.6V
Parameter
Min.
Typ.
Max.
Units
TESL(6)
Erase Suspend Latency
30
us
TPSL(6)
Program Suspend Latency
30
us
TPRS(4)
Latency between Program Resume and next Suspend
20
100
us
TERS(5)
Latency between Erase Resume and next Suspend
20
100
us
tPP
Page program time (up to 256 bytes)
1.6
2.5
ms
tPE
Page erase time
16
30
ms
tSE
Sector erase time
16
30
ms
tBE1
Block erase time for 32K bytes
16
30
ms
tBE2
Block erase time for 64K bytes
16
30
ms
tCE
Chip erase time
96
160
ms
Note
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction.
4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be
observed before issuing the next program suspend command. However, in order for a Program operation to
make progress, the average tPRS in resume-to-suspend loop(s) must be more than 100us. Not 100% tested.
5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be
observed before issuing the next erase suspend command. However, in order for an Erase operation to make
progress, the average tERS in resume-to-suspend loop(s) must be more than 100us. Notes. Not 100% tested.
6. Latency time is required to complete Erase/Program Suspend operation.
7. The value guaranteed by characterization, not 100% tested in production.
Figure 5-4 Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCLH tCLL
tCHSH
tSHCH
SCLK
tDVCH
tCHDX
SI
MSB
SO
High-Z
Puya Semiconductor
tCHCL
tCLCH
LSB
Page 12 of 106
P25Q32SH Datasheet
Figure 5-5 Output Timing
CS#
tCLH
SCLK
tCLQV
tCLQV
tCLQX
tSHQZ
tCLL
tCLQX
tQLQH
SO
LSB
tQHQL
SI
Least significant address bit (LIB) in
Figure 5-6 Hold Timing
CS#
tCHHL
SCLK
tHLCH
tHLQZ
SO
tCHHH
tHHCH
tHHQX
HOLD#
SI do not care during HOLD operation.
Figure 5-7 WP Timing
CS#
tWHSL
tSHWL
WP#
SCLK
SI
Write status register is allowed
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Write status register is not allowed
Page 13 of 106
P25Q32SH Datasheet
5.5 Operation Conditions
At Device Power-Up and Power-Down
AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for
the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to
be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 5-8
AC Timing at Device Power-Up
VCC
VCC(min)
GND
tVR
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB
MSB
SI
tCLCH
High-Z
SO
Figure 5-9 Power-up Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully accessible
VWI
Time
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Page 14 of 106
P25Q32SH Datasheet
Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
Figure 5-10 Power down-up Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
VPWD(max)
Device is fully
accessible
tPWD
Time
Symbol
Parameter
VPWD
VCC voltage needed to below VPWD for ensuring
initialization will occur
tPWD
tVSL
tVR
VWI
The minimum duration for ensuring initialization will occur
VCC(min.) to device operation
VCC Rise Time
Write Inhibit Voltage
min
300
150
1
1.20
max
unit
1
V
500000
1.55
us
us
us/V
V
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The
Status Register contains 00h (all Status Register bits are 0).
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Page 15 of 106
P25Q32SH Datasheet
6 Data Protection
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control
register architecture of the device constrains that the memory contents can only be changed after specific
command sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may
protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and
completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL)
before issuing other commands to change data.
• Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the
memory array that can be read but not change.
• Hardware Protection Mode: WP# going low to protected the BP0~BP4bits and SRP0~1bits
• Deep Power-Down Mode: By entering deep power down mode, the flash device is under protected from
writing all commands except the Release form Deep Power-Down Mode command.
Protected Area Sizes
Table 6-1. P25Q32SH Protected Area Sizes (WPS=0, CMP bit = 0)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
63
3F0000H-3FFFFFH
64KB
Upper 1/64
0
0
0
1
0
62 to 63
3E0000H-3FFFFFH
128KB
Upper 1/32
0
0
0
1
1
60 to 63
3C0000H-3FFFFFH
256KB
Upper 1/16
0
0
1
0
0
56 to 63
380000H-3FFFFFH
512KB
Upper 1/8
0
0
1
0
1
48 to 63
300000H-3FFFFFH
1MB
Upper 1/4
0
0
1
1
0
32 to 63
200000H-3FFFFFH
2MB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/64
0
1
0
1
0
0 to 1
000000H-01FFFFH
128KB
Lower 1/32
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/16
0
1
1
0
0
0 to 7
000000H-07FFFFH
512KB
Lower 1/8
0
1
1
0
1
0 to 15
000000H-0FFFFFH
1MB
Lower 1/4
0
1
1
1
0
0 to 31
000000H-3FFFFFH
2MB
Lower 1/2
x
x
1
1
1
0 to 63
000000H-1FFFFFH
2MB
ALL
1
0
0
0
1
63
3FF000H-3FFFFFH
4KB
Upper 1/1024
1
0
0
1
0
63
3FE000H-3FFFFFH
8KB
Upper 1/512
1
0
0
1
1
63
3FC000H-3FFFFFH
16KB
Upper 1/256
1
0
1
0
x
63
3F8000H- 3FFFFFH
32KB
Upper 1/128
1
0
1
1
0
63
3F8000H- 3FFFFFH
32KB
Upper 1/128
1
1
0
0
1
0
000000H-000FFFH
4KB
Lower 1/1024
1
1
0
1
0
0
000000H-001FFFH
8KB
Lower 1/512
Puya Semiconductor
Page 16 of 106
P25Q32SH Datasheet
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
1
1
0
1
1
0
000000H-003FFFH
16KB
Lower 1/256
1
1
1
0
x
0
000000H-007FFFH
32KB
Lower 1/128
1
1
1
1
0
0
000000H-007FFFH
32KB
Lower 1/128
Table 6-2.
P25Q32SH Protected Area Sizes (WPS=0, CMP bit = 1)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
All
000000H-3FFFFFH
4MB
ALL
0
0
0
0
1
0 to 62
000000H-3EFFFFH
4032KB
Lower 63/64
0
0
0
1
0
0 to 61
000000H-3DFFFFH
3968KB
Lower 31/32
0
0
0
1
1
0 to 59
000000H-3BFFFFH
3840KB
Lower 15/16
0
0
1
0
0
0 to 55
000000H-37FFFFH
3584KB
Lower 7/8
0
0
1
0
1
0 to 47
000000H-2FFFFFH
3MB
Lower 3/4
0
0
1
1
0
0 to 31
000000H-1FFFFFH
2MB
Lower 1/2
0
1
0
0
1
1 to 63
010000H-3FFFFFH
4032KB
Upper 63/64
0
1
0
1
0
2 to 63
020000H-3FFFFFH
3968KB
Upper 31/32
0
1
0
1
1
4 to 63
040000H-3FFFFFH
3840KB
Upper 15/16
0
1
1
0
0
8 to 63
080000H-3FFFFFH
3584KB
Upper 7/8
0
1
1
0
1
16 to 63
100000H-3FFFFFH
3MB
Upper 3/4
0
1
1
1
0
32 to 63
200000H-3FFFFFH
2MB
Upper 1/2
x
x
1
1
1
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 63
000000H-3FEFFFH
4092KB
Lower 1023/1024
1
0
0
1
0
0 to 63
000000H-3FDFFFH
4088KB
Lower 511/512
1
0
0
1
1
0 to 63
000000H-3FBFFFH
4080KB
Lower 255/256
1
0
1
0
x
0 to 63
000000H-3F7FFFH
4064KB
Lower 127/128
1
0
1
1
0
0 to 63
000000H-3F7FFFH
4064KB
Lower 127/128
1
1
0
0
1
0 to 63
001000-3FFFFFH
4092KB
Upper 1023/1024
1
1
0
1
0
0 to 63
002000-3FFFFFH
4088KB
Upper 511/512
1
1
0
1
1
0 to 63
004000-3FFFFFH
4080KB
Upper 255/256
1
1
1
0
x
0 to 63
008000-3FFFFFH
4064KB
Upper 127/128
1
1
1
1
0
0 to 63
008000-3FFFFFH
4064KB
Upper 127/128
Note:
1. X=don’t care
2. If any erase or program command specifies a memory that contains protected data portion, this command will be
ignored.
Puya Semiconductor
Page 17 of 106
P25Q32SH Datasheet
Table 6-3.
P25Q32SH Individual Block Protection (WPS=1)
Block
Sector/Block
Sector 15 (4KB)
Sector 14 (4KB)
Block 63
-
Sector 1 (4KB)
Sector 0 (4KB)
Block 62
Block 62 (64KB)
Individual Block
Locks:
32 Sectors(Top/Bottom)
62 Blocks
Individual Block Lock:
36h+Address
Block2 ~61
-------
Individual Block Unlock:
39h+Address
Read Block Lock:
3Dh+Address
Block 1
Block 1 (64KB)
Global Block Lock:
7Eh
Sector 15 (4KB)
Global Block Unlock:
98h
Sector 14 (4KB)
Block 0
Sector 1 (4KB)
Sector 0 (4KB)
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
Puya Semiconductor
Page 18 of 106
P25Q32SH Datasheet
7
Memory Address Mapping
The memory array can be erased in three levels of granularity including a full chip erase. The size of the erase
blocks is optimized for both code and data storage applications, allowing both code and data segments to
reside in their own erase regions.
Each device has
Each block has
Each sector has
Each page has
4M
64/32K
4K
256
bytes
16K
256/128
16
-
pages
1024
16/8
-
-
sectors
64/128
-
-
-
blocks
P25Q32SH Memory Organization
62
……
……
Puya Semiconductor
3FF000H
3FFFFFH
……
……
……
1008
3F0000H
3F0FFFH
1007
3EF000H
3EFFFFH
……
……
……
992
3E0000H
3E0FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
……
……
1~0
0
1023
3~2
1
Sector
125~124
63
Block 32K
127~126
Block 64K
Address Range
Page 19 of 106
P25Q32SH Datasheet
8 Device Operation
Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. When correct
command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS#
rising edge.
Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 8-1.
For the following instructions: RDID, RDSR, RDSR1, RDSCUR, READ, FREAD, DREAD, 2READ, 4READ,
QREAD, RDSFDP, RES, REMS, DREMS, QREMS, the shifted-in instruction sequence is followed by a dataout sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions:
WREN, WRDI, WRSR, PE, SE, BE32K, BE, CE, PP, QPP, DP, ERSCUR, PRSCUR, SUSPEND, RESUME,
RSTEN, RST, the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected
and not executed.
During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 8-1 Serial Peripheral Interface Modes Supported
CPOL CPHA
shift in
(Serial mode 0)
0
0
SCLK
(Serial mode 3)
1
1
SCLK
SI
SO
shift out
MSB
MSB
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA
indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported.
Puya Semiconductor
Page 20 of 106
P25Q32SH Datasheet
Power Up
Device Initialization
& Status Register Refresh
Hardware
Standard SPI
Dual SPI
Quad SPI
Reset
Enable QPI (38h)
Hardware
Reset
SPI Reset
(66h + 99h)
Disable QPI (FFh)
QPI
QPI Reset
(66h + 99h)
Standard SPI
The P25Q32SH features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input
data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The P25Q32SH supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
Read”(3BHand BBH) commands. These commands allow data to be transferred to or from the device at two
times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
Quad SPI
The P25Q32SH supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast
Read”(6BH,EBH,E7H) commands. These commands allow data to be transferred to or from the device at four
times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 andIO3. Quad SPI commands
require the non-volatile Quad Enable bit(QE) in Status Register to be set.
QPI
The P25Q32SH supports Quad Peripheral Interface (QPI) operations only when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enable the QPI (38H)” command. The QPI mode
utilizes all four IO pins to input the command code. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given times. “Enable the QPI(38H)”and “Disable the
QPI(FFH)”commands are used to switch between these two modes. Upon power-up and after software reset
using “”Reset (99H)”command, the default state of the device is Standard/Dual/Quad SPI mode. The QPI
mode requires the non-volatile Quad Enable bit (QE) in Status Register to be set.
Puya Semiconductor
Page 21 of 106
P25Q32SH Datasheet
SPI / QPI DTR Read Instructions
To effectively improve the read operation throughput without increasing the serial clock frequency, P25Q32SH
introduces multiple DTR (Double Transfer Rate) Read instructions that support Standard/Dual/Quad SPI and
QPI modes. The byte-long instruction code is still latched into the device on the rising edge of the serial clock
similar to all other SPI/QPI instructions. Once a DTR instruction code is accepted by the device, the address
input and data output will be latched on both rising and falling edges of the serial clock.
Software Reset
The P25Q32SH can be reset to the initial power-on state by a software Reset sequence, either in SPI mode or
QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset (99h). If the
command sequence is successfully accepted, the device will take approximately 30uS (tReady) to reset. No
command will be accepted during the reset period.
If QE bit is set to 1, the HOLD or RESET function will be disabled, the pin will become one of the four data I/O
pins.
Puya Semiconductor
Page 22 of 106
P25Q32SH Datasheet
9 Hold Feature
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop
the operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin
signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation
will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin
signal while Serial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will
not end until Serial Clock being low).
Figure 9-1 Hold Condition Operation
CS#
SCLK
HOLD#
HOLD
HOLD
During the HOLD operation, the Serial Data Output (SO) is high impedance when Hold# pin goes low and will
keep high impedance until Hold# pin goes high. The Serial Data Input (SI) is don't care if both Serial Clock
(SCLK) and Hold# pin goes low and will keep the state until SCLK goes low and Hold# pin goes high. If Chip
Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start
communication with chip, the HOLD# must be at high and CS# must be at low.
Note: The HOLD feature is disabled during Quad I/O mode.
Puya Semiconductor
Page 23 of 106
P25Q32SH Datasheet
10 Commands
10.1 Commands listing
Figure 10-1 Command set(STR Standard/Dual/Quad SPI instruction)
Abbr.
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
Read Array (fast)
FREAD
0Bh
3
1
1+
n bytes read out until CS# goes high
Read Array (low power)
READ
03h
3
0
1+
n bytes read out until CS# goes high
Read Dual Output
DREAD
3Bh
3
1
1+
n bytes read out by Dual output
Read 2IO
2READ
BBh
3
1(2)
1+
n bytes read out by 2IO
Read Quad Output
QREAD
6Bh
3
1
1+
n bytes read out by Quad output
Read 4IO
4READ
EBh
3
3(5)
1+
n bytes read out by 4IO
Read Word 4IO
WREAD
E7h
3
1
1+
n bytes word read out by 4IO
Page Erase
PE
81h
3
0
0
erase selected page
Sector Erase (4K bytes)
SE
20h
3
0
0
erase selected sector
Block Erase (32K bytes)
BE32
52h
3
0
0
erase selected 32K block
Block Erase (64K bytes)
BE
D8h
3
0
0
erase selected 64K block
Chip Erase
CE
60h/C7h
0
0
0
erase whole chip
Page Program
PP
02h
3
0
1+
program selected page
QPP
32h
3
0
1+
quad input to program selected page
Commands
Function description
Read
Program and Erase
Quad page program
Program/Erase Suspend
PES
75h
0
0
0
suspend program/erase operation
Program/Erase Resume
PER
7Ah
0
0
0
continue program/erase operation
Write Enable
WREN
06h
0
0
0
sets the write enable latch bit
Write Disable
WRDI
04h
0
0
0
resets the write enable latch bit
VWREN
50h
0
0
0
Write enable for volatile SR
SBLK
36h
3
0
0
Individual block lock
Individual Block Unlock
SBULK
39h
3
0
0
Individual block unlock
Read Block Lock Status
RDBLOCK
3Dh
3
0
0
Read individual block lock register
GBLK
7Eh
0
0
0
Whole chip block protect
GBULK
98h
0
0
0
Whole chip block unprotect
Erase Security Registers
ERSCUR
44h
3
0
0
Erase security registers
Program Security Registers
PRSCUR
42h
3
0
1+
Program security registers
Read Security Registers
RDSCUR
48h
3
1
1+
Read value of security register
Protection
Volatile SR Write Enable
Individual Block Lock
Global Block Lock
Global Block Unlock
Security
Puya Semiconductor
Page 24 of 106
P25Q32SH Datasheet
Command set(Standard/Dual/Quad SPI)
Cont’d
Abbr.
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
Read Status Register
RDSR
05h
0
0
1
read out status register
Read Status Register-1
RDSR1
35h
0
0
1
Read out status register-1
Read Configure Register
RDCR
15h
0
0
1
Read out configure register
Write Status Register
WRSR
01h
0
0
1
Write data to status registers
Write Status Register-1
WRSR1
31h
0
0
1
Write data to status registers-1
Write Configure Register
WRCR
11h
0
0
1
Write data to configuration register
Commands
Function
Status Register
Data Buffer
Buffer clear
BFCR
9Eh
0
0
0
Clear all buffer data
Buffer Load
BFLD
9Ah
3
0
0
Load data from main memory to buffer
Buffer Read
BFRD
9Bh
3
1
1+
Read data out from buffer
Buffer Write
BFWR
9Ch
3
0
1+
Write data to buffer
Buffer to Main Memory Page
Program
BFPP
9Dh
3
0
0
Program buffer data to main memory
RSTEN
66h
0
0
0
Enable reset
RST
99h
0
0
0
Reset
Enable QPI
QPIEN
38h
0
0
0
Enable QPI mode
Read Manufacturer/device ID
RDID
9Fh
0
0
1 to 3
Read Manufacture ID
Dual Read Manufacture ID
REMS
DREMS
90h
92h
3
3
1
1+
1+
Quad Read Manufacture ID
QREMS
94h
3
1
1+
DP
B9h
0
0
0
enters deep power-down mode
RDP/RES
ABh
3
0
1
Read electronic ID data
SBL
77h
0
0
0
Set burst length
RDSFDP
5Ah
Read SFDP parameter
FFh
Release from read enhanced
Other Commands
Reset Enable
Reset
Deep Power-down
Release Deep Power-down /
Read Electronic ID
Set burst length
Read SFDP
Release read enhanced
Read unique ID
RUID
4Bh
4
1+
output JEDEC ID: 1-byte manufacturer
ID & 2-byte device ID
Read manufacturer ID/device ID data
Dual output read manufacture/device ID
Quad output read manufacture/device
ID
Read unique ID
Command set (STR QPI Instructions)
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
Fast read
0Bh
3
5/2/3/4
1+
n bytes read out until CS# goes high
Burst Read with Wrap
0Ch
3
5/2/3/4
1+
n bytes burst read with wrap by 4IO
Read Word 4x I/O
EBh
3
5/2/3/4
1+
n bytes read out by 4IO
Page Program
02h
3
0
1+
program selected page
Page Erase
81h
3
0
0
erase selected page
Sector Erase (4K bytes)
20h
3
0
0
erase selected sector
Commands
Abbr.
Function description
Read
Program and Erase
Puya Semiconductor
Page 25 of 106
P25Q32SH Datasheet
Code
ADR
Bytes
DMY
Bytes
Data
Bytes
Block Erase (32K bytes)
52h
3
0
0
erase selected 32K block
Block Erase (64K bytes)
D8h
3
0
0
erase selected 64K block
60h/C7h
0
0
0
erase whole chip
Program/Erase Suspend
75h
0
0
0
suspend program/erase operation
Program/Erase Resume
7Ah
0
0
0
continue program/erase operation
Write Enable
06h
0
0
0
sets the write enable latch bit
Volatile SR Write Enable
50h
0
0
0
Write enable for volatile status register
Write Disable
04h
0
0
0
resets the write enable latch bit
Individual Block Lock
36h
3
0
0
Individual block lock
Individual Block Unlock
39h
3
0
0
Individual block unlock
Read Block Lock Status
3Dh
3
0
0
Read individual block lock register
Global Block Lock
7Eh
0
0
0
Whole chip block protect
Global Block Unlock
98h
0
0
0
Whole chip block unprotect
Read Status Register
05h
0
0
1
read out status register
Read Status Register-1
35h
0
0
1
Read out status register-1
Read Configure Register
15h
0
0
1
Read out configure register
Commands
Abbr.
Chip Erase
Function description
Protection
Status Register
Write Status Register
WRSR
01h
0
0
1
Write data to status registers-0
Write Status Register-1
WRSR1
31h
0
0
1
Write data to status registers-1
Write Configure Register
WRCR
11h
0
0
1
Write data to configuration register
Buffer Clear
9Eh
0
0
0
Clear all buffer data
Buffer Load
9Ah
3
0
0
Load data from memory to buffer
Buffer Read
9Bh
3
1
1+
Read data out from buffer
Buffer Write
9Ch
3
0
1+
Write data to buffer
Buffer to Main Memory
Page Program
9Dh
3
0
0
Program buffer data to main memory
Deep Power-down
B9h
0
0
0
enters deep power-down mode
Release Deep Powerdown/Read Electronic ID
ABh
3
0
1
Read electronic ID data
Set Read Parameters
C0h
0
0
1
Set read dummy and wrap
Read Manufacture ID
90h
3
1+
Read manufacturer ID/device ID data
Read Manufacturer/device
ID
9Fh
0
1 to 3
output JEDEC ID: 1-byte manufacturer
ID & 2-byte device ID
Read SFDP
5Ah
Data Buffer
Other Commands
0
Read SFDP parameter
Disable QPI
FFh
Reset Enable
66h
0
0
0
Enable reset
Reset
99h
0
0
0
Reset
Puya Semiconductor
Release from read enhanced
Page 26 of 106
P25Q32SH Datasheet
Command set(DTR SPI Instructions)
Abbr.
Code
ADR
Bytes
DMY
Cycles
Data
Bytes
DTR Fast Read
DTRFRD
0Dh
3
6
1+
DTR n byte fast read out
DTR 2IO Read
2DTRD
BDh
3
2+4
1+
DTR n byte read out by 2IO
DTR 4IO Read
4DTRD
EDh
3
1+7
1+
DTR n byte read out by 4IO
Code
ADR
Bytes
DMY
Cycles
Data
Bytes
0Eh
3
8
1+
DTR n bytes burst read with wrap by
4IO
Commands
Function description
Command set(DTR QPI Instructions)
Commands
Abbr.
DTR Burst Read with Wrap
Function description
DTR Fast Read
DTRFRD
0Dh
3
8
1+
DTR n byte fast read out
DTR 4IO Read
4DTRD
EDh
3
1+7
1+
DTR n byte fast read out
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3,…..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. Fast Read Quad I/O Data
IO0 = (x, x, x, x, D4, D0,…)
IO1 = (x, x, x, x, D5, D1,…)
IO2 = (x, x, x, x, D6, D2,…)
IO3 = (x, x, x, x, D7, D3,…)
6. Fast Word Read Quad I/O Data
IO0 = (x, x, D4, D0,…)
IO1 = (x, x, D5, D1,…)
IO2 = (x, x, D6, D2,…)
IO3 = (x, x, D7, D3,…)
7. Fast Word Read Quad I/O Data: the lowest address bit must be 0.
8. QPI Command, Address, Data input/output format:
CLK #0 1 2 3 4 5 6 7 8 9 10 11
IO0= C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0,
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P25Q32SH Datasheet
IO1= C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2= C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3= C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
9. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=000100, A9-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=001000, A9-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=001100, A9-A0= Byte Address;
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10.2 Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like
PP, QPP, PE, SE, BE32K, BE, CE, BFPP and WRSR, WRCR, ERSCUR, PRSCUR which are intended to
change the device content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
Figure 10-2 Write Enable (WREN) Sequence (Command 06)
CS#
SCLK
0
1
SI
SO
2
3
4
5
6
7
Command
06H
High-Z
Figure 10-2a Write Enable (WREN) Sequence (QPI)
CS#
0
1
SCLK
Command
06H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
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P25Q32SH Datasheet
10.3 Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes
high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR/WRCR) instruction completion
- Page Program (PP) instruction completion
- Quod Page Program (QPP) instruction completion
- Page Erase (PE) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE32K,BE) instruction completion
- Chip Erase (CE) instruction completion
- Buffer to Main Memory Page Program(BFPP) instruction completion
- Erase Security Register (ERSCUR) instruction completion
- Program Security Register (PRSCUR) instruction completion
- Reset (RST) instruction completion
- Write Enable for Volatile Status Register
Figure 10-3 Write Disable (WRDI) Sequence (Command 04)
CS#
SCLK
0
1
SI
SO
2
3
4
5
6
7
Command
04H
High-Z
Figure 10-3a Write Disable (WRDI) Sequence (QPI)
CS#
0
1
SCLK
Command
04H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
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P25Q32SH Datasheet
10.4 Write Enable for Volatile Status Register
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to change
the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit
write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for Volatile
Status Register command must be issued prior to a Write Status Register command. The Write Enable for
Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
The sequence of issuing Write Enable for Volatile Status Register instruction is: CS# goes low→ sending
Write Enable for Volatile Status Register instruction code→ CS# goes high.
Figure 10-4 Write Enable for Volatile Status Register Sequence (Command 50)
CS#
0
1
2
3
4
5
6
7
SCLK
Command(50H )
SI
SO
High-Z
Figure 10-4a Write Enable for Volatile Status Register Sequence (QPI)
CS#
0
1
SCLK
Command
50H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
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P25Q32SH Datasheet
10.5 Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time
(even in program/erase/write status register condition). It is recommended to check the Write in Progress
(WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress. For command code “05H”, the SO will output Status Register bits S7~S0. The command code
“35H”, the SO will output Status Register bits S15~S8.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status
Register data out on SO. The SIO[3:1] are "don't care".
Figure 10-5 Read Status Register (RDSR) Sequence (Command 05 or 35)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI
05Hor35H
SO
High-Z
S7~S0 or S15~S8 out
7 6
MSB
5
4
3
2
S7~S0 or S15~S8 out
1
0
4
5
7 6
MSB
5
4
3
2
1
0
7
Figure 10-5a Read Status Register (RDSR) Sequence (QPI)
CS#
0
1
2
3
SCLK
Command
05H or 35H
SI(IO0)
4
0
4
0
4
SO(IO1)
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
S7-S0 or S15-S8 out
Status Register
S15
SUS
S14
CMP
S13
LB3
S12
LB2
S11
LB1
S10
EP_FAIL
S9
QE
S8
SRP1
S7
SRP0
S6
BP4
S5
BP3
S4
BP2
S3
BP1
S2
BP0
S1
WEL
S0
WIP
The definition of the status register bits is as below:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
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WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command is accepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status
Register (WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the
relevant memory area (as defined in Table “Protected Area Sizes”).becomes protected against Page Program
(PP), Page Erase (PE), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3,
BP2, BP1, and BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) command is executed, only if the Block Protect (BP4, BP3, BP2, BP1and BP0) are set to
“None protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply lockdown or one time programmable protection
SRP1
SRP0
WP#
Status Register
0
0
x
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
x
1
1
x
Power Supply LockDown(1)
One Time Program(2)
Description
The Status Register and Configure Register can be
written to after a Write Enable command,
WP#=0,
the Status Register and Configure Register
WEL=1.(Default)
locked and cannot be written to.
WP#=1, the Status Register and Configure Register is
unlocked and can be written to after a Write Enable
command,
WEL=1.
Status
Register
and Configure Register are protected
and cannot be written to again until the next PowerDown, Register
Power-Upand
cycle.
Status
Configure Register are permanently
protected and cannot be written to.
NOTE:
1. When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact PUYA for details.
QE bit.
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation.
When the QE bit is set to 1 (Default) the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set
to 1 during standard SPI or Dual SPI operation if the WP# or HOLD# pins are tied directly to the power supply
or ground),When the QE pin is set to 0, the WP# pin and HOLD# pin are enable.
EP_FAIL bit.
The Erase/Program Fail bit is a read only bit which shows the status of the last Program/Erase operation. The
bit will be set to "1" if the program/erase operation failed or interrupted by reset or the program/erase region
was protected. It will be automatically cleared to "0" if the next program/erase operation succeeds. Please
note that it will not interrupt or stop any operation in the flash memory.
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that
provide the write protect control and status to the Security Registers. The default state of LB3-LB1are0, the
security registers are unlocked. The LB3-LB1bitscan be set to 1 individually using the Write Register
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P25Q32SH Datasheet
instruction. The LB3-LB1bits are One Time Programmable, once its set to 1, the Security Registers will
become read-only permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4-BP0
bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details.
The default setting is CMP=0.
SUS bit
The SUS bit is read only bit in the status register (S15) that is set to 1 after executing an Program/Erase
Suspend (75H) command. The SUS bit is cleared to 0 by Program/Erase Resume (7AH) command as well as
a power-down, power-up cycle.
10.6 Read Configure Register (RDCR)
The RDCR instruction is for reading Configure Register Bits. The Read Configure Register can be read at any
time (even in program/erase/write status register condition). It is recommended to check the Write in Progress
(WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress.
The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Configure
Register data out on SO. The SIO[3:1] are "don't care".
Figure 10-6 Read Status Register (RDCR) Sequence (Command 15)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI
15H
High-Z
SO
Configure Register Out
7 6
MSB
5
4
3
2
Configure Register Out
1
0
4
5
7 6
MSB
5
4
3
2
1
0
7
Figure 10-6a Read Status Register (RDCR) Sequence (QPI)
CS#
0
1
2
3
SCLK
Command
15H
SI(IO0)
4
0
4
0
4
SO(IO1)
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
C7-C0 out
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P25Q32SH Datasheet
Configure Register
Bit7
HOLD/RST
Bit6
DRV1
Bit5
DRV0
Bit4
MPM1
Bit3
MPM0
Bit2
WPS
Bit1
DC
Bit0
DLP
HOLD/RST bit.
The HOLD/RST bit is a non-volatile Read/Write bit in the Configure Register which is used to determine
whether /HOLD or /RESET function should be implemented on the hardware pin for 8-pin packages. When
HOLD/RST=0 (factory default), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET. However,
/HOLD or /RESET functions are only available when QE=0. If QE is set to 1, the /HOLD and /RESET functions
are disabled, the pin acts as a dedicated data I/O pin.
DRV1 & DRV0 bit.
The DRV1 & DRV0 bits are non-volatile Read/Write bits which are used to determine the output driver
strength for the Read operations.
This feature is available on special order. Please contact PUYA for details.
DRV1,DRV0
Drive Strength
0,0 (default)
60%
0,1
100%
1,0
140%
1,1
40%
MPM1 & MPM0 bit.
The Multi Page Mode(MPM) bits are volatile Read/Write bits which allows Quad/Dual Page operation.
MPM1,MPM0
Page Size
0,0 (default)
256byte
0,1
512byte
1,0
1024byte
1,1
reserved
The page size is defined by MPM bits as above table. When the MPM bits are set to (0,0) (Default) the page
size is 256bytes. When the MPM bits are set to (0,1), the page size is 512bytes. When the MPM bits are set to
(1,0), the page size is 1024bytes.
This bit controls the page programming buffer address wrap point. Legacy SPI devices generally have used a
256 Byte page programming buffer and defined that if data is loaded into the buffer beyond the 255 Byte
locations, the address at which additional bytes are loaded would be wrapped to address zero of the buffer.
The P25Q32SH provides a 512/1024 Byte page programming buffer that can increase programming
performance. For legacy software compatibility, this configuration bit provides the option to continue the
wrapping behavior at the 256 Byte boundary or to enable full use of the available 512/1024 Byte buffer by not
wrapping the load address at the 256 Byte boundary. When the MPM bits are set to (0,1), the page erase
instruction (81h) will erase the data of the chosen Dual Page to be "1". When the MPM bits are set to (1,0),
the page erase instruction (81h) will erase the data of the chosen Quad Page to be "1".
WPS bit.
The WPS bit is a non-volatile Read/Write bit in the Configure Register which is used to select which Write
Protect scheme should be used. When WPS=0(default), the device will use the combination of CMP, BP[4:0]
bits to protect a specific area of the memory array. When WPS=1, the device will utilize the Individual Block
Locks to protect any individual sector or blocks. The default value for all Individual Block Lock bits is 1 upon
device power on or after reset.
DC bit
The Dummy Cycle (DC) bit is a volatile bit. The Dummy Cycle (DC) bit can be used to configure the number of
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P25Q32SH Datasheet
dummy clocks for “SPI 2 X IO Read (BBH)” command, “SPI 4X I/O Read (EBH)” command.
Table Dummy Cycle Table
DC1
SPI
command
BB SPI
EB SPI
0(default)
1
0(default)
1
Number of dummy
cycles 4
8
6
10
Max Read Freq.
104MHz
120MHz
104MHz
120MHz
DLP bit.
The DLP bit is Data Learning Pattern Enable bit, which is volatile writable by 11H command. For DTR Read
commands, a pre-defined “Data Learning Pattern” can be used by the flash memory controller to determine
the flash data output timing on I/O pins. When DLP=1, in dummy cycles, the flash will output “00110100” Data
Learning Pattern sequence on each of the I/O pins . During this period, controller can fine tune the data
latching timing for each I/O pins to achieve optimum system performance. DLP=0(default) will disable the
Data Learning Pattern output.
10.7 Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. For
command code "01H", the new values will be written to the status register0(S7~S0). For command code
"31H", the new values will be written to the status register1(S15~S8).Before it can be accepted, a Write
Enable (WREN) command must previously have been executed. After the Write Enable (WREN) command
has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the
CMP and QE and SRP1 bits will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status
Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle
is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect
(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is
entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status
Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits data boundary; otherwise, the instruction will be rejected and not
executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in
progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed,
and the Write Enable Latch (WEL) bit is reset.
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P25Q32SH Datasheet
Figure 10-7 Write Status Register (WRSR) Sequence (Command 01 or 31)
CS#
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
SCLK
Command
Status Register0/1 in
01 H or 31H
SI
7
6
5
MSB
4
3
2
1
0
High-Z
SO
Figure 10-7a Write Status Register (WRSR) Sequence (QPI)
CS#
0
1
2
3
SCLK
Command
01H or 31H
SI(IO0)
4
0
SO(IO1)
5
1
WP#(IO2)
6
2
HOLD#(IO3)
7
3
Status Register0/1
10.8 Write Configure Register (WRCR)
The Write Configure Register (WRCR) command allows new values to be written to the Configure Register.
Before it can be accepted, a Write Enable (WREN) command must previously have been executed. After the
Write Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch
(WEL).
The sequence of issuing WRCR instruction is: CS# goes low→ sending WRCR instruction code→ Configure
Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits data boundary; otherwise, the instruction will be rejected and not
executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress.
The WIP sets 1 during the tW timing, and sets 0 when Write Configure Register Cycle is completed, and the
Write Enable Latch (WEL) bit is reset.
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P25Q32SH Datasheet
Figure 10-9 Write Configure Register (WRCR) Sequence (Command 11)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
Configure Register in
11H
7
6
5
MSB
4
3
2
0
1
High - Z
SO
Figure 10-9a Write Configure Register (WRCR) Sequence (QPI)
CS#
0
1
2
3
SCLK
Command
11H
SI(IO0)
4
0
SO(IO1)
5
1
WP#(IO2)
6
2
HOLD#(IO3)
7
3
Configure Register in
10.9 Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The
address is automatically increased to the next higher address after each byte data is shifted out, so the whole
memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest
address has been reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte
address on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 10-10 Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
SO
03H
High - Z
24 - bit address
23 22 21
3
2
1
0
Data Out1
MSB
MSB
Puya Semiconductor
7
6
5
4
3
2
Data Out2
1
0
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P25Q32SH Datasheet
10.10 Fast Read (FREAD)
The FAST READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK,
and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte
can be at any location. The address is automatically increased to the next higher address after each byte data
is shifted out, so the whole memory can be read out at a single FREAD instruction. The address counter rolls
over to 0 when the highest address has been reached.
The sequence of issuing FREAD instruction is: CS# goes low→ sending FREAD instruction code→3-byte
address on SI→ 1-dummy byte address on SI→data out on SO→ to end FREAD operation can use CS# to
high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-10 Fast Read (FREAD) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
0BH
23 22
21
3
2
1
0
High - Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Fast Read in QPI mode
The Fast Read command is also supported in QPI mode. In QPI mode, the number of dummy clocks is
configured by the “Set Read Parameters (C0H)” command to accommodate a wide range application with
different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the
Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4/6/8.
Figure 10-10a Fast Read Sequence (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
SCLK
Command
0BH
A23-16
A15-8
A7-0
IO switch from
input to output
Dummy*
SI(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
7
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
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Byte1
Byte2
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P25Q32SH Datasheet
10.11 DTR Fast Read(DTR_FREAD)
The DTR Fast Read instruction is similar to the Fast Read instruction except that the 24-bit address input and
the data output require DTR (Double Transfer Rate) operation. This is accomplished by adding six “dummy”
clocks after the 24-bit address. The dummy clocks allow the devices internal circuits additional time for setting
up the initial address. During the dummy clocks the data value on the DO pin is a “don’t care”.
Figure 10-11 DTR Fast Read Sequence (Command 0D)
CS#
0
1
2
3
4
5
6
7
8
9
10
17
18
19
SCLK
24- Bit Address
Command
0DH
SI
23 22 21 20 19 18
5
4
3
2
1
0
High Impedance
SO
CS#
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
SCLK
SI
0
6 Dummy Clocks
Data Out 1
SO
Data Out 2
Data Out 3
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DTR Fast Read in QPI Mode
The DTR Fast Read instruction is also supported in QPI mode.
Figure 10-11a DTR Fast Read Sequence (QPI)
CS#
0
1
2
3
4
A23-16
A15-8
A7-0
5
11
12
13
14
SCLK
Command
0Dh
Ios switch from
input to output
8 Dummy Clocks
SI(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
7
Byte1
Puya Semiconductor
Byte2
Byte3
Page 40 of 106
P25Q32SH Datasheet
10.12 Dual Read (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of
SCLK at a maximum frequency fT. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out
at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been
reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte
address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-12 Dual Read Mode Sequence (Command 3B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
24- bit address
3BH
23 22 21
3
2
1
0
High - Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
Puya Semiconductor
6
4
2
0
6
4
2
0
6
Data Out1
Data Out2
7 5 3 1 7 5 3 1
MSB
MSB
7
Page 41 of 106
P25Q32SH Datasheet
10.13 2IO Read (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is
latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling
edge of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole memory
can be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address
has been reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 8-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-13 2IO Read Sequence (Command BB M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
BBH
6
SO(IO1)
7
4
2
0
6
5
3
1
7
A23-16
4
2
0
6
5
3
1
7
A15-8
4
2
0
5
3
1
A7-0
6
4
2
0
7
5
3
1
M7-0/dummy
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
Note:
1. M[5-4] = (1,0) is inhibited.
2. DC bit can set the number of dummy clocks.
Puya Semiconductor
Page 42 of 106
P25Q32SH Datasheet
2IO Continuous Read
“BBh” command supports 2IO Continuous Read which can further reduce command overhead through setting
the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next 2IO Read command (after CS# is raised and then lowered) does not
require the BBH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Figure 10-13a 2IO Continue Read ( M5-4 = (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Command
SI(IO0)
BBH
SO(IO1)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
A23-16
A15-8
A7-0
M7-0/dummy
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte1
Byte2
Byte3
Byte4
CS#
0
1
2
3
4
5
6
7
8
SI(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
A23-16
A15-8
A7-0
M7-0/dummy
Byte1
Byte2
Note:
1. 2IO Continue Read, if M5-4 = 1, 0. If not using Continue Read recommend to set M5-4 ≠ 1, 0.
2. DC bit can set the number of dummy clocks.
10.14 DTR 2IO Read (DTR_2READ)
The DTR 2IO Read (BDh) instruction allows for improved random access while maintaining two IO pins, IO0
and IO1. It is similar to the DREAD (3Bh) instruction but with the capability to input the Address bits (A23-0)
two bits per clock. This reduced instruction overhead may allow for code execution (XIP) directly from the Dual
SPI in some applications.
Puya Semiconductor
Page 43 of 106
P25Q32SH Datasheet
Figure 10-14 DTR 2IO Read Sequence (Command BD M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
A23-16
BDH
SI
SO
10
A15-8
A7-0
M7-0
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
CS#
15
16
17
18
19
20
21
22
23
24
25
26
27
SCLK
Ios switch from
input to output
SI
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte 1
Byte 3
Byte 2
Byte 4
DTR 2IO Continuous Read
The BDh instruction supports Continuous Read Mode which can further reduce overhead through setting the
"continuous Read Mode" bits(M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode”
bits (M5-4) = (1, 0), then the next Read command (after CS# is raised and then lowered) does not require the
BDH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BDH
command code, thus returning to normal operation. It is recommended to input FFFFh on IO0 for the next
instruction (16 clocks), to ensure M4 = 1 and return the device to normal operation.
Figure 10-14a DTR 2IO Continuous Read Sequence (Command BD M5-4 = (1,0))
CS#
0
91
2
3
4
5
6
7
SCLK
A23-16
A15-8
10
A7-0
M7-0
SI
22
20
18
16
14
12
10
8
6
4
2
0
6
4
2
0
SO
23
21
19
17
15
13
11
9
7
5
3
1
7
5
3
1
CS#
7
8
9
10
11
12
13
14
15
16
17
18
19
SCLK
Ios switch from
input to output
SI
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
SO
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
Byte 1
Puya Semiconductor
Byte 2
Byte 3
Byte 4
Page 44 of 106
P25Q32SH Datasheet
10.15 Quad Read (QREAD)
The QREAD instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the QREAD instruction. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing QREAD instruction is: CS# goes low→ sending QREAD instruction → 3-byte
address on SI → 8-bit dummy cycle → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QREAD
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-15 Quad Read Sequence (Command 6B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
SI(IO0)
24-Bit address
6BH
23
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
22 21
3
2
1
0
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0)
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
HOLD#(IO3)
Byte1
Puya Semiconductor
Byte2
Byte3
Byte4
Page 45 of 106
P25Q32SH Datasheet
10.16 4IO Read (4READ)
The 4READ instruction enable quad throughput of Serial NOR Flash in read mode. A Quad Enable (QE) bit of
status Register must be set to "1" before sending the 4READ instruction. The address is latched on rising
edge of SCLK, and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a
maximum frequency fQ. The first address byte can be at any location. The address is automatically increased
to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once
writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address
interleave on SIO3, SIO2, SIO1 & SIO0→2+4 dummy cycles→data out interleave on SIO3, SIO2, SIO1 &
SIO0→ to end 4READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 10-16 4IO Read Sequence (Command EB M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
EBH
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1
Byte2
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. M[5-4] = (1,0) is inhibited.
3. DC bit can set the number of dummy clocks.
Puya Semiconductor
Page 46 of 106
P25Q32SH Datasheet
4IO Read in QPI mode
The 4READ instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy
clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of
applications with different needs for either maximum Fast Read frequency or minimum data access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as
either 10, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 10. In
QPI mode, the “Continuous Read Mode” bits M7- 0 are also considered as dummy clocks. In the default
setting, the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for 4IO Read instruction. Please refer to the
description on next pages.
“Wrap Around” feature is not available in QPI mode for 4IO Read instruction. To perform a read operation with
fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must be
used.
Figure 10-16a 4IO Read in QPI mode Sequence (QPI M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
SCLK
Command
EBH A23-16
IO switch from
input to output
Dummy*
A15-8
A7-0
M7-0
SI(IO0)
20
16
12
8
4
0
4
0
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
7
3
7
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
Byte1
Byte2
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. M[5-4] = (1,0) is inhibited.
4IO Continuous Read
“EBh” command supports 4IO Continuous Read which can further reduce command overhead through setting
the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read
Mode” bits (M5-4) = (1, 0), then the next 4IO Read command (after CS# is raised and then lowered) does not
require the EBH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first EBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Puya Semiconductor
Page 47 of 106
P25Q32SH Datasheet
Figure 10-16b 4IO Continuous Read Sequence ( M5-4 = (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
EBH
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1
Byte2
CS#
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
8
9
10 11 12 13 14 15
SCLK
A23-16 A15-8 A7-0
M7-0
Dummy
Byte1
Byte2
Note:
1. 4IO Continuous Read Mode, if M5-4 = 1, 0. If not using Continuous Read recommend to set M5-4 ≠ 1, 0.
2. DC bit can set the number of dummy clocks.
10.17 Set Burst Read
The Set Burst with Wrap command is used in conjunction with “4IO Read” command to access a fixed length
of 8/16/32/64-byte section within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap command sequence: CS# goes low → Send Set Burst with Wrap command → Send
24 dummy bits→ Send 8 bits “Wrap bits” → CS# goes high.
W6,W5
W4=0
W4=1 (default)
Wrap Aroud
Wrap Length
Wrap Aroud
Wrap Length
0,0
Yes
8-byte
No
N/A
0,1
Yes
16-byte
No
N/A
1,0
Yes
32-byte
No
N/A
1,1
Yes
64-byte
No
N/A
If the W6-W4 bits are set by the Set Burst with Wrap command, all the following “4IO Read” command will use
the W6-W4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function
and return to normal read operation, another Set Burst with Wrap command should be issued to set W4=1.
Puya Semiconductor
Page 48 of 106
P25Q32SH Datasheet
Figure 10-17 Set Burst Read (SBL) Sequence (Command 77)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
Command
SI(IO0)
77H
X
X
X
X
X
X
4
X
SO(IO1)
X
X
X
X
X
X
5
X
WP#(IO2)
X
X
X
X
X
X
6
X
HOLD#(IO3)
X
X
X
X
X
X
X
X
W6-W4
10.18 DTR 4IO Read (DTR_4READ)
The DTR 4IO Read (EDh) instruction is similar to the DTR 2IO Read (BDh) instruction, except that address
and data bits are input and output through four pins IO0, IO1, IO2 and IO3, and 1 byte “Continuous Read
Mode” data(M7-0) and 7 Dummy clocks are required in SPI mode prior to the data output. The Quad I/O
dramatically reduces instruction overhead allowing faster random access for code execution (XIP) directly
from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable the DTR 4IO Read
Instruction.
Figure 10-18 DTR 4IO Read Mode Sequence (Command ED M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
19
17 18
20
SCLK
4
0
4
0
4
0
4
0
IO switch from
input to output
4 0 4 0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
Command
SI(IO0)
EDH
A23-16 A15-8
A7-0
M7-0
7Dummy
clocks
4
Byte 1 Byte2
Note: 1. Hi-impedance is inhibited for the mode clock cycles. 2. M[5-4] = (1,0) is inhibited.
DTR 4IO Continuous Read
The DTR 4IO Read instruction can further reduce instruction overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input Address bits (A23/A31-0). The upper nibble of the (M7-4) controls the length
of the next DTR 4IO Read instruction through the inclusion or exclusion of the first byte instruction code. The
lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the
falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next DTR 4IO Read instruction (after /CS is raised
and then lowered) does not require the EDh instruction code. This reduces the instruction sequence by eight
clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous
Puya Semiconductor
Page 49 of 106
P25Q32SH Datasheet
Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is raised and then lowered)
requires the first byte instruction code, thus returning to normal operation. It is recommended to input FFh on
IO0 for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.
Figure 10-18a DTR 4IO Continuous Read Mode Sequence (Command ED M5-4 = (1,0))
CS#
0
1
2
3
4
10
12
11
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
IO switch from
input to output
4 0 4 0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0
7Dummy
clocks
Byte 1 Byte2
4
Byte3
Note: 1. Hi-impedance is inhibited for the mode clock cycles.
2. DTR 4IO Continuous Read Mode, if M5-4 = 1, 0. If not using Continuous Read recommend to set M54 ≠ 1, 0.
DTR 4IO Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The DTR 4IO Read instruction can also be used to access a specific portion within a page by issuing a “Set
Burst Read” (77h) command prior to EDh. The “Set Burst Read” (77h) command can either enable or disable
the “Wrap Around” feature for the following EDh commands. When “Wrap Around” is enabled, the data being
accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at
the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to
terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst Read” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or
disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page.
DTR 4IO Read (EDh) in QPI Mode
The DTR 4IO Read instruction is also supported in QPI mode. In QPI mode, the “Continuous Read Mode” bits
M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous
Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.
“Wrap Around” feature is not available in QPI mode for DTR 4IO Read instruction. To perform a read operation
with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch) instruction must
be used.
Puya Semiconductor
Page 50 of 106
P25Q32SH Datasheet
Figure 10-18b DTR 4IO Read Mode Sequence (QPI ED M5-4 ≠ (1,0))
CS#
0
1
2
3
5
4
6
12
14
13
SCLK
Command
SI(IO0)
4
0
4
0
4
0
4
0
IO switch from
input to output
4 0 4 0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
EDH
A23-16 A15-8 A7-0
7Dummy
clocks
M7-0
4
Byte3
Byte 1 Byte2
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. M[5-4] = (1,0) is inhibited.
10.19 4IO Word Read(E7h)
The 4IO Word Read command is similar to the 4 IO Read command except that the lowest address bit (A0)
must equal 0 and only 2-dummy clock. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The Quad Enable
bit (QE) of Status Register (S9) must be set to enable for the 4IO Word read command.
Figure 10-19 4IO Word Read Sequence ( M5-4 ≠ (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21
SCLK
Command
SI(IO0)
E7H
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0 Dummy Byte1
Byte2
4IO Word Read with “Continuous Read Mode”
The 4IO Word Read command can further reduce command overhead through setting the “Continuous Read
Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4) = (1, 0),
then the next 4IO Word Read command (after CS# is raised and then lowered) does not require the E7H
command code. If the “Continuous Read Mode” bits (M5-4) do not equal to (1, 0), the next command requires
the first E7H command code, thus returning to normal operation. A “Continuous Read Mode” Reset command
can be used to reset (M5-4) before issuing normal command.
Puya Semiconductor
Page 51 of 106
P25Q32SH Datasheet
Figure 10-19a 4IO Word Read Sequence ( M5-4 = (1,0) )
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21
SCLK
Command
SI(IO0)
E7H
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
A23-16 A15-8 A7-0
M7-0 Dummy Byte1
Byte2
CS#
0
1
2
3
4
5
6
7
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
8
9
10 11 12 13
SCLK
A23-16 A15-8 A7-0
M7-0 Dummy Byte1
Byte2
4IO Word Read with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The 4IO Word Read command can be used to access a specific portion within a page by issuing “Set Burst
with Wrap”(77H) commands prior to E7H. The “Set Burst with Wrap”(77H) command can either enable or
disable the “Wrap Around” feature for the following E7H commands. When “Wrap Around” is enabled, the data
being accessed can be limited to either an8/16/32/64-byte section of a 256-byte page. The output data starts
at the initial address specified in the command, once it reaches the ending boundary of the 8/16/32/64-byte
section, the output will wrap around the beginning boundary automatically until CS# is pulled high to terminate
the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill
the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read commands.
The “Set Burst with Wrap” command allows three “Wrap Bits”W6-W4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-W5 is used to specify the length of the wrap around section
within a page.
Puya Semiconductor
Page 52 of 106
P25Q32SH Datasheet
10.20 Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to configure
the number of dummy clocks for “Fast Read (0Bh)”, “4IO Read (EBh)” , “Burst Read with Wrap (0Ch)” , “Buffer
Read (9Bh)” & “Read SFDP Mode (5Ah)” instructions, and to configure the number of bytes of “Wrap Length”
for the “Burst Read with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks for
various Fast Read instructions in Dual/Quad SPI mode are configured by DC bit. The “Wrap Length” is set by
W5-4 bit in the “Set Burst with Wrap (77h)” instruction. This setting will remain unchanged when the device is
switched from Standard SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy
clocks is 10 which includes “Continuous Read Mode” byte M7-0. The number of dummy clocks is only
programmable for “Fast Read (0Bh)”, “4IO Read (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the
QPI mode. Whenever the device is switched from SPI mode to QPI mode, the number of dummy clocks
should be set again, prior to any 0Bh, EBh or 0Ch instructions.
P5-P4
Dummy Clocks
0,0
0,1
1,0
1,1
10
4
6
8
Maximum Read
Freq.
133MHz
80MHz
104MHz
120MHz
P1-P0
Wrap Length
0,0
0,1
1,0
1,1
8-byte
16-byte
32-byte
64-byte
Figure 10-20 Set Read Parameters Sequence ( QPI )
CS#
0
1
2
3
SCLK
Command
C0H
SI(IO0)
P4
P0
SO(IO1)
P5
P1
P6
P2
P7
P3
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Read
Parameter
Page 53 of 106
P25Q32SH Datasheet
10.21 Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0CH)” command provides an alternative way to perform the read operation with
“Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode,
except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap
Around” once the ending boundary is reached. The “Wrap Length” and the number of dummy clocks can be
configured by the “Set Read Parameters (C0H)” command.
Figure 10-21 Burst Read with Wrap Sequence ( QPI )
CS#
0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
SCLK
Command
0CH A23-16
A15-8
A7-0
IO switch from
input to output
Dummy*
SI(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
7
Byte1
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
Byte2
10.22 DTR Burst Read with Wrap (0Eh)
The “DTR Burst Read with Wrap (0EH)” command provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. This command is similar to the “Fast Read (0BH)” command in QPI mode,
except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap
Around” once the ending boundary is reached. The “Wrap Length” can be configured by the “Set Read
Parameters (C0H)” command.
Figure 10-22 Burst Read with Wrap Sequence ( QPI )
CS#
0
1
2
3
5
4
6
12
14
13
SCLK
Command
SI(IO0)
4
0
4
0
4
0
IO switch from
input to output
4 0 4 0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
0Eh
A23-16 A15-8 A7-0
Puya Semiconductor
Dummy
clocks
Byte 1 Byte2
4
Byte3
Page 54 of 106
P25Q32SH Datasheet
10.23 Data Learning Pattern
The data learning pattern supports system/memory controller determine valid window of data output more
easily and improve data capture reliability while the flash memory is running in high frequency.
Data learning pattern can be enabled or disabled by setting the bit0 of Configure Register(data learning
pattern enable bit). Once the DLP bit is set, the data learning pattern is inputted into dummy cycles.
Enabling data learning pattern bit(DLP bit) will not affect the function of continue read mode bit. In dummy
cycles, continuous mode bit still operates with the same function. Data learning pattern will output after
continuous mode bit.
The data learning pattern is a fixed 8-bit data pattern (00110100). For STR(single transfer rate) instructions,
the complete 8 bits will start to output right after the continuous mode bit. While dummy cycle is not sufficient
of 8 cycles, the rest of the DLP bits will be cut. For DTR(double transfer rate) instructions, the complete 8 bits
will start to output during the last 4 dummy cycle.
Figure 10-23 Fast Read with DLP bits output Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24- bit address
23 22 21
0BH
3
2
1
0
High- Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
48 49
SCLK
Dummy Cycles
SI
Data Out1
DLP Bits Output
SO
7
6
5
4
3
2
1
0
7 6
MSB
5
4
8
9 10
3
Data Out2
2
1
0
7 6
MSB
5
Figure 10-23a Dual Read with DLP bits output Sequence
CS#
0
1
2
3
4
5
6
7
28 29 30 31
SCLK
Command
SI
24- bit address
3BH
23 22 21
3
2
1
0
High- Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Cycles
SI
SO
Puya Semiconductor
7
7
6
6
5 4 3 2 1
DLP Bits Output
0
5 4 3 2 1
DLP Bits Output
0
6
4
2
0
Data Out1
7 5
MSB
3
6
4
2
0
6
1
7
Data Out2
1
7 5
MSB
3
Page 55 of 106
P25Q32SH Datasheet
Figure 10-23b Quad Read with DLP bits output Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
SI(IO0)
24-Bit address
6BH
23
SO(IO1)
High-Z
WP#(IO2)
High-Z
HOLD#(IO3)
High-Z
22 21
3
2
1
0
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
7
6
5
4
3
2
1
0
4
0
4
0
4
0
4
0
4
7
6
5
4
3
2
1
0
5
1
5
1
5
1
5
1
5
7
6
5
4
3
2
1
0
6
2
6
2
6
2
6
2
6
7
6
5 4 3 2 1
DLP Bits Output
0
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Byte4
Figure 10-23b 4IO Read and Burst Read with DLP bits output Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Dummy Cycles
Command
SI(IO0)
4
0
4
0
4
0
4
0
7
6
5
4
4
0
4
0
4
5
1
5
1
5
1
5
1
7
6
5
4
5
1
5
1
5
WP#(IO2)
6
2
6
2
6
2
6
2
7
6
5
4
6
2
6
2
6
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
6
5
4
7
3
7
3
7
SO(IO1)
EBH or 0CH
A23-16 A15-8 A7-0
Puya Semiconductor
M7-0 DLP Bits Output Byte 1 Byte 2
Page 56 of 106
P25Q32SH Datasheet
Figure 10-23c 4IO Read and Burst Read with DLP bits output Sequence in QPI mode
CS#
0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
SCLK
Command
IO switch from
input to output
A23-16
A15-8
A7-0
Dummy*
M7-0
SI(IO0)
20
16
12
8
4
0
4
0
7
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
7
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
7
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
7
3
7
3
7
EBH or 0CH
DLP data out
from MSB
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
Byte1
Byte2
Figure 10-23c DTR 4IO Read with DLP bits output Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
11
SCLK
Command
SI( IO0)
EDH
4
0
4
0
4
0
4
0
SO( IO1)
5
1
5
1
5
1
5
1
WP#( IO2)
6
2
6
2
6
2
6
2
HOLD#( IO3)
7
3
7
3
7
3
7
3
A23- 16 A15-8
A7-0
M7-0
CS#
12
13
14
15
16
17
19
18
20
SCLK
Dummy Cycles
SI( IO0)
7
6
5
4
3
2
1
0
4
0
4
0
4
SO( IO1)
7
6
5
4
3
2
1
0
5
1
5
1
5
WP#( IO2)
7
6
5
4
3
2
1
0
6
2
6
2
6
HOLD#( IO3)
7
6
5
4
3
2
1
0
7
3
7
3
7
DLP Bits Output
Puya Semiconductor
Byte1
Byte2
Page 57 of 106
P25Q32SH Datasheet
10.24 Enable QPI (38H)
The device support both Standard/Dual/Quad SPI and QPI mode. The “Enable QPI (38H)” command can
switch the device from SPI mode to QPI mode. See the command Table 2a for all support QPI commands. In
order to switch the device to QPI mode, the Quad Enable (QE) bit in Status Register-1 must be set to 1 first,
and “Enable QPI (38H)” command must be issued. If the QE bit is 0, the “Enable QPI (38H)” command will be
ignored and the device will remain in SPI mode. When the device is switched from SPI mode to QPI mode,
the existing Write Enable Latch and Program/Erase Suspend status, and the Wrap Length setting will remain
unchanged.
Figure 10-24 Enable QPI Sequence (38H )
CS#
SCLK
SI(IO0)
38H
10.25 Disable QPI (FFH)
To exit the QPI mode and return to Standard/Dual/Quad SPI mode, the “Disable QPI (FFH)” command must
be issued. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure 10-25 Disable QPI Sequence (QPI )
CS#
0
1
SCLK
Command
FFH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Page 58 of 106
P25Q32SH Datasheet
10.26 Page Erase (PE)
The Page Erase (PE) instruction is for erasing the data of the chosen Page to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE).
To perform a Page Erase with the standard page size (256 bytes), an instruction of 81h must be clocked into
the device followed by three address bytes comprised of 2 page address bytes that specify the page in the
main memory to be erased, and 1 dummy byte.
The sequence of issuing PE instruction is: CS# goes low → sending PE instruction code→ 3-byte address on
SI → CS# goes high.
Figure 10-26 Page Erase Sequence (Command 81)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
81H
23 22
MSB
2
1
6
7
0
Figure 10-26a Page Erase Sequence (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
81H
Puya Semiconductor
A23-16
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 59 of 106
P25Q32SH Datasheet
10.27 Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable
(WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase
(SE). Any address of the sector is a valid address for Sector Erase (SE) instruction. The CS# must go high
exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will
be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on
SI → CS# goes high. The SIO[3:1] are don't care.
Figure 10-27 Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
20H
23 22
MSB
2
1
0
Figure 10-27a Sector Erase (SE) Sequence (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
20H
A23-16
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write
in progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1
during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL)
bit is reset. If the sector is protected by BP4, BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will
not be executed on the sector.
Puya Semiconductor
Page 60 of 106
P25Q32SH Datasheet
10.28 Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is
used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the
Write Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block is a valid
address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least
significant bit of address byte has been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high. The SIO[3:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The
Write in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets
during the tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch
(WEL) bit is cleared. If the block is protected by BP4, BP3, BP2, BP1,BP0 bits, the array data will be protected
(no change) and the WEL bit still be reset.
Figure 10-28 Block Erase 32K(BE32K)
Sequence (Command 52 )
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
52H
Figure 10-28a Block Erase 32K(BE32K)
23 22
MSB
2
1
0
Sequence (QPI )
CS#
0
1
2
3
4
5
6
7
SCLK
Command
52H
Puya Semiconductor
A23-16
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 61 of 106
P25Q32SH Datasheet
10.29 Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used
for 64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable
Latch (WEL) bit before sending the Block Erase (BE). Any address of the block is a valid address for Block
Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte
been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on
SI→CS# goes high. The SIO[3:1] are "don't care".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP4, BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed
on the block.
Figure 10-29 Block Erase (BE)
Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
D8H
Figure 10-29a Block Erase (BE)
23 22
MSB
2
1
6
7
0
Sequence (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
D8H A23-16
Puya Semiconductor
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 62 of 106
P25Q32SH Datasheet
10.30 Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise,
the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the chip is protected by BP4,BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It
will be only executed when all Block Protect(BP4, BP3, BP2, BP1, BP0) are set to “None protected”.
Figure 10-30 Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
60H or C7H
Figure 10-30a Chip Erase (CE) Sequence (QPI)
CS#
0
1
SCLK
Command
C7H or 60H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
10.31 Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP).
The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to
be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page are
programmed from the start address of the same page (from the address A7-A0 are all 0). If more than 256
bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous
data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed at the
requested address of the page.
For the very best performance, programming should be done in full pages of 256 bytes aligned on 256 byte
boundaries with each Page being programmed only once. Using the Page Program (PP) command to load an
entire page, within the page boundary, will save overall programming time versus loading less than a page
Puya Semiconductor
Page 63 of 106
P25Q32SH Datasheet
into the program buffer.
It is possible to program from one byte up to a page size in each Page programming operation. Please refer to
the P25Q serial flash application note for multiple byte program operation within one page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not
be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1
during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL)
bit is reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will
not be executed. The SIO[3:1] are "don't care".
Figure 10-31 Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
24- bit address
02H
23 22 21
3
Data Byte 1
2
1 0
MSB
7
6
5
4
3
2
1
0
MSB
2078
2079
2077
2076
2075
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2073
2072
CS#
1
0
SCLK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0 7
MSB
6
5
4
3
2
Data Byte 256
1
0
MSB
7
6
5
4
3
2
MSB
Figure 10-31a Page Program (PP) Sequence (QPI)
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
519
2
518
1
517
0
516
CS#
SCLK
Command
02H
A23-16 A15-8 A7-0
Byte1
Byte2
Byte256
SI(IO0)
A20 A16 A12 A8 A4
A0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
A21 A17 A13 A9 A5
A1
5
1
5
1
5
1
5
1
5
0
5
1
5
1
WP#(IO2)
A22 A18 A14 A10 A6 A2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
A23 A19 A15 A11 A7 A3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
MSB
Puya Semiconductor
Page 64 of 106
P25Q32SH Datasheet
10.32 Quad Page Program (QPP)
The Quad Page Program (QPP) instruction is for programming the memory to be "0". A Write Enable
(WREN)instruction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be
set to "1" before sending the Quad Page Program (QPP). The Quad Page Programming takes four pins:
SIO0, SIO1, SIO2, and SIO3 as data input, which can improve programmer performance and the
effectiveness of application. The QPP operation frequency supports as fast as fQPP. The other function
descriptions are as same as standard page program.
The sequence of issuing QPP instruction is: CS# goes low→ sending QPP instruction code→ 3-byte address
on SIO0 → at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 10-32 Quad Page Program (QPP) Sequence (Command 32)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32
33 34 35 36 37 38 39
SCLK
Command
SI(IO0)
24- bit address
32H
23 22 21
Byte1
3
2
1
0
Byte2
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
MSB
543
541
542
540
539
537
48 49 50 51 52 53 54 55
538
40 41 42 43 44 45 46 47
536
CS#
SCLK
Byte11 Byte12
Byte253
Byte256
SI(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
Puya Semiconductor
Page 65 of 106
P25Q32SH Datasheet
10.33 Buffer Clear
The Buffer Clear instruction is for reset all buffer data to "FF". The data buffer will be 256 bytes (normal mode)
or 512bytes (dual page mode) or 1024 bytes (quad page mode). The Buffer data reset will begin when the
CS# pin goes high. There is a latency of tBC, after which the device is ready to accept the next instruction.
The sequence of issuing Buffer Clear instruction is: CS# goes low →
→ CS# goes high.
sending Buffer Clear instruction code
Figure 10-35 Buffer Clear Sequence (Command 9E)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
9EH
Figure 10-35a Buffer Clear Sequence (QPI)
CS#
0
1
SCLK
Command
9EH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Page 66 of 106
P25Q32SH Datasheet
10.34 Buffer Load
The Buffer Load instruction is for load main memory data to the data buffer . The data buffer will be 256 bytes
(normal mode) or 512bytes (dual page mode) or 1024 bytes (quad page mode). The address A23-A8(normal
mode) or A23-A9(dual page mode) or A23-A10(quad page mode) which specify the page in main memory to
be load data to buffer.
The sequence of issuing Buffer Load instruction is: CS# goes low →
3-byte address on SI → CS# goes high.
sending Buffer Load instruction code →
The transfer of the page of data from the main memory to the buffer will begin when the CS# pin goes high.
During the page transfer time (tXFR), the WIP bit in the Status Register can be read to determine whether or
not the transfer has been completed.
Figure 10-33 Buffer Load Sequence (Command 9A)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
9AH
23 22
MSB
2
1
0
Figure 10-33a Buffer Load Sequence (QPI)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
9AH
Puya Semiconductor
A23-16
A15- 8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 67 of 106
P25Q32SH Datasheet
10.35 Buffer Read
The Buffer Read instruction is for reading data out from the data buffer. The data buffer will be 256 bytes
(normal mode) or 512bytes (dual page mode) or 1024 bytes (quad page mode). The first address byte can be
at any location. The address is automatically increased to the next higher address after each byte data is
shifted out, so the whole data buffer can be read out at a single Buffer Read instruction. The address counter
rolls over to 0 when the highest address (FFh for normal mode /1FF for dual page mode /3FF for quad page
mode) has been reached.
The sequence of issuing Buffer Read instruction is: CS# goes low→ sending Buffer Read instruction code→3byte address on SI→ 1-dummy byte address on SI→ data out on SO→ to end Buffer Read operation can use
CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, Buffer Read instruction is rejected without
any impact on the Program/Erase/Write Status Register current cycle.
Figure 10-34 Buffer Read Sequence (Command 9B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24- bit address
9BH
23 22
21
3
2
1
0
High- Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Figure 10-34a Buffer Read Sequence (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
17 18 19 20 21
SCLK
Command
9BH
A23-16
A15-8
A7-0
IO switch from
input to output
Dummy*
SI(IO0)
20 16 12
8
4
0
4
0
4
0
4
SO(IO1)
21 17 13
9
5
1
5
1
5
1
5
WP#(IO2)
22 18 14 10
6
2
6
2
6
2
6
HOLD#(IO3)
23 19 15 11
7
3
7
3
7
3
7
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
Puya Semiconductor
Byte1
Byte2
Page 68 of 106
P25Q32SH Datasheet
10.36 Buffer Write
The Buffer Write instruction is for send data to data buffer. The data buffer size will be 256 bytes (normal
mode) or 512bytes (dual page mode) or 1024 bytes (quad page mode). The first address byte can be at any
location. The address is automatically increased to the next higher address after each byte data is shifted in.
If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data
will continue to be loaded into the data buffer until CS Pin goes to high.
The sequence of issuing Buffer Write instruction is: CS# goes low → sending Buffer Write instruction code →
3-byte address on SI → at least 1-byte on data on SI → CS# goes high.
Figure 10-35 Buffer Write Sequence (Command 9C)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
24- bit address
9CH
23 22 21
3
Data Byte 1
2
1 0
MSB
7
6
5
4
3
2
1
0
MSB
2079
2077
2078
2075
6
2076
2073
7
2074
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CS#
1
0
SCLK
Data Byte 2
SI
7
6
5
4
3
Data Byte 3
2
1
0 7
MSB
6
5
4
3
Data Byte 256
2
1
0
MSB
5
4
3
2
MSB
Figure 10-35a Buffer Write Sequence (QPI)
3
4
5
6
7
8
9 10
11
12 13 14 15 16 17
519
2
518
1
517
0
516
CS#
SCLK
Command
A23-16 A15-8 A7-0
9CH
Byte1
Byte2
Byte256
SI(IO0)
A20 A16 A12 A8
A4
A0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO(IO1)
A21 A17 A13 A9
A5
A1
5
1
5
1
5
1
5
1
5
0
5
1
5
1
WP#(IO2)
A22 A18 A14 A10 A6
A2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
A23 A19 A15 A11 A7
A3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
MSB
Puya Semiconductor
Page 69 of 106
P25Q32SH Datasheet
10.37 Buffer to Main Memory Page Program
The Buffer to Main Memory Page Program instruction allows data that is stored in the data buffers to be
written into a pre-erased page in the main memory array. It is necessary that the page in main memory to be
written be previously erased in order to avoid programming errors. A Write Enable (WREN) instruction must
execute to set the Write Enable Latch (WEL) bit before sending the Buffer to Main Memory Page Program
instruction. The data buffer will be 256 bytes (normal mode) or 512bytes (dual page mode) or 1024 bytes
(quad page mode). The address A23-A8(normal mode) or A23-A9(dual page mode) or A23-A10(quad page
mode) which specify the page in main memory to be programmed.
The sequence of issuing Buffer to Main Memory Page Program instruction is: CS# goes low → sending
Buffer to Main Memory Page Program instruction code → 3-byte address on SI → CS# goes high.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked during the Buffer to Main Memory Page Program cycle is in
progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the
Write Enable Latch (WEL) bit is reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Buffer to
Main Memory Page Program instruction will not be executed.
Figure 10-36 Buffer to Main Memory Page Program Sequence (Command 9D)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
24-bit address
9DH
23 22
MSB
2
1
6
7
0
Figure 10-36a Buffer to Main Memory Page Program Sequence (QPI)
CS#
0
1
2
3
4
5
SCLK
Command
9DH
Puya Semiconductor
A23-16
A15- 8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 70 of 106
P25Q32SH Datasheet
10.38 Erase Security Registers (ERSCUR)
The product provides three 1024-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending ERSCUR instruction
→ sending 24 bit address → CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security
Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress,
the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. The Security
Registers Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the
LB bit is set to 1, the Security Registers will be permanently locked; the Erase Security Registers command
will be ignored.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001
00
Byte Address
Security Register #2
00H
0010
00
Byte Address
Security Register #3
00H
0011
00
Byte Address
Figure 10-37 Erase Security Registers (ERSCUR) Sequence (Command 44)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
Puya Semiconductor
44H
24 bit address
23 22
MSB
2
1
0
Page 71 of 106
P25Q32SH Datasheet
10.39 Program Security Registers (PRSCUR)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to 1024
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have
been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers
command.
The Program Security Registers command sequence: CS# goes low → sending PRSCUR instruction
→ sending 24 bit address → sending at least one byte data → CS# goes high.
As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001
00
Byte Address
Security Register #2
00H
0010
00
Byte Address
Security Register #3
00H
0011
00
Byte Address
Figure 10-38 Program Security Registers (PRSCUR) Sequence (Command 42)
CS#
0
1
2
3
4
5
6
7
8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
42H
24- bit address
23 22 21
3
Data Byte 1
2
1 0 7
MSB
6
5
4
3
2
1
0
MSB
4127
4125
4126
4123
6
4124
7
4122
4120
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
4121
CS#
1
0
SCLK
Data Byte 2
SI
7
6
MSB
Puya Semiconductor
5
4
3
2
Data Byte 3
1
0 7 6
MSB
5
4
3
2
Data Byte 1024
1
0
5
4
3
2
MSB
Page 72 of 106
P25Q32SH Datasheet
10.40 Read Security Registers (RDSCUR)
The Read Security Registers command is similar to Fast Read command. The command is followed by a 3byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then the
memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A9-A0 address reaches
the last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving CS# high.
The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → sending
24 bit address → 8 bit dummy byte → Security Register data out on SO → CS# goes high.
Address
A23-16
A15-12
A11-10
A9-0
Security Register #1
00H
0001
00
Byte Address
Security Register #2
00H
0010
00
Byte Address
Security Register #3
00H
0011
00
Byte Address
Figure 10-39 Read Security Registers (RDSCUR) Sequence (Command 48)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24- bitaddress
23 22 21
48H
3
2
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
Puya Semiconductor
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Page 73 of 106
P25Q32SH Datasheet
10.41 Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to
entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Powerdown mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the
device is not active and all Write/Program/Erase instruction are ignored.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode
(RDP) , Read Electronic Signature (RES) instruction, and soft reset instruction(66H, 99H). (RES instruction to
allow the ID been read out). When Power- down, the deep power-down mode automatically stops, and when
power-up, the device automatically is in standby mode. For RDP instruction the CS# must go high exactly at
the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not
be executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep
Power-down mode and reducing the current to ISB2.
Figure 10-40 Deep Power-down (DP) Sequence (Command B9)
CS#
SCLK
SI
0
1
2
3
4
5
6
tDP
7
Command
Standby mode
Deep power-down mode
B9H
Figure 10-40a Deep Power-down (DP) Sequence (QPI)
tDP
CS#
0
1
SCLK
Command
B9H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Stand-by mode
Puya Semiconductor
Deep Power-down mode
Page 74 of 106
P25Q32SH Datasheet
10.42 Release form Deep Power-Down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven high, the device is put in the Stand-by Power mode. If the device was not
previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is
delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max). Once in the Stand-by
Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table
of ID Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For
new design, please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also
allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on
the current program/erase/ write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs
repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was
not previously in Deep Power-down mode, the device transition to standby mode is immediate.
If the device
was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS#
must remain to high at least tRES2 (max). Once in the standby mode, the device waits to be selected, so it
can be receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-Down Mode.
Figure 10-41 Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
SCLK
Command
SI
SO
ABH
High-Z
tRES2
3 Dummy Bytes
23 22
2
1
0
MSB
Electronic Signature Out
7
MSB
Puya Semiconductor
6
5
4
3
2
1
0
Deep Power-down mode
Standby Mode
Page 75 of 106
P25Q32SH Datasheet
Figure 10-41a Read Electronic Signature (RES) Sequence (QPI)
tRES2
CS#
0
1
2
3
4
5
6
7
8
SCLK
3 dummy bytes
Command
IO switch from
input to output
ABH
SI(IO0)
4
0
SO(IO1)
5
1
WP#(IO2)
6
2
7
3
HOLD#(IO3)
Device ID
Deep Power-down mode Stand-by mode
Figure 10-41b Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
tRES1
7
SCLK
Command
SI
ABH
Deep Power- down mode
Stand-by mode
Figure 10-41c Release from Deep Power-down (RDP) Sequence (QPI)
CS#
tRES1
0
1
SCLK
Command
ABH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Deep Power-down mode Stand-by mode
Puya Semiconductor
Page 76 of 106
P25Q32SH Datasheet
10.43 Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID
values are listed in "Table ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed
by two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for PUYA (85h) and the
device ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the address
byte is 00h, the manufacturer ID will be output first, followed by the device ID. If the address byte is 01h, then
the device ID will be output first, followed by the manufacturer ID. While CS# is low, the manufacturer and
device IDs can be read continuously, alternating from one to the other. The instruction is completed by driving
CS# high.
Figure 10-42 Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
2 dummy byte and
1 address byte
23 22 21
3 2
Command
SI
90H
1
0
High-Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
Device ID
Manufacturer ID
SO
7
6
5
4
3
2
1
0
MSB
7
6
5
4
3
2
1
0
MSB
Figure 10-42a Read Electronic Manufacturer & Device ID (REMS) Sequence (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
SCLK
Command
90H
A23-16
A15-8
IO switch from
input to output
A7-0
SI(IO0)
20
16
12
8
4
0
4
0
4
0
SO(IO1)
21
17
13
9
5
1
5
1
5
1
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
MID
Puya Semiconductor
Device ID
Page 77 of 106
P25Q32SH Datasheet
10.44 Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)
The DREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID
which takes two pins: SIO0, SIO1 as address input and ID output I/O
The instruction is initiated by driving the CS# pin low and shift the instruction code "92h" followed by two
dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte
address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction
is completed by driving CS# high.
Figure 10-43 DUAL I/O Read Electronic Manufacturer & Device ID (DREMS) Sequence (Command 92)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
20 21 22 23
SCLK
Command
SI(IO0)
92H
SO(IO1)
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
Dummy byte
4
2
0
6
5
3
1
7
ADD byte
Dummy byte
4
2
0
5
3
1
dummy
CS#
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI(IO0)
6
SO(IO1)
7
4
2
0
6
5
3
1
7
MFRID
Puya Semiconductor
4
2
0
6
5
3
1
7
DeviceID
4
2
0
6
5
3
1
7
MFRID
(Repeat)
4
2
0
6
5
3
1
7
DeviceID
(Repeat)
4
2
0
6
5
3
1
7
MFRID
(Repeat)
4
2
0
5
3
1
DeviceID
(Repeat)
Page 78 of 106
P25Q32SH Datasheet
10.45 Quad I/O Read Electronic Manufacturer ID & Device ID (QREMS)
The QREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID
which takes four pins: SIO0, SIO1,SIO2,SIO3 as address input and ID output I/O
The instruction is initiated by driving the CS# pin low and shift the instruction code "94h" followed by two
dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for PUYA (85h) and the
Device ID are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the one-byte
address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer ID.
The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction
is completed by driving CS# high.
Figure 10-44 QUAD I/O Read Electronic Manufacturer & Device ID (QREMS) Sequence (Command 94)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
SI(IO0)
94H
4
0
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
6
2
HOLD#(IO3)
7
3
7
3
7
3
7
3
7
3
A23-16 A15-8 A7-0
Dummy
MFRID DID
CS#
24 25 26 27 28 29 30 31
SCLK
SI(IO0)
4
0
4
0
4
0
4
0
SO(IO1)
5
1
5
1
5
1
5
1
WP#(IO2)
6
2
6
2
6
2
6
2
HOLD#(IO3) 7
3
7
3
7
3
7
3
MFRID DID MFRID DID
Repeat Repeat Repeat Repeat
Puya Semiconductor
Page 79 of 106
P25Q32SH Datasheet
10.46 Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
PUYA Manufacturer ID and Device ID are list as "Table . ID Definitions”.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID
data out on SO→ to end RDID operation can use CS# to high at any time during data out. While Program
/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of
program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
Figure 10-45 Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
9FH
SO
7
6
Manufacturer ID
5 4 3 2 1
0
MSB
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
Memory Type ID
6 5 4 3 2 1
MSB
0
7
Capacity ID
5 4 3 2
6
1
0
MSB
Figure 10-45a Read Identification (RDID) Sequence (QPI)
CS#
0
1
2
3
4
5
6
SCLK
Command
9FH
IO switch from
input to output
SI(IO0)
4
0
12
8
4
0
SO(IO1)
5
1
13
9
5
1
WP#(IO2)
6
2
14 10
6
2
HOLD#(IO3)
7
3
15
7
3
MID
11
ID15-8
ID7-0
Table ID Definitions
P25Q32SH
Puya Semiconductor
RDID
manufacturer ID
command
85
memory type
60
RES
electronic ID
command
15
memory density
16
REMS
manufacturer ID
device ID
command
85
15
Page 80 of 106
P25Q32SH Datasheet
10.47 Program/Erase Suspend/Resume
The Suspend instruction interrupts a Page Program, Page Erase, Sector Erase, or Block Erase operation to
allow access to the memory array. After the program or erase operation has entered the suspended state, the
memory array can be read except for the page(s) being programmed or the page(s) or sector or block being
erased.
Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page(s) Program
All but the Page(s) being programmed
Page(s) Erase
All but the Page(s) being erased
Sector Erase(4KB)
All but the 4KB Sector being erased
Block Erase(32KB)
All but the 32KB Block being erased
Block Erase(64KB)
All but the 64KB Block being erased
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the
Write Enable Latch (WEL) bit clears to “0” and the SUS sets to “1”, after which the device is ready to accept
one of the commands listed in "Table Acceptable Commands During Program/Erase Suspend after
tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings. "Table Acceptable
Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL
latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the
Suspend instruction.
Status Register bit 15 (SUS) can be read to check the suspend status. The SUS (Program/Erase Suspend Bit)
sets to “1” when a program or erase operation is suspended. The SUS clears to “0” when the program or
erase operation is resumed.
Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command name
Command
Suspend Type
Code
Program Suspend
Erase Suspend
READ
03H
•
•
FAST READ
0BH
•
•
DTRFRD
0DH
•
•
DREAD
3BH
•
•
QREAD
6BH
•
•
2READ
BBH
•
•
2DTRD
BDH
•
•
4READ
EBH
•
•
Word read
E7H
•
•
4DTRD
EDH
•
•
Burst Read with Wrap
0CH
•
•
DTR Burst Read with Wrap
0EH
•
•
QPIEN
38H
•
•
Disable QPI
FFH
•
•
RDSFDP
5AH
•
•
RDID
9FH
•
•
REMS
90H
•
•
DREMS
92H
•
•
QREMS
94H
•
•
SBL
77H
•
•
Puya Semiconductor
Page 81 of 106
P25Q32SH Datasheet
Command name
Command
Code
Set Read Parameter
WREN
RESUME
PP
QPP
Erase Security Registers
Program Security Registers
read Security Registers
Buffer clear
Buffer load
Buffer read
Buffer write
Buffer to memory program
Individual Block Lock
Individual Block Unlock
Read Block Lock Status
Global Block Lock
Global Block Unlock
C0H
06H
7AH
02H
32H
44H
42H
48H
9EH
9AH
9BH
9CH
9DH
36H
39H
3DH
7EH
98H
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Acceptable Commands During Suspend（tPSL/tESL not required）
Command name
Command Code
Suspend Type
Program Suspend
Erase Suspend
WRDI
04H
•
•
RDSR
05H
•
•
RDSR1
35H
•
•
RES
ABH
•
•
RSTEN
66H
•
•
RST
99H
•
•
NOP
00H
•
•
Figure 10-46 Resume to Suspend Latency
tPRS / tERS
CS#
Resume Command
Suspend Command
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
Puya Semiconductor
Page 82 of 106
P25Q32SH Datasheet
10.48 Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN)
instruction must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to finish before the suspended erase can be resumed. The Status Register can be polled to determine the
status of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the
Page Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 10-47 Suspend to Read/Program Latency
tPSL / tESL
Read/Program command
Suspend Command
CS#
0
SCLK
1
2
3
4
5
6
tPSL: Program latency
tESL: Erase latency
7
Command
SI
75H
Figure 10-47a Suspend to Read/Program Latency(QPI)
CS#
tPSL/tESL
0
1
SCLK
Command
75H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Read/Program Command
Notes:
1. Please note that Program only available after the Erase-Suspend operation
2. To check suspend ready information, please read status register bit15 (SUS2) and bit10(SUS1)
Puya Semiconductor
Page 83 of 106
P25Q32SH Datasheet
10.49 Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Page Erase, Sector Erase, or Block Erase
operation. Before issuing the Resume instruction to restart a suspended erase operation, make sure that there
is no Page Program operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1”
and the SUS2 or SUS1 is cleared to “0”. The program or erase operation will continue until finished ("Resume
to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or
tERS must be observed before issuing another Suspend instruction ("Resume to Suspend Latency").
Figure 10-48 Resume to Read Latency
tSE / tBE / tPP
Resume Command
CS#
0
SCLK
1
2
3
4
Read Command
5
6
7
Command
SI
7AH
Figure 10-48a Resume to Read Latency(QPI)
CS#
0
1
SCLK
Command
7AH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Resume previously suspended program or erase
10.50 No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not
affect any other command.
The SIO[3:1] are don't care.
Puya Semiconductor
Page 84 of 106
P25Q32SH Datasheet
10.51 Individual Block Lock (SBLK)
The Individual Block Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block Locks, the WPS bit in Configure Register must be set to 1.
If WPS=0, the write protection will be determined by the combination of CMP, BP[4:0] bits in the Status
Registers. The Individual Block Lock bits are volatile bits. The default values after device power up or after a
Reset are 1, so the entire memory array is being protected.
The SBLK instruction is for write protection a specified block (or sector) of memory, using AMAX-A16 or
(AMAX-A12) address bits to assign a 64Kbyte block (or 4K bytes sector) to be protected as read only.
The WREN (Write Enable) instruction is required before issuing SBLK instruction.
The sequence of issuing SBLK instruction is: CS# goes low → send SBLK (36h) instruction→ send 3-byte
address assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high
exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
Figure 10-50 Individual Block Lock(Command 36H)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9
29 30 31
Command
SI
24BitsAddress
36H
23 22
MSB
2
1
6
7
0
Figure 10-50a Individual Block Lock(QPI)
CS#
0
1
2
3
4
5
SCLK
Command
36H
Puya Semiconductor
A23-16
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 85 of 106
P25Q32SH Datasheet
10.52 Individual Block Unlock (SBULK)
The Individual Block Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block Locks, the WPS bit in Configure Register must be set to 1.
If WPS=0, the write protection will be determined by the combination of CMP, BP[4:0] bits in the Status
Registers. The Individual Block Lock bits are volatile bits. The default values after device power up or after a
Reset are 1, so the entire memory array is being protected.
The SBULK instruction will cancel the block (or sector) write protection state using AMAX-A16 or (AMAX-A12)
address bits to assign a 64Kbyte block (or 4K bytes sector) to be unprotected.
The WREN (Write Enable) instruction is required before issuing SBULK instruction.
The sequence of issuing SBULK instruction is: CS# goes low → send SBULK (39h) instruction→ send 3-byte
address assign one block (or sector) to be protected on SI pin → CS# goes high. The CS# must go high
exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
Figure 10-51 Individual Block Unlock(Command 39H)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9
29 30 31
Command
SI
24BitsAddress
39H
23 22
MSB
2
1
6
7
0
Figure 10-51a Individual Block Unlock(QPI)
CS#
0
1
2
3
4
5
SCLK
Command
39H
Puya Semiconductor
A23-16
A15-8
A7-0
SI(IO0)
20
16
12
8
4
0
SO(IO1)
21
17
13
9
5
1
WP#(IO2)
22
18
14
10
6
2
HOLD#(IO3)
23
19
15
11
7
3
Page 86 of 106
P25Q32SH Datasheet
10.53 Read Block Lock Status (RDBLK)
The Individual Block Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block Locks, the WPS bit in Configure Register must be set to 1.
If WPS=0, the write protection will be determined by the combination of CMP, BP[4:0] bits in the Status
Registers. The Individual Block Lock bits are volatile bits. The default values after device power up or after a
Reset are 1, so the entire memory array is being protected.
The RDBLOCK instruction is for reading the status of protection lock of a specified block (or sector), using
AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K bytes sector) and read protection
lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate that this block has be
protected, that user can read only but cannot write/program /erase this block. The status bit is "0" to indicate
that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Dh) instruction → send
3-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction.
Figure 10-52 Read Block Lock Status(Command 3DH)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
SI
24- bit address
3DH
23
3
2
1
0
Data Byte
MSB
High-Z
SO
22 21
6
7
MSB
5
4
3
2
1
0
Figure 10-52a Read Block Lock Status (QPI)
CS#
0
1
2
3
4
5
6
7
8
9
10
SCLK
Command
3DH
A23-16
A15-8
IO switch from
input to output
A7-0
SI(IO0)
20 16 12
8
4
0
X
0
X
0
SO(IO1)
21 17 13
9
5
1
X
X
X
X
WP#(IO2)
22 18 14 10
6
2
X
X
X
X
HOLD#(IO3)
23 19 15 11
7
3
X
X
X
X
Lock Value
Puya Semiconductor
Page 87 of 106
P25Q32SH Datasheet
10.54 Global Block Lock (GBLK)
The GBLK instruction is for enable the lock protection block of the whole chip. The WREN (Write Enable)
instruction is required before issuing GBLK instruction.
The sequence of issuing GBLK instruction is: CS# goes low → send GBLK (7Eh) instruction →CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't
care" in SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be
executed.
Figure 10-53 Global Block Lock(Command 7EH)
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
Command
7EH
High-Z
Figure 10-53a Global Block Lock(QPI)
CS#
0
1
SCLK
Command
7EH
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Page 88 of 106
P25Q32SH Datasheet
10.55 Global Block Unlock (GBULK)
The GBULK instruction is for disable the lock protection block of the whole chip. The WREN (Write Enable)
instruction is required before issuing GBULK instruction.
The sequence of issuing GBULK instruction is: CS# goes low → send GBULK (98h) instruction →CS# goes
high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't
care" in SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be
executed.
Figure 10-54 Global Block Unlock(Command 98H)
CS#
SCLK
SI
SO
0
1
2
3
4
5
6
7
Command
98H
High-Z
Figure 10-54a Global Block Unlock(QPI)
CS#
0
1
SCLK
Command
98H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Page 89 of 106
P25Q32SH Datasheet
10.56 Software Reset (RSTEN/RST)
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on, except the EP_FAIL bit.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform
the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the ResetEnable will be invalid.
The SIO[3:1] are "don't care".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data
under processing could be damaged or lost.
Figure 10-55 Software Reset Recovery
CS#
66H
99H
tReady
Mode
Stand-by Mode
Figure 10-55a Reset Sequence
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCLK
Command
Command
66H
99H
SI
High -Z
SO
Figure 10-55b Reset Sequence(QPI)
CS#
0
1
0
1
SCLK
Command
Command
66H
99H
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
Puya Semiconductor
Page 90 of 106
P25Q32SH Datasheet
10.57 RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the
device is at the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation
and data could be lost. During the resetting cycle, the SO data becomes high impedance and the current will
be reduced to minimum.
Figure 10-58 RESET Timing
CS#
tRHSL
SCLK
tRH
tRS
RESET#
tRLRH
tREADY1/tREADY2
RESET Timing (Power On)
Symbol
Parameter
tRHSL
Reset# high before CS# low
Min.
10
Typ.
Max.
Unit
us
tRS
Reset# setup time
150
ns
tRH
Reset# hold time
150
ns
Reset# low pulse width
10
us
Reset Recovery time
30
us
tRLRH
tREADY1
RESET Timing (Other Operation)
Symbol
Parameter
tRHSL
Reset# high before CS# low
Min.
10
Typ.
Max.
Unit
us
tRS
Reset# setup time
150
ns
tRH
Reset# hold time
150
ns
Reset# low pulse width
10
us
Reset Recovery time (except
WRSR/WRCR)
30
us
Reset Recovery time (for WRSR/WRCR)
120
ms
tRLRH
tREADY2
Puya Semiconductor
Page 91 of 106
P25Q32SH Datasheet
10.58 Read Unique ID (RUID)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
P25QSxx device. The Unique ID can be used in conjunction with user software methods to help prevent
copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →Dummy
Byte1 →Dummy Byte2 →Dummy Byte3 → Dummy Byte4 → 128bit Unique ID Out → CS# goes high.
The command sequence is show below.
Figure 10-56 Read Unique ID (RUID) Sequence (Command 4B)
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
SO
3 bytes dummy
4BH
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43
164 165 166
SCLK
DummyByte
SI
128 bit unique serial number
SO
Puya Semiconductor
127 126 125 124
MSB
3
2
1
0
Page 92 of 106
P25Q32SH Datasheet
10.59 Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to accommodate
divergent features from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC
Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is same as FREAD: CS# goes low→ send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→ send 1 dummy byte on SI pin→ read SFDP code on SO→ to end
RDSFDP operation can use CS# to high at any time during data out.
SFDP is a JEDEC Standard, JESD216B.
Figure 10-57 Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
5AH
23 22
21
3
2
1
0
High - Z
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
DummyByte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
7 6
MSB
5
4
3
Data Out2
2
1
0
7 6
MSB
5
Figure 10-57a Read Serial Flash Discoverable Parameter (RDSFDP) Sequence(QPI)
CS#
0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
SCLK
Command
5AH
A23-16
A15-8
A7-0
IO switch from
input to output
Dummy*
SI(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO(IO1)
21
17
13
9
5
1
5
1
5
1
5
WP#(IO2)
22
18
14
10
6
2
6
2
6
2
6
HOLD#(IO3)
23
19
15
11
7
3
7
3
7
3
7
*“Set Read Parameters” command (C0H)
can set the number of dummy clocks
Puya Semiconductor
Byte1
Byte2
Page 93 of 106
P25Q32SH Datasheet
Serial Flash Discoverable Parameter (SFDP) Table
Table Signature and Parameter Identification Data Values
Description
SFDP Signature
Comment
Fixed:50444653H
Add(H)
DW Add
Data
Data
(Byte)
(Bit)
00H
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
SFDP Minor Revision Number
Start from 00H
04H
07:00
00H
00H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Start from 0x00H
09H
15:08
00H
00H
Start from 0x01H
0AH
23:16
01H
01H
0BH
31:24
09H
09H
0CH
07:00
30H
30H
0DH
15:08
00H
00H
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
85H
85H
Start from 0x00H
11H
15:08
00H
00H
Start from 0x01H
12H
23:16
01H
01H
13H
31:24
03H
03H
Unused
Contains 0xFFH and can never be
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
How many DWORDs in the
Parameter table
First address of JEDEC Flash
Parameter table
Unused
Contains 0xFFH and can never be
changed
ID Number
It is indicates PUYA
(PUYADevice Manufacturer ID)
manufacturer ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
How many DWORDs in the
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of PUYA Flash
14H
07:00
60H
60H
Parameter table
15H
15:08
00H
00H
16H
23:16
00H
00H
17H
31:24
FFH
FFH
Unused
Contains 0xFFH and can never be
changed
Puya Semiconductor
Page 94 of 106
P25Q32SH Datasheet
Table
Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
(Byte)
DW Add
Data
Data
(Bit
)
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
01:00
01b
02
1b
03
0b
11: not support 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
Write Enable Instruction
0: Nonvolatile status bit
Requested for Writing to Volatile
Status Registers
1: Volatile status bit
(BP status register bit)
30H
E5H
0: Use 50H Opcode,
Write Enable Opcode Select for
Writing to Volatile Status Registers
1: Use 06H Opcode,
Note: If target flash status register is
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
1b
Nonvolatile, then bits3 and 4 must
be set to 00b.
Unused
Contains 111b and can never be
changed
4KB Erase Opcode
(1-1- 2) Fast Read
31H
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
32H
F9H
(1-2- 2) FastRead
0=Not support, 1=Support
20
1b
(1-4- 4) Fast Read
0=Not support, 1=Support
21
1b
(1-1- 4) Fast Read
0=Not support, 1=Support
22
1b
23
1b
33H
31:24
FFH
37H:34H
31:00
Unused
Unused
Flash Memory Density
(1-4- 4) Fast Read Number of Wait
states
0 0000b: Wait states (Dummy
04:00
Clocks) not support
Mode Bits
000b:Mode Bits not support
(1-4- 4) Fast Read Opcode
(1-1- 4) Fast Read Number of Wait
states
39H
0 0000b: Wait states (Dummy
Clocks) not support
00100b
44H
07:05
010b
15:08
EBH
20:16
01000b
3AH
(1-1- 4) Fast Read Number of
Mode Bits
(1-1- 4) Fast Read Opcode
Puya Semiconductor
000b:Mode Bits not support
3BH
FFH
01FFFFFFH
38H
(1-4- 4) Fast Read Number of
20H
EBH
08H
23:21
000b
31:24
6BH
6BH
Page 95 of 106
P25Q32SH Datasheet
Description
Comment
(1-1- 2) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
Clocks) not support
Add(H)
DW Add
(Byte)
(Bit)
04:00
Data
01000b
3CH
(1-1- 2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(1-1- 2) Fast Read Opcode
(1-2- 2) Fast Read Number
of Wait states
3DH
0 0000b: Wait states (Dummy
Clocks) not support
08H
07:05
000b
15:08
3BH
20:16
00000b
3EH
(1-2- 2) Fast Read Number
of Mode Bits
000b: Mode Bits not support
(1-2- 2) Fast Read Opcode
(2-2- 2) Fast Read
3FH
0=not support 1=support
Unused
0=not support 1=support
Unused
3BH
80H
23:21
100b
31:24
BBH
00
0b
03:01
111b
04
1b
07:05
111b
40H
(4-4- 4) Fast Read
Data
BBH
FEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
23:21
000b
47H
31:24
FFH
FFH
49H:48H
15:00
0xFFH
0xFFH
20:16
00100b
(2-2- 2) Fast Read Number
of Wait states
(2-2- 2) Fast Read Number
of Mode Bits
0 0000b: Wait states (Dummy
Clocks) not support
46H
000b: Mode Bits not support
(2-2- 2) Fast Read Opcode
Unused
(4-4- 4) Fast Read Number of Wait
0 0000b: Wait states (Dummy
states
Clocks) not support
(4-4- 4) Fast Read Number
of Mode Bits
Sector Type 1 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector Type 4 erase Opcode
Puya Semiconductor
Sector/block size=2^N bytes
0x00b: this sector type don’t exist
44H
4AH
000b: Mode Bits not support
(4-4- 4) Fast Read Opcode
00H
23:21
010b
4BH
31:24
EBH
EBH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
08H
08H
53H
31:24
81H
81H
Page 96 of 106
P25Q32SH Datasheet
Table Parameter Table (1): PUYA Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
61H:60H
63H:62H
Data
Data
15:00
3600H
3600H
31:16
2300H
2300H
2000H=2.000V
Vcc Supply Maximum Voltage
2700H=2.700V
3600H=3.600V
1650H=1.650V
Vcc Supply Minimum Voltage
2250H=2.250V
2350H=2.350V
2700H=2.700V
HW Reset# pin
0=not support 1=support
00
0b
HW Hold# pin
0=not support 1=support
01
1b
0=not support 1=support
02
1b
0=not support 1=support
03
1b
Deep Power Down Mode
SW Reset
SW Reset Opcode
Should be issue Reset Enable(66H)
before Reset cmd.
65H:64H
11:04
1001 1001b
(99H)
F99EH
Program Suspend/Resume
0=not support 1=support
12
1b
Erase Suspend/Resume
0=not support 1=support
13
1b
14
1b
15
1b
66H
23:16
77H
77H
67H
31:24
64H
64H
00
1b
01
0b
09:02
36H
10
0b
Unused
Wrap Around Read mode
0=not support 1=support
Wrap - Around Read mode Opcode
08H:support 8B wrap
- around read
Wrap - Around Read data length
16H:8B&16B
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individual block lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support 1=support
0=Volatile
1=Nonvolatile
Individual block lock Opcode
Individual blocklock Volatile
protect bit default protect status
0=protect 1=unprotect
Secured OTP
0=not support 1=support
11
1b
Read Lock
0=not support 1=support
12
0b
Permanent Lock
0=not support
1=support
13
1b
Unused
15:14
11b
Unused
31:16
FFFFH
Puya Semiconductor
E8D9H
6BH:68H
FFFFH
Page 97 of 106
P25Q32SH Datasheet
11 Ordering Information
P 25 Q32S H A –SU H– I T
Company Designator
P = Puya Semiconductor
Product Family
25 = SPI interface flash
Product Serial
Q = Q serial
Memory Density
32S = 32Mb
Operation Voltage
H = 2.3V~3.6V
Generation
A = A Version
Default = blank
Package Type
SS = SOP8 150mil
SU = SOP8 208mil
TS = TSSOP8
WF = WAFER
UX = USON8 3x2x0.55mm
NX = USON8 3x4x0.55mm
WX = WSON8 6x5x0.75mm
Plating Technology
H : RoHS Compliant Halogen free, Antimony free
Q: RoHS Compliant Halogen free, Antimony free, with QE=1
Device Grade
I = - 40 ~ 85C
K = - 40 ~ 105C
Packing Type
T = TUBE
R = TAPE & REEL
Y = TRAY
W = WAFER
Puya Semiconductor
Page 98 of 106
P25Q32SH Datasheet
12 Valid Part Numbers and Top Marking
The following table provides the valid part numbers for the P25Q32SH Flash Memory. Please contact PUYA
for specific availability by density and package type. PUYA Flash memories use a 14-digit Product Number for
ordering.
Package Type
SS
SOP8 150mil
SS
SOP8 150mil
SS
SOP8 150mil
SS
SOP8 150mil
SU*
SOP8 208mil
SU*
SOP8 208mil
SU*
SOP8 208mil
SU*
SOP8 208mil
TS*
TSSOP8
TS*
TSSOP8
UX*
USON8 3x2mm
NX*
USON8 3x4mm
WX*
WSON8 6x5mm
Product Number
Density
P25Q32SH-SSH-IT
32M-bit
P25Q32SH-SSH-IR
32M-bit
P25Q32SH-SSQ-IT
32M-bit
P25Q32SH-SSQ-IR
32M-bit
P25Q32SH-SUH-IT
32M-bit
P25Q32SH-SUH-IR
32M-bit
P25Q32SH-SUQ-IT
32M-bit
P25Q32SH-SUQ-IR
32M-bit
P25Q32SH-TSH-IT
32M-bit
P25Q32SH-TSH-IR
32M-bit
P25Q32SH-UXH-IR
32M-bit
P25Q32SH-NXH-IR
32M-bit
P25Q32SH-WXH-IR
32M-bit
Top Side
Marking
P25Q32SH
xxxxxxx
P25Q32SH
xxxxxxx
P25Q32SH
xxQxxxx
P25Q32SH
xxQxxxx
P25Q32SH
xxxxxxx
P25Q32SH
xxxxxxx
P25Q32SH
xxQxxxx
P25Q32SH
xxQxxxx
P25Q32SH
xxxxxxx
P25Q32SH
xxxxxxx
Q32S
Hxxx
Q32S
Hxxx
P25Q32SH
xxxxxxx
Temp.
Packing
Type
85C
Tube
85C
Reel
85C
Tube
85C
Reel
85C
Tube
85C
Reel
85C
Tube
85C
Reel
85C
Reel
85C
Reel
85C
Reel
85C
Reel
85C
Reel
Note：There is no mass production of the package marked with "*", if necessary, please contact Puya sales
Puya Semiconductor
Page 99 of 106
P25Q32SH Datasheet
13 Package Information
13.1 8-Lead SOP(150mil)
h x45°
A2
A
b
e
C
D
8
0.25mm
GAUGE PLANE
E1
E
A1
k
1
L
L1
Common Dimensions
(Unit of Measure=millimeters)
Symbol
Min
Typ
Max
A
-
-
1.750
0.100
-
0.250
A2
1.250
-
-
b
0.280
-
0.480
c
0.170
-
0.230
D
4.800
4.900
5.000
E
5.800
6.000
6.200
E1
3.800
3.900
4.000
e
-
1.270
-
h
0.250
-
0.500
k
0°
-
8°
L
0.400
-
1.270
L1
-
1.040
-
A1
Note：1. D im ensions are not to scale
TITLE
DRAWING NO.
REV
SP-8
A
8-lead SOP
Puya Semiconductor
Page 100 of 106
P25Q32SH Datasheet
13.2 8-Lead SOP(208mil)
A2
A
b
e
C
D
8
0.25mm
GAUGE PLANE
E1
E
A1
k
1
L
Common Dimensions
(Unit of Measure=millimeters)
Symbol
Min
Typ
Max
A
-
-
2.150
A1
0.050
-
0.250
A2
1.700
-
1.900
b
0.350
-
0.500
c
0.100
-
0.250
D
5.130
-
5.330
E
7.700
8.100
E1
5.180
5.380
e
-
1.270
-
k
0°
-
8°
L
0.500
-
0.850
Note：1. D im ensions are not to scale
TITLE
DRAWING NO.
REV
SP-8
A
8-lead SOP(200mil)
Puya Semiconductor
Page 101 of 106
P25Q32SH Datasheet
13.3 8-Lead TSSOP
D
8
5
C
E
E1
1
4
A
A1
A2
b
e
CP
α
L
L1
Common Dimensions
(Unit of Measure=millimeters)
Symbol
A
Min
Typ
Max
-
-
1.200
A1
0.050
-
0.150
A2
0.800
1.000
1.050
b
0.190
-
0.300
c
0.090
-
0.200
-
0.100
CP
D
e
2.900
-
3.000
0.650
3.100
-
E
6.200
6.400
6.600
E1
4.300
4.400
4.500
L
0.450
0.600
0.750
L1
-
α
0°
1.000
-
8°
Note：1. D im ensions are not to scale
TITLE
8-lead TSSOP
Puya Semiconductor
DRAWING NO.
REV
TS-8
A
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P25Q32SH Datasheet
13.4 8-Land USON(3x2x0.55mm)
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P25Q32SH Datasheet
13.5 8-Land USON(3x4x0.55mm)
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P25Q32SH Datasheet
13.6 8-Land WSON(6x5x0.75mm)
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P25Q32SH Datasheet
14 Revision History
Rev.
Date
Description
Note
V1.0
2020-11-13
Initial Release Version
-
V1.1
2020-11-27
Update ACDC Characteristics.
-
V1.2
2021-03-01
Add RESET Timing
-
V1.3
2021-07-21
Ordering Information Plating Technology Add Q : QE=1 Option
-
V1.4
2021-08-10
Update Valid Part Numbers
-
Puya Semiconductor Co., Ltd.
IMPORTANT NOTICE
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products or specifications herein. Puya Semiconductor does not assume any responsibility
for use of any its products for any particular purpose, nor does Puya Semiconductor
assume any liability arising out of the application or use of any its products or circuits.
Puya Semiconductor does not convey any license under its patent rights or other rights
nor the rights of others.
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