P25Q40SH-SSH-IT

Puya Flash Application Note Migration from P25Q40H to P25Q40SH SPI Flash Application Note The document provides conversion guidelines for migrating from the P25Q40H to the P25Q40SH SPI Flash,and discusses the specification differences. Puya Semiconductor (Shanghai) Co., Ltd Puya Semiconductor Page 1 of 11 Puya Flash Application Note Contents 1 2 3 4 5 6 7 8 Introduction ....................................................................................................................................................3 Feature Comparison and Differences ...........................................................................................................3 2.1 Hardware Package ............................................................................................................................4 2.2 IO Mode .............................................................................................................................................5 2.3 Status Registers ................................................................................................................................5 2.4 Configure Registers ...........................................................................................................................6 2.5 Active Status Interrupt .......................................................................................................................6 2.6 Block Protection Scheme ..................................................................................................................6 2.7 Buffer Access .....................................................................................................................................6 Command Set Comparison ...........................................................................................................................7 DC Comparison .............................................................................................................................................9 AC Comparison .......................................................................................................................................... 10 5.1 Erase/Program Timing .................................................................................................................... 10 Conclusion .................................................................................................................................................. 10 Reference Documents ................................................................................................................................ 10 Revision History........................................................................................................................................... 11 Puya Semiconductor Page 2 of 11 Puya Flash Application Note 1 Introduction PUYA P25Q40SH Flash is a feature rich and cost-optimized serial peripheral interface (SPI) non-volatile NOR flash family. This application note provides conversion guidelines for migrating from the P25Q40H to the P25Q40SH Flash. This application note is based on information available to date from datasheets and other application notes publicly available from PUYA. Please refer also to the latest relevant specifications. The document discusses the specification differences when migrating from P25Q40H to P25Q40SH. 2 Feature Comparison and Differences PUYA P25Q40H products are well suited for migration to PUYA P25Q40SH products. Some of the reasons are compatible pinouts, packages, command set, and 4KB sector structure. Both P25Q40H and P25Q40SH devices support Single (Standard) I/O, Dual I/O, and Quad I/O modes. The main differences between P25Q40H and P25Q40SH are listed in the table below: Table 2-1. High Level Feature Support Comparison Feature / Parameter Supple Voltage Single (Standard) IO Operations Dual IO Operations Quad IO Operations QPI Standard Normal Read SCK Frequency (max) Standard Fast Read SCK Frequency (max) Dual Fast Read SCK Frequency (max) Quad Fast Read SCK Frequency (max) Software Protection Individual Block Protection One Time Programmable Region(s) Buffer access Erase(PE,SE,BE) time Typ. Erase(CE) time Typ. Configure Register Temperature Range Option Puya Semiconductor P25Q40H 2.3V-3.6V √ √ √ not support 55 MHz 104 MHz 104 MHz 104 MHz √ not support 3 x 512 Bytes not support 8ms 8ms not support -40C to +85C P25Q40SH 2.3V-3.6V √ √ √ √ 55 MHz 104 MHz 104 MHz 104 MHz √ √ 3 x 512 Bytes √ 16ms 16ms √ -40C to +85C Page 3 of 11 Puya Flash Application Note 2.1 Hardware Package The pinouts of P25Q40H and P25Q40SH are identical. CS# 1 8 VCC SO 2 7 HOLD#/RESET# WP# 3 6 GND 4 5 CS# 1 8 VCC SO 2 7 HOLD#/RESET# SCLK WP# 3 6 SCLK SI GND 4 5 SI 8-PIN SOP (150mil/208mil) and TSSOP 8-Land USON (3x2/3x4/1.5x1.5mm)/ WSON (6x5mm) Top View Bottom View VCC CS# CS# VCC HOLD# SO SO HOLD# SCLK WP# WP# SCLK SI GND GND SI 8-Ball WLCSP Ball Assignment Table 2-1-1 Pin Descriptions No. Symbol Extension 1 CS# 2 SO SIO1 3 WP# SIO2 4 GND - 5 SI SIO0 6 SCLK - 7 HOLD#/RESET# SIO3 8 Vcc - Puya Semiconductor Remarks Chip select Serial data output for 1 x I/O Serial data input and output for 4 x I/O read mode Write protection active low Serial data input and output for 4 x I/O read mode Ground of the device Serial data input for 1x I/O Serial data input and output for 4 x I/O read mode Serial interface clock input Hardware Reset Pin Active low or to pause the device without deselecting the device Serial data input and output for 4 x I/O read mode Power supply of the device Page 4 of 11 Puya Flash Application Note 2.2 IO Mode Both P25Q40H and P25Q40SH support Single, Dual, Quad SPI. P25Q40SH supports QPI, while P25Q40H does not. 2.3 Status Registers Both PUYA P25Q40H and P25Q40SH have two status registers: SR1 and SR2. Only non-volatile status register bits SRP0, BP4, BP3, BP2, BP1, BP0 (Status Register-1), CMP, LB3, LB2, LB1, QE, SRP1 (Status Register-2) can be written. All other status register bit locations are read-only and will not be affected by the Write Status Register instruction. Table 2-3-1. Status Register Bits Assignments SR Bits P25Q40H P25Q40SH Function SUS: Erase\Program Suspend status S15 SUS1 SUS SUS1: Erase Suspend status S14 CMP CMP Complement Protect S13 LB3 LB3 S12 LB2 LB2 Security Lock Bits S11 LB1 LB1 SUS2: Program Suspend status S10 SUS2 EP_FAIL EP_FAIL: the status of the last Program/Erase operation S9 QE QE Quad Enable S8 SRP1 SRP1 Status Register Protect S7 SRP0 SRP0 S6 BP4 BP4 S5 BP3 BP3 S4 BP2 BP2 Block Protect Bits S3 BP1 BP1 S2 BP0 BP0 S1 WEL WEL Write Enable S0 WIP WIP Write In Progress Table 2-3-2. Write Status Register P/N Commands Abbr. Code ADR Bytes DMY Bytes Data Bytes P25Q40H / P25Q40SH (with ordering option "D" ) Write Status Register WRSR 01h 0 0 2 Write Status Register WRSR 01h 0 0 1 Write Status Register-1 WRSR1 31h 0 0 1 P25Q40SH Puya Semiconductor Function Write data to status registers Write data to status registers Write data to status registers-1 Page 5 of 11 Puya Flash Application Note 2.4 Configure Registers P25Q40SH supports Configure Register, while P25Q40H does not. Table 2-4-1. Configure Register Bits Assignments SR Bits P25Q40SH Function Bit7 HOLD/RST HOLD/RST: /HOLD or /RESET function select Bit6 DRV1 Bit5 DRV0 Bit4 MPM1 Bit3 MPM0 Bit2 WPS Write Protect scheme Bit1 DC the Dummy Cycle bit Bit0 DLP Data Learning Pattern Enable bit the output driver strength for the Read operations the Multi Page Mode Table 2-4-2. Write Configure Register P/N Commands Abbr. Code ADR Bytes DMY Bytes Data Bytes P25Q40SH Write Configure Register WRCR 11h 0 0 1 Function Write data to configuration register 2.5 Active Status Interrupt P25Q40H supports the ASI command to simplify the readout of the WIP bit, while P25Q40SH does not. It is useful for these ultra low power applications by avoid reading WIP bit continuously after erase or program operation. 2.6 Block Protection Scheme Both PUYA P25Q40H and P25Q40SH (WPS=0) support Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be read but not change. P25Q40SH also support Individual Block/Sector protection, and it is only valid when WPS=1. 2.7 Buffer Access P25Q40SH supports Buffer access, while P25Q40H does not. Puya Semiconductor Page 6 of 11 Puya Flash Application Note 3 Command Set Comparison Both P25Q40H and P25Q40SH share similar instructions (op-codes) in their command-set, which determine a compatible set of internal algorithms. Nevertheless, not all commands are supported when comparing one with the other. Table below shows a comparison summary of the command set of P25Q40H and P25Q40SH. Please refer to the data sheet for more information. Table 3-1 Command Sets Compare List Commands Read Read Array (fast) Read Array (low power) Read Dual Output Read 2x I/O Read Quad Output Read 4x I/O Read Word 4IO Program and Erase Page Erase Sector Erase (4K bytes) Block Erase (32K bytes) Block Erase (64K bytes) Chip Erase Abbr. Code P25Q40H P25Q40SH FREAD READ DREAD 2READ QREAD 4READ WREAD 0Bh 03h 3Bh BBh 6Bh EBh E7h √ √ √ 1 dummy bytes √ 3 dummy bytes not support √ √ √ 1\2 dummy bytes √ 3\5 dummy bytes √ PE SE BE32 BE64 81h 20h 52h D8h 60h C7h 02h A2h 32h 75h B0h 7Ah 30h √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ not support √ √ not support √ not support WREN WRDI VWREN SBLK SBULK RDBLOCK GBLK GBULK 06h 04h 50h 36h 39h 3Dh 7Eh 98h √ √ √ not support not support not support not support not support √ √ √ √ √ √ √ √ ERSCUR PRSCUR RDSCUR 44h 42h 48h √ √ √ √ √ √ CE Page Program Dual-IN Page Program Quad page program PP 2PP QPP Program/Erase Suspend PES Program/Erase Resume PER Protection Write Enable Write Disable Volatile SR Write Enable Individual Block Lock Individual Block Unlock Read Block Lock Status Global Block Lock Global Block Unlock Security Erase Security Registers Program Security Registers Read Security Registers Puya Semiconductor Page 7 of 11 Puya Flash Application Note Status Register Read Status Register Read Status Register-1 Read Configure Register Active Status Interrupt Write Status Register Write Configure Register Data Buffer Buffer clear Buffer Load Buffer Read Buffer Write Buffer to Main Memory Page Program Other Commands Reset Enable Reset Enable QPI Read Manufacturer/device ID Read Manufacture ID Dual Read Manufacture ID Quad Read Manufacture ID Deep Power-down RDSR RDSR1 RDCR ASI \ \ 05h 35h 15h 25h \ \ √ √ √ √ not support √ √ not support Please refer to Table 2-3-2 Please refer to Table 2-4-2 BFCR BFLD BFRD BFWR BFPP 9Eh 9Ah 9Bh 9Ch 9Dh not support not support not support not support not support √ √ √ √ √ RSTEN RST QPIEN RDID REMS DREMS QREMS DP 66h 99h 38h 9Fh 90h 92h 94h B9h √ √ not support √ √ √ √ √ √ √ √ √ √ √ √ √ Release Deep Power-down / Read Electronic ID RDP/RES ABh √ √ Set burst length Read SFDP Release read enhanced Read unique ID Other STR QPI Instructions SBL RDSFDP RUID 77h 5Ah FFh 4Bh √ √ √ √ √ √ √ √ \ \ not support √ Puya Semiconductor Page 8 of 11 Puya Flash Application Note 4 DC Comparison Table 10. P25Q40H DC Typical Value @25C Sym. Parameter Conditions IDPD Deep power down current CS#=Vcc, all other inputs at 0V or Vcc ISB Standby current CS#, HOLD#, WP#=VIH all inputs at CMOS levels f=1MHz; SO=Open Low power read current ICC1 (03h) f=33MHz; SO=Open f=50MHz; SO=Open ICC2 Read current (0Bh) f=85MHz; SO=Open ICC3 Program current CS#=Vcc ICC4 CE Erase current CS#=Vcc Typ.(3.0V) 0.3 9 0.5 1 1 1.5 1.5 2 Units uA uA mA mA mA mA mA mA Table 10. P25Q40SH DC Typical Value @25C Sym. Parameter Conditions IDPD Deep power down current CS#=Vcc, all other inputs at 0V or Vcc ISB Standby current CS#, HOLD#, WP#=VIH all inputs at CMOS levels f=33MHz(03h); IOUT=0mA Read current(STR) ICC1 f=85MHz; IOUT=0mA (1, 2, 4 IO) f=120MHz; IOUT=0mA ICC2 Program current CS#=Vcc ICC3 Erase current CS#=Vcc Typ.(3.0V) 0.6 10 2 5 6 2.5 2.5 Units uA uA mA mA mA mA mA Puya Semiconductor Page 9 of 11 Puya Flash Application Note 5 AC Comparison 5.1 Erase/Program Timing PUYA P25Q40H has much shorter Erase time for page/sector/block/chip. Table 5-1 AC parameters for program and erase Sym. TESL(6) TPSL(6) TPRS(4) TERS(5) tPP tPE tSE tBE1 tBE2 tCE Parameter (1.65V to 3.6V ) Min. Erase Suspend Latency Program Suspend Latency Latency between Program Resume and next Suspend Latency between Erase Resume and next Suspend Page program time (up to 256 bytes) Page erase time Sector erase time Block erase time for 32K bytes Block erase time for 64K bytes Chip erase time P25Q40H Typ. Max. 30 30 20 20 2 8 8 8 8 8 3 12 12 12 12 12 P25Q40SH Min. Typ. Max. 30 30 20 20 2 3 16 30 16 30 16 30 16 30 16 30 Units us us us us ms ms ms ms ms ms 6 Conclusion Migrating from P25Q40H to P25Q40SH is straightforward and requires minimal accommodation in regards to either system software or hardware. Additionally, P25Q40SH support more functions such as QPI mode, Individual block protection, Buffer access, etc. P25Q40H SPI flash has much shorter erase time. 7 Reference Documents Table 7-1 shows the datasheet versions used for comparison in this application note. For the most current specification, please refer to the Website at: http://www.puyasemi.com/ Table 7-1 Datasheet Version Table Datasheet P25Q40H P25Q40SH Puya Semiconductor Location Website Website Versions V1.8 V1.1 Page 10 of 11 Puya Flash Application Note 8 Revision History Rev. Date V1.0 2020.12.01 Description Preliminary release Author LSQ Puya Semiconductor Co., Ltd. IMPORTANT NOTICE Puya Semiconductor reserves the right to make changes without further notice to any products or specifications herein. Puya Semiconductor does not assume any responsibility for use of any its products for any particular purpose, nor does Puya Semiconductor assume any liability arising out of the application or use of any its products or circuits. Puya Semiconductor does not convey any license under its patent rights or other rights nor the rights of others. Puya Semiconductor Page 11 of 11