74HC4051PW

74HC4051PW ※ ※ ※ Qualified for Automotive Applications Wide Analog Input Voltage Range of 5 V Max Low ON Resistance 70 Typical (VCC  V = 4.5 V) EE  40 Typical (VCC  VEE = 9 V)  ※ ※ ※ Low Crosstalk Between Switches ※ Operation Control Voltage = 2 V to 6 V ※ Switch Voltage = 0 V to 10 V ※ M OR PW PACKAGE (TOP VIEW) Fast Switching and Propagation Speeds CHANNEL I/O A4 CHANNEL I/O A6 Break-Before-Make Switching High Noise Immunity N IL = 30%, N IH = 30% of VCC , VCC = 5 V COM OUT/IN A 3 14 VCC CHANNEL I/O A2 CHANNEL I/O A1 CHANNEL I/O A7 4 13 CHANNEL I/O A0 CHANNEL I/O A5 5 12 CHANNEL I/O A3 E 6 11 ADDRESS SEL S0 VEE GND 7 10 ADDRESS SEL S1 8 9 ADDRESS SEL S2 1 16 2 15 SOP-16 description This device is a digitally controlled analog switch that utilizes silicon-gate CMOS technology to achieve operating speeds similar to LSTTL, with the low power consumption of standard CMOS integrated circuits. This analog multiplexer/demultiplexer controls analog voltages that may vary across the voltage supply range (i.e., VCC to VEE ). These bidirectional switches allow any analog input to be used as an output and vice versa. The switches have low ON resistance and low OFF leakages. In addition, the device has an enable control (E) that, when high, disables all switches to their OFF state. www.slkormicro.com 1 74HC4051PW FUNCTION TABLE INPUTS ON CHANNEL(S) E S2 S1 L L L L A0 L L L H A1 L L H L A2 L L H H A3 L H L L A4 L H L H A5 L H H L A6 L H H H A7 H X X X None S0 X = Don't care logic diagram (positive logic) CHANNEL I/O VCC A7 A6 A5 A4 A3 A2 A1 A0 16 4 2 5 1 12 15 14 13 TG TG S0 11 TG S 1 S2 TG Binary To 1 of 8 Decoder With Enable 10 Logic Level Conversion 9 3 TG TG TG E 6 TG 8 7 GND VEE www.slkormicro.com 2 COM OUT/IN A 74HC4051PW absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC  VEE (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 10.5 V ......................................................... Supply voltage range, VCC . 0.5 V to 7 V ........................................................ . +0.5 V to 7 V Supply voltage range, VEE + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA Input clamp current, I IK (V I < 0.5 V or V I > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 mA Output clamp current, IOK (V O < VEE  0.5 V or V O > VCC + 0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 mA Switch current (V I > VEE  0.5 V or V I < VCC Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . .50 mA VEE current, IEE ....................................................................... . . 20 mA Package thermal impedance,JA (see Note 2): M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108C/W Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50C Lead temperature (during soldering): At distance 1/16 1/32 inch (1.59 0.79 mm) from case for 10 s max . . . . . . . . . . . . . . . . . . . . . . . 300C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages referenced to GND unless otherwise specified. 2. The package thermal impedance is calculated in accordance with JESD 51-7. † recommended operating conditions (see Note 3) MIN VCC Supply voltage (see Note 4) Supply voltage, VCC  VEE VEE (see Figure 1) Supply voltage, (see Note 4 and Figure 2) VCC = 2 V VIH VCC = 4.5 V High-level input voltage High level VCC = 6 V VCC = VIL VI Input control voltage VIS Analog switch I/O voltage tt TA NOTES: Operating free-air temperature 3. 4. V 2 10 V 0 6 V 1.5 3.15 V 4.2 2V 0.5 1.35 0 VCC V VEE VCC V VCC = 2 V 0 1000 VCC = 4.5 V 0 500 VCC = 6 V 0 400 40 125 All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. In certain applications, the external load resistor current may include both VCC and signal-line components. To avoid drawing VCC current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6 V (calculated from ron values shown in electrical characteristics table). No VCC current flows through R L if the switch current flows into the COM OUT/IN A terminal. www.slkormicro.com 3 V 1.8 VCC = 6 V Input transition (rise and fall) time UNIT 6 VCC = 4.5 V Low-level input voltage Low level MAX 2 ns C 74HC4051PW recommended operating area as a function of supply voltages GND)  V CC  8 6 HCT HC 4 2 6 HCT 2 0 0 2 4 6 8 10 HC 4 (V (V GND)  V CC  8 0 12 0 2 (VCC  V )  V EE PARAMETER over recommended operating VEE free-air 0V See Figure VIS = VCC or VEE 8 VIS = VCC to VEE ∆ Ron IIZ Between any two channels For switch OFF: When VIS = VCC , VOS = VEE; When VIS = VEE , VOS = VCC For switch ON: All applicable combinations of VIS and VOS ICC www.slkormicro.com (unless TA = 40C TO 125C UNIT TYP MAX 4.5 V 70 160 240 MIN MAX 0V 6V 60 140 210 4.5 V 4.5 V 40 120 180 0V 4.5 V 90 180 270 0V 6V 80 160 240 4.5 V 4.5 V 45 130 195 0V 4.5 V 10 8.5 0V 6V 4.5 V 4.5 V 0V 6V   5 0.2 2 5 V 5V 0.4 4 0V 6V 0.1 1 When VIS = VEE, VOS = VCC 0V 6V 8 160 When VIS = VCC, VOS = VEE 5 V 5V 16 320 VI = VCC or GND IO = 0, VI 0, or GND = VCC range A voltage levels, VI = VIH or VIL IIL temperature T A = 25C VCC MIN Ron 8 Figure 2 TEST CONDITIONS IO = 1 mA, VI = VIH or V IL, 6 (VEE  GND)  V Figure 1 electrical characteristics otherwise noted) 4 A A 4 74HC4051PW switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VEE V CL = 15 pF tpdpd IN OUT CC 5V 0V CL = 50 pF 4.5 V MIN TYP 4 ten CL = 50 pF 4.5 V 12 18 6V 10 15 8 12 4.5 V 225 340 45 68 6V 38 57 32 48 4.5 V 5V tdis 0V CL = 50 pF 4.5 V CI Control ns 19 225 340 4.5 V 45 68 6V 38 57 4.5 V 32 48 10 10 CL = 50 pF ns 19 4.5 V 2V OUT ns 4.5 V CL = 15 pF ADDRESS SEL or E MAX 90 5V 0V UNIT MIN 60 2V OUT MAX 2V CL = 15 pF ADDRESS SEL or E TA = 40C TO 125C TA = 25C ns pF operating characteristics, VCC = 5 V, T A = 25C, Input t r, t f = 6 ns PARAMETER Cpd NOTE 5: 50 Power dissipation capacitance (see Note 5) Cpd is used to determine the dynamic power consumption, per package. 2f PD = Cpd VCC 2 fI + (C L + C S) O VCC f = output frequency O fI = input frequency CL = output load capacitance C = switch capacitance S VCC = supply voltage www.slkormicro.com TYP 5 UNIT pF 74HC4051PW analog channel characteristics, T A PARAMETER TEST CONDITIONS CI Switch input capacitance CCOM Common output capacitance fmax Minimum switch frequency response at 3 dB See Figure 3 and Figure 9, and Notes 6 and 7 Sine wave distortion Sine-wave See Figure 4 E or ADDRESS SEL to switch feed-through noise 6. VEE See Figure 55, and Notes 7 and 8 Switch OFF signal feed through NOTES: = 25C See Figure 6 and Figure 10, and Notes 7 and 8 VCC MIN TYP MAX UNIT 5 pF 25 pF 2.25 V 2.25 V 145 4.5 V 4.5 V 180 2.25 V 2.25 V 0.035 4.5 V 4.5 V 0.018 2.25 V 2.25 V (TBD) 4.5 V 4.5 V (TBD) 2.25 V 2.25 V 73 4.5 V 4.5 V 75 MHz % mV dB Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz. 7. VIS is centered at (VCC  VEE)/2. 8. Adjust input for 0 dBm. PARAMETER MEASUREMENT INFORMATION VCC VIS 0.1 mF VCC VOS Switch ON 50 10 pF Sine Wave dB Meter VIS VIS VI = VIH VOS 10 k 50 pF Distortion Meter VCC/2 VCC/2 fIS = 1 kHz to 10 kHz Figure 3. Frequency-Response Test Circuit www.slkormicro.com 10 mF Switch ON Figure 4. Sine-Wave Distortion Test Circuit 6 74HC4051PW PARAMETER MEASUREMENT INFORMATION E VCC f IS 1-MHz Sine Wave VPP VOS 600 W VCC /2 Switch Alternating ON and OFF tr , tf6 ns fCONT = 1 MHz 50% Duty Cycle 0.1F VOS 50 pF Scope VC = VIL R R VCC/2 VCC/2 VCC/2 Figure 5. Control to Switch Feedthrough Noise Test Circuit www.slkormicro.com Switch OFF VIS 600 W R = 50 C = 10 pF VCC VOS C dB Meter Figure 6. Switch OFF Signal Feedthrough Test Circuit 7 74HC4051PW PARAMETER MEASUREMENT INFORMATION VCC Test Point From Output Under Test PARAMETER S1 ten RL = 1 k tdis CL (see Note A) S2 S1 S2 tPZH Open Closed tPZL Closed Open tPHZ Open Closed tPLZ Closed Open Open Open tpd VEE LOAD CIRCUIT Input 50% VCC VCC 50% VCC V t PLH In-Phase Output 50% 10% tPHL 90% Out-of-Phase Output 90% tr 50% VCC 10% V OL tf 50% 10% 90% tr tf VOL A. B. C. For clock inputs, fmax is measured with the input duty cycle at 50%. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as t tPLH and tPHL are the same as t www.slkormicro.com en pd . . 8 CC 10% VOL t PHZ 50% V 90% CC C L includes probe and test-fixture capacitance. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50, t r = 6 ns, t f = 6 ns. E. H. 50% VCC VOLTAGE WAVEFORMS OUTPUT ENABLE AND DISABLE TIMES D. 0V tPLZ t PZH Output Waveform 2 (see Note B) CC V Output Waveform 1 (see Note B) VOH VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: tPZL VOH tPLH 50% VCC 10% 50% V 50% VCC EE tPHL 90% VCC Output Control V OH 0 V 74HC4051PW Figure 7. Load Circuit and Voltage Wavefor TYPICAL CHARACTERISTICS 120 ON Resistance    100 80 VCC  V = 4.5 V EE 60 VCC  VEE = 6V 40 VCC  VEE = 9 V 20 1 2 3 4 5 6 7 8 9 Input Signal Voltage  V Figure 8. Typical ON Resistance vs Input Signal Voltage 0 0 VCC = 4.5 V GND = 4.5 V VEE = 4.5 V RL = 50 PIN 12 TO 3 4 20 dB dB 2 VCC = 2.25 V GND = 2.25 V VEE = 2.25 V RL = 50 PIN 12 TO 3 6 VCC = 2.25 V GND = 2.25 V VEE = 2.25 V RL = 50 PIN 12 TO 3 40 60 8 VCC = 4.5 V GND = 4.5 V VEE = 4.5 V RL = 50 PIN 12 TO 3 80 10 10K 100K 1M 10M 100M Frequency  Hz 10K 100K 1M Frequency  Hz Figure 9. Channel ON Bandwidth www.slkormicro.com 100 10M 100M Figure 10. Channel OFF Feedthrough 9 74HC4051PW SOP-16 Package Outline Dimensions D A3 A2 A A1 b E E1 e SYMBOL 0.25 c θ L L1 www.slkormicro.com 10 MILLIMETER MIN NOM MAX A - - 1.75 A1 0.10 - 0.25 A2 A3 0.97 1.07 1.60 b 0.35 1.02 - c 0.19 - D 9.80 E 5.80 3.80 E1 e 0.46 0.25 10.0 6.00 6.20 4.00 1.27BSC L L1 0.70 θ 0 0.5 1.00 1.40BSC - 8°