GD32F105VGT6

GigaDevice Semiconductor Inc. GD32F105xx ARM® Cortex™-M3 32-bit MCU Datasheet GD32F105xx Datasheet Table of Contents Table of Contents ........................................................................................................... 1 List of Figures ................................................................................................................ 3 List of Tables .................................................................................................................. 4 1. General description ................................................................................................. 5 2. Device overview ....................................................................................................... 6 2.1. Device information ...................................................................................................... 6 2.2. Block diagram .............................................................................................................. 8 2.3. Pinouts and pin assignment ....................................................................................... 9 2.4. Memory map .............................................................................................................. 12 2.5. Clock tree ................................................................................................................... 16 2.6. Pin definitions ............................................................................................................ 17 2.6.1. GD32F105Zx LQFP144 pin definitions ................................................................................. 17 2.6.2. GD32F105Vx LQFP100 pin definitions ................................................................................ 26 2.6.3. GD32F105Rx LQFP64 pin definitions .................................................................................. 33 3. Functional description .......................................................................................... 38 3.1. ARM® Cortex™-M3 core ........................................................................................... 38 3.2. On-chip memory ........................................................................................................ 38 3.3. Clock, reset and supply management ...................................................................... 39 3.4. Boot modes ................................................................................................................ 39 3.5. Power saving modes ................................................................................................. 40 3.6. Analog to digital converter (ADC) ............................................................................ 40 3.7. Digital to analog converter (DAC) ............................................................................. 41 3.8. DMA ............................................................................................................................ 41 3.9. General-purpose inputs/outputs (GPIOs) ................................................................ 41 3.10. Timers and PWM generation ................................................................................. 42 3.11. Real time clock (RTC) ............................................................................................ 43 3.12. Inter-integrated circuit (I2C) .................................................................................. 43 3.13. Serial peripheral interface (SPI) ............................................................................ 44 3.14. Universal synchronous asynchronous receiver transmitter (USART) ............... 44 3.15. Inter-IC sound (I2S) ................................................................................................ 44 1 GD32F105xx Datasheet 3.16. Universal serial bus full-speed (USBFS) .............................................................. 45 3.17. Controller area network (CAN) .............................................................................. 45 3.18. External memory controller (EXMC) ..................................................................... 45 3.19. Debug mode ........................................................................................................... 46 3.20. Package and operation temperature ..................................................................... 46 4. Electrical characteristics ....................................................................................... 47 4.1. Absolute maximum ratings ....................................................................................... 47 4.2. Recommended DC characteristics ........................................................................... 47 4.3. Power consumption .................................................................................................. 48 4.4. EMC characteristics .................................................................................................. 49 4.5. Power supply supervisor characteristics ................................................................ 49 4.6. Electrical sensitivity .................................................................................................. 50 4.7. External clock characteristics .................................................................................. 51 4.8. Internal clock characteristics ................................................................................... 52 4.9. PLL characteristics.................................................................................................... 53 4.10. Memory characteristics ......................................................................................... 53 4.11. GPIO characteristics .............................................................................................. 53 4.12. ADC characteristics ............................................................................................... 54 4.13. DAC characteristics ............................................................................................... 54 4.14. I2C characteristics ................................................................................................. 54 4.15. SPI characteristics ................................................................................................. 55 5. Package information.............................................................................................. 56 6. Ordering information ............................................................................................. 58 7. Revision history ..................................................................................................... 59 2 GD32F105xx Datasheet List of Figures Figure 2-1. GD32F105xx block diagram .................................................................................................... 8 Figure 2-2. GD32F105Zx LQFP144 pinouts ............................................................................................... 9 Figure 2-3. GD32F105Vx LQFP100 pinouts ............................................................................................. 10 Figure 2-4. GD32F105Rx LQFP64 pinouts ............................................................................................... 11 Figure 2-5. GD32F105xx clock tree .......................................................................................................... 16 Figure 5-1. LQFP package outline............................................................................................................ 56 3 GD32F105xx Datasheet List of Tables Table 2-1. GD32F105xx devices features and peripheral list .................................................................. 6 Table 2-2. GD32F105xx devices features and peripheral list (continued) ............................................. 7 Table 2-3. GD32F105xx memory map ...................................................................................................... 12 Table 2-4. GD32F105Zx LQFP144 pin definitions ................................................................................... 17 Table 2-5. GD32F105Vx LQFP100 pin definitions ................................................................................... 26 Table 2-6. GD32F105Rx LQFP64 pin definitions .................................................................................... 33 Table 4-1. Absolute maximum ratings ..................................................................................................... 47 Table 4-2. DC operating conditions ......................................................................................................... 47 Table 4-3. Power consumption characteristics ...................................................................................... 48 Table 4-4. EMS characteristics ................................................................................................................. 49 Table 4-5. EMI characteristics .................................................................................................................. 49 Table 4-6. Power supply supervisor characteristics.............................................................................. 49 Table 4-7. ESD characteristics ................................................................................................................. 50 Table 4-8. Static latch-up characteristics ................................................................................................ 50 Table 4-9. High speed external clock (HXTAL) generated from a crystal/ceramic characteristics ... 51 Table 4-10. Low speed external clock (LXTAL) generated from a crystal/ceramic characteristics .. 51 Table 4-11. High speed internal clock (IRC8M) characteristics ............................................................ 52 Table 4-12. Low speed internal clock (IRC40K) characteristics ........................................................... 52 Table 4-13. PLL characteristics ................................................................................................................ 53 Table 4-14. Flash memory characteristics .............................................................................................. 53 Table 4-15. I/O port characteristics .......................................................................................................... 53 Table 4-16. ADC characteristics ............................................................................................................... 54 Table 4-17. DAC characteristics ............................................................................................................... 54 Table 4-18. I2C characteristics ................................................................................................................. 54 Table 4-19. SPI characteristics ................................................................................................................. 55 Table 5-1. LQFP package dimensions ..................................................................................................... 57 Table 6-1. Part ordering code for GD32F105xx devices ........................................................................ 58 Table 7-1. Revision history ....................................................................................................................... 59 4 GD32F105xx Datasheet 1. General description The GD32F105xx device belongs to the connectivity line of GD32 MCU Family. It is a 32-bit general-purpose microcontroller based on the ARM® Cortex™-M3 RISC core with enhanced connectivity performance and best ratio in terms of processing power, reduced power consumption and peripheral set. The Cortex™-M3 is a next generation processor core which is tightly coupled with a Nested Vectored Interrupt Controller (NVIC), SysTick timer and advanced debug support. The GD32F105xx device incorporates the ARM® Cortex™-M3 32-bit processor core operating at 108 MHz frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up to 1 MB on-chip Flash memory and up to 96 KB SRAM memory. An extensive range of enhanced I/Os and peripherals connected to two APB buses. The devices offer up to two 12-bit ADCs, up to two 12-bit DACs, up to four general-purpose 16-bit timers, two basic timers plus two PWM advanced-control timer, as well as standard and advanced communication interfaces: up to three SPIs, two I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS. The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C temperature range. Several power saving modes provide the flexibility for maximum optimization between wakeup latency and power consumption, an especially important consideration in low power applications. The above features make the GD32F105xx devices suitable for a wide range of applications, especially in areas such as industrial control, motor drives, power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS, LED display and so on. 5 GD32F105xx Datasheet 2. Device overview 2.1. Device information Table 2-1. GD32F105xx devices features and peripheral list GD32F105xx Part Number RB RC RD RE RF RG V8 VB Flash (KB) 64 128 256 384 512 768 1024 64 128 SRAM (KB) 64 64 96 96 96 96 96 64 64 ADC Connectivity Timers R8 GPTM(16 4 4 4 4 4 4 4 4 4 bit) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) Advanced 1 1 1 2 2 2 2 1 1 TM(16 bit) (0) (0) (0) (0,7) (0,7) (0,7) (0,7) (0) (0) SysTick 1 1 1 1 1 1 1 1 1 Basic TM(16 2 2 2 2 2 2 2 2 2 bit) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) Watchdog 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 U(S)ART 5 5 5 5 5 5 5 5 5 I2C 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 3 (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) 2 2 2 2 2 2 2 2 2 (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) CAN 2.0B 2 2 2 2 2 2 2 2 2 USBFS 1 1 1 1 1 1 1 1 1 GPIO 51 51 51 51 51 51 51 80 80 EXMC 0 0 0 0 0 0 0 1 1 EXTI 16 16 16 16 16 16 16 16 16 Units 2 2 2 2 2 2 2 2 2 Channels 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 I2S DAC Package LQFP64 LQFP100 6 GD32F105xx Datasheet Table 2-2. GD32F105xx devices features and peripheral list (continued) GD32F105xx Part Number VD VE VF VG ZC ZD ZE ZF ZG Flash (KB) 256 384 512 768 1024 256 384 512 768 1024 SRAM (KB) 96 96 96 96 96 96 96 96 96 96 ADC Connectivity Timers VC GPTM(16 4 4 4 4 4 4 4 4 4 4 bit) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) (1-4) Advanced 1 2 2 2 2 2 2 2 2 2 TM(16 bit) (0) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) (0,7) SysTick 1 1 1 1 1 1 1 1 1 1 Basic TM(16 2 2 2 2 2 2 2 2 2 2 bit) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) (5-6) Watchdog 2 2 2 2 2 2 2 2 2 2 RTC 1 1 1 1 1 1 1 1 1 1 U(S)ART 5 5 5 5 5 5 5 5 5 5 I2C 2 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 3 3 (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) 2 2 2 2 2 2 2 2 2 2 (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) (1-2) CAN 2.0B 2 2 2 2 2 2 2 2 2 2 USBFS 1 1 1 1 1 1 1 1 1 1 GPIO 80 80 80 80 80 112 112 112 112 112 EXMC 1 1 1 1 1 1 1 1 1 1 EXTI 16 16 16 16 16 16 16 16 16 16 Units 2 2 2 2 2 2 2 2 2 2 Channels 16 16 16 16 16 16 16 16 16 16 DAC 2 2 2 2 2 2 2 2 2 2 I2S Package LQFP100 LQFP144 7 GD32F105xx Datasheet 2.2. Block diagram Figure 2-1. GD32F105xx block diagram SW/JTAG TPIU NVIC ICode DCode System ARM Cortex-M3 Processor Fmax:108MHz POR/ PDR Flash Memory Controller Ibus Flash Memory PLL F max : 108MHz Dbus FMC Master Master Slave EXMC Slave Slave CRC LDO 1.2V RCU AHB Peripherals Slave AHB Matrix GP DMA 12 chs USBFS SRAM Controller AHB to APB Bridge2 IRC 8MHz SRAM HXTAL 3-25MHz AHB to APB Bridge1 LVD Interrput request CAN0 USART0 Slave 12-bit SAR ADC Slave SPI0 WWDGT ADC0~1 TIMER1~3 EXTI SPI1~2 GPIOA USART1~2 GPIOB I2C0 Powered By V DDA GPIOE APB1: Fmax = 54MHZ GPIOD APB2: Fmax = 108MHz GPIOC Powered By VDDA I2C1 FWDGT RTC GPIOF DAC GPIOG TIMER4~6 TIMER0 UART3~4 TIMER7 CAN1 8 GD32F105xx Datasheet 2.3. Pinouts and pin assignment Figure 2-2. GD32F105Zx LQFP144 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 VSS_10 VDD_10 PD6 PD7 PG9 PG10 PG11 PG12 PG13 PG14 VSS_11 VDD_11 PG15 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 144143142141140139138137136135134133 132131130129128127126125124123122121120 119118117116115114113112111110109 PE2 1 108 PE3 PE4 2 107 VSS_2 3 106 NC PE5 PE6 4 105 PA13 5 104 PA12 VBAT 6 103 PA11 PC13-TAMPER-RTC PC14-OSC32IN 7 102 PA10 8 101 PA9 PC15-OSC32OUT 9 100 PA8 PF0 10 99 PC9 PF1 11 98 PC8 PF2 12 97 PC7 PF3 PF4 13 96 PC6 14 95 VDD_9 PF5 15 94 VSS_9 VSS_5 16 93 PG8 92 PG7 91 PG6 90 PG5 89 PG4 88 PG3 VDD_2 VDD_5 17 PF6 18 PF7 19 PF8 20 PF9 21 PF10 22 87 PG2 OSCIN 23 86 PD15 OSCOUT GigaDevice GD32F105Zx LQFP144 24 85 PD14 NRST 25 84 VDD_8 PC0 26 83 VSS_8 PC1 27 82 PD13 PC2 28 81 PD12 PC3 VSSA 29 80 PD11 30 79 PD10 VREFVREF+ 31 78 PD9 32 77 PD8 VDDA 33 76 PB15 PA0_WKUP 34 75 PB14 PA1 35 74 PB13 PA2 36 73 PB12 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD_1 VSS_1 PB11 PB10 PE15 PE13 PE14 PE12 PE11 VDD_7 PE10 VSS_7 PE8 PE9 PE7 PG1 PG0 PF15 PF14 VDD_6 PF13 VSS_6 PF12 PB2 PF11 PB1 PC5 PB0 PA7 PC4 PA6 PA5 VDD_4 PA4 VSS_4 PA3 9 GD32F105xx Datasheet Figure 2-3. GD32F105Vx LQFP100 pinouts PA14 PA15 PC10 PC11 PC12 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PB4 PB3 PB5 PB6 PB7 BOOT0 PB8 PB9 PE0 PE1 VSS_3 VDD_3 PE2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 PE3 PE4 2 74 VSS_2 3 73 NC PE5 PE6 4 72 PA13 5 71 PA12 VBAT 6 PC13-TAMPER-RTC PC14-OSC32IN 7 70 69 PA10 8 68 PA9 PC15-OSC32OUT 9 67 PA8 VSS_5 10 66 PC9 VDD_5 11 65 PC8 64 PC7 63 PC6 14 62 PD15 OSCIN 12 GigaDevice GD32F105Vx LQFP100 VDD_2 PA11 OSCOUT NRST PC0 13 15 61 PD14 PC1 16 60 PD13 PC2 PC3 17 59 PD12 18 58 PD11 VSSA 19 57 PD10 VREFVREF+ 20 56 PD9 21 55 PD8 VDDA 22 54 PB15 PA0-WKUP 23 53 PB14 PA1 24 52 PB13 PA2 25 51 PB12 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSS_1 VDD_1 PB11 PB10 PE15 PE14 PE13 PE11 PE12 PE10 PE9 PE8 PE7 PB2 PB1 PC5 PB0 PA7 PC4 PA6 PA5 PA4 VDD_4 PA3 VSS_4 10 GD32F105xx Datasheet Figure 2-4. GD32F105Rx LQFP64 pinouts PA14 PA15 PC10 PC11 PC12 PB3 PD2 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VBAT 1 48 VDD_2 PC13-TAMPER-RTC 2 47 VSS_2 PA13 PC14-OSC32IN 3 46 PC15-OSC32OUT PD0-OSCIN 4 45 PA12 5 44 PA11 PD1 OSCOUT 6 43 PA10 42 PA9 NRST PC0 7 PC1 9 PC2 PC3 VSSA GigaDevice GD32F105Rx LQFP64 41 PA8 40 PC9 10 39 PC8 11 38 PC7 12 37 PC6 VDDA 13 36 PB15 PA0-WKUP 14 35 PB14 PA1 15 34 PB13 PA2 16 33 PB12 8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VSS_1 VDD_1 PB11 PB10 PB2 PB1 PB0 PC5 PC4 PA7 PA6 PA5 PA4 VDD_4 PA3 VSS_4 11 GD32F105xx Datasheet 2.4. Memory map Table 2-3. GD32F105xx memory map Pre-defined Regions Bus External device AHB Address Peripherals 0xA000 0000 - 0xA000 0FFF EXMC - SWREG 0x9000 0000 - 0x9FFF FFFF EXMC - PC CARD 0x7000 0000 - 0x8FFF FFFF EXMC - NAND External RAM EXMC 0x6000 0000 - 0x6FFF FFFF NOR/PSRAM/SRA M Peripheral AHB 0x5000 0000 - 0x5003 FFFF USBFS 0x4008 0000 - 0x4FFF FFFF Reserved 0x4004 0000 - 0x4007 FFFF Reserved 0x4002 BC00 - 0x4003 FFFF Reserved 0x4002 B000 - 0x4002 BBFF Reserved 0x4002 A000 - 0x4002 AFFF Reserved 0x4002 8000 - 0x4002 9FFF Reserved 0x4002 6800 - 0x4002 7FFF Reserved 0x4002 6400 - 0x4002 67FF Reserved 0x4002 6000 - 0x4002 63FF Reserved 0x4002 5000 - 0x4002 5FFF Reserved 0x4002 4000 - 0x4002 4FFF Reserved 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF CRC 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF Reserved 0x4002 2400 - 0x4002 27FF Reserved 0x4002 2000 - 0x4002 23FF FMC 0x4002 1C00 - 0x4002 1FFF Reserved 0x4002 1800 - 0x4002 1BFF Reserved 0x4002 1400 - 0x4002 17FF Reserved 0x4002 1000 - 0x4002 13FF RCU 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 12 GD32F105xx Datasheet Pre-defined Regions Bus APB2 APB1 Address Peripherals 0x4001 8000 - 0x4001 83FF Reserved 0x4001 7C00 - 0x4001 7FFF Reserved 0x4001 7800 - 0x4001 7BFF Reserved 0x4001 7400 - 0x4001 77FF Reserved 0x4001 7000 - 0x4001 73FF Reserved 0x4001 6C00 - 0x4001 6FFF Reserved 0x4001 6800 - 0x4001 6BFF Reserved 0x4001 5C00 - 0x4001 67FF Reserved 0x4001 5800 - 0x4001 5BFF Reserved 0x4001 5400 - 0x4001 57FF Reserved 0x4001 5000 - 0x4001 53FF Reserved 0x4001 4C00 - 0x4001 4FFF Reserved 0x4001 4800 - 0x4001 4BFF Reserved 0x4001 4400 - 0x4001 47FF Reserved 0x4001 4000 - 0x4001 43FF Reserved 0x4001 3C00 - 0x4001 3FFF Reserved 0x4001 3800 - 0x4001 3BFF USART0 0x4001 3400 - 0x4001 37FF TIMER7 0x4001 3000 - 0x4001 33FF SPI0 0x4001 2C00 - 0x4001 2FFF TIMER0 0x4001 2800 - 0x4001 2BFF ADC1 0x4001 2400 - 0x4001 27FF ADC0 0x4001 2000 - 0x4001 23FF GPIOG 0x4001 1C00 - 0x4001 1FFF GPIOF 0x4001 1800 - 0x4001 1BFF GPIOE 0x4001 1400 - 0x4001 17FF GPIOD 0x4001 1000 - 0x4001 13FF GPIOC 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF GPIOA 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF AFIO 0x4000 CC00 - 0x4000 FFFF Reserved 0x4000 C800 - 0x4000 CBFF Reserved 0x4000 C400 - 0x4000 C7FF Reserved 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF DAC 0x4000 7000 - 0x4000 73FF PMU 13 GD32F105xx Datasheet Pre-defined Regions Bus Address Peripherals 0x4000 6C00 - 0x4000 6FFF BKP 0x4000 6800 - 0x4000 6BFF CAN1 0x4000 6400 - 0x4000 67FF CAN0 0x4000 6000 - 0x4000 63FF SRAM AHB Reserved 0x4000 5800 - 0x4000 5BFF I2C1 0x4000 5400 - 0x4000 57FF I2C0 0x4000 5000 - 0x4000 53FF UART4 0x4000 4C00 - 0x4000 4FFF UART3 0x4000 4800 - 0x4000 4BFF USART2 0x4000 4400 - 0x4000 47FF USART1 0x4000 4000 - 0x4000 43FF Reserved 0x4000 3C00 - 0x4000 3FFF SPI2/I2S2 0x4000 3800 - 0x4000 3BFF SPI1/I2S1 0x4000 3400 - 0x4000 37FF Reserved 0x4000 3000 - 0x4000 33FF FWDGT 0x4000 2C00 - 0x4000 2FFF WWDGT 0x4000 2800 - 0x4000 2BFF RTC 0x4000 2400 - 0x4000 27FF Reserved 0x4000 2000 - 0x4000 23FF Reserved 0x4000 1C00 - 0x4000 1FFF Reserved 0x4000 1800 - 0x4000 1BFF Reserved 0x4000 1400 - 0x4000 17FF TIMER6 0x4000 1000 - 0x4000 13FF TIMER5 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF Reserved 0x2003 0000 - 0x2005 FFFF Reserved 0x2002 0000 - 0x2002 FFFF Reserved 0x2001 C000 - 0x2001 FFFF Reserved 0x2001 8000 - 0x2001 BFFF Reserved 0x2000 0000 - 0x2000 4FFF AHB bytes 0x4000 5C00 - 0x4000 5FFF 0x2000 5000 - 0x2001 7FFF Code CAN SRAM 512 SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF F000 - 0x1FFF F7FF Boot loader 14 GD32F105xx Datasheet Pre-defined Regions Bus Address Peripherals 0x1FFF C010 - 0x1FFF EFFF 0x1FFF C000 - 0x1FFF C00F 0x1FFF B000 - 0x1FFF BFFF 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved 0x1FFF 0000 - 0x1FFF 77FF Reserved 0x1FFE C010 - 0x1FFE FFFF Reserved 0x1FFE C000 - 0x1FFE C00F Reserved 0x1001 0000 - 0x1FFE BFFF Reserved 0x1000 0000 - 0x1000 FFFF Reserved 0x083C 0000 - 0x0FFF FFFF Reserved 0x0830 0000 - 0x083B FFFF Reserved 0x0810 0000 - 0x082F FFFF 0x0802 0000 - 0x080F FFFF Main Flash 0x0800 0000 - 0x0801 FFFF 0x0030 0000 - 0x07FF FFFF 0x0010 0000 - 0x002F FFFF 0x0002 0000 - 0x000F FFFF Reserved Aliased to Main Flash or Boot loader 0x0000 0000 - 0x0001 FFFF 15 GD32F105xx Datasheet 2.5. Clock tree Figure 2-5. GD32F105xx clock tree (to FMC) USB OTG Prescaler 1,1.5,2,2.5 1 SCS[1:0] CK_FMC CK_IRC8M 8 MHz IRC8M 0 1 PLLSEL PREDV0 0 1 CK_USBFS (to USBFS) 00 /2 3-25 MHz HXTAL 48 MHz ×2,3,4 …,32 PLL CK_PLL 10 AHB Prescaler ÷1,2...512 CK_SYS 108 MHz max CK_AHB 108 MHz max CK_EXMC EXMC enable (to EXMC) HCLK 01 PLLMF AHB enable /1,2,3… 15,16 (to AHB bus,Cortex-M3,SRAM,DMA) CK_CST Clock Monitor ÷8 (to Cortex-M3 SysTick) FCLK PREDV0SEL EXT1 to CK_OUT (free running clock) CK_HXTAL APB1 Prescaler ÷1,2,4,8,16 CK_APB1 PCLK1 to APB1 peripherals 54 MHz max Peripheral enable ×8..14,16, 20 PLL1 TIMER1,2,3,4,5,6 if(APB1 prescale =1)x1 else x 2 CK_PLL1 ×8..14,16, 20 PLL2 PREDV1 0 CK_PLL2 x2 CK_I2S 1 APB2 Prescaler ÷1,2,4,8,16 CK_RTC 01 (to RTC) 10 RTCSRC[1:0] 40 KHz IRC40K CK_OUT0 CK_APB2 PCLK2 to APB2 peripherals 108 MHz max Peripheral enable I2S1/2SEL PLL2MF 11 32.768 KHz LXTAL to TIMER1,2,3,4, 5,6 PLL1MF /1,2,3… 15,16 /128 CK_TIMERx TIMERx enable TIMER0,7 if(APB2 prescale =1)x1 else x 2 ADC Prescaler ÷2,4,6,8,12,1 6 CK_TIMERx TIMERx enable to TIMER0,7 CK_ADCx to ADC0,1 14 MHz max CK_FWDGT (to FWDGT) 00xx 0100 0101 0110 0111 1000 1001 1010 1011 NO CLK CK_SYS CK_IRC8M CK_HXTAL /2 CK_PLL CK_PLL1 /2 CK_PLL2 EXT1 CK_PLL2 CKOUT0SEL[3:0] Legend: HXTAL: High speed external clock LXTAL: Low speed external clock IRC8M: High speed internal clock IRC40K: Low speed internal clock 16 GD32F105xx Datasheet 2.6. Pin definitions 2.6.1. GD32F105Zx LQFP144 pin definitions Table 2-4. GD32F105Zx LQFP144 pin definitions Pin Name Pins Pin Type (1) I/O Functions description Level(2) Default: PE2 PE2 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT PE6 5 I/O 5VT VBAT 6 P 7 I/O 8 I/O 9 I/O PF0 10 I/O 5VT PF1 11 I/O 5VT PF2 12 I/O 5VT PF3 13 I/O 5VT PF4 14 I/O 5VT PF5 15 I/O 5VT VSS_5 16 P Default: VSS_5 VDD_5 17 P Default: VDD_5 PC14- Default: PE4 Alternate:TRACED1, EXMC_A20 Default: PE5 Alternate:TRACED2, EXMC_A21 Default: PE6 Alternate:TRACED3, EXMC_A22 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN PC15OSC32OU Alternate: TRACED0, EXMC_A19 Default: PC13 RTC OSC32IN Default: PE3 Default: VBAT PC13TAMPER- Alternate: TRACECK, EXMC_A23 Default: PC15 Alternate: OSC32OUT T Default: PF0 Alternate: EXMC_A0 Default: PF1 Alternate: EXMC_A1 Default: PF2 Alternate: EXMC_A2 Default: PF3 Alternate: EXMC_A3 Default: PF4 Alternate: EXMC_A4 Default: PF5 Alternate: EXMC_A5 17 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PF6 PF6 18 I/O PF7 19 I/O PF8 20 I/O PF9 21 I/O PF10 22 I/O OSCIN 23 I OSCOUT 24 O NRST 25 I/O PC0 26 I/O PC1 27 I/O PC2 28 I/O PC3 29 I/O VSSA 30 P Default: VSSA VREF- 31 P Default: VREF- VREF+ 32 P Default: VREF+ VDDA 33 P Default: VDDA Alternate: EXMC_NIORD Default: PF7 Alternate: EXMC_NREG Default: PF8 Alternate: EXMC_NIOWR Default: PF9 Alternate: EXMC_CD Default: PF10 Alternate: EXMC_INTR Default: OSCIN Remap: PD0 Default: OSCOUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC01_IN10 Default: PC1 Alternate: ADC01_IN11 Default: PC2 Alternate: ADC01_IN12 Default: PC3 Alternate: ADC01_IN13 Default: PA0 PA0WKUP 34 I/O Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI Default: PA1 PA1 35 I/O Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1, TIMER4_CH1 Default: PA2 PA2 36 I/O Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2 PA3 37 I/O Default: PA3 Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3, 18 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) TIMER4_CH3 VSS_4 38 P Default: VSS_4 VDD_4 39 P Default: VDD_4 Default: PA4 PA4 40 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, I/O DAC_OUT0 Remap:SPI2_NSS, I2S2_WS PA5 41 Default: PA5 I/O Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 42 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, I/O TIMER7_BKIN Remap: TIMER0_BKIN Default: PA7 PA7 43 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, I/O TIMER7_CH0_ON Remap: TIMER0_CH0_ON PC4 44 I/O PC5 45 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 46 Alternate: ADC01_IN8, TIMER2_CH2, I/O TIMER7_CH1_ON Remap: TIMER0_CH1_ON Default: PB1 PB1 47 Alternate: ADC01_IN9, TIMER2_CH3, I/O TIMER7_CH2_ON Remap: TIMER0_CH2_ON PB2 48 I/O 5VT Default: PB2, BOOT1 PF11 49 I/O 5VT PF12 50 I/O 5VT VSS_6 51 P Default: VSS_6 VDD_6 52 P Default: VDD_6 PF13 53 I/O 5VT PF14 54 I/O 5VT Default: PF11 Alternate: EXMC_NIOS16 Default: PF12 Alternate: EXMC_A6 Default: PF13 Alternate: EXMC_A7 Default: PF14 19 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: EXMC_A8 PF15 55 I/O 5VT PG0 56 I/O 5VT PG1 57 I/O 5VT Default: PF15 Alternate: EXMC_A9 Default: PG0 Alternate: EXMC_A10 Default: PG1 Alternate: EXMC_A11 Default: PE7 PE7 58 I/O 5VT Alternate: EXMC_D4 Remap: TIMER0_ETI Default: PE8 PE8 59 I/O 5VT Alternate: EXMC_D5 Remap: TIMER0_CH0_ON Default: PE9 PE9 60 I/O 5VT Alternate: EXMC_D6 Remap: TIMER0_CH0 VSS_7 61 P Default: VSS_7 VDD_7 62 P Default: VDD_7 Default: PE10 PE10 63 I/O 5VT Alternate: EXMC_D7 Remap: TIMER0_CH1_ON Default: PE11 PE11 64 I/O 5VT Alternate: EXMC_D8 Remap: TIMER0_CH1 Default: PE12 PE12 65 I/O 5VT Alternate: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 PE13 66 I/O 5VT Alternate: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 67 I/O 5VT Alternate: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 68 I/O 5VT Alternate: EXMC_D12 Remap: TIMER0_BKIN Default: PB10 PB10 69 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 20 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PB11 PB11 70 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 71 P Default: VSS_1 VDD_1 72 P Default: VDD_1 Default: PB12 PB12 73 I/O 5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX Default: PB13 PB13 74 I/O 5VT Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX Default: PB14 PB14 75 I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON PB15 76 I/O 5VT PD8 77 I/O 5VT Default: PB15 Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD Default: PD8 Alternate: EXMC_D13 Remap: USART2_TX Default: PD9 PD9 78 I/O 5VT Alternate: EXMC_D14 Remap: USART2_RX Default: PD10 PD10 79 I/O 5VT Alternate: EXMC_D15 Remap: USART2_CK Default: PD11 PD11 80 I/O 5VT Alternate: EXMC_A16 Remap: USART2_CTS Default: PD12 PD12 81 I/O 5VT Alternate: EXMC_A17 Remap: TIMER3_CH0, USART2_RTS Default: PD13 PD13 82 I/O 5VT Alternate: EXMC_A18 Remap: TIMER3_CH1 VSS_8 83 P Default: VSS_8 VDD_8 84 P Default: VDD_8 PD14 85 I/O Default: PD14 5VT Alternate: EXMC_D0 Remap: TIMER3_CH2 21 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PD15 PD15 86 I/O 5VT Alternate: EXMC_D1 Remap: TIMER3_CH3 Default: PG2 PG2 87 I/O 5VT PG3 88 I/O 5VT PG4 89 I/O 5VT PG5 90 I/O 5VT PG6 91 I/O 5VT PG7 92 I/O 5VT PG8 93 I/O 5VT VSS_9 94 P Default: VSS_9 VDD_9 95 P Default: VDD_9 Alternate: EXMC_A12 Default: PG3 Alternate: EXMC_A13 Default: PG4 Alternate: EXMC_A14 Default: PG5 Alternate: EXMC_A15 Default: PG6 Alternate: EXMC_INT1 Default: PG7 Alternate: EXMC_INT2 Default: PG8 Default: PC6 PC6 96 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0 Remap: TIMER2_CH0 Default: PC7 PC7 97 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1 Remap: TIMER2_CH1 Default: PC8 PC8 98 I/O 5VT Alternate: TIMER7_CH2 Remap: TIMER2_CH2 Default: PC9 PC9 99 I/O 5VT Alternate: TIMER7_CH3 Remap: TIMER2_CH3 Default: PA8 PA8 100 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF Default: PA9 PA9 101 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS PA10 102 I/O 5VT PA11 103 I/O 5VT Default: PA10 Alternate: USART0_RX, TIMER0_CH2, USBFS_ID Default: PA11 22 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 104 I/O 5VT Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI I/O 5VT Default: JTMS, SWDIO PA13 105 NC 106 VSS_2 107 P Default: VSS_2 VDD_2 108 P Default: VDD_2 PA14 109 I/O Remap: PA13 - 5VT Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 110 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 111 I/O 5VT Alternate: UART3_TX Remap: USART2_TX, SPI2_SCK, I2S2_CK Default: PC11 PC11 112 I/O 5VT Alternate: UART3_RX Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 113 I/O 5VT Alternate: UART4_TX Remap: USART2_CK, SPI2_MOSI, I2S2_SD Default: PD0 PD0 114 I/O 5VT Alternate: EXMC_D2 Remap: CAN0_RX Default: PD1 PD1 115 I/O 5VT Alternate: EXMC_D3 Remap: CAN0_TX PD2 116 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, UART4_RX Default: PD3 PD3 117 I/O 5VT Alternate: EXMC_CLK Remap: USART1_CTS Default: PD4 PD4 118 I/O 5VT Alternate: EXMC_NOE Remap: USART1_RTS 23 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PD5 PD5 119 I/O 5VT Alternate: EXMC_NWE Remap: USART1_TX VSS_10 120 Default: VSS_10 VDD_10 121 Default: VDD_10 Default: PD6 PD6 122 I/O 5VT Alternate: EXMC_NWAIT Remap: USART1_RX Default: PD7 PD7 123 I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK Default: PG9 PG9 124 I/O 5VT PG10 125 I/O 5VT PG11 126 I/O 5VT PG12 127 I/O 5VT PG13 128 I/O 5VT PG14 129 I/O 5VT VSS_11 130 P Default: VSS_11 VDD_11 131 P Default: VDD_11 PG15 132 I/O 5VT Alternate: EXMC_NE1, EXMC_NCE2 Default: PG10 Alternate: EXMC_NCE3_0, EXMC_NE2 Default: PG11 Alternate: EXMC_NCE3_1 Default: PG12 Alternate: EXMC_NE3 Default: PG13 Alternate: EXMC_A24 Default: PG14 Alternate: EXMC_A25 Default: PG15 Default: JTDO PB3 133 I/O 5VT Alternate:SPI2_SCK, I2S2_CK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 134 I/O 5VT Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 135 I/O Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX Default: PB6 PB6 136 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX 24 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PB7 PB7 137 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX BOOT0 138 I Default: BOOT0 Default: PB8 PB8 139 I/O 5VT Alternate: TIMER3_CH2 Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 140 I/O 5VT Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX Default: PE0 PE0 141 I/O 5VT PE1 142 I/O 5VT VSS_3 143 P Default: VSS_3 VDD_3 144 P Default: VDD_3 Alternate: TIMER3_ETI, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. 25 GD32F105xx Datasheet 2.6.2. GD32F105Vx LQFP100 pin definitions Table 2-5. GD32F105Vx LQFP100 pin definitions Pin Name Pins Pin Type (1) I/O PE2 1 I/O 5VT PE3 2 I/O 5VT PE4 3 I/O 5VT PE5 4 I/O 5VT PE6 5 I/O 5VT VBAT 6 P 7 I/O 8 I/O 9 I/O PC13TAMPERRTC PC14OSC32IN PC15OSC32OU T Functions description Level(2) Default: PE2 Alternate: TRACECK, EXMC_A23 Default: PE3 Alternate: TRACED0, EXMC_A19 Default: PE4 Alternate:TRACED1, EXMC_A20 Default: PE5 Alternate:TRACED2, EXMC_A21 Default: PE6 Alternate:TRACED3, EXMC_A22 Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT VSS_5 10 P Default: VSS_5 VDD_5 11 P Default: VDD_5 OSCIN 12 I OSCOUT 13 O NRST 14 I/O PC0 15 I/O PC1 16 I/O PC2 17 I/O PC3 18 I/O VSSA 19 P Default: VSSA VREF- 20 P Default: VREF- Default: OSCIN Remap: PD0 Default: OSCOUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC01_IN10 Default: PC1 Alternate: ADC01_IN11 Default: PC2 Alternate: ADC01_IN12 Default: PC3 Alternate: ADC01_IN13 26 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) VREF+ 21 P Default: VREF+ VDDA 22 P Default: VDDA Default: PA0 PA0WKUP 23 I/O Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI(3) Default: PA1 PA1 24 I/O Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1, TIMER4_CH1 Default: PA2 PA2 25 I/O Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2 Default: PA3 PA3 26 I/O Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3, TIMER4_CH3 VSS_4 27 P Default: VSS_4 VDD_4 28 P Default: VDD_4 Default: PA4 PA4 29 I/O Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0 Remap:SPI2_NSS, I2S2_WS PA5 30 I/O Default: PA5 Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 31 I/O Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BKIN(3) Remap: TIMER0_BKIN Default: PA7 PA7 32 I/O Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON(3) Remap: TIMER0_CH0_ON PC4 33 I/O PC5 34 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 35 I/O Alternate: ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON(3) Remap: TIMER0_CH1_ON 27 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PB1 PB1 36 Alternate: ADC01_IN9, TIMER2_CH3, I/O TIMER7_CH2_ON(3) Remap: TIMER0_CH2_ON PB2 37 I/O 5VT Default: PB2, BOOT1 Default: PE7 PE7 38 I/O 5VT Alternate: EXMC_D4 Remap: TIMER0_ETI Default: PE8 PE8 39 I/O 5VT Alternate: EXMC_D5 Remap: TIMER0_CH0_ON Default: PE9 PE9 40 I/O 5VT Alternate: EXMC_D6 Remap: TIMER0_CH0 Default: PE10 PE10 41 I/O 5VT Alternate: EXMC_D7 Remap: TIMER0_CH1_ON Default: PE11 PE11 42 I/O 5VT Alternate: EXMC_D8 Remap: TIMER0_CH1 Default: PE12 PE12 43 I/O 5VT Alternate: EXMC_D9 Remap: TIMER0_CH2_ON Default: PE13 PE13 44 I/O 5VT Alternate: EXMC_D10 Remap: TIMER0_CH2 Default: PE14 PE14 45 I/O 5VT Alternate: EXMC_D11 Remap: TIMER0_CH3 Default: PE15 PE15 46 I/O 5VT Alternate: EXMC_D12 Remap: TIMER0_BKIN Default: PB10 PB10 47 I/O 5VT Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 48 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 49 P Default: VSS_1 28 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) VDD_1 50 P PB12 51 I/O Default: VDD_1 Default: PB12 5VT Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX Default: PB13 PB13 52 I/O 5VT Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX Default: PB14 PB14 53 I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON PB15 54 I/O 5VT Default: PB15 Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD Default: PD8 PD8 55 I/O 5VT Alternate: EXMC_D13 Remap: USART2_TX Default: PD9 PD9 56 I/O 5VT Alternate: EXMC_D14 Remap: USART2_RX Default: PD10 PD10 57 I/O 5VT Alternate: EXMC_D15 Remap: USART2_CK Default: PD11 PD11 58 I/O 5VT Alternate: EXMC_A16 Remap: USART2_CTS Default: PD12 PD12 59 I/O 5VT Alternate: EXMC_A17 Remap: TIMER3_CH0, USART2_RTS Default: PD13 PD13 60 I/O 5VT Alternate: EXMC_A18 Remap: TIMER3_CH1 Default: PD14 PD14 61 I/O 5VT Alternate: EXMC_D0 Remap: TIMER3_CH2 Default: PD15 PD15 62 I/O 5VT Alternate: EXMC_D1 Remap: TIMER3_CH3 Default: PC6 PC6 63 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0(3) Remap: TIMER2_CH0 29 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PC7 PC7 64 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1(3) Remap: TIMER2_CH1 Default: PC8 PC8 65 I/O 5VT Alternate: TIMER7_CH2(3) Remap: TIMER2_CH2 Default: PC9 PC9 66 I/O 5VT Alternate: TIMER7_CH3(3) Remap: TIMER2_CH3 Default: PA8 PA8 67 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF Default: PA9 PA9 68 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS PA10 69 I/O 5VT Default: PA10 Alternate: USART0_RX, TIMER0_CH2, USBFS_ID Default: PA11 PA11 70 I/O 5VT Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 71 I/O 5VT Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI PA13 72 I/O 5VT Default: JTMS, SWDIO Remap: PA13 NC 73 VSS_2 74 P Default: VSS_2 VDD_2 75 P Default: VDD_2 PA14 76 I/O 5VT Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 77 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 78 I/O 5VT Alternate: UART3_TX Remap: USART2_TX, SPI2_SCK, I2S2_CK PC11 79 I/O 5VT Default: PC11 Alternate: UART3_RX 30 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 80 I/O 5VT Alternate: UART4_TX Remap: USART2_CK, SPI2_MOSI, I2S2_SD Default: PD0 PD0 81 I/O 5VT Alternate: EXMC_D2 Remap: CAN0_RX Default: PD1 PD1 82 I/O 5VT Alternate: EXMC_D3 Remap: CAN0_TX PD2 83 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, UART4_RX Default: PD3 PD3 84 I/O 5VT Alternate: EXMC_CLK Remap: USART1_CTS Default: PD4 PD4 85 I/O 5VT Alternate: EXMC_NOE Remap: USART1_RTS Default: PD5 PD5 86 I/O 5VT Alternate: EXMC_NWE Remap: USART1_TX Default: PD6 PD6 87 I/O 5VT Alternate: EXMC_NWAIT Remap: USART1_RX Default: PD7 PD7 88 I/O 5VT Alternate: EXMC_NE0, EXMC_NCE1 Remap: USART1_CK Default: JTDO PB3 89 I/O 5VT Alternate:SPI2_SCK, I2S2_CK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 90 I/O 5VT Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 91 I/O Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX PB6 92 I/O 5VT Default: PB6 Alternate: I2C0_SCL, TIMER3_CH0 31 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Remap: USART0_TX, CAN1_TX Default: PB7 PB7 93 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1, EXMC_NADV Remap: USART0_RX BOOT0 94 I Default: BOOT0 Default: PB8 PB8 95 I/O 5VT Alternate: TIMER3_CH2 Remap: I2C0_SCL, CAN0_RX Default: PB9 PB9 96 I/O 5VT Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX Default: PE0 PE0 97 I/O 5VT PE1 98 I/O 5VT VSS_3 99 P Default: VSS_3 VDD_3 100 P Default: VDD_3 Alternate: TIMER3_ETI, EXMC_NBL0 Default: PE1 Alternate: EXMC_NBL1 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available in GD32F105VD/E/F/G devices. 32 GD32F105xx Datasheet 2.6.3. GD32F105Rx LQFP64 pin definitions Table 2-6. GD32F105Rx LQFP64 pin definitions Pin Name Pins VBAT Pin Type (1) I/O Functions description Level(2) 1 P 2 I/O 3 I/O 4 I/O OSCIN 5 I OSCOUT 6 O NRST 7 I/O PC0 8 I/O PC1 9 I/O PC2 10 I/O PC3 11 I/O VSSA 12 P Default: VSSA VDDA 13 P Default: VDDA PC13TAMPERRTC PC14OSC32IN PC15OSC32OU T Default: VBAT Default: PC13 Alternate: TAMPER-RTC Default: PC14 Alternate: OSC32IN Default: PC15 Alternate: OSC32OUT Default: OSCIN Remap: PD0 Default: OSCOUT Remap: PD1 Default: NRST Default: PC0 Alternate: ADC01_IN10 Default: PC1 Alternate: ADC01_IN11 Default: PC2 Alternate: ADC01_IN12 Default: PC3 Alternate: ADC01_IN13 Default: PA0 PA0WKUP 14 I/O Alternate: WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI(3) Default: PA1 PA1 15 I/O Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1, TIMER4_CH1 Default: PA2 PA2 16 I/O Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2 PA3 17 I/O Default: PA3 Alternate: USART1_RX, ADC01_IN3, 33 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) TIMER1_CH3, TIMER4_CH3 VSS_4 18 P Default: VSS_4 VDD_4 19 P Default: VDD_4 Default: PA4 PA4 20 Alternate: SPI0_NSS, USART1_CK, ADC01_IN4, I/O DAC_OUT0 Remap:SPI2_NSS, I2S2_WS PA5 21 Default: PA5 I/O Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1 Default: PA6 PA6 22 Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0, I/O TIMER7_BKIN(3) Remap: TIMER0_BKIN Default: PA7 PA7 23 Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1, I/O TIMER7_CH0_ON(3) Remap: TIMER0_CH0_ON PC4 24 I/O PC5 25 I/O Default: PC4 Alternate: ADC01_IN14 Default: PC5 Alternate: ADC01_IN15 Default: PB0 PB0 26 Alternate: ADC01_IN8, TIMER2_CH2, I/O TIMER7_CH1_ON(3) Remap: TIMER0_CH1_ON Default: PB1 PB1 27 Alternate: ADC01_IN9, TIMER2_CH3, I/O TIMER7_CH2_ON(3) Remap: TIMER0_CH2_ON PB2 28 I/O 5VT PB10 29 I/O 5VT Default: PB2, BOOT1 Default: PB10 Alternate: I2C1_SCL, USART2_TX Remap: TIMER1_CH2 Default: PB11 PB11 30 I/O 5VT Alternate: I2C1_SDA, USART2_RX Remap: TIMER1_CH3 VSS_1 31 P Default: VSS_1 VDD_1 32 P Default: VDD_1 PB12 33 I/O 5VT Default: PB12 34 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Alternate: SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BKIN, I2S1_WS, CAN1_RX Default: PB13 PB13 34 I/O 5VT Alternate: SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX Default: PB14 PB14 35 I/O 5VT Alternate: SPI1_MISO, USART2_RTS, TIMER0_CH1_ON Default: PB15 PB15 36 I/O 5VT Alternate: SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD Default: PC6 PC6 37 I/O 5VT Alternate: I2S1_MCK, TIMER7_CH0(3) Remap: TIMER2_CH0 Default: PC7 PC7 38 I/O 5VT Alternate: I2S2_MCK, TIMER7_CH1(3) Remap: TIMER2_CH1 Default: PC8 PC8 39 I/O 5VT Alternate: TIMER7_CH2(3) Remap: TIMER2_CH2 Default: PC9 PC9 40 I/O 5VT Alternate: TIMER7_CH3(3) Remap: TIMER2_CH3 Default: PA8 PA8 41 I/O 5VT Alternate: USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF Default: PA9 PA9 42 I/O 5VT Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS PA10 43 I/O 5VT Default: PA10 Alternate: USART0_RX, TIMER0_CH2, USBFS_ID Default: PA11 PA11 44 I/O 5VT Alternate: USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3 Default: PA12 PA12 45 I/O 5VT Alternate: USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI PA13 46 I/O 5VT Default: JTMS, SWDIO Remap: PA13 35 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) VSS_2 47 P Default: VSS_2 VDD_2 48 P Default: VDD_2 PA14 49 I/O 5VT Default: JTCK, SWCLK Remap: PA14 Default: JTDI PA15 50 I/O 5VT Alternate: SPI2_NSS, I2S2_WS Remap: TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS Default: PC10 PC10 51 I/O 5VT Alternate: UART3_TX Remap: USART2_TX, SPI2_SCK, I2S2_CK Default: PC11 PC11 52 I/O 5VT Alternate: UART3_RX Remap: USART2_RX, SPI2_MISO Default: PC12 PC12 53 I/O 5VT Alternate: UART4_TX Remap: USART2_CK, SPI2_MOSI, I2S2_SD PD2 54 I/O 5VT Default: PD2 Alternate: TIMER2_ETI, UART4_RX Default: JTDO PB3 55 I/O 5VT Alternate:SPI2_SCK, I2S2_CK Remap: PB3, TRACESWO, TIMER1_CH1, SPI0_SCK Default: NJTRST PB4 56 I/O 5VT Alternate: SPI2_MISO Remap: TIMER2_CH0, PB4, SPI0_MISO Default: PB5 PB5 57 I/O Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX Default: PB6 PB6 58 I/O 5VT Alternate: I2C0_SCL, TIMER3_CH0 Remap: USART0_TX, CAN1_TX Default: PB7 PB7 59 I/O 5VT Alternate: I2C0_SDA , TIMER3_CH1 Remap: USART0_RX BOOT0 60 I PB8 61 I/O Default: BOOT0 Default: PB8 5VT Alternate: TIMER3_CH2 Remap: I2C0_SCL, CAN0_RX 36 GD32F105xx Datasheet Pin Name Pins Pin I/O Functions description Type(1) Level(2) Default: PB9 PB9 62 I/O 5VT Alternate: TIMER3_CH3 Remap: I2C0_SDA, CAN0_TX VSS_3 63 P Default: VSS_3 VDD_3 64 P Default: VDD_3 Notes: (1) Type: I = input, O = output, P = power. (2) I/O Level: 5VT = 5 V tolerant. (3) Functions are available in GD32F105RD/E/F/G devices. 37 GD32F105xx Datasheet 3. Functional description 3.1. ARM® Cortex™-M3 core The Cortex™-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.  32-bit ARM® Cortex™-M3 processor core  Up to 108 MHz operation frequency  Single-cycle multiplication and hardware divider  Integrated Nested Vectored Interrupt Controller (NVIC)  24-bit SysTick timer The Cortex™-M3 processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction sets. Some system peripherals listed below are also provided by Cortex™-M3:  Internal Bus Matrix connected with ICode bus, DCode bus, system bus, Private Peripheral Bus (PPB) and debug accesses (AHB-AP) 3.2.  Nested Vectored Interrupt Controller (NVIC)  Flash Patch and Breakpoint (FPB)  Data Watchpoint and Trace (DWT)  Instrument Trace Macrocell (ITM)  Memory Protection Unit (MPU)  Serial Wire JTAG Debug Port (SWJ-DP)  Trace Port Interface Unit (TPIU) On-chip memory  Up to 1024 Kbytes of Flash memory  Up to 96 Kbytes of SRAM The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate buses to fetch instructions and load/store data. 1024 Kbytes of inner Flash and 96 Kbytes of inner SRAM at most is available for storing programs and data, both accessed (R/W) at CPU clock speed with zero wait states. The Table 2-3. GD32F105xx memory map shows the memory map of the GD32F105xx series of devices, including code, SRAM, peripheral, and other pre-defined regions. 38 GD32F105xx Datasheet 3.3. Clock, reset and supply management  Internal 8 MHz factory-trimmed RC and external 4 to 16 MHz crystal oscillator  Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator  Integrated system clock PLL  2.6 to 3.6 V application supply and I/Os  Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage detector (LVD) The Clock Control Unit (CCU) provides a range of oscillator and clock functions. These include speed internal RC oscillator and external crystal oscillator, high speed and low speed two types. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 108 MHz. The maximum allowed frequency of the lowspeed APB domain is 54 MHz. See Figure 2-5. GD32F105xx clock tree for details on the clock tree. The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor core and peripheral IP components. Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper operation starting from/down to 2.6 V. The device remains in reset mode when VDD is below a specified threshold. The embedded low voltage detector (LVD) monitors the power supply, compares it to the voltage threshold and generates an interrupt as a warning message for leading the MCU into security. Power supply schemes:  VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator. Provided externally through VDD pins.  VSSA, VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.  VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32kHz oscillator and backup registers (through power switch) when VDD is not present. 3.4. Boot modes At startup, boot pins are used to select one of three boot options:  Boot from main flash memory (default)  Boot from system memory  Boot from on-chip SRAM The boot loader is located in the internal boot ROM memory (system memory). It is used to reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6), USBFS in device mode (PA9, PA11 and PA12). It also can be used to transfer and update the Flash memory code, the data and the vector table sections. In default condition, boot from bank 0 of Flash memory is selected. It also supports to boot from bank 1 of Flash memory by 39 GD32F105xx Datasheet setting a bit in option bytes. 3.5. Power saving modes The MCU supports three kinds of power saving modes to achieve even lower power consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating modes reduce the power consumption and allow the application to achieve the best balance between the CPU operating time, speed and power consumption.  Sleep mode In sleep mode, only the clock of CPU core is off. All peripherals continue to operate and any interrupt/event can wake up the system.  Deep-sleep mode In deep-sleep mode, all clocks in the 1.2V domain are off, and all of the high speed crystal oscillator (IRC8M, HXTAL) and PLL are disabled. Only the contents of SRAM and registers are retained. Any interrupt or wakeup event from EXTI lines can wake up the system from the deep-sleep mode including the 16 external lines, the RTC alarm, the LVD output, and USB wakeup. When exiting the deep-sleep mode, the IRC8Mis selected as the system clock.  Standby mode In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of IRC8M, HXTAL and PLL are disabled. The contents of SRAM and registers (except Backup registers) are lost. There are four wakeup sources for the standby mode, including the external reset from NRST pin, the RTC alarm, the FWDGT reset, and the rising edge on WKUP pin. 3.6. Analog to digital converter (ADC)  12-bit SAR ADC engine  Up to 1 MSPS conversion rate  Conversion range: VSSA to VDDA (2.6 to 3.6 V)  Temperature sensor Up to two 12-bit 1 μs multi-channel ADCs are integrated in the device. Each is a total of up to 21 multiplexed external channels. An analog watchdog block can be used to detect the channels, which are required to remain within a specific threshold window. A configurable channel management block of analog inputs also can be used to perform conversions in single, continuous, scan or discontinuous mode to support more advanced usages. The ADCs can be triggered from the events generated by the general-purpose timers (TIMERx) and the advanced-control timers (TIMER0 and TIMER7) with internal connection. The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage 40 GD32F105xx Datasheet into a digital value. 3.7. Digital to analog converter (DAC)  Two 12-bit DAC converters of independent output channel  8-bit or 12-bit mode in conjunction with the DMA controller The two 12-bit buffered DAC channels are used to generate variable analog outputs. The DACs are designed with integrated resistor strings structure. The DAC channels can be triggered by the timer update outputs or EXTI with DMA support. In dual DAC channel operation, conversions could be done independently or simultaneously. The maximum output value of the DAC is VREF+. 3.8. DMA  7 channel DMA0 controller and 5 channel DMA1 controller  Peripherals supported: Timers, ADC, SPIs, I2Cs, USARTs, DAC, I2S The flexible general-purpose DMA controllers provide a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Four types of access method are supported: peripheral to peripheral, peripheral to memory, memory to peripheral, memory to memory Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel requests are determined by software configuration and hardware channel number. Transfer size of source and destination are independent and configurable. 3.9. General-purpose inputs/outputs (GPIOs)  Up to 112 fast GPIOs, all mappable on 16 external interrupt vectors (EXTI)  Analog input/output configurable  Alternate function input/output configurable There are up to 112 general purpose I/O pins (GPIO) in GD32F105xx, named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0-PF15, PG0-PG15 to implement logic input/output functions. Each of the GPIO ports has related control and configuration registers to satisfy the requirements of specific applications. The external interrupts on the GPIO pins of the device have related control and configuration registers in the External Interrupt Control Unit (EXTI). The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the package pins. Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current capable except 41 GD32F105xx Datasheet for analog inputs. 3.10. Timers and PWM generation  Up to two 16-bit advanced-control timer (TIMER0 & TIMER7), four 16-bit general-purpose timers (GPTM), and two 16-bit basic timer (TIMER5 & TIMER6)  Up to 4 independent channels of PWM, output compare or input capture for each GPTM and external trigger input  16-bit, motor control PWM advanced-control timer with programmable dead-time generation for output match  Encoder interface controller with two inputs using quadrature decoder  24-bit SysTick timer down counter  2 watchdog timers (Independent watchdog and window watchdog) The advanced-control timer (TIMER0 & TIMER7) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable deadtime generation. It can also be used as a complete general-purpose timer. The 4 independent channels can be used for  Input capture  Output compare  PWM generation (edge- or center-aligned counting modes)  Single pulse mode output If configured as a general-purpose 16-bit timer, it has the same functions as the TIMERx timer. It can be synchronized with external signals or to interconnect with other GPTMs together which have the same architecture and features. The general-purpose timer (GPTM), known as TIMER1 ~ TIMER4 can be used for a variety of purposes including general time, input signal pulse width measurement or output waveform generation such as a single pulse generation or PWM output, up to 4 independent channels for input capture/output compare. The GPTM also supports an encoder interface with two inputs using quadrature decoder. The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation. They can also be used as a simple 16-bit time base. The GD32F105xx have two watchdog peripherals, free watchdog timer and window watchdog timer. They offer a combination of high safety level, flexibility of use and timing accuracy. The free watchdog timer includes a 12-bit down-counting counter and an 8-bit prescaler, It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in deep-sleep and standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. The window watchdog timer is based on a 7-bit down counter that can be set as free-running. 42 GD32F105xx Datasheet It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. The SysTick timer is dedicated for OS, but could also be used as a standard down counter. It features: 3.11.  A 24-bit down counter  Auto reload capability  Maskable system interrupt generation when the counter reaches 0  Programmable clock source Real time clock (RTC)  32-bit up-counter with a programmable 20-bit prescaler  Alarm function  Interrupt and wake-up event The real time clock is an independent timer which provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit programmable counter for long-term measurement using the compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz from external crystal oscillator. 3.12. Inter-integrated circuit (I2C)  Up to two I2C bus interfaces can support both master and slave mode with a frequency up to 400 kHz  Provide arbitration function, optional PEC (packet error checking) generation and checking  Supports 7-bit and 10-bit addressing mode and general call addressing mode The I2C interface is an internal circuit allowing communication with an external I2C interface which is an industry standard two line serial interface used for connection to external hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line (SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode and up to 400 KHz in fast mode. The I2C module also has an arbitration detect function to prevent the situation where more than one master attempts to transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C interface to perform packet error checking for I2C data. 43 GD32F105xx Datasheet 3.13. Serial peripheral interface (SPI)  Up to three SPI interfaces with a frequency of up to 18 MHz  Support both master and slave mode  Hardware CRC calculation and transmit automatic CRC error checking The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO & MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by the DMA controller. The SPI interface may be used for a variety of purposes, including simplex synchronous transfers on two lines with a possible bidirectional data line or reliable communication using CRC checking. 3.14. Universal synchronous asynchronous receiver transmitter (USART)  Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz  Supports both asynchronous and clocked synchronous serial communication modes  IrDA SIR encoder and decoder support  LIN break generation and detection  USARTs support ISO 7816-3 compliant smart card interface The USART (USART0, USART1 and USART2) are used to translate data between parallel and serial interfaces, provides a flexible full duplex data exchange using synchronous or asynchronous transfer. It is also commonly used for RS-232 standard communication. The USART includes a programmable baud rate generator which is capable of dividing the system clock to produce a dedicated clock for the USART transmitter and receiver. The USART also supports DMA function for high speed data communication except UART4. 3.15. Inter-IC sound (I2S)  Two I2S bus Interfaces with sampling frequency from 8 kHz to 192 kHz  Support either master or slave mode The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio applications by 3-wire serial lines. GD32F105xx contain two I2S-bus interfaces that can be operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and SPI2. The audio sampling frequency from 8 kHz to 192 kHz is supported with less than 0.5% accuracy error. 44 GD32F105xx Datasheet 3.16. Universal serial bus full-speed (USBFS)  One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s  Internal main PLL for USB CLK compliantly The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction formatting is performed by the hardware, including CRC generation and checking. The status of a completed USB transfer or error condition is indicated by status registers. An interrupt is also generated if enabled. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency divided from APB1 should be 12 MHz above. 3.17. Controller area network (CAN)  Two CAN2.0B interface with communication frequency up to 1 Mbit/s  Internal main PLL for USB CLK compliantly Controller area network (CAN) is a method for enabling serial communication in field bus. The CAN protocol has been used extensively in industrial automation and automotive applications. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three message deep for reception. It also provides 14 scalable/configurable identifier filter banks for selecting the incoming messages needed and discarding the others. 3.18. External memory controller (EXMC)  Supported external memory: SRAM, PSRAM, ROM and NOR-Flash, NAND Flash and CF card  Up to 16-bit data bus  Support to interface with Motorola 6800 and Intel 8080 type LCD directly External memory controller (EXMC) is an abbreviation of external memory controller. It is divided in to several sub-banks for external device support, each sub-bank has its own chip selection signal but at one time, only one bank can be accessed. The EXMC support code execution from external memory except NAND Flash and CF card. The EXMC also can be configured to interface with the most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system cost and complexity. 45 GD32F105xx Datasheet 3.19. Debug mode  Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. 3.20. Package and operation temperature  LQFP144 (GD32F105Zx), LQFP100 (GD32F105Vx), LQFP64 (GD32F105Rx)  Operation temperature range: -40°C to +85°C (industrial level) 46 GD32F105xx Datasheet 4. Electrical characteristics 4.1. Absolute maximum ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Table 4-1. Absolute maximum ratings Symbol Parameter Min Max Unit VDD External voltage range VSS - 0.3 VSS + 3.6 V VDDA External analog supply voltage VSSA - 0.3 VSSA + 3.6 V VBAT External battery supply voltage VSS - 0.3 VSS + 3.6 V Input voltage on 5V tolerant pin VSS - 0.3 VDD + 4.0 V Input voltage on other I/O VSS - 0.3 4.0 V IIO Maximum current for GPIO pins — 25 mA TA Operating temperature range -40 +85 °C TSTG Storage temperature range -55 +150 °C TJ Maximum junction temperature — 125 °C VIN 4.2. Recommended DC characteristics Table 4-2. DC operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD Supply voltage — 2.6 3.3 3.6 V VDDA Analog supply voltage Same as VDD 2.6 3.3 3.6 V VBAT Battery supply voltage — 1.8 — 3.6 V 47 GD32F105xx Datasheet 4.3. Power consumption The power measurements specified in the tables represent that code with data executing from on-chip Flash with the following specifications. Table 4-3. Power consumption characteristics Symbol Parameter Conditions Min Typ Max Unit VDD=VBAT=3.3V, HXTAL=8MHz, System — 45.2 — mA — 36.0 — mA -— 32.4 — mA — 26.1 — mA — 23.2 — mA — 13.9 — mA — 0.65 1.4 mA — 20.5 — μA — 10.1 — μA — 6.8 — μA clock=108 MHz, All peripherals enabled VDD=VBAT=3.3V, HXTAL=8MHz, System Supply current clock =108 MHz, All peripherals disabled (Run mode) VDD=VBAT=3.3V, HXTAL=8MHz, System clock =72MHz, All peripherals enabled VDD=VBAT=3.3V, HXTAL=8MHz, System Clock =72 MHz, All peripherals disabled VDD=VBAT=3.3V, HXTAL=8MHz, CPU clock IDD Supply current off, All peripherals enabled (Sleep mode) VDD=VBAT=3.3V, HXTAL=8MHz, CPU clock off, All peripherals disabled Supply current (Deep-Sleep mode) RTC on, All GPIOs analog mode Supply current VDD=VBAT=3.3V, LDO off, LXTAL off, (Standby mode) IRC40K on, RTC on Battery supply IBAT VDD=VBAT=3.3V, All clock off, IRC40K on, current (Standby mode) VDD not available, VBAT=3.3V, LDO off, LXTAL on, IRC40K off, RTC on VDD not available, VBAT=3.3 V, LDO off, LXTAL off, IRC40K on, RTC on 48 GD32F105xx Datasheet 4.4. EMC characteristics EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is given in the Table 4-4. EMS characteristics, based on the EMS levels and classes compliant with IEC 61000 series standard. Table 4-4. EMS characteristics Symbol VESD Parameter Conditions Voltage applied to all device pins to VDD = 3.3 V, TA = +25 °C induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst applied to VFTB induce a functional disturbance through 100 pF on VDD and VSS pins Level/Class 3A VDD = 3.3 V, TA = +25 °C 4A conforms to IEC 61000-4-4 EMI (Electromagnetic Interference) emission testing result is given in the Table 4-5. EMI characteristics, compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 4-5. EMI characteristics Symbol Parameter Conditions 4.5. Peak level frequency band Unit 56M 72M 108M 0.1 to 2 MHz