MS51
1T 8051
8-bit Microcontroller
NuMicro® Family
MS51 32K Series
MS51FC0AE
MS51XC0BE
MS51EC0AE
MS51TC0AE
MS51PC0AE
MS51 SERIES DATASHEET
Datasheet
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
Nov. 28, 2019
Page 1 of 80
Rev 1.00
MS51
TABLE OF CONTENTS
1 GENERAL DESCRIPTION .............................................................................. 7
2 FEATURES ...................................................................................................... 8
3 PARTS INFORMATION ................................................................................. 12
3.1 Package Type .............................................................................................................. 12
3.2 MS51 Series Selection Gude .................................................................................... 12
3.3 MS51 Series Selection Code ..................................................................................... 13
4 PIN CONFIGURATION .................................................................................. 14
4.1 MS51 32K Series Multi Function Pin Diagram........................................................ 14
4.1.1 QFN 33-pin Package Pin Diagram ............................................................................. 14
4.1.2 LQFP 32-pin Package Pin Diagram ........................................................................... 15
4.1.3 TSSOP 28-pin Package Pin Diagram ........................................................................ 16
4.1.4 TSSOP 20-pin Package Pin Diagram ........................................................................ 16
4.1.5 QFN 20-pin Package Pin Diagram ............................................................................. 17
4.2 MS51 32K Series Pin Description ............................................................................. 18
5 BLOCK DIAGRAM ......................................................................................... 22
5.1 MS51 32K Series Block Diagram.............................................................................. 22
6 FUNCTIONAL DESCRIPTION ....................................................................... 23
6.1 Memory Organization.................................................................................................. 23
6.1.1 Overview .......................................................................................................................... 23
MS51 SERIES DATASHEET
6.2 Flash Memory Control ................................................................................................ 24
6.2.1 Reset ................................................................................................................................ 24
6.3 General Purpose I/O (GPIO) ..................................................................................... 33
6.4 Timer.............................................................................................................................. 34
6.4.1 Timer/Counter 0 And 1 ................................................................................................... 34
6.4.2 Timer2 And Input Capture ............................................................................................. 34
6.4.3 Timer 3 ............................................................................................................................. 36
6.5 Pulse Width Modulated (PWM) ................................................................................. 37
6.5.1 Overview .......................................................................................................................... 37
6.6 Watchdog Timer (WDT) .............................................................................................. 39
6.6.1 Overview .......................................................................................................................... 39
6.7 Self Wake-Up Timer (WKT) ....................................................................................... 40
6.7.1 Overview .......................................................................................................................... 40
6.8 Serial Port (UART0 & UART1) .................................................................................. 41
6.8.1 Overview .......................................................................................................................... 41
6.9 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4) .......................................................... 42
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6.9.1 Overview .......................................................................................................................... 42
6.10
2
Inter-Integrated Circuit (I C) ................................................................................. 44
6.10.1 Overview .......................................................................................................................... 44
6.11
Serial Peripheral Interface (SPI) ......................................................................... 45
6.11.1 Overview .......................................................................................................................... 45
6.12
12-Bit Analog-To-Digital Converter (ADC) ......................................................... 48
6.12.1 Overview .......................................................................................................................... 48
7 APPLICATION CIRCUIT ................................................................................ 49
7.1 Power supply scheme................................................................................................. 49
7.2 Peripheral Application scheme .................................................................................. 50
8 ELECTRICAL CHARACTERISTICS.............................................................. 51
8.1 General Operating Conditions ................................................................................... 51
8.2 DC Electrical Characteristics ..................................................................................... 52
8.2.1 Supply Current Characteristics ..................................................................................... 52
8.2.2 Wakeup Time from Low-Power Modes ....................................................................... 54
8.2.3 I/O DC Characteristics ................................................................................................... 55
8.3 AC Electrical Characteristics ..................................................................................... 58
8.3.1 Internal High Speed RC Oscillator (HIRC) ................................................................. 58
8.3.2 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
60
8.3.3 External 4~24 MHz High Speed Clock Input Signal Characteristics ...................... 61
8.3.4 10 kHz Internal Low Speed RC Oscillator (LIRC) ..................................................... 62
MS51 SERIES DATASHEET
8.3.5 I/O AC Characteristics ................................................................................................... 63
8.4 Analog Characteristics ................................................................................................ 64
8.4.1 Reset and Power Control Block Characteristics ........................................................ 64
8.4.2 12-bit SAR ADC .............................................................................................................. 65
8.5 Flash DC Electrical Characteristics .......................................................................... 67
8.6 Absolute Maximum Ratings ....................................................................................... 68
8.6.1 Voltage Characteristics .................................................................................................. 68
8.6.2 Current Characteristics .................................................................................................. 68
8.6.3 Thermal Characteristics................................................................................................. 69
8.6.4 EMC Characteristics ...................................................................................................... 70
8.6.5 Package Moisture Sensitivity(MSL) ............................................................................. 71
8.6.6 Soldering Profile ............................................................................................................. 72
9 PACKAGE DIMENSIONS .............................................................................. 73
9.1 QFN 33-pin (4.0 x 4.0 x 0.8 mm) .............................................................................. 73
9.2 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)............................................................................. 74
9.3 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ......................................................................... 75
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9.4 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ........................................................................ 76
9.5 QFN 20-pin (3.0 x 3.0 x 0.6mm) .............................................................................. 77
10 ABBREVIATIONS .......................................................................................... 78
10.1
Abbreviations List .................................................................................................. 78
11 REVISION HISTORY ..................................................................................... 79
MS51 SERIES DATASHEET
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MS51
LIST OF FIGURES
Figure 4.1-1 Pin Assignment of LQFP-32 Package ....................................................................... 14
Figure 4.1-2 Pin Assignment of LQFP-32 Package ....................................................................... 15
Figure 4.1-3 Pin Assignment of TSSOP28 Package ..................................................................... 16
Figure 4.1-4 Pin Assignment of TSSOP20 Package ..................................................................... 16
Figure 4.1-5 Pin Assignment of QFN20 Package .......................................................................... 17
Figure 5.1-1 Functional Block Diagram .......................................................................................... 22
Figure 6.2-1 CONFIG0 Any Reset Reloading ................................................................................ 29
Figure 6.2-2 CONFIG2 Power-On Reset Reloading ...................................................................... 31
Figure 6.4-1 Timer 2 Block Diagram .............................................................................................. 35
Figure 6.4-2 Timer 3 Block Diagram .............................................................................................. 36
Figure 6.7-1 Self Wake-Up Timer Block Diagram .......................................................................... 40
Figure 6.9-1 SC Controller Block Diagram ..................................................................................... 42
Figure 6.11-1 SPI Block Diagram................................................................................................... 45
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection ........................................................ 46
Figure 6.11-3 SPI Single-Master, Single-Slave Interconnection .................................................... 46
®
Figure 7.1-1 NuMicro MS51 Power supply circuit ........................................................................ 49
®
Figure 7.2-1 NuMicro MS51 Peripheral interface circuit .............................................................. 50
Figure 8.6-1 Soldering profile from J-STD-020C ........................................................................... 72
Figure 9.1-1 QFN-33 Package Dimension ..................................................................................... 73
Figure 9.2-1 LQFP-32 Package Dimension ................................................................................... 74
Figure 9.3-1 TSSOP-28 Package Dimension ................................................................................ 75
MS51 SERIES DATASHEET
Figure 9.4-1 TSSOP-20 Package Dimension ................................................................................ 76
Figure 9.5-1 QFN-20 Package Dimension for MS51XC0BE ......................................................... 77
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List of Tables
Table 6.5-1 PWM Pin Define And Enable Control Register ........................................................... 38
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars.......................................... 39
Table 6.9-1 Smart Card or UART Pin Define And Enable Control Register .................................. 43
Table 8.1-1 General operating conditions ...................................................................................... 51
Table 8.2-1 Current consumption in Normal Run mode ................................................................ 52
Table 8.2-2 Current consumption in Idle mode .............................................................................. 53
Table 8.2-3 Chip Current Consumption in Power down mode ...................................................... 53
Table 8.2-4 Low-power mode wakeup timings .............................................................................. 54
Table 8.2-5 I/O input characteristics .............................................................................................. 55
Table 8.2-6 I/O output characteristics ............................................................................................ 56
Table 8.2-7 nRESET Input Characteristics .................................................................................... 57
Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics ............................ 58
Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics .............................. 59
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator .......................................... 60
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal ................................................... 61
Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics ............................... 62
Table 8.3-6 I/O AC characteristics ................................................................................................. 63
Table 8.4-1 Reset and power control unit ...................................................................................... 64
Table 8.4-2 Minimum Brown-out Detect Pulse Width .................................................................... 65
Table 8.4-3 ADC characteristics .................................................................................................... 66
Table 8.5-1 Flash memory characteristics ..................................................................................... 67
MS51 SERIES DATASHEET
Table 8.6-1 Voltage characteristics ................................................................................................ 68
Table 8.6-2 Current characteristics ................................................................................................ 68
Table 8.6-3 Thermal characteristics ............................................................................................... 69
Table 8.6-4 EMC characteristics .................................................................................................... 70
Table 8.6-5 Package Moisture Sensitivity(MSL) ............................................................................ 71
Table 8.6-6 Soldering Profile.......................................................................................................... 72
Table 10.1-1 List of Abbreviations.................................................................................................. 78
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MS51
1
GENERAL DESCRIPTION
The MS51 is an embedded Flash type, 8-bit high performance 1T 8051-based microcontroller. The
instruction set is fully compatible with the standard 80C51 and performance enhanced.
The MS51 contains a up to 32 Kbytes of main Flash called APROM, in which the contents of User
Code resides. The MS51 Flash supports In-Application-Programming (IAP) function, which enables
on-chip firmware updates. IAP also makes it possible to configure any block of User Code array to be
used as non-volatile data storage, which is written by IAP and read by IAP or MOVC instruction. There
is an additional Flash called LDROM, in which the Boot Code normally resides for carrying out InSystem-Programming (ISP). The LDROM size is configurable with a maximum of 4 Kbytes. To
facilitate programming and verification, the Flash allows to be programmed and read electronically by
parallel Writer or In-Circuit-Programming (ICP). Once the code is confirmed, user can lock the code for
security.
The MS51 provides rich peripherals including 256 bytes of SRAM, 2 Kbytes of auxiliary RAM (XRAM),
Up to 29 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-channel
input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-bit autoreload Timer3 for general purpose or baud rate generator, two UARTs with frame error detection and
2
automatic address recognition, three ISO 7816-3 interfaces, one SPI, one I C, six basic PWM output
channels, six enhanced PWM output channels, eight-channel shared pin interrupt for all I/O, and one
12-bit ADC. The peripherals are equipped with 24 sources with 4-level-priority interrupts capability.
The MS51 is equipped with three clock sources and supports switching on-the-fly via software. The
three clock sources include external clock input, 10 kHz internal oscillator, and one 16 MHz internal
precise oscillator that is factory trimmed to ±1% at room temperature. The MS51 provides additional
power monitoring detection such as power-on reset and 4-level brown-out detection, which stabilizes
the power-on/off sequence for a high reliability system design.
The MS51 microcontroller operation consumes a very low power with two economic power modes to
reduce power consumption － Idle and Power-down mode, which are software selectable. Idle mode
turns off the CPU clock but allows continuing peripheral operation. Power-down mode stops the whole
system clock for minimum power consumption. The system clock of the MS51 can also be slowed
down by software clock divider, which allows for a flexibility between execution performance and
power consumption.
MS51 SERIES DATASHEET
With high performance CPU core and rich well-designed peripherals, the MS51 benefits to meet a
general purpose, home appliances, or motor control system accomplishment.
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MS51
2
FEATURES
Core and System
8051
Brown-out Detector (BOD)
Low Voltage Reset (LVR)
Security
Fully static design 8-bit high performance 1T 8051-based
CMOS microcontroller.
Instruction set fully compatible with MCS-51.
4-priority-level interrupts capability.
Dual Data Pointers (DPTRs).
4-level selection, with brown-out interrupt and reset option.
(4.4V / 3.7V / 2.7V / 2.2V)
LVR with 2.0V threshold voltage level
96-bit Unique ID (UID)
128-bit Unique Customer ID (UCID)
128-bytes security protection memory SPROM
Up to 32 KBytes of APROM for User Code.
4/3/2/1 Kbytes of Flash for loader (LDROM) configure from
APROM for In-System-Programmable (ISP)
Flash Memory accumulated with pages of 128 Bytes from
APROM by In-Application-Programmable (IAP) means whole
APROM can be use as Data Flash
An additional 128 bytes security protection memory SPROM
Code lock for security by CONFIG
256 Bytes on-chip RAM.
Additional 2 KBytes on-chip auxiliary RAM (XRAM) accessed
by MOVX instruction.
4~24 MHz High-speed external crystal oscillator (HXT) for
precise timing operation
Default 16 MHz high-speed internal oscillator (HIRC) trimmed
to ±1% (accuracy at 25 °C, 3.3 V), ±2% in -20~105°C.
Selectable 24 MHz high-speed internal oscillator (HIRC).
10 kHz low-speed internal oscillator (LIRC) calibrating to ±1%
Memories
MS51 SERIES DATASHEET
Flash
SRAM
Clocks
External Clock Source
Internal Clock Source
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MS51
by software from high-speed internal oscillator
Timers
16-bit Timer
Two 16-bit Timers/Counters 0 and 1 compatible with standard
8051.
One 16-bit Timer2 with three-channel input capture module
and 9 input pin can be selected.
One 16-bit auto-reload Timer3, which can be the baud rate
clock source of UART0 and UART1.
6-bit free running up counter for WDT time-out interval.
Selectable time-out interval is 6.40 ms ~ 1.638s since
WDT_CLK = 10 kHz (LIRC).
Able to wake up from Power-down or Idle mode
Interrupt or reset selectable on watchdog time-out
16-bit free running up counter for time-out interval.
Clock sources from LIRC
Able self Wake-up wake up from Power-down or Idle mode,
and auto reload count value.
Supports Interrupt
Up To 12 output pins can be selected
Supports maximum clock source frequency up to 24 MHz
Supports up to Three PWM modules, each module provides 6
output channels.
Supports independent mode for PWM output
Supports complementary mode for 3 complementary paired
PWM output channels
Dead-time insertion with 8-bit resolution
Supports 16-bit resolution PWM counter
Supports mask function and tri-state enable for each PWM pin
Supports brake function
Supports trigger ADC on the following events
Analog input voltage range: 0 ~ AVDD.
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 8 single-end analog input channels
1 internal channels, they are band-gap voltage (VBG).
Maximum ADC peripheral clock frequency is 1 MHz.
Up to 500 KSPS sampling rate.
Watchdog
Wake-up Timer
MS51 SERIES DATASHEET
PWM
Analog Interfaces
Analog-to-Digital
Converter (ADC)
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MS51
Software Write 1 to ADCS bit.
External pin (STADC) trigger
PWM trigger.
Support continues convert function auto store the A/D
conversion result in XRAM.
Supports up to 2 UARTs: UART0, UART1,
Three sets ISO 7816-3 device configuration as UART
UART baud rate clock from HIRC or HXT.
Full-duplex asynchronous communications
Programmable 9 bit.
TXD and RXD pins of UART0 exchangeable via software.
1 sets of I C devices
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
7-bit addressing mode
Standard mode (100 kbps) and Fast mode (400 kbps).
Supports 8-bit time-out counter requesting the I C interrupt if
2
the I C bus hangs up and timer-out counter overflows
Multiple address recognition (four slave addresses with mask
option)
Supports hold time programmable
1 sets of SPI devices
Supports Master or Slave mode operation
Supports MSB first or LSB first transfer sequence
slave mode up to 12 MHz
Three sets ISO 7816-3 device
Supports ISO 7816-3 compliant T=0, T=1
Supports full-duplex UART mode.
Four I/O modes:
Quasi-bidirectional mode
Push-Pull Output mode
Open-Drain Output mode
Input only with high impendence mode
Schmitt trigger input / TTL mode selectable.
Each I/O pin configured as interrupt source with edge/level
Communication Interfaces
UART
2
IC
MS51 SERIES DATASHEET
SPI
ISO-7816
GPIO
Nov. 28, 2019
th
2
2
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MS51
trigger setting
̅̅̅̅̅̅̅ and INT1
̅̅̅̅̅̅̅.
Standard interrupt pins INT0
Supports high drive and high sink current I/O
I/O pin internal pull-up or pull-down resistor enabled in input
mode.
Maximum I/O Speed is 24 MHz
Enabling the pin interrupt function will also enable the wake-up
function
ESD
HBM pass 8 kV
EFT
> ± 4.4 kV
Latch-up
150 mA pass
ESD & EFT
MS51 SERIES DATASHEET
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MS51
3
PARTS INFORMATION
3.1
Package Type
Part
No.
MSOP10
TSSOP14
TSSOP20
QFN20
TSSOP28
LQFP32
QFN33
MS51BA9AE
MS51DA9AE
MS51FB9AE
MS51FC0AE
MS51XB9AE
MS51XB9BE
MS51XC0BE
MS51EC0AE
MS51PC0AE
MS51TC0AE
3.2 MS51 Series Selection Gude
SRAM (KB)
LDROM (KB) [1]
I/O
Timer/
PWM
ISO-7816 [2]
UART
SPI
I2C
ADC(12-Bit)
Package
MS51 SERIES DATASHEET
Part Number
Flash (KB)
Connectivity
MS51BA9AE
8
1
4
8
4
5
-
2
-
1
5-ch
MSOP10
MS51DA9AE
8
1
4
12
4
5
-
2
1
1
7-ch
TSSOP14
MS51XB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20 [3]
MS51XB9BE
16
1
4
18
4
6
-
2
1
1
8-ch
QFN20 [3]
MS51FB9AE
16
1
4
18
4
6
-
2
1
1
8-ch
TSSOP20
MS51FC0AE
32
2
4
18
4
8
3
2
1
1
10-ch
TSSOP20
MS51XC0BE
32
2
4
18
4
8
3
2
1
1
10-ch
QFN20
MS51EC0AE
32
2
4
26
4
10
3
2
1
1
15-ch
TSSOP28
MS51PC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
LQFP32
MS51TC0AE
32
2
4
30
4
12
3
2
2
1
15-ch
QFN33
Note:
1.
2.
3.
4.
ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM.
ISO-7816 configurable as UART function, GPIO defined as UART2 ~ UART5.
Detailed package information please refer to Chapter 7
This document is only for 32K flash size part number product
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MS51
3.3 MS51 Series Selection Code
MS
51
F
B
9
A
E
Core
Line
Package
Flash
SRAM
Reserve
Temperature
1T 8051
51: Base
Industry
B: MSOP10 (3x3 mm)
A: 8 KB
0: 2 KB
D: TSSOP14 (4.4x5.0 mm)
B: 16 KB
1: 4 KB
E: TSSOP28 (4.4x9.7 mm)
C: 32 KB
2: 8/12 KB
F: TSSOP20 (4.4x6.5 mm)
3: 16 KB
I: SOP8 (4x5 mm)
6: 32 KB
O: SOP20 (300 mil)
8: 64 KB
P: LQFP32 (7x7 mm)
9: 1 KB
T: QFN33 (4x4 mm)
A: 96 KB
E:-40 ~ 105°C
U: SOP28 (300 mil)
X: QFN20 (3x3mm)
MS51 SERIES DATASHEET
Nov. 28, 2019
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MS51
4
PIN CONFIGURATION
Users can find pin configuaration informations by using NuTool - PinConfigure. The NuTool ®
PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users
configure GPIO multi-function correctly and handily.
4.1 MS51 32K Series Multi Function Pin Diagram
4.1.1
QFN 33-pin Package Pin Diagram
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P3.2 / PWM3_CH0
P3.1 / PWM2_CH1
P3.5 / SPI0_SS
24
23
22
21
20
19
18
17
Corresponding Part Number: MS51TC0AE
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
25
16
P2.1 / ADC_CH9 / PWM2_CH0
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
26
15
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
27
14
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
28
13
P2.4 / ADC_CH12 / T0
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
29
12
P1.3 / STADC / I2C0_SCL / ADC_CH13
UART0_TXD / ADC_CH3 / P0.6
30
11
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
UART0_RXD / ADC_CH2 / P0.7
31
10
P3.6 / UART1_RXD
9
P3.7 / UART1_TXD
QFN33
33 VSS
1
2
3
4
5
6
7
8
nRESET / P2.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
32
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
MS51 SERIES DATASHEET
UART3_RXD / PWM3_CH1 / P3.4
Top transparent view
Figure 4.1-1 Pin Assignment of LQFP-32 Package
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MS51
4.1.2
LQFP 32-pin Package Pin Diagram
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
P3.2 / PWM3_CH0
P3.1 / PWM2_CH1
P3.5 / SPI0_SS
24
23
22
21
20
19
18
17
Corresponding Part Number: MS51PC0AE
PWM0_BRAKE / CLKO / PWM0_CH0 / P3.3
25
16
P2.1 / ADC_CH9 / PWM2_CH0
UART1_RXD / I2C0_SCL / ICE_CLK / P0.2
26
15
P2.2 / ADC_CH10 / PWM1_CH1 / UART4_RXD
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
27
14
P2.3 / ADC_CH11 / PWM1_CH0 / UART4_TXD
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
28
13
P2.4 / ADC_CH12 / T0
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
29
12
P1.3 / STADC / I2C0_SCL / ADC_CH13
UART0_TXD / ADC_CH3 / P0.6
30
11
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
UART0_RXD / ADC_CH2 / P0.7
31
10
P3.6 / UART1_RXD
UART3_RXD / PWM3_CH1 / P3.4
32
9
P3.7 / UART1_TXD
1
2
3
4
5
6
7
8
nRESET / P2.0
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
VDD
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
MS51 SERIES DATASHEET
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
LQFP32
Figure 4.1-2 Pin Assignment of LQFP-32 Package
Nov. 28, 2019
Page 15 of 80
Rev 1.00
MS51
4.1.3
TSSOP 28-pin Package Pin Diagram
Corresponding Part Number: MS51EC0AE
1
28
P1.7 / ADC_CH0 / INT1 / UART2_RXD / SPI0_CLK
2
27
P3.0 / ADC_CH1 / OSCIN / INT0 / UART2_TXD / SPI0_MOSI
VDD
3
26
P2.0 / nRESET
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
4
25
P3.4 / PWM3_CH1 / UART3_RXD
SPI0_MISO / UART3_RXD / ADC_CH15 / P2.5
5
24
P0.7 / ADC_CH2 / UART0_RXD
PWM1_CH1 / ADC_CH14 / PWM0_BRAKE / I2C0_SDA / PWM0_CH1 / P1.4
6
23
P0.6 / ADC_CH3 / UART0_TXD
ADC_CH13 / I2C0_SCL / STADC / P1.3
7
22
P0.5 / ADC_CH4 / IC6 / PWM0_CH2 / T0 / UART3_TXD / PWM2_CH0
T0 / ADC_CH12 / P2.4
8
21
P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
UART4_TXD / PWM1_CH0 / ADC_CH11 / P2.3
9
20
P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
UART4_RXD / PWM1_CH1 / ADC_CH10 / P2.2
10
19
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
PWM2_CH0 / ADC_CH9 / P2.1
11
18
P3.3 / PWM0_CH0 / CLKO / PWM0_BRAKE
SPI0_SS / P3.5
12
17
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
PWM1_CH0 / UART3_TXD / IC0 / PWM0_CH0 / P1.2
13
16
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
PWM1_CH1 / UART3_RXD / PWM0_CH1 / IC1 / CLKO / ADC_CH7 / P1.1
14
15
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
TSSOP28
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
Figure 4.1-3 Pin Assignment of TSSOP28 Package
4.1.4
TSSOP 20-pin Package Pin Diagram
Corresponding Part Number: MS51FC0AE
1
20
P0.4 / ADC_CH5 / IC3 / PWM0_CH3 / STADC / UART2_RXD / PWM2_CH1
UART0_TXD / ADC_CH3 / P0.6
2
19
P0.3 / ADC_CH6 / IC5 / PWM0_CH5 / UART2_TXD / PWM3_CH1
UART0_RXD / ADC_CH2 / P0.7
3
18
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
nRESET / P2.0
4
17
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
5
16
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
6
15
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
VSS
7
14
P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
8
13
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
VDD
9
12
P1.3 / STADC / I2C0_SCL / ADC_CH13
PWM3_CH1 / UART3_TXD / IC7 / SPI0_SS / PWM0_CH5 / P1.5
10
11
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
TSSOP20
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
MS51 SERIES DATASHEET
Figure 4.1-4 Pin Assignment of TSSOP20 Package
Nov. 28, 2019
Page 16 of 80
Rev 1.00
MS51
4.1.5
QFN 20-pin Package Pin Diagram
16
17
PWM2_CH0 / UART3_TXD / T0 / PWM0_CH2 / IC6 / ADC_CH4 / P0.5
18
UART0_TXD / ADC_CH3 / P0.6
19
P0.1 / PWM0_CH4 / SPI0_MISO / IC4 / HXTOUT / PWM3_CH0
P0.0 / PWM0_CH3 / SPI0_MOSI / IC3 / UART1_RXD / T1 / HXTIN / PWM2_CH1
P1.0 / PWM0_CH2 / SPI0_CLK / IC2 / UART1_TXD / PWM2_CH0
P1.1 / ADC_CH7 / CLKO / IC1 / PWM0_CH1 / UART3_RXD / PWM1_CH1
13
12
11
P0.2 / ICE_CLK / I2C0_SCL / UART1_RXD
15
PWM3_CH1 / UART2_TXD / PWM0_CH5 / IC5 / ADC_CH6 / P0.3
PWM2_CH1 / UART2_RXD / STADC / PWM0_CH3 / IC3 / ADC_CH5 / P0.4
14
Corresponding Part Number: MS51XC0BE
10
P1.2 / PWM0_CH0 / IC0 / UART3_TXD / PWM1_CH0
Top transparent view
QFN20
9
P1.3 / STADC / I2C0_SCL / ADC_CH13
8
P1.4 / PWM0_CH1 / I2C0_SDA / PWM0_BRAKE / ADC_CH14 / PWM1_CH1
7
P1.5 / PWM0_CH5 / SPI0_SS / IC7 / UART3_TXD / PWM3_CH1
6
VDD
33 VSS
1
2
3
4
5
SPI0_CLK / UART2_RXD / INT1 / ADC_CH0 / P1.7
VSS
UART1_TXD / I2C0_SDA / ICE_DAT / P1.6
MS51 SERIES DATASHEET
nRESET / P2.0
20
SPI0_MOSI / UART2_TXD / INT0 / OSCIN / ADC_CH1 / P3.0
UART0_RXD / ADC_CH2 / P0.7
Figure 4.1-5 Pin Assignment of QFN20 Package
Nov. 28, 2019
Page 17 of 80
Rev 1.00
MS51
4.2 MS51 32K Series Pin Description
Pin Number
MS51XC0BE
QFN 20
MS51FC0AE
TSSOP20
MS51EC0AE
TSSOP28
MS51PC0AE
LQFP 32
MS51TC0AE
QFN 33
6
4
9
7
3
1
6
4
13
16
16
23
VDD
VSS
P0.0
PWM0_CH3
PWM2_CH1
IC3
SPI0_MOSI
UART1_RX
XT1_IN
OSCIN
T1
14
17
17
24
P0.1
PWM0_CH4
PWM3_CH0
IC4
SPI0_MISO
XT1_OUT
P0.2
MS51 SERIES DATASHEET
15
18
19
26
16
19
20
27
17
20
21
28
18
1
22
29
I2C0_SCL
UART1_RXD
ICE_CLK
P0.3
ADC_CH6
PWM0_CH5
PWM3_CH1
IC5
UART2_TXD6
SC0_CLK6
P0.4
ADC_CH5
PWM0_CH3
PWM2_CH1
IC3
UART2_RXD6
SC0_DAT
STADC
P0.5
ADC_CH4
PWM0_CH2
PWM2_CH0
IC6
UART3_TXD
SC1_CLK
T0
19
Nov. 28, 2019
2
23
30
Multi-Function Description[1]
Symbol
P0.6
ADC_CH3
Page 18 of 80
Supply voltage VDD for operation.
Ground potential.
Port 0 bit 0.
PWM0 output channel 3.
PWM2 output channel 1.
Input capture channel 3.
SPI master output/slave input.
UART1 receive input.
External 4~24 MHz (high speed) crystal input
pin.
If the EXTEN[1:0] = 10b, OSCIN is the external
clock input pin.
External count input to Timer/Counter 1 or its
toggle output.
Port 0 bit 1.
PWM0 output channel 4.
PWM3 output channel 0.
Input capture channel 4.
SPI master input/slave output.
External 4~24 MHz (high speed) crystal output
pin.
Port 0 bit 2.
2
I C clock.
UART1 receive input.
ICE / ICP clock input.
Port 0 bit 3.
ADC input channel 6.
PWM0 output channel5
PWM3 output channel1
Input capture channel 5.
UART2 transmit data output.
Smart Card 0 clock pin
Port 0 bit 4.
ADC input channel 5.
PWM0 output channel 3.
PWM2 output channel 1.
Input capture channel 3.
UART2 receive input.
Smart Card 0 data pin
External start ADC trigger
Port 0 bit 5.
ADC input channel 4.
PWM0 output channel 2.
PWM2 output channel 0.
Input capture channel 6.
UART3 transmit data output.
Smart card clock pin.
External count input to Timer/Counter 0 or its
toggle output.
Port 0 bit 6.
ADC input channel 3.
Rev 1.00
MS51
Pin Number
MS51XC0BE
QFN 20
MS51FC0AE
TSSOP20
MS51EC0AE
TSSOP28
MS51PC0AE
LQFP 32
MS51TC0AE
QFN 33
20
3
24
31
12
15
15
22
11
14
14
21
10
13
13
20
9
12
7
12
MS51 SERIES DATASHEET
8
11
6
11
UART0_TXD
P0.7
ADC_CH2
UART0_RXD
P1.0
PWM0_CH2
PWM2_CH0
IC2
SPI0_CLK
UART1_TXD
P1.1
ADC_CH7
PWM0_CH1
PWM1_CH1
IC1
UART3_RXD
SC1_DAT
CLKO
P1.2
PWM0_CH0
PWM1_CH0
IC0
UART3_TXD6
SC1_CLK6
P1.3
ADC_CH13
UART0 transmit data output.
Port 0 bit 7.
ADC input channel 2.
UART0 transmit data output.
Port 1 bit 0.
PWM0 output channel 2.
PWM2 output channel 0.
Input capture channel 2.
SPI0 clock.
UART1 receive input.
Port 1 bit 1
ADC input channel 7.
PWM0 output channel 1.
PWM1 output channel 1.
Input capture channel 1.
UART3 receive input.
Smart Card 1 data pin.
System clock output.
Port 1 bit 2.
PWM0 output channel 0.
PWM1 output channel 0.
Input capture channel 0.
UART3 transmit data output.
Smart Card 1 clock pin.
Port 1 bit 3.
ADC input channel 13.
I2C0_SCL
I C0 clock.
External start ADC trigger
Port 1 bit 4.
ADC input channel 14.
PWM0 output channel 1.
PWM1 output channel 1.
STADC
P1.4
ADC_CH14
PWM0_CH1
PWM1_CH1
I2C0_SDA
7
10
4
7
5
8
2
5
3
6
28
3
Nov. 28, 2019
Multi-Function Description[1]
Symbol
PWM0_Brake
P1.5
PWM0_CH5
PWM3_CH1
IC7
SPI0_SS
UART3_TXD6
SC1_CLK6
P1.6
I2C0_SDA
UART1_TXD
ICE_DAT
P1.7
ADC_CH0
SPI0_CLK
UART2_RXD6
SC0_DAT6
INT1
Page 19 of 80
2
2
I C0 data.
PWM0 Fault Brake input.
Port 1 bit 5.
PWM0 output channel 5.
PWM3 output channel 1.
Input capture channel 7.
SPI0 slave select input.
UART3 transmit data output.
Smart card 2 clock pin
Port 1 bit 6.
2
I C0 data.
UART1 transmit data output.
ICE data input or output.
Port 1 bit 7.
ADC input channel 0.
SPI0 clock.
UART2 receive input.
Smart Card 0 data pin
External interrupt 1 input.
Rev 1.00
MS51
Pin Number
MS51XC0BE
QFN 20
MS51FC0AE
TSSOP20
MS51EC0AE
TSSOP28
MS51PC0AE
LQFP 32
MS51TC0AE
QFN 33
Symbol
P2.0
1
4
26
1
nRESET
-
-
11
16
-
-
10
15
-
-
9
14
-
-
8
13
P2.1
ADC_CH9
PWM2_CH0
P2.2
ADC_CH10
PWM1_CH1
UART4_RX6
SC2_DAT6
P2.3
ADC_CH11
PWM1_CH0
UART4_TXD6
SC2_CLK6
P2.4
ADC_CH12
T0
MS51 SERIES DATASHEET
-
-
5
8
2
5
27
2
P2.5
ADC_CH15
SPI0_MISO
UART3_RXD6
SC1_DAT6
P3.0
ADC_CH1
PI0_MOSI
UART2_TXD6
SC0_CLK6
INT0
OSCIN
-
-
-
18
-
-
-
19
-
-
18
25
-
-
25
32
-
-
12
17
-
-
-
9
Nov. 28, 2019
P3.1
PWM2_CH1
P3.2
PWM3_CH0
P3.3
PWM0_CH0
CLK_OUT
PWM0_Brake
P3.4
PWM3_CH1
UART3_RXD6
SC1_DAT6
P3.5
SPI0_SS
P3.6
UART1_TXD
Page 20 of 80
Multi-Function Description[1]
Port 2 bit 0 input pin available when RPD
(CONFIG0.2) is programmed as 0.
It is a Schmitt trigger input pin for hardware
device reset. A low on this pin resets the device.
nRESET pin has an internal pull-up resistor
allowing power-on reset by simply connecting
an external capacitor to VSS.
Port 2 bit 1.
ADC input channel 9.
PWM2 output channel 0.
Port 2 bit 2.
ADC input channel 10.
PWM1 output channel 1.
UART4 receive input.
Smart card 2 data pin
Port 2 bit 3.
ADC input channel 11.
PWM1 output channel 0.
UART4 transmit data output.
Smart card 2 clock pin
Port 2 bit 4.
ADC input channel 12.
External count input to Timer/Counter 0 or its
toggle output.
Port 2 bit 5.
ADC input channel 15.
SPI master input/slave output.
UART3 receive input.
Smart card 1 data pin
Port 3 bit 0.
ADC input channel 1.
SPI master output/slave input.
UART2 transmit data output.
Smart card 0 clock pin
External interrupt 0 input.
If the EXTEN[1:0] = 11b, OSCIN is the external
clock input pin.
Port 3 bit 1.
PWM2 output channel 1.
Port 3 bit 2.
PWM3 output channel 0.
Port 3 bit 3.
PWM3 output channel 0.
System clock output.
PWM0 Fault Brake input.
Port 3 bit 4.
PWM3 output channel 0.
UART3 receive input.
Smart card 0 data pin
Port 3 bit 5.
SPI0 slave select input.
Port 3 bit 6.
UART1 transmit data output.
Rev 1.00
MS51
Pin Number
MS51XC0BE
QFN 20
MS51FC0AE
TSSOP20
MS51EC0AE
TSSOP28
MS51PC0AE
LQFP 32
MS51TC0AE
QFN 33
-
-
-
10
Symbol
P3.7
UART1_RXD
Multi-Function Description[1]
Port 3 bit 7.
UART1 receive input.
Note:
1. All I/O pins can be configured as a interrupt pin. This feature is not listed in multi-function description
2. UART0_TXD and UART0_RXD pins are software exchangeable by UART0PX (AUXR1.2).
3. [I2C] alternate function remapping option. I2C pins is software switched by I2CPX (I2CON.0).
4. [STADC] alternate function remapping option. STADC pin is software switched by STADCPX(ADCCON1.6).
5. PIOx register decides which pins are PWM or GPIO.
6. UART2_TXD and UART2_RXD pin is defined by AUXR2 register. UART3_TXD, UART3_RXD, UART4_TXD
and UART4_RXD pin defined by AUXR3 register.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 21 of 80
Rev 1.00
MS51
5
BLOCK DIAGRAM
5.1 MS51 32K Series Block Diagram
Figure 5.1-1 Functional Block Diagram shows the MS51 functional block diagram and gives the outline
of the device. User can find all the peripheral functions of the device in the diagram.
1T High
Performance
8051 Core
Memory
Access
POR / LVR / BOD
32 KB APROM
Flash
Timer 0/1
Max. 4KB
LDROM Flash
Timer 2
with
Input Capture
P1[7:0]
P2[5:0]
P3[7:0]
MS51 SERIES DATASHEET
Any Port
INT0
INT1
8
P1
6
P2
Digital
Peripheral
UART0/1_TX
UART0/1_RX
Serial Ports
(UART 0/1)
UART2/3/4_TX
UART2/3/4_RX
UART2/3/4
(ISO 7816-3 port)
I2C0_SDA
I2C0_SCL
I2C0
8
P3
8
ICAP0~2
Watchdog Timer
8-bit Internal Bus
GPIO
3
Self Wake-up
Timer
2 Kbytes XRAM
(Auxiliary RAM)
P0
T0
Timer 3
256 bytes
Internal RAM
P0[7:0]
VSS
T1
Max. Bytes
Data Flash
(page: 128B)
8
Power
Management
VDD
SPI0
GPIO Interrupt
PWM0/1/2/3
6
6
15
External Interrupt
12-bit ADC
SPI0_MOSI
SPI0_MISO
SPI0_SS
SPI0_SCK
PWM0CH0~5
PWM1/2/3CH0~1
FB0
AIN0~7, 9~15
STADC
Analog
Peripheral
System Clock
XIN
XOUT
4-24 MHz
Oscillator Circuit
(HXT)
16/24 MHz Internal
RC Oscillator
(HIRC)
Clock Divider
10 kHz Internal RC
Oscillator
(LIRC)
System Clock
Source
Figure 5.1-1 Functional Block Diagram
Nov. 28, 2019
Page 22 of 80
Rev 1.00
MS51
6
FUNCTIONAL DESCRIPTION
6.1 Memory Organization
6.1.1
Overview
A standard 80C51 based microcontroller divides the memory into two different sections, Program
Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the
Data Memory is used to store data or variations during the program execution.
The Data Memory occupies a separate address space from Program Memory. In MS51, there are 256
bytes of internal scratch-pad RAM. For many applications those need more internal RAM, the MS51
provides another on-chip 2 Kbytes of RAM, which is called XRAM, accessed by MOVX instruction.
The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application
ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG
bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have
different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash
control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O
pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these
modes.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 23 of 80
Rev 1.00
MS51
6.2
Flash Memory Control
6.2.1
Reset
6.2.1.1 Overview
The MS51 has several options to place device in reset condition. It also offers the software flags to
indicate the source, which causes a reset. In general, most SFR go to their Reset value irrespective of
the reset condition, but there are several reset source indicating flags whose state depends on the
source of reset. User can read back these flags to determine the cause of reset using software. There
are five ways of putting the device into reset state. They are power-on reset, brown-out reset, external
reset, WDT reset, and software reset.
6.2.1.2 Power-On Reset (POR) and Low Voltage Reset (LVR)
The MS51 incorporates an internal power-on reset (POR) and a low voltage reset (LVR). During a
power-on process of rising power supply voltage VDD, the POR or LVR will hold the MCU in reset
mode when VDD is lower than the voltage reference thresholds. This design makes CPU not access
program Flash while the VDD is not adequate performing the Flash reading. If an undetermined
operating code is read from the program Flash and executed, this will put CPU and even the whole
system in to an erroneous state. After a while, VDD rises above the threshold where the system can
work, the selected oscillator will start and then program code will execute from 0000H. At the same
time, a power-on flag POF (PCON.4) will be set 1 to indicate a cold reset, a power-on process
complete. Note that the contents of internal RAM will be undetermined after a power-on. It is
recommended that user gives initial values for the RAM block.
The POF is recommended to be cleared to 0 via software to check if a cold reset or warm reset
performed after the next reset occurs. If a cold reset caused by power off and on, POF will be set 1
again. If the reset is a warm reset caused by other reset sources, POF will remain 0. User may take a
different course to check other reset flags and deal with the warm reset event. For detailed electrical
characteristics, refer to the table 35-7 and 35-8.
PCON – Power Control
MS51 SERIES DATASHEET
Register
SFR Address
PCON
87H, All pages
Reset Value
POR: 0001_0000b
Others: 000U _0000b
7
6
5
4
3
2
1
0
SMOD
SMOD0
LPR
POF
GF1
GF0
PD
IDL
R/W
R/W
RW
R/W
R/W
R/W
R/W
R/W
Bit
Name
4
POF
Description
Power-on reset flag
This bit will be set as 1 after a power-on reset. It indicates a cold reset, a power-on reset complete.
This bit remains its value after any other resets. This flag is recommended to be cleared via
software.
6.2.1.3 Brown-Out Reset
The brown-out detection circuit is used for monitoring the VDD level during execution. When VDD drops
to the selected brown-out trigger level (VBOD), the brown-out detection logic will reset the MCU if
Nov. 28, 2019
Page 24 of 80
Rev 1.00
MS51
BORST (BODCON0.2) setting 1. After a brown-out reset, BORF (BODCON0.1) will be set as 1 via
hardware. BORF will not be altered by any reset other than a power-on reset or brown-out reset itself.
This bit can be set or cleared by software.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 25 of 80
Rev 1.00
MS51
BODCON0 – Brown-out Detection Control 0
Register
SFR Address
Reset Value
POR,CCCC XC0X b
BODCON0
BOD, UUUU XU1X b
A3H, Page 0, TA protected
Others,UUUU XUUX b
7
6
5
4
3
2
1
0
BODEN
BOV[2:0]
BOF
BORST
BORF
BOS
R/W
R/W
R/W
R/W
R/W
R
Bit
Name
1
BORF
Description
Brown-out reset flag
When the MCU is reset by brown-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software.
6.2.1.4 External Reset and Hard Fault Reset
̅̅̅̅̅̅ is an input with a Schmitt trigger. An external reset is accomplished by
The external reset pin RST
̅̅̅̅̅̅
holding the RST pin low for at least 24 system clock cycles to ensure detection of a valid hardware
reset signal. The reset circuitry then synchronously applies the internal reset signal. Thus, the reset is
a synchronous operation and requires the clock to be running to cause an external reset.
MS51 SERIES DATASHEET
Once the device is in reset condition, it will remain as long as ̅̅̅̅̅̅
RST pin is low. After the ̅̅̅̅̅̅
RST high is
removed, the MCU will exit the reset state and begin code executing from address 0000H. If an
external reset applies while CPU is in Power-down mode, the way to trigger a hardware reset is
slightly different. Since the Power-down mode stops system clock, the reset signal will asynchronously
cause the system clock resuming. After the system clock is stable, MCU will enter the reset state.
There is a RSTPINF (AUXR0.6) flag, which indicates an external reset took place. After the external
reset, this bit will be set as 1 via hardware. RSTPINF will not change after any reset other than a
power-on reset or the external reset itself. This bit can be cleared via software.
Hard Fault reset will occur if CPU fetches instruction address over Flash size, HardF (AUXR0.5) flag
will be set via hardware. HardF will not change after any reset other than a power-on reset or the
external reset itself. This bit can be cleared via software. If MCU run in OCD debug mode and
OCDEN = 0, hard fault reset will be disabled. Only HardF flag be asserted.
Nov. 28, 2019
Page 26 of 80
Rev 1.00
MS51
AUXR1 – Auxiliary Register 1
Register
SFR Address
Reset Value
POR: 0000 0000b,
AUXR1
Software reset: 1U00 0000b,
A2H , Page 0
nRESET pin: U100 0000b,
Others: UUU0 0000b
7
6
5
4
3
2
1
0
SWRF
RSTPINF
HardF
SLOW
GF2
UART0PX
0
DPS
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Bit
Name
6
RSTPINF
Description
External reset flag
When the MCU is reset by the external reset, this bit will be set via hardware. It is recommended
that the flag be cleared via software.
5
HardF
Hard Fault reset flag
Once CPU fetches instruction address over Flash size while EHFI (EIE1.4)=0, MCU will reset
and this bit will be set via hardware. It is recommended that the flag be cleared via software.
Note: If MCU run in OCD debug mode and OCDEN = 0, Hard fault reset will disable. Only
HardF flag be asserted.
6.2.1.5 Watchdog Timer Reset
MS51 SERIES DATASHEET
The WDT is a free running timer with programmable time-out intervals and a dedicated internal clock
source. User can clear the WDT at any time, causing it to restart the counter. When the selected timeout occurs but no software response taking place for a while, the WDT will reset the system directly
and CPU will begin execution from 0000H.
Once a reset due to WDT occurs, the WDT reset flag WDTRF (WDCON.3) will be set. This bit keeps
unchanged after any reset other than a power-on reset or WDT reset itself. User can clear WDTRF via
software.
WDCON – Watchdog Timer Control
Register
SFR Address
Reset Value
WDCON
AAH, Page 0, TA protected
WDT 0000_1UUU b
POR 0000_0111 b
Others 0000_UUUU b
7
6
5
4
3
WDTR
WDCLR
WDTF
WIDPD
WDTRF
WDPS[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
Nov. 28, 2019
Page 27 of 80
2
1
0
Rev 1.00
MS51
Bit
Name
3
WDTRF
Description
WDT reset flag
When the CPU is reset by WDT time-out event, this bit will be set via hardware. This flag is
recommended to be cleared via software after reset.
6.2.1.6 Software Reset
The MS51 provides a software reset, which allows the software to reset the whole system just similar
to an external reset, initializing the MCU as it reset state. The software reset is quite useful in the end
of an ISP progress. For example, if an ISP of Boot Code updating User Code finishes, a software
reset can be asserted to re-boot CPU to execute new User Code immediately. Writing 1 to SWRST
(CHPCON.7) will trigger a software reset. Note that this bit is writing TA protection. The instruction that
sets the SWRST bit is the last instruction that will be executed before the device reset. See demo
code below.
If a software reset occurs, SWRF (AUXR0.7) will be automatically set by hardware. User can check it
as the reset source indicator. SWRF keeps unchanged after any reset other than a power-on reset or
software reset itself. SWRF can be cleared via software.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 28 of 80
Rev 1.00
MS51
CONFIG0
7
6
5
4
3
2
1
0
CBS
-
OCDPWM
OCDEN
-
RPD
LOCK
-
R/W
-
R/W
R/W
-
R/W
R/W
-
Factory default value: 1111 1111b
Bit
Name
7
CBS
Description
CONFIG boot select
This bit defines from which block that MCU re-boots after resets except software reset.
1 = MCU will re-boot from APROM after resets except software reset.
0 = MCU will re-boot from LDROM after resets except software reset.
5
OCDPWM
PWM output state under OCD halt
This bit decides the output state of PWM when OCD halts CPU.
1 = Tri-state pins those are used as PWM outputs.
0 = PWM continues.
Note that this bit is valid only when the corresponding PIO bit of PWM channel is set as 1.
4
OCDEN
OCD enable
1 = OCD Disabled.
0 = OCD Enabled.
Note: If MCU run in OCD debug mode and OCDEN = 0, hard fault reset will be disabled and
only Hard F flag be asserted.
2
RPD
Reset pin disable
1 = The reset function of P2.0/Nrst pin Enabled. P2.0/Nrst functions as the external reset pin.
0 = The reset function of P2.0/Nrst pin Disabled. P2.0/Nrst functions as an input-only pin P2.0.
MS51 SERIES DATASHEET
1
LOCK
Chip lock enable
1 = Chip is unlocked. Flash Memory is not locked. Their contents can be read out through a
parallel Writer/ICP programmer.
0 = Chip is locked. Whole Flash Memory is locked. Their contents read through a parallel
Writer or ICP programmer will be all blank (FFH). Programming to Flash Memory is invalid.
Note that CONFIG bytes are always unlocked and can be read. Hence, once the chip is
locked, the CONFIG bytes cannot be erased or programmed individually. The only way to
disable chip lock is execute “whole chip erase”. However, all data within the Flash Memory
and CONFIG bits will be erased when this procedure is executed.
If the chip is locked, it does not alter the IAP function.
CONFIG0
7
6
5
4
3
2
1
0
CBS
-
OCDPWM
OCDEN
-
RPD
LOCK
-
Software reset does not reload
CHPCON
7
6
5
4
3
2
1
0
SWRST
IAPFF
-
-
-
-
BS
IAPEN
Figure 6.2-1 CONFIG0 Any Reset Reloading
Nov. 28, 2019
Page 29 of 80
Rev 1.00
MS51
CONFIG1
7
6
5
4
3
2
1
-
-
-
-
-
LDSIZE[2:0]
-
-
-
-
-
R/W
0
Factory default value: 1111 1111b
Bit
Name
2:0
LDSIZE[2:0]
Description
LDROM size select
This field selects the size of LDROM.
111 = No LDROM. APROM is 32 Kbytes.
110 = LDROM is 1 Kbytes. APROM is 31 Kbytes.
101 = LDROM is 2 Kbytes. APROM is 30 Kbytes.
100 = LDROM is 3 Kbytes. APROM is 29 Kbytes.
0xx = LDROM is 4 Kbytes. APROM is 28 Kbytes.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 30 of 80
Rev 1.00
MS51
CONFIG2
7
6
5
4
3
2
1
0
CBODEN
CBOV[2:0]
BOIAP
CBORST
-
-
R/W
R/W
R/W
R/W
-
-
Factory default value: 1111 1111b
Bit
Name
7
Description
CBODEN
CONFIG brown-out detect enable
1 = Brown-out detection circuit on.
0 = Brown-out detection circuit off.
5:4
CBOV[1:0]
CONFIG brown-out voltage select
11 = VBOD is 2.2V.
10 = VBOD is 2.7V.
01 = VBOD is 3.7V.
00 = VBOD is 4.4V.
3
BOIAP
Brown-out inhibiting IAP
This bit decides whether IAP erasing or programming is inhibited by brown-out status. This bit
is valid only when brown-out detection is enabled.
1 = IAP erasing or programming is inhibited if VDD is lower than VBOD.
0 = IAP erasing or programming is allowed under any workable V DD.
2
CBORST
CONFIG brown-out reset enable
This bit decides whether a brown-out reset is caused by a power drop below VBOD.
1 = Brown-out reset Enabled.
0 = Brown-out reset Disabled.
MS51 SERIES DATASHEET
CONFIG2
7
6
CBODEN
BODCON0
7
6
BODEN
5
4
CBOV[2:0]
5
3
2
1
0
BOIAP
CBORST
-
-
4
BOV[2:0]
3
2
1
0
BOF
BORST
BORF
BOS
Figure 6.2-2 CONFIG2 Power-On Reset Reloading
Nov. 28, 2019
Page 31 of 80
Rev 1.00
MS51
CONFIG4
7
6
5
4
3
2
1
0
WDTEN[3:0]
-
-
-
-
R/W
-
-
-
-
Factory default value: 1111 1111b
Bit
Name
7:4
Description
WDTEN[3:0]
WDT enable
This field configures the WDT behavior after MCU execution.
1111 = WDT is Disabled. WDT can be used as a general purpose timer via software control.
0101 = WDT is Enabled as a time-out reset timer and it stops running during Idle or Powerdown mode.
Others = WDT is Enabled as a time-out reset timer and it keeps running during Idle or Powerdown mode.
3:0
-
Reserved
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 32 of 80
Rev 1.00
MS51
6.3
General Purpose I/O (GPIO)
The MS51 has a maximum of 30 general purpose I/O pins which 29 bit-addressable general I/O pins
grouped as 4 ports, P0 to P3, and 1 input only pin as P20. Each port has its port control register (Px
register). The writing and reading of a port control register have different meanings. A write to port
control register sets the port output latch logic value, whereas a read gets the port pin logic state.
These four modes are quasi-bidirectional (standard 8051 port structure), push-pull, input-only, and
open-drain modes. Each port spends two special function registers PxM1 and PxM2 to select the I/O
mode of port Px. The list below illustrates how to select the I/O mode of Px.n. Note that the default
configuration of is input-only (high-impedance) after any reset.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 33 of 80
Rev 1.00
MS51
6.4
6.4.1
Timer
Timer/Counter 0 And 1
6.4.1.1 Overview
Timer/Counter 0 and 1 on MS51 are two 16-bit Timers/Counters. Each of them has two 8-bit registers
those form the 16-bit counting register. For Timer/Counter 0 they are TH0, the upper 8-bit register, and
TL0, the lower 8-bit register. Similarly Timer/Counter 1 has two 8-bit registers, TH1 and TL1. TCON
and TMOD can configure modes of Timer/Counter 0 and 1.
̅ bit in TMOD. Each Timer/Counter has its own
The Timer or Counter function is selected by the C/T
selection bit. TMOD.2 selects the function for Timer/Counter 0 and TMOD.6 selects the function for
Timer/Counter 1
When configured as a “Timer”, the timer counts the system clock cycles. The timer clock is 1/12 of the
system clock (FSYS) for standard 8051 capability or direct the system clock for enhancement, which is
selected by T0M (CKCON.3) bit for Timer 0 and T1M (CKCON.4) bit for Timer 1. In the “Counter”
mode, the countering register increases on the falling edge of the external input pin T0. If the sampled
value is high in one clock cycle and low in the next, a valid 1-to-0 transition is recognized on T0 or T1
pin.
The Timers 0 and 1 can be configured to automatically to toggle output whenever a timer overflow
occurs. The same device pins that are used for the T0 and T1 count inputs are also used for the timer
toggle outputs. This function is enabled by control bits T0OE and T1OE in the CKCON register, and
apply to Timer 0 and Timer 1 respectively. The port outputs will be logic 1 prior to the first timer
̅ bit should be cleared
overflow when this mode is turned on. In order for this mode to function, the C/T
selecting the system clock as the clock source for the timer.
Note that the TH0 (TH1) and TL0 (TL1) are accessed separately. It is strongly recommended that in
mode 0 or 1, user should stop Timer temporally by clearing TR0 (TR1) bit before reading from or
writing to TH0 (TH1) and TL0 (TL1). The free-running reading or writing may cause unpredictable
result.
MS51 SERIES DATASHEET
6.4.2
Timer2 And Input Capture
6.4.2.1 Overview
Timer 2 is a 16-bit up counter cascaded with TH2, the upper 8 bits register, and TL2, the lower 8 bit
register. Equipped with RCMP2H and RCMP2L, Timer 2 can operate under compare mode and auto̅̅̅̅̅̅ (T2CON.0). An 3-channel input capture module makes Timer 2
reload mode selected by CM/RL2
detect and measure the width or period of input pulses. The results of 3 input captures are stores in
C0H and C0L, C1H and C1L, C2H and C2L individually. The clock source of Timer 2 is from the
system clock pre-scaled by a clock divider with 8 different scales for wide field application. The clock is
enabled when TR2 (T2CON.2) is 1, and disabled when TR2 is 0. The following registers are related to
Timer 2 function.
Nov. 28, 2019
Page 34 of 80
Rev 1.00
MS51
C0L
P1.5/IC7
P0.5/IC6
P0.3/IC5
P0.1/IC4
P0.4/IC3
P0.0/IC3
P1.0/IC2
P1.1/IC1
P1.2/IC0
1000
0111
0110
0101
0100
0011
0010
0001
0000
CAP1
CAP2
CAPF0
CAPF0
[00]
CAP0
C0H
CAPF1
Noise
Filter
Input Capture Interrupt
[01]
CAPF2
ENF0
(CAPCON2.4)
[10]
or
CAPEN0
(CAPCON0.4)
CAP0LS[1:0]
(CAPCON1[1:0])
Input Capture 0 Module
Input Capture 1 Module
Input Capture 2 Module
Input Capture Flags (CAPF[2:0])
CAPF0
CAPF1
CAPF2
Clear Timer 2
CAPCR[1]
(T2MOD.3)
CMPCR
(T2MOD.2)
Clear
Counter
Clear Timer 2
FSYS
Pre-scalar
TL2
TH2
TF2
Timer 2 Interrupt
TR2
(T2CON.2)
T2DIV[2:0]
(T2MOD[6:4])
CAPF0
CAPF1
CAPF2
LDTS[1:0]
(T2MOD[1:0])
00
01
10
11
=
LDEN[1]
(T2MOD.7)
RCMP2L
RCMP2H
Timer 2 Module
[1] Once CAPCR and LDEN are both set, an input capture event only clears TH2 and TL2 without reloading RCMP2H and RCMP2L contents.
MS51 SERIES DATASHEET
Figure 6.4-1 Timer 2 Block Diagram
Nov. 28, 2019
Page 35 of 80
Rev 1.00
MS51
6.4.3
Timer 3
6.4.3.1 Overview
Timer 3 is implemented simply as a 16-bit auto-reload, up-counting timer. The user can select the prescale with T3PS[2:0] (T3CON[2:0]) and fill the reload value into RH3 and RL3 registers to determine
its overflow rate. User then can set TR3 (T3CON.3) to start counting. When the counter rolls over
FFFFH, TF3 (T3CON.4) is set as 1 and a reload is generated and causes the contents of the RH3 and
RL3 registers to be reloaded into the internal 16-bit counter. If ET3 (EIE1.1) is set as 1, Timer 3
interrupt service routine will be served. TF3 is auto-cleared by hardware after entering its interrupt
service routine.
Timer 3 can also be the baud rate clock source of both UARTs. For details, please see Section 錯誤!
找不到參照來源。“錯誤! 找不到參照來源。”.
FSYS
TR3
(T3CON.3)
Pre-scalar
(1/1~1/128)
T3PS[2:0]
(T3CON[2:0])
Timer 3
Overflow
Internal 16-bit Counter
0
7 0
RL3
TF3
(T3CON.4)
Timer 3 Interrupt
7
RH3
Figure 6.4-2 Timer 3 Block Diagram
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 36 of 80
Rev 1.00
MS51
6.5 Pulse Width Modulated (PWM)
6.5.1
Overview
The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can
used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a
simple digital to analog converter output through a low pass filter circuit.
The MS51 PWM0 is especially designed for motor control by providing three pairs, maximum 16-bit
resolution of PWM0 output with programmable period and duty. The architecture makes user easy to
drive the one-phase or three-phase brushless DC motor (BLDC), or three-phase AC induction motor.
Each of six PWM can be configured as one of independent mode, complementary mode, or
synchronous mode. If the complementary mode is used, a programmable dead-time insertion is
available to protect MOS turn-on simultaneously. The PWM waveform can be edge-aligned or centeraligned with variable interrupt points.
The MS51 PWM1/2/3 provide individual configurable period and duty. maximum 16-bit resolution
output. Each of two PWM1/2/3 can be configured as one of independent mode, complementary mode,
or synchronous mode.The PWM1/2/3 waveform can be edge-aligned or center-aligned with variable
interrupt points.
PWM output pin define and enable control register table.
PWM Channel
PWM0_CH0
PWM0_CH1
PWM0_CH2
Control register 1
Output
Pin
SFR Byte Name Bit name
Value
Control register2
SFR Byte Name
Bit name
Value
MS51 SERIES DATASHEET
P1.2
PIOCON0[0]
PIO12
1
AUXR4[1:0]
PWM1C0P
00
P1.1
PIOCON0[1]
PIO11
1
AUXR4[3:2]
PWM1C1P
00
P1.4
PIOCON1[1]
PIO14
1
AUXR4[1:0]
PWM1C0P
00
P3.3
PIOCON2[6]
PIO33
1
-
-
-
P1.0
PIOCON0[2]
PIO10
1
AUXR4[5:4]
PWM2C0P
00
P0.5
PIOCON1[2]
PIO05
1
AUXR4[5:4]
PWM2C0P
00
P0.0
PIOCON0[3]
PIO00
1
AUXR4[7:6]
PWM2C1P
00
P0.4
PIOCON1[3]
PIO04
1
AUXR4[7:6]
PWM2C1P
00
P0.1
PIOCON0[4]
PIO01
1
AUXR5[1:0]
PWM3C0P
00
P0.3
PIOCON0[5]
PIO03
1
AUXR5[3:2]
PWM3C1P
00
P1.5
PIOCON1[5]
PIO15
1
AUXR5[3:2]
PWM3C1P
00
P2.3
PIOCON2[2]
PIO23
1
AUXR4[1:0]
PWM1C0P
00
P1.2
PIOCON0[0]
PIO12
1
AUXR4[1:0]
PWM1C0P
00
P2.2
PIOCON2[1]
PIO22
1
P1.4
PIOCON1[1]
PIO14
1
P1.1
PIOCON0[1]
PIO11
1
11
P2.1
PIOCON2[0]
PIO21
1
00
P1.0
PIOCON0[2]
PIO10
1
P0.5
PIOCON1[2]
PIO05
1
P3.0
-
-
-
PWM0_CH3
PWM0_CH4
PWM0_CH5
PWM1_CH0
PWM1_CH1
PWM2_CH0
PWM2_CH1
Nov. 28, 2019
Page 37 of 80
01
AUXR4[3:2]
AUXR4[5:4]
PWM1C1P
PWM2C0P
10
01
10
AUXR4[7:6]
PWM2C1P
00
Rev 1.00
MS51
PWM Channel
PWM3_CH0
Control register 1
Output
Pin
SFR Byte Name Bit name
Value
Control register2
SFR Byte Name
Bit name
Value
P3.1
PIOCON2[4]
PIO31
1
01
P0.0
PIOCON0[3]
PIO00
1
10
P0.4
PIOCON1[3]
PIO04
1
11
P3.2
PIOCON2[5]
PIO32
1
01
P0.1
PIOCON0[4]
PIO01
1
P17
PIOCON1[7]
PIO17
1
AUXR5[1:0]
PWM3C0P-
10
11
Table 6.5-1 PWM Pin Define And Enable Control Register
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 38 of 80
Rev 1.00
MS51
6.6 Watchdog Timer (WDT)
6.6.1
Overview
The MS51 provides one Watchdog Timer (WDT). It can be configured as a time-out reset timer to
reset whole device. Once the device runs in an abnormal status or hangs up by outward interference,
a WDT reset recover the system. It provides a system monitor, which improves the reliability of the
system. Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or
electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the
periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system,
which is able to operate during Idle or Power-down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the
WDT to operate as a time-out reset timer or a general purpose timer.
1
× 64 , where
FLIRC × clock dividerscalar
FLIRC is the frequency of internal 10 kHz oscillator. The following table shows an example of the
Watchdog time-out interval with different pre-scales.
The Watchdog time-out interval is determined by the formula
WDT Time-Out Timing[1]
MS51 SERIES DATASHEET
WDPS.2
WDPS.1
WDPS.0
Clock Divider Scale
0
0
0
1/1
6.40 ms
0
0
1
1/4
25.60 ms
0
1
0
1/8
51.20 ms
0
1
1
1/16
102.40 ms
1
0
0
1/32
204.80 ms
1
0
1
1/64
409.60 ms
1
1
0
1/128
819.20 ms
1
1
1
1/256
1.638 s
Note: This is an approximate value since the deviation of LIRC.
Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars
Since the limitation of the maxima vaule of WDT timer delay. To up MS51 from idle mode or power
down mode suggest use WKT function see Chapter 6.7 Self Wake-Up Timer (WKT).
Nov. 28, 2019
Page 39 of 80
Rev 1.00
MS51
6.7 Self Wake-Up Timer (WKT)
6.7.1
Overview
The MS51 has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in
low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode.
When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power
management mode. WKT has one clock source, internal 10 kHz. Note that the system clock frequency
must be twice over WKT clock. If WKT starts counting, the selected clock source will remain active
once the device enters Idle or Power-down mode. Note that the selected clock source of WKT will not
automatically enabled along with WKT configuration. User should manually enable the selected clock
source and waiting for stability to ensure a proper operation.
The WKT is implemented simply as a 8-bit auto-reload, up-counting timer with pre-scale 1/1 to 1/2048
selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK register to determine its
overflow rate. The WKTR (WKCON.3) can be set to start counting. When the counter rolls over FFH,
WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of the RWK register
to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT interrupt service
routine will be served.
10 kHz Internal
Oscillator
FLIRC
WKTR
(WKCON.3)
Pre-scalar
(1/1~1/2048)
Internal 16-bit Counter
WKPS[2:0]
(WKCON[2:0]) 0
WKT
Overflow
WKTF
(WKCON.4)
WKT Interrupt
15
RWK
Figure 6.7-1 Self Wake-Up Timer Block Diagram
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 40 of 80
Rev 1.00
MS51
6.8 Serial Port (UART0 & UART1)
6.8.1
Overview
The MS51 includes two enhanced full duplex serial ports enhanced with automatic address
recognition and framing error detection. As control bits of these two serial ports are implemented the
same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but
only to serial port 0.
Each serial port supports one synchronous communication mode, Mode 0, and three modes of full
duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it
can transmit and receive simultaneously. The serial port is also receiving-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the
register. The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads
the transmitting register, and reading SBUF accesses a physically separate receiving register. There
are four operation modes in serial port. In all four modes, transmission initiates by any instruction that
uses SBUF as a destination register.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 41 of 80
Rev 1.00
MS51
6.9 ISO 7816-3 Interface (SC0~2 & UART2 ~ 4)
6.9.1
Overview
The HAG035 provides ISO 7816-3 Interface controller (SC controller) with asynchronous protocal
based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the smartcard reset function and
card detection function. This controller also provides UART emulation for high precision baud rate
communication.
Internal Data Bus
RX_IN
RX_FIFO
Control and Status
Registers
TX_FIFO
RX Shift
Register
TX/RX
Control Unit
TX Shift
Register
Baud Rate
Generator
ETU Clock
Generator
TX_OUT
Figure 6.9-1 SC Controller Block Diagram
MS51 SERIES DATASHEET
ISO-7816-3 T = 0, T = 1 compliant
Programmable transmission clock frequency
Programmable extra guard time selection
Supports auto inverse convention function
Supports UART mode
–
Full duplex, asynchronous communications
–
Supports programmable baud rate generator for each channel
–
Programmable transmitting data delay time between the last stop bit leaving the TXFIFO and the de-assertion by setting SCnEGT register
–
Programmable even, odd or no parity bit generation and detection
–
Programmable stop bit, 1 or 2 stop bit generation
Following is the ISO 7816-3 multi function pin define
SFR Define
URAT Pin
SC Pin
Pin Name
SFR Byte Name
SFR Bit Name
AUXR2[7:6]
UART2TXP
P0.3
UART2_TXD
SC0_CLK
01
P3.0
10
P0.4
UART2_RXD
SC0_DAT
01
AUXR2[5:4]
P1.7
Nov. 28, 2019
Value
UART2RXP
10
Page 42 of 80
Rev 1.00
MS51
SFR Define
URAT Pin
SC Pin
Pin Name
SFR Byte Name
SFR Bit Name
P1.2
UART3_TXD
SC1_CLK
UART3_RXD
SC1_DAT
P1.5
Value
01
AUXR3[3:2]
UART3TXP
10
P0.5
11
P1.1
01
P2.5
AUXR3[1:0]
UART3RXP
P3.4
10
11
UART4_TXD
SC2_CLK
P2.3
AUXR3[7:6]
UART4TXP
01
UART4_RXD
SC2_DAT
P2.2
AUXR3[5:4]
UART4RXP
01
Table 6.9-1 Smart Card or UART Pin Define And Enable Control Register
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 43 of 80
Rev 1.00
MS51
2
6.10
Inter-Integrated Circuit (I C)
6.10.1 Overview
2
The MS51 provides two Inter-Integrated Circuit (I C) bus to serves as an serial interface between the
2
microcontrollers and the I C devices such as EEPROM, LCD module, temperature sensor, and so on.
2
The I C bus used two wires design (a serial data line I2C0_SDA and a serial clock line I2C0_SCL) to
transfer information between devices.
2
The I C bus uses bi-directional data transfer between masters and slaves. There is no central master
and the multi-master system is allowed by arbitration between simultaneously transmitting masters.
The serial clock synchronization allows devices with different bit rates to communicate via one serial
2
bus. The I C bus supports four transfer modes including master transmitter, master receiver, slave
2
receiver, and slave transmitter. The I C interface only supports 7-bit addressing mode. A special mode
2
General Call is also available. The I C can meet both standard (up to 100kbps) and fast (up to 400k
bps) speeds.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 44 of 80
Rev 1.00
MS51
6.11
Serial Peripheral Interface (SPI)
6.11.1 Overview
The MS51 provides two Serial Peripheral Interface (SPI) block to support high-speed serial
communication. SPI is a full-duplex, high-speed, synchronous communication bus between
microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It
provides either Master or Slave mode, high-speed rate up to FSYS/2, transfer complete and write
collision flag. For a multi-master system, SPI supports Master Mode Fault to protect a multi-master
conflict.
FSYS
S
M
MSB
MOSI
CLOCK
SPR0
SPR1
M
S
Write Data Buffer
8-bit Shift Register
Read Data Buffer
Select
MISO
LSB
Pin Contorl Logic
Divider
/2, /4, /8, /16
Clock Logic
SPCLK
DISMODF
SSOE
MSTR
SPIEN
SS
MSTR
SPI Status Register
SPI Interrupt
SPR0
SPR1
CPOL
CPHA
LSBFE
MSTR
SSOE
SPIEN
SPIEN
DISMODF
SPIOVF
MODF
WCOL
MS51 SERIES DATASHEET
SPIF
SPI Status Control Logic
SPI Control Register
Internal
Data Bus
Figure 6.11-1 SPI Block Diagram
Figure15.1 SPI Block Diagram shows SPI block diagram. It provides an overview of SPI architecture in
this device. The main blocks of SPI are the SPI control register logic, SPI status logic, clock rate
control logic, and pin control logic. For a serial data transfer or receiving, The SPI block exists a write
data buffer, a shift out register and a read data buffer. It is double buffered in the receiving and
transmit directions. Transmit data can be written to the shifter until when the previous transfer is not
complete. Receiving logic consists of parallel read data buffer so the shift register is free to accept a
second data, as the first received data will be transferred to the read data buffer.
The four pins of SPI interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift
̅̅̅̅). The MOSI pin is used to transfer a 8-bit data in series from the
Clock (SPCLK), and Slave Select (SS
Master to the Slave. Therefore, MOSI is an output pin for Master device and an input for Slave.
Nov. 28, 2019
Page 45 of 80
Rev 1.00
MS51
Respectively, the MISO is used to receive a serial data from the Slave to the Master.
The SPCLK pin is the clock output in Master mode, but is the clock input in Slave mode. The shift
clock is used to synchronize the data movement both in and out of the devices through their MOSI and
MISO pins. The shift clock is driven by the Master mode device for eight clock cycles. Eight clocks
exchange one byte data on the serial lines. For the shift clock is always produced out of the Master
device, the system should never exist more than one device in Master mode for avoiding device
conflict.
̅̅̅̅). The signal should stay low for any
Each Slave peripheral is selected by one Slave Select pin (SS
̅̅̅̅
Slave access. When SS is driven high, the Slave device will be inactivated. If the system is multislave, there should be only one Slave device selected at the same time. In the Master mode MCU, the
̅̅̅̅
SS pin does not function and it can be configured as a general purpose I/O. However, ̅̅̅̅
SS can be used
as Master Mode Fault detection (see chapter 錯誤! 找不到參照來源。 錯誤! 找不到參照來源。) via
software setting if multi-master environment exists. The MS51 also provides auto-activating function to
̅̅̅̅ between each byte-transfer.
toggle SS
Master/Slave
MCU1
Master/Slave
MCU2
MISO
MISO
MOSI
MOSI
SPCLK
MS51 SERIES DATASHEET
Slave device 1
Slave device 2
I/O
PORT
SO
SI
SCK
SS
SI
SO
SCK
SS
0
1
2
3
SO
0
1
2
3
SI
SS
SCK
SS
SS
I/O
PORT
SPCLK
Slave device 3
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection
Figure 6.11-2 shows a typical interconnection of SPI devices. The bus generally connects devices
together through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. The
Master devices select the individual Slave devices by using four pins of a parallel port to control the
four ̅̅̅̅
SS pins. MCU1 and MCU2 play either Master or Slave mode. The ̅̅̅̅
SS should be configured as
Master Mode Fault detection to avoid multi-master conflict.
MOSI
MOSI
MISO
MISO
SPI shift register
7 6 5 4 3 2 1 0
SPI shift register
7 6 5 4 3 2 1 0
SPCLK SPCLK
SPI clock
generator
SS
Master MCU
*
SS
GND
Slave MCU
* SS configuration follows DISMODF and SSOE bits.
Figure 6.11-3 SPI Single-Master, Single-Slave Interconnection
Nov. 28, 2019
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Rev 1.00
MS51
Figure 6.11-3 shows the simplest SPI system interconnection, single-master and signal-slave. During
a transfer, the Master shifts data out to the Slave via MOSI line. While simultaneously, the Master
shifts data in from the Slave via MISO line. The two shift registers in the Master MCU and the Slave
MCU can be considered as one 16-bit circular shift register. Therefore, while a transfer data pushed
from Master into Slave, the data in Slave will also be pulled in Master device respectively. The transfer
effectively exchanges the data, which was in the SPI shift registers of the two MCUs.
By default, SPI data is transferred MSB first. If the LSBFE (SPCR.5) is set, SPI data shifts LSB first.
This bit does not affect the position of the MSB and LSB in the data register. Note that all the following
description and figures are under the condition of LSBFE logic 0. MSB is transmitted and received
first.
There are three SPI registers to support its operations, including SPI control register (SPCR), SPI
status register (SPSR), and SPI data register (SPDR). These registers provide control, status, data
storage functions, and clock rate selection. The following registers relate to SPI function.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 47 of 80
Rev 1.00
MS51
6.12
12-Bit Analog-To-Digital Converter (ADC)
6.12.1 Overview
The HAG035 is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows
conversion of an analog input signal to a 12-bit binary representation of that signal. The HAG035 is
selected as 8-channel inputs in single end mode. The internal band-gap voltage 1.22 V also can be
the internal ADC input. The analog input, multiplexed into one sample and hold circuit, charges a
sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter.
The converter then generates a digital result of this analog level via successive approximation and
stores the result in the result registers. The ADC controller also supports continuous conversion and
storage result data into XRAM.
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 48 of 80
Rev 1.00
MS51
7
APPLICATION CIRCUIT
7.1 Power supply scheme
EXT_PWR
10uF+0.1uF
MS51
Series
as close to the EXT_PWR as possible
VDD
VSS
EXT_VSS
0.1uF*N
as close to VDD as possible
®
Figure 7.1-1 NuMicro MS51 Power supply circuit
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 49 of 80
Rev 1.00
MS51
7.2 Peripheral Application scheme
DVCC
SPI_SS
SPI_CLK
SPI_MISO
SPI_MOSI
DVCC
ICE / ICP
Interface
CS
VDD
CLK
MISO
MOSI
VSS
SPI
Device
100K
100K
VDD
ICE_DAT
100 *
100 *
DVCC
ICE_CLK
nRESET
DVCC
VSS
MS51 Series
DVCC
4.7K
4.7K
I2C_SCL
CLK
VDD
I2C_SDA
DIO
VSS
I2C
Device
10K
nRESET
Reset
Circuit
10 uF
RS 232 Transceiver
UART_RXD
ROUT
UART_TXD
TIN
RIN
UART
TOUT
PC COM Port
*ICE/ICP interface ICE_DAT/ICE_CLK pin 100ohm resister is selectable only for filter the disturb of noise on the circuit.
®
Figure 7.2-1 NuMicro MS51 Peripheral interface circuit
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 50 of 80
Rev 1.00
MS51
8
ELECTRICAL CHARACTERISTICS
Please refer to the relative Datasheet for detailed information about the MS51 electrical
characteristics.
8.1 General Operating Conditions
(VDD-VSS = 2.4 ~ 5.5V, TA = 25C, Fsys = 16 MHz unless otherwise specified.)
Symbol
Parameter
Min
Typ
Max
Unit
℃
TA
Temperature
-40
-
105
VDD
Operation voltage
2.4
-
5.5
AVDD[*1]
VBG
Analog operation voltage
VDD
1.17
Band-gap voltage[2]
Test Conditions
V
1.30
TA = 25 °C
1.33
TA = -40°C ~105 °C,
1.22
1.14
Note:
1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between V DD and
AVDD can be tolerated during power-on and power-off operation .
2. Based on characterization, tested in production.
Table 8.1-1 General operating conditions
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 51 of 80
Rev 1.00
MS51
8.2 DC Electrical Characteristics
8.2.1
Supply Current Characteristics
The current consumption is a combination of internal and external parameters and factors such as
operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program
location in memory and so on. The current consumption is measured as described in below condition
and table to inform test characterization result.
All GPIO pins are in push pull mode and output high.
The maximum values are obtained for VDD = 2.4V ~ 5.5 V and maximum ambient
temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise
specified.
VDD = AVDD
When the peripherals clock base is the system clock Fsys.
Program run “while (1);” in Flash.
Typ [6]
Symbol
Conditions
Fsys
Unit
TA = 25 °C
IDD_RUN
Normal run mode,
executed from Flash, all
peripherals disable
Max[6][7]
MS51 SERIES DATASHEET
24 MHz(HIRC)[1]
@5.5V
3.6
24 MHz(HIRC)[1]
@3.3V
3.2
24 MHz(HIRC)[1]
@2.4V
2.9
16 MHz (HIRC) [1]
@5.5V
3.3
16 MHz (HIRC) [1]
@3.3V
3.1
16 MHz (HIRC) [1]
@2.4V
2.8
10 kHz (LIRC)[2]
0.30
TA = -40 °C TA = 25 °C
4.2
4.6
TA = 105 °C
4.8
mA
3.4
3.9
4.6
0.32
0.46
2.33
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-1 Current consumption in Normal Run mode
Nov. 28, 2019
Page 52 of 80
Rev 1.00
MS51
Typ [3]
Symbol
Conditions
Max[3][4]
Fsys
Unit
TA = 25 °C
24 MHz(HIRC)[1]
@5.5V
24 MHz(HIRC)[1]
@3.3V
24 MHz(HIRC)[1]
@2.4V
IDD_IDLE
Idle mode, executed from
Flash, all peripherals
disable
16 MHz (HIRC)[1]
@5.5V
16 MHz (HIRC)[1]
@3.3V
16 MHz (HIRC)[1]
@2.4V
10 kHz (LIRC)[2]
TA = 25 °C TA = 85 °C
TA = 105 °C
2.8
2.4
2.9
3.2
3.8
2.2
mA
2.2
1.9
2.5
2.6
3.2
0.5
0.9
2.3
1.8
0.3
Notes:
1. This value base on HIRC enable, LIRC enable
2. This value base on HIRC disable, LIRC enable
3. LVR17 enabled, POR enable and BOD enable.
4. Based on characterization, not tested in production unless otherwise specified.
Table 8.2-2 Current consumption in Idle mode
Typ[1]
Symbol
Max[2]
Test Conditions
Unit
MS51 SERIES DATASHEET
TA = 25 °C
Power down mode, all peripherals disable@5.5V
6.5
Power down mode, all peripherals disable@3.3V
6
Power down mode, all peripherals disable@2.4V
5.8
TA = -40 °C
TA = 25 °C
TA = 105 °C
6.2
9
55
IDD_PD
µA
Power down mode, LVR enable all other peripherals
disable
7.5
6.7
10
57
Power down mode, LVR enable BOD enable all
other peripherals disable
180
165
197
292
[3]
Notes:
1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 disabled, POR disabled and BOD disabled.
2. Based on characterization, not tested in production unless otherwise specified.
3. Based on characterization, tested in production.
Table 8.2-3 Chip Current Consumption in Power down mode
Nov. 28, 2019
Page 53 of 80
Rev 1.00
MS51
8.2.2
Wakeup Time from Low-Power Modes
Symbol
tWU_IDLE[1]
tWU_NPD[2][3]
Parameter
Typ
Max
Unit
5
6
cycles
-
30
µs
30
µs
Wakeup from IDLE mode
Fsys = HIRC @16MHz
Wakeup from Power down mode
Fsys = HIRC @ 24MHz
Notes:
1. Measured on a wakeup phase with a 16 MHz HIRC oscillator.
2. Based on test during characterization, not tested in production.
3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first.
Table 8.2-4 Low-power mode wakeup timings
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 54 of 80
Rev 1.00
MS51
8.2.3
8.2.3.1
I/O DC Characteristics
PIN Input Characteristics
Symbol
Parameter
VIL
Input low voltage
VIL1
Input low voltage
(I/O with TTL input)
VIH
Input high voltage
Min
Typ
Max
Unit
0
-
0.3*VDD
V
VSS-0.3
-
0.2VDD-0.1
V
0.2VDD+0.9
-
VDD+0.3
V
0.7*VDD
-
VDD
V
-
0.2*VDD
-
V
Test Conditions
Input high voltage
VIH1
VHY[1]
(I/O with Schmitt trigger input and Xin)
Hysteresis voltage of schmitt input
-1
ILK[2]
1
A
Input leakage current
-1
1
VSS < VIN < VDD,
Open-drain or input only mode
VDD < VIN < 5.5 V,
Open-drain or input only mode
Notes:
1. Guaranteed by characterization result, not tested in production.
2. Leakage could be higher than the maximum value, if abnormal injection happens.
3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than
the maximum value, if positive current is injected on adjacent pins
Table 8.2-5 I/O input characteristics
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 55 of 80
Rev 1.00
MS51
8.2.3.2
I/O Output Characteristics
Symbol
Parameter
Min
Source current for quasibidirectional mode and high
level
Typ
Max
Unit
-7.4
-
-7.5
µA
-7.3
-
-7.5
µA
-7.3
-
-7.5
µA
-57.2
-
-58.3
µA
-9
-
-9.6
mA
-6
-
-6.6
mA
-4.2
-
-4.9
mA
-18
-
-20
mA
18
-
20
mA
16
-
18
mA
9.7
-
11
mA
-
5
-
pF
ISR[1] [2]
Source current for push-pull
mode and high level
ISK[1] [2]
MS51 SERIES DATASHEET
CIO
[1]
Sink current for push-pull
mode and low level
I/O pin capacitance
Test Conditions
VDD = 5.5 V
VIN =(VDD-0.4) V
VDD = 3.3 V
VIN =(VDD-0.4) V
VDD = 2.4 V
VIN =(VDD-0.4) V
VDD = 5.5 V
VIN = 2.4 V
VDD = 5.5 V
VIN =(VDD-0.4) V
VDD = 3.3 V
VIN =(VDD-0.4) V
VDD = 2.7 V
VIN =(VDD-0.4) V
VDD = 5.5 V
VIN = 2.4 V
VDD = 5.5 V
VIN = 0.4 V
VDD = 3.3 V
VIN = 0.4 V
VDD = 2.4 V
VIN = 0.4 V
Notes:
1. Guaranteed by characterization result, not tested in production.
2. The ISR and ISK must always respect the abslute maximum current and the sum of I/O, CPU and peripheral must not
exceed ΣIDD and ΣISS.
Table 8.2-6 I/O output characteristics
Nov. 28, 2019
Page 56 of 80
Rev 1.00
MS51
8.2.3.3
nRESET Input Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VILR
Negative going threshold, nRESET
-
-
0.3*VDD
V
VIHR
Positive going threshold, nRESET
0.7*VDD
-
-
V
45
-
60
RRST[1]
Internal nRESET pull up resistor
tFR[1]
Test Conditions
VDD = 5.5 V
KΩ
45
-
65
-
1.5
-
nRESET input response time
VDD = 2.4 V
Normal run and Idle mode
µs
10
-
25
Power down mode
Notes:
1. Guaranteed by characterization result, not tested in production.
2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable.
Table 8.2-7 nRESET Input Characteristics
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 57 of 80
Rev 1.00
MS51
8.3 AC Electrical Characteristics
8.3.1
Internal High Speed RC Oscillator (HIRC)
8.3.1.1 16MHz RC Oscillator (HIRC)
Symbol.
VDD
Parameter
Operating voltage
Oscillator frequnecy
Min
Typ
Max
Unit
2.4
-
5.5
V
-
16[1]
-
MHz
-1[3]
-
1[3]
%
-2[4]
-
2[4]
%
4[4]
%
FHRC
Frequency drift over temperarure and
volatge
-4[4]
IHRC[2]
Operating current
-
490
550
µA
TS[3]
Stable time
-
3
5
µs
Test Conditions
TA = 25 °C,
VDD = 3.3
TA = 25 °C,
VDD = 3.3V
TA = -20 C ~ +105 °C,
VDD = 2.4 ~ 5.5V
TA = -40 C ~ -20 °C,
VDD = 2.4 ~ 5.5V
TA = -40C ~ +105 °C,
VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
MS51 SERIES DATASHEET
Table 8.3-1 16 MHz Internal High Speed RC Oscillator(HIRC) characteristics
Nov. 28, 2019
Page 58 of 80
Rev 1.00
MS51
8.3.1.2 24MHz RC Oscillator (HIRC)
Symbol.
VDD
Parameter
Operating voltage
Oscillator frequnecy
Min
Typ
Max
Unit
2.4
-
5.5
V
-
24[1]
-
MHz
-1[3]
-
1[3]
%
-2[4]
-
2[4]
%
4[4]
%
Test Conditions
TA = 25 °C,
VDD = 3.3
TA = 25 °C,
VDD = 3.3V
FHRC
Frequency drift over temperarure and
volatge
-4[4]
IHRC[2]
Operating current
-
490
550
µA
TS[3]
Stable time
-
3
5
µs
TA = -20C ~ +85 °C,
VDD = 2.4 ~ 5.5V
TA = -40C ~ +105 °C,
VDD = 2.4 ~ 5.5V
TA = -40C ~ +105 °C,
VDD = 2.4 ~ 5.5V
Notes:
1. Default setting value for the product
2. Based on reload value.
3. Based on characterization, tested in production.
4. Guaranteed by characterization result, not tested in production.
5. Guaranteed by design.
Table 8.3-2 24MHz Internal High Speed RC Oscillator(HIRC) characteristics
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 59 of 80
Rev 1.00
MS51
8.3.2
External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics
The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator
oscillator. All the information given in this secion are based on characterization results obtained with
typical external components. In the application, the external components have to be placed as close
as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order
to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer
for more details on the resonator characteristics (frequency, package, accuracy).
Min[1]
Typ
Max[1]
Unit
1.8
-
5.5
V
Internal feedback resister
-
500
-
kΩ
Oscillator frequency
4
-
24
MHz
-
80
180
4 MHz, Gain = L0
-
110
300
8 MHz, Gain = L1
-
180
500
-
230
650
16 Mhz, Gain = L3
-
360
975
24 MHz, Gain = L4
-
3500
3700
4 MHz, Gain = L0
-
950
1050
8 MHz, Gain = L1
-
700
850
-
450
550
16 Mhz, Gain = L3
-
400
570
24 MHz, Gain = L4
40
-
60
Symbol
VDD
Rf
fHXT
IHXT
TS
DuHXT
Parameter
Operating voltage
Current consumption
Stable time
Duty cycle
µA
µs
Test Conditions[2]
12 MHz, Gain = L2
12 MHz, Gain = L2
%
MS51 SERIES DATASHEET
Notes:
1. Guaranteed by characterization, not tested in production.
2. L0 ~ L4 defined by SFR XLTCON[6:4] HXSG
Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator
Nov. 28, 2019
Page 60 of 80
Rev 1.00
MS51
8.3.3
External 4~24 MHz High Speed Clock Input Signal Characteristics
For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive
external clock. The external clock signal has to respect the below Table. The characteristics result
from tests performed using a wavefrom generator.
Symbol
fHXT_ext
Parameter
External user clock source
frequency
Min [*1]
Typ
Max [*1]
Unit
4
-
24
MHz
Test Conditions
tCHCX
Clock high time
8
-
-
ns
tCLCX
Clock low time
8
-
-
ns
tCLCH
Clock rise time
-
-
10
ns
Low (10%) to high level (90%)
rise time
tCHCL
Clock fall time
-
-
10
ns
High (90%) to low level (10%)
fall time
40
-
60
%
DuE_HXT
Duty cycle
VIH
Input high voltage
0.7*VDD
-
VDD
V
VIL
Input low voltage
VSS
-
0.3*VDD
V
External
clock source
XT1_IN
tCLCL
MS51 SERIES DATASHEET
tCLCH
VIH
VIL
90%
tCLCX
10%
tCHCL
tCHCX
Notes:
1. Guaranteed by characterization, not tested in production.
Table 8.3-4 External 4~24 MHz High Speed Clock Input Signal
Nov. 28, 2019
Page 61 of 80
Rev 1.00
MS51
8.3.4
10 kHz Internal Low Speed RC Oscillator (LIRC)
Symbol
VDD
Parameter
Min
Typ
Max
Unit
2.4
-
5.5
V
-
10
-
kHz
-10[1]
-
10[1]
%
TA = 25 °C,
VDD = 5V
-35[2]
-
35[2]
%
TA=-40~105°C
Without software calibration
Operating current
-
0.85
1
µA
VDD = 3.3V
Stable time
-
500
-
μs
TA=-40~105°C
Operating voltage
Oscillator frequnecy
FLRC
ILRC[3]
TS
Frequency drift over temperarure
and volatge
Test Conditions
Notes:
1. Guaranteed by characterization, tested in production.
2. Guaranteed by characterization, not tested in production.
3. Guaranteed by design.
Table 8.3-5 10 kHz Internal Low Speed RC Oscillator(LIRC) characteristics
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 62 of 80
Rev 1.00
MS51
8.3.5
I/O AC Characteristics
Symbol
tf(IO)out
tf(IO)out
tr(IO)out
MS51 SERIES DATASHEET
tr(IO)out
fmax(IO)out[*3]
Parameter
Normal mode [4] output high (90%) to low level (10%)
falling time
High slew rate mode [5] output high (90%) to low level
(10%) falling time
Normal mode [4] output low (10%) to high level (90%)
rising time
High slew rate mode [5] output low (10%) to high level
(90%) rising time
Typ.
Max[*1].
4.6
5.1
CL = 30 pF, VDD >= 5.5 V
2.9
3.3
CL = 10 pF, VDD >= 5.5 V
6.6
8
Unit
Test Conditions[*2]
CL = 30 pF, VDD >= 3.3 V
ns
4.3
5
CL = 10 pF, VDD >= 3.3 V
8.5
12.5
CL = 30 pF, VDD >= 2.4 V
8.0
10.7
CL = 10 pF, VDD >= 2.4 V
4.0
4.3
CL = 30 pF, VDD >= 5.5 V
2.1
2.5
CL = 10 pF, VDD >= 5.5 V
4.9
5.8
CL = 30 pF, VDD >= 3.3 V
ns
3.0
3.7
CL = 10 pF, VDD >= 3.3 V
9.5
13.8
CL = 30 pF, VDD >= 2.4 V
5.4
7.4
CL = 10 pF, VDD >= 2.4 V
5.6
6.1
CL = 30 pF, VDD >= 5.5 V
3.4
3.7
CL = 10 pF, VDD >= 5.5 V
8.1
9.4
CL = 30 pF, VDD >= 3.3 V
ns
5.1
5.8
CL = 10 pF, VDD >= 3.3 V
15.1
20.3
CL = 30 pF, VDD >= 2.4 V
9.6
12.4
CL = 10 pF, VDD >= 2.4 V
4.8
5.2
CL = 30 pF, VDD >= 5.5 V
2.1
2.5
CL = 10 pF, VDD >= 5.5 V
6.4
7.4
CL = 30 pF, VDD >= 3.3 V
ns
3.0
3.7
CL = 10 pF, VDD >= 3.3 V
12.7
16.9
CL = 30 pF, VDD >= 2.4 V
5.4
7.4
CL = 10 pF, VDD >= 2.4 V
24
24
CL = 30 pF, VDD >= 2.4 V
I/O maximum frequency
MHz
CL = 10 pF, VDD >= 2.4 V
Notes:
1. Guaranteed by characterization result, not tested in production.
2. CL is a external capacitive load to simulate PCB and device loading.
3. The maximum frequency is defined by
.
4. PxSR.n bit value = 0, Normal output slew rate
5. PxSR.n bit value = 1, high speed output slew rate
Table 8.3-6 I/O AC characteristics
Nov. 28, 2019
Page 63 of 80
Rev 1.00
MS51
8.4 Analog Characteristics
8.4.1
Reset and Power Control Block Characteristics
The parameters in below table are derived from tests performed under ambient temperature.
Symbol
Parameter
Min
Typ
Max
Unit
20
µA
Test Conditions
IPOR[*1]
POR operating current
10
ILVR[*1]
LVR operating current
0.5
-
1
AVDD = 5.5V
IBOD[*1]
BOD operating current
-
0.5
2.9
AVDD = 5.5V
VPOR
POR reset voltage
1
1.15
1.3
VLVR
LVR reset voltage
1.7
2.0
2.4
-
VBOD
BOD brown-out detect voltage
4.25
4.4
4.55
BOV[1:0] = [0,0]
3.55
3.7
3.85
BOV[1:0] = [0,1]
2.60
2.7
2.80
BOV[1:0] = [1,0]
2.10
2.2
2.35
BOV[1:0] = [1,1]
V
AVDD = 5.5V
-
TLVR_SU[*1]
LVR startup time
60
-
80
TLVR_RE[1]
LVR respond time
0.4
-
4
180
-
350
Fsys = LIRC
µs
Fsys = HIRC@16MHz
TBOD_SU[1]
BOD startup time
180
-
320
Fsys = HIRC@16MHz
TBOD_RE[1]
BOD respond time
2.5
-
5
Fsys = HIRC@16MHz
Notes:
1. Guaranteed by characterization, not tested in production.
2. Design for specified applcaiton.
MS51 SERIES DATASHEET
Table 8.4-1 Reset and power control unit
VDD
RVDDR
RVDDF
VBOD
VLVR
VPOR
Time
Nov. 28, 2019
Page 64 of 80
Rev 1.00
MS51
BODFLT
(BODCON1.1)
0
BOD Operation Mode
System Clock
Source
Normal mode
(LPBOD[1:0] = [0,0])
Any clock source
Typ. 1μs
Low power mode 1
(LPBOD[1:0] = [0,1])
Any clock source
16 (1/FLIRC)
Low power mode 2
(LPBOD[1:0] = [1,0])
Any clock source
64 (1/FLIRC)
Low power mode 3
(LPBOD[1:0] = [1,1])
Any clock source
256 (1/ FLIRC)
1
Normal operation: 32 (1/FSYS)
Idle mode: 32 (1/FSYS)
Power-down mode: 2 (1/FLIRC)
HIRC/ECLK
Normal mode
(LPBOD[1:0] = [0,0])
Minimum Brown-out Detect Pulse Width
LIRC
2 (1/FLIRC)
Low power mode 1
(LPBOD[1:0] = [0,1])
Any clock source
18 (1/FLIRC)
Low power mode 2
(LPBOD[1:0] = [1,0])
Any clock source
66 (1/FLIRC)
Low power mode 3
(LPBOD[1:0] = [1,1])
Any clock source
258 (1/ FLIRC)
Table 8.4-2 Minimum Brown-out Detect Pulse Width
8.4.2
12-bit SAR ADC
Symbol
Min
Typ
Max
Unit
Temperature
-40
-
105
℃
AVDD
Analog operating voltage
2.7
-
5.5
V
AVDD = VDD
VREF
Reference voltage
2.7
-
AVDD
V
VREF = AVDD
0
-
VREF
V
TA
MS51 SERIES DATASHEET
VIN
Parameter
ADC channel input voltage
Test Conditions
AVDD = VDD = VREF = 5.5 V
IADC[*1]
Operating current (AVDD + VREF current)
-
-
418
µA
FADC = 500 kHz
TCONV = 17 * TADC
NR
FADC[1]
TSMP
TCONV
TEN
INL[*1]
[*1]
DNL
Resolution
ADC conversion rate
12
Bit
FADC = 1/TADC
-
-
500
kHz
0.375
-
2.12
μs
0.417
-
1.54
μs
-
-
1.625
μs
Enable to ready time
20
-
-
μs
Integral Non-Linearity Error
-3
-
+3
LSB
VREF = AVDD =VDD
Differential Non-Linearity Error
-2
-
+4
LSB
VREF = AVDD=VDD
Sampling Time [2]
Conversion time
Nov. 28, 2019
Page 65 of 80
TADC = TSMP +TCONV
Fsys = 16MHz;
Fsys = 24MHz;
For Min. ADCAQT = 1 [3]
Rev 1.00
MS51
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
EG[*1]
Gain error
-3.5
-
+0.4
LSB
VREF = AVDD=VDD
EO[*1]T
Offset error
-2
-
+2.8
LSB
VREF = AVDD=VDD
EA[*1]
Absolute Error
-7
+7
LSB
VREF = AVDD=VDD
Notes:
1. Guaranteed by characterization result, not tested in production.
2. ADC sampling time =.
4 * ADCAQT 6
, FADCAQT is defined in ADCDIV (ADCCON2[3:1]). As default FADCAQT = FSYS
FADCAQT
(ADCDIV=0),
3. Since the minima sampling time must over 370ns that means when FADCAQT = 24MHz, ADCAQT should be defined as
1 at least. This value is defined by software.
Table 8.4-3 ADC characteristics
EF (Full scale error) = EO + EG
Gain Error
EG
Offset Error
EO
4095
4094
4093
4092
Ideal transfer curve
7
MS51 SERIES DATASHEET
6
ADC
output
code
5
Actual transfer curve
4
3
2
DNL
1
1 LSB
Offset Error
EO
Analog input voltage
(LSB)
4095
Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer
curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and
gain error from the actual transfer curve.
Nov. 28, 2019
Page 66 of 80
Rev 1.00
MS51
8.5 Flash DC Electrical Characteristics
The devices are shipped to customers with the Flash memory erased.
Symbol
Parameter
Min
Typ
Max
Unit
1.62
1.8
1.98
V
Test Condition
VFLA[1]
Supply voltage
TERASE
Page erase time
-
5
-
ms
TPROG
Program time
-
10
-
µs
IDD1
Read current
-
4
-
mA
IDD2
Program current
-
4
-
mA
IDD3
Erase current
-
12
-
mA
100,000
-
50
-
-
year
100 kcycle[3] TA = 55℃
25
-
-
year
100 kcycle[3] TA = 85℃
10
-
-
year
100 kcycle[3] TA = 105℃
NENDUR
TRET
Endurance
Data retention
cycles[2]
TA = 25℃
TJ = -40℃~125℃
Notes:
1. VFLA is source from chip internal LDO output voltage.
2. Number of program/erase cycles.
3. Guaranteed by design.
Table 8.5-1 Flash memory characteristics
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 67 of 80
Rev 1.00
MS51
8.6 Absolute Maximum Ratings
Volrage Stesses above the absolute maximum ratings may cause permanent damage to the device.
The limiting values are stress ratings only and cannot be used to functional operation of the device.
Exposure to the absolute maximum ratings may affect device reliability and proper operation is not
guaranteed.
8.6.1
Voltage Characteristics
Symbol
VDD-VSS[*1]
ΔVDD
|VDD –AVDD|
ΔVSS
|VSS - AVSS|
VIN
Description
Min
Max
Unit
-0.3
6.5
V
Variations between different power pins
-
50
mV
Allowed voltage difference for VDD and AVDD
-
50
mV
Variations between different ground pins
-
50
mV
Allowed voltage difference for VSS and AVSS
-
50
mV
VSS-0.3
5.5
V
DC power supply
Input voltage on I/O
Notes:
1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply.
Table 8.6-1 Voltage characteristics
8.6.2
Current Characteristics
Symbol
ΣIDD[*1]
ΣISS
Description
MS51 SERIES DATASHEET
Min
Max
Maximum current into VDD
-
200
Maximum current out of VSS
-
200
Maximum current sunk by a I/O Pin
-
22
Maximum current sourced by a I/O Pin
-
10
-
100
-
100
Unit
mA
IIO
Maximum current sunk by total I/O Pins[*2]
Maximum current sourced by total I/O Pins
[*2]
Note:
1.
Maximum allowable current is a function of device maximum power dissipation.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not
be sunk/sourced between two consecutive power supply pins.
3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN 30 sec.
Time with 5°C of actual peak temperature
Peak temperature range
260°C
Ramp-down rate
6°C/sec ax.
Time 25°C to peak temperature
8 min. max
Note:
1. Determined according to J-STD-020C
Table 8.6-6 Soldering Profile
Nov. 28, 2019
Page 72 of 80
Rev 1.00
MS51
9
9.1
PACKAGE DIMENSIONS
QFN 33-pin (4.0 x 4.0 x 0.8 mm)
MS51 SERIES DATASHEET
Figure 9.1-1 QFN-33 Package Dimension
Nov. 28, 2019
Page 73 of 80
Rev 1.00
MS51
9.2
LQFP 32-pin (7.0 x 7.0 x 1.4 mm)
MS51 SERIES DATASHEET
Figure 9.2-1 LQFP-32 Package Dimension
Nov. 28, 2019
Page 74 of 80
Rev 1.00
MS51
9.3
TSSOP 28-pin (4.4 x 9.7 x 1.0 mm)
MS51 SERIES DATASHEET
Figure 9.3-1 TSSOP-28 Package Dimension
Nov. 28, 2019
Page 75 of 80
Rev 1.00
MS51
9.4
TSSOP 20-pin (4.4 x 6.5 x 0.9 mm)
MS51 SERIES DATASHEET
Figure 9.4-1 TSSOP-20 Package Dimension
Nov. 28, 2019
Page 76 of 80
Rev 1.00
MS51
9.5
QFN 20-pin (3.0 x 3.0 x 0.6mm)
MS51 SERIES DATASHEET
Figure 9.5-1 QFN-20 Package Dimension for MS51XC0BE
Nov. 28, 2019
Page 77 of 80
Rev 1.00
MS51
10 ABBREVIATIONS
10.1
Abbreviations List
MS51 SERIES DATASHEET
Acronym
Description
ADC
Analog-to-Digital Converter
BOD
Brown-out Detection
GPIO
General-Purpose Input/Output
Fsys
Frequency of system clock
HIRC
12 MHz Internal High Speed RC Oscillator
IAP
In Application Programming
ICP
In Circuit Programming
ISP
In System Programming
LDO
Low Dropout Regulator
LIRC
10 kHz internal low speed RC oscillator (LIRC)
LVR
Low Voltage $eset
PDMA
Peripheral Direct Memory Access
POR
Power On Reset
PWM
Pulse Width Modulation
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver/Transmitter
UCID
Unique Customer ID
WKT
Wakeup Timer
WDT
Watchdog Timer
Table 10.1-1 List of Abbreviations
Nov. 28, 2019
Page 78 of 80
Rev 1.00
MS51
11 REVISION HISTORY
Date
Revision
Description
2019.11.28
1.00
Initial release
MS51 SERIES DATASHEET
Nov. 28, 2019
Page 79 of 80
Rev 1.00
MS51
MS51 SERIES DATASHEET
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
Nov. 28, 2019
Page 80 of 80
Rev 1.00
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