博雅科技
闪存非易失性存储器系列
BY25Q256FS
256M BIT（32M Byte）串行接口闪存
产品特性
● 串行外围接口
- 标准串行接口：SCLK, /CS, SI, SO, /WP, /HOLD
- 双线串行接口：SCLK, /CS, IO0, IO1, /WP, /HOLD
- 四线串行接口：SCLK, /CS, IO0, IO1, IO2, IO3
- 纯四线模式（QPI）：SCLK, /CS, IO0, IO1, IO2, IO3
- 支持双倍传输速率（DTR）
- 支持 3 字节地址模式和 4 字节地址模式
● 数据读取
- 单线普通读（串行）：支持最大 55 兆赫兹时钟频率
- 快速读（串行）：支持最大 100 兆赫兹时钟频率（负载电容 30pF 情况下）
- 双线读数据传输速率高达 200 兆比特每秒
- 四线读数据传输速率高达 400 兆比特每秒
- 双倍传输速率下四线读数据传输速率高达 400 兆比特每秒
- 支持 XIP（本地执行）操作：连续读模式支持 8/16/32/64 字节回绕读取
● 数据编程
- 串行输入页编程，一次编程支持 1 到 256 字节
- 支持编程挂起和恢复
● 数据擦除
- 区块擦除（64 或 32 千字节）
- 扇区擦除（4 千字节）
- 整芯片擦除
- 支持擦除挂起和恢复
● 编程和擦除速度
- 页编程时间：典型值 0.6 毫秒
- 扇区擦除时间：典型值 50 毫秒
- 区块擦除时间：典型值 0.15 秒（32 千字节）或 0.25 秒（64 千字节）
- 整芯片擦除时间：典型值 80 秒
● 灵活统一的存储架构
- 4 千字节扇区
- 32 或 64 千字节区块
● 低功耗
- 工作电流最大 25 毫安
- 睡眠模式电流最大 5 微安
● 软件和硬件写保护
- 3 个 512 字节的带一次编程（OTP）功能的安全寄存器
- 支持串行闪存功能可查询参数表 (SFDP) 寄存器
- 通过/WP 引脚开启或禁用数据保护
- 支持自顶向下数据保护，自底向上数据保护，互补数据保护
- 支持高级区块或扇区数据保护（固定保护或密码保护）
● 单一电源供电
- 工作电压范围：2.7~3.6 伏特
● 工作温度范围
- 商业级(0℃ to +70℃)
- 工业级(-40℃ to +85℃)
● 擦写耐久度和数据保存年限
- 任意扇区编程-擦写循环次数典型值 10 万次
- 数据保存年限典型值 20 年
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Boya Microelectronics
Memory Series
BY25Q256FS
256M BIT SPI NOR FLASH
Features
● Serial Peripheral Interface
- Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD
- Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD
- Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
- QPI: SCLK, /CS, IO0, IO1, IO2, IO3
- DTR (Double Transfer Rate) Read
- 3 or 4-Byte Addressing Mode
● Read
- Normal Read (Serial): 55MHz clock rate
- Fast Read (Serial): 100MHz clock rate with 30PF load
- Dual I/O data transfer up to 200Mbits/S
- Quad I/O & QPI data transfer up to 400Mbits/S
- DTR Quad I/O Data transfer up to 400Mbits/s
- Allows XIP (execute in place) Operation: Continuous Read with 8/16/32/64-byte Wrap
● Program
- Serial-input Page Program up to 256bytes
- Program Suspend and Resume
● Erase
- Block Erase (64/32 KB)
- Sector Erase (4 KB)
- Chip Erase
- Erase Suspend and Resume
● Program/Erase Speed
- Page Program time: 0.6ms typical
- Sector Erase time: 50ms typical
- Block Erase time: 0.15/0.25s typical
- Chip Erase time: 80s typical
● Flexible Architecture
- Sector of 4K-byte
- Block of 32/64K-byte
● Low Power Consumption
- 25mA maximum active current
- 5uA maximum power down current
● Software/Hardware Write Protection
- 3x512-Byte Security Registers with OTP Locks
- Discoverable Parameters (SFDP) register
- Enable/Disable protection with /WP Pin
- Top/Bottom, Complement array protection
- Advanced Block/Sector Protection (Solid and Password Protect)
● Single Supply Voltage
- Full voltage range: 2.7~3.6V
● Temperature Range
- Commercial (0℃ to +70℃)
- Industrial (-40℃ to +85℃)
● Cycling Endurance/Data Retention
- Typical 100k Program-Erase cycles on any sector
- Typical 20-year data retention
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Contents
BY25Q256FS
Contents
1. Description...................................................................................... 6
2. Signal Description .......................................................................... 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
Input/Output Summary .......................................................................................8
Chip Select (/CS) ...............................................................................................8
Serial Clock (SCLK) ..........................................................................................9
Serial Input (SI)/IO0...........................................................................................9
Serial Data Output (SO)/IO1................................................................................9
Write Protect (/WP)/IO2 .....................................................................................9
HOLD (/HOLD) /RESET /IO3 ............................................................................9
RESET ........................................................................................................... 10
VCC Power Supply .......................................................................................... 10
VSS Ground .................................................................................................... 10
4.1
4.2
4.3
4.4
4.5
Standard SPI Instructions .................................................................................. 12
Dual SPI Instructions........................................................................................ 12
Quad SPI Instructions ....................................................................................... 12
QPI Instructions ............................................................................................... 13
3-Byte/4-Byte Address Modes ........................................................................... 13
5.1
Supply Voltage................................................................................................. 14
5.1.1
Operating Supply Voltage..................................................................... 14
5.1.2
Power-up Conditions............................................................................ 14
5.1.3
Device Reset........................................................................................ 14
5.1.4
Power-down ......................................................................................... 14
Active Power and Standby Power Modes ............................................................ 14
Hold Condition ................................................................................................ 15
Software Reset & Hardware RESET................................................................... 16
5.4.1
Software Reset .................................................................................... 16
5.4.2
Hardware Reset (/HOLD pin or /RESET pin) ........................................ 16
5.4.3
Hardware Reset (JEDEC Standard Hardware Reset) ........................... 16
Write Protect Features....................................................................................... 18
Status Register ................................................................................................. 19
5.6.1
Status Register Table ........................................................................... 19
5.6.2
The Status and Control Bits.................................................................. 20
Array Memory Protection.................................................................................. 23
5.7.1
Block Protect Table (WPS=0) ............................................................... 23
5.7.2
Advanced Block/Sector Protection (WPS=1) ........................................ 25
Extended Address Register ................................................................................ 31
3. Block/Sector Addresses ............................................................... 11
4. SPI/QPI Operation ....................................................................... 12
5. Operation Features ...................................................................... 14
5.2
5.3
5.4
5.5
5.6
5.7
5.8
6. Device Identification ..................................................................... 32
7. Instructions Description................................................................ 33
7.1
Configuration and Status Instructions ................................................................. 43
7.1.1
Write Enable (06H)............................................................................... 43
7.1.2
Write Enable for Volatile Status Register (50H) .................................... 44
7.1.3
Write Disable (04H) .............................................................................. 45
7.1.4
Read Status Register (05H or 35H or 15H) .......................................... 46
7.1.5
Write Status Register (01H or 31H or 11H) ........................................... 47
7.1.6
Read Extended Address Register (C8H) .............................................. 48
7.1.7
Write Extended Address Register (C5H)............................................... 50
7.1.8
Enter 4-Byte Address Mode (B7H) ....................................................... 51
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Contents
7.2
7.3
7.4
7.5
BY25Q256FS
7.1.9
Exit 4-Byte Address Mode (E9H) .......................................................... 52
7.1.10 Enter QPI Mode (38H).......................................................................... 53
7.1.11 Exit QPI Mode (FFH)............................................................................ 53
7.1.12 Enable Reset (66H) and Reset Device (99H) ....................................... 54
Read Instructions ............................................................................................. 55
7.2.1
Read Data (03H) .................................................................................. 55
7.2.2
Read Data with 4-Byte Address (13H) .................................................. 56
7.2.3
Fast Read (0BH) .................................................................................. 57
7.2.4
DTR Fast Read (0DH).......................................................................... 59
7.2.5
Fast Read with 4-Byte Address (0CH) .................................................. 61
7.2.6
Dual Output Fast Read (3BH) .............................................................. 62
7.2.7
Fast Read Dual Output with 4-Byte Address (3CH) .............................. 63
7.2.8
Quad Output Fast Read (6BH) ............................................................. 64
7.2.9
Fast Read Quad Output with 4-Byte Address (6CH) ............................. 66
7.2.10 Dual I/O Fast Read (BBH) .................................................................... 67
7.2.11 DTR Fast Read Dual I/O (BDH)............................................................ 70
7.2.12 Fast Read Dual I/O with 4-Byte Address (BCH) .................................... 73
7.2.13 Quad I/O Fast Read (EBH)................................................................... 75
7.2.14 DTR Fast Read Quad I/O(EDH) ........................................................... 80
7.2.15 Fast Read Quad I/O with 4-Byte Address (ECH) .................................. 84
7.2.16 DTR Quad I/O Fast Read with 4- Byte Address (EEH) ......................... 87
7.2.17 Quad I/O Word Fast Read (E7H).......................................................... 90
7.2.18 Set Burst with Wrap (77H) .................................................................... 92
7.2.19 Set Read Parameters (C0H) ................................................................ 93
7.2.20 Burst Read with Wrap (0CH) ................................................................ 94
7.2.21 DTR Burst Read with Wrap (0EH) ........................................................ 96
ID and Security Instructions .............................................................................. 97
7.3.1
Read Manufacture ID/ Device ID (90H) ................................................ 97
7.3.2
Dual I/O Read Manufacture ID/ Device ID (92H) .................................. 98
7.3.3
Quad I/O Read Manufacture ID/ Device ID (94H) ................................. 99
7.3.4
Read JEDEC ID (9FH) ....................................................................... 100
7.3.5
Read Unique ID Number (4Bh) .......................................................... 102
7.3.6
Deep Power-Down (B9H) ................................................................... 103
7.3.7
Release from Deep Power-Down/Read Device ID (ABH) ................... 105
7.3.8
Read Security Registers (48H) ........................................................... 107
7.3.9
Erase Security Registers (44H) .......................................................... 109
7.3.10 Program Security Registers (42H) .......................................................112
7.3.11 Read Serial Flash Discoverable Parameter (5AH) ...............................113
Program and Erase Instructions ........................................................................ 115
7.4.1
Page Program (02H) ...........................................................................115
7.4.2
Page Program with 4-Byte Address (12H) ...........................................117
7.4.3
Quad Page Program (32H)..................................................................118
7.4.4
Quad Input Page Program with 4-Byte Address (34H) .........................119
7.4.5
Sector Erase (20H) ............................................................................ 121
7.4.6
Sector Erase with 4-Byte Address (21H) ............................................ 123
7.4.7
32KB Block Erase (52H) .................................................................... 124
7.4.8
32KB Block Erase with 4-Byte Address (5CH) .................................... 126
7.4.9
64KB Block Erase (D8H) .................................................................... 127
7.4.10 64KB Block Erase with 4-Byte Address (DCH) ................................... 129
7.4.11 Chip Erase (60/C7H) .......................................................................... 130
7.4.12 Program/Erase Suspend (75H) .......................................................... 131
7.4.13 Program/Erase Resume (7AH)........................................................... 135
Advanced Block/Sector Protection Instructions .................................................. 136
7.5.1
Read Lock Register (2DH) ................................................................. 136
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Contents
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10
7.5.11
7.5.12
7.5.13
7.5.14
7.5.15
7.5.16
7.5.17
7.5.18
BY25Q256FS
Write Lock Register (2CH).................................................................. 136
SPB Lock Bit Clear (A6H) .................................................................. 137
Read SPB Lock Register (A7H).......................................................... 138
Read SPB Status (E2H) ..................................................................... 139
SPB Program (E3H) ........................................................................... 141
SPB Erase (E4H) ............................................................................... 143
Read DPB Status (3DH)..................................................................... 143
Dynamic Protection Block/Sector Lock (36H) ..................................... 145
Dynamic Protection Block/Sector Unlock (39H) .................................. 146
Read Unprotect Solid Protect Bit (AAH) ............................................. 148
Unprotect Solid Protect Bit Set (A8H) ................................................. 149
Unprotect Solid Protect Bit Clear (A9H) .............................................. 150
Global Block/Sector Lock (7Eh).......................................................... 151
Global Block/Sector Unlock (98h) ....................................................... 152
Read Password Register (27H) .......................................................... 153
Write Password Register (28H) .......................................................... 154
Password Unlock (29H)...................................................................... 155
8. Electrical Characteristics............................................................ 157
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Absolute Maximum Ratings ............................................................................ 157
Operating Ranges ........................................................................................... 157
Latch Up Characteristics ................................................................................. 158
Power-up Timing ........................................................................................... 158
DC Electrical Characteristics ........................................................................... 159
AC Measurement Conditions ........................................................................... 160
AC Electrical Characteristics ........................................................................... 160
9.1
9.2
9.3
9.4
Package 8-Pin SOP 208-mil............................................................................. 164
Package SOP16-300mil .................................................................................. 165
Package 8-Pad WSON (5x6mm) ...................................................................... 166
Package 8-Pad WSON (6x8mm) ...................................................................... 167
10.1
10.2
Valid part Numbers and Top Side Marking ........................................................ 169
Minimum Packing Quantity (MPQ) .................................................................. 170
9. Package Information .................................................................. 164
10. Order Information ....................................................................... 168
11. Document Change History......................................................... 171
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Description
BY25Q256FS
1. Description
The BY25Q256FS is 256M-bit Serial Peripheral Interface(SPI) Flash memory, supports the
Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (/WP), and I/O3
(/HOLD), Reset; and supports the QPI: Serial Clock, Chip Select, I/O0, I/O1, I/O2, and I/O3, Reset;
The Dual I/O data is transferred with speed of 216Mbits/s and the Quad I/O & Quad output & QPI
data is transferred with speed of 432Mbits/s. The Double Transfer Rate (DTR) Read is transferred
with speed of 432Mbits/s. The device uses a single low voltage power supply, ranging from 2.7
Volt to 3.6 Volt.
Additionally, the device supports JEDEC standard manufacturer and device ID and three
512-bytes Security Registers.
In order to meet environmental requirements, Boya Microelectronics offers 8-pin SOP 208mil,
8-pad WSON 5x6-mm, 8-pad WSON 6x8-mm,16-pin SOP 300mil, and other special order
packages, please contacts Boya Microelectronics for ordering information.
Figure 1. Logic diagram
VCC
SCLK
SO
SI
/CS
BY25QXX
/WP
/HOLD
VSS
Figure 2. Pin Configuration SOP 208 mil
Top View
December 2020
/CS
1
(IO1)SO
2
8
SOP8 208mil
VCC
7
/HOLD(IO3)
(IO2)/WP
3
6
SCLK
VSS
4
5
SI(IO0)
Rev 1.9
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Description
BY25Q256FS
Figure 3. Pin Configuration WSON 5x6-mm and WSON 6*8-mm
/CS
1
8
VCC
2
7
Top View
/HOLD(IO3)
(IO2)/WP
3
6
SCLK
VSS
4
5
SI(IO0)
(IO1)SO
Figure 4. Pin Configuration SOP16 300 mil
Top View
/HOLD(IO3)
December 2020
16
SCLK
VCC
1
2
15
SI(IO0)
/RESET
3
14
NC
NC
4
13
NC
NC
5
12
NC
SOP16 300mil
NC
6
11
NC
/CS
7
10
VSS
/SO(IO1)
8
9
/WP(IO2)
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BY25Q256FS
Signal Description
2. Signal Description
During all operations, VCC must be held stable and within the specified valid range: VCC (min) to
VCC (max).
All of the input and output signals must be held High or Low (according to voltages of VIH, VOH,
VIL or VOL, see DC Electrical Characteristics). These signals are described next.
2.1
Input/Output Summary
Table 1. Signal Names
Pin Name
I/O
/CS
I
SO (IO1)
I/O
/WP (IO2)
I/O
VSS
SI (IO0)
I/O
SCLK
I
/HOLD/RESET (IO3) (1)
I/O
/RESET (1)
VCC
I
Description
Chip Select
Serial Output for single bit data Instructions. IO1 for Dual or
Quad Instructions
Write Protect in single bit or Dual data Instructions. IO2 in
Quad mode. The signal has an internal pull-up resistor and
may be left unconnected in the host system if not used for
Quad Instructions
Ground
Serial Input for single bit data Instructions. IO0 for Dual or
Quad Instructions
Serial Clock
Hold (pause) serial transfer in single bit or Dual data
Instructions when QE=0, HOLD/RST=0. IO3 in
Quad-I/O/QPI mode. Also can be configured either as a
/RESET pin when QE=0, HOLD/RST=1. The signal has an
internal pull-up resistor and may be left unconnected in the
host system if not used for Quad Instructions
Reset input
Core and I/O Power Supply
Notes:
1. Two reset functions exist in 16-pin SOP 300mil packages at the same time
2.2
Chip Select (/CS)
The chip select signal indicates when an instruction for the device is in process and the other
signals are relevant for the memory device. When the /CS signal is at the logic high state, the
device is not selected and all input signals are ignored and all output signals are high impedance.
Unless an internal Program, Erase or Write Status Registers embedded ope ration is in progress,
the device will be in the Standby Power mode. Driving the /CS input to logic low state enables the
device, placing it in the Active Power mode. After Power Up, a falling edge on /CS is required prior
to the start of any instruction.
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BY25Q256FS
Signal Description
2.3
Serial Clock (SCLK)
This input signal provides the synchronization reference for the SPI interface. Instructions,
addresses, or data input are latched on the rising edge of the SCLK signal. Data output changes
after the falling edge of SCLK.
2.4
Serial Input (SI)/IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses,
and data to be programmed. Values are latched on the rising edge of serial SCLK clock signal.
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCLK clock signal)
as well as shifting out data (on the falling edge of SCLK).
2.5
Serial Data Output (SO)/IO1
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of the serial SCLK clock signal.
SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions,
addresses, and data to be programmed (values latched on rising edge of serial SCLK clock signal)
as well as shifting out data (on the falling edge of SCLK).
2.6
Write Protect (/WP)/IO2
When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1 and SRP0) of the
Status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to
the Status Registers. This prevents any alteration of the Status Registers. As a consequence, all
the data bytes in the memory area that are protected by the Block Protect, BP4, BP3 bits in the
status registers, are also hardware protected against data modification while /WP remains Low.
The /WP function is not available when the Quad mode is enabled (QE) in Status Registe r 2
(SR2[1]=1).
The /WP function is replaced by IO2 for input and output during Quad mode for receiving
addresses, and data to be programmed (values are latched on rising edge of the SCLK signal) as
well as shifting out data (on the falling edge of SCLK). /WP has an internal pull-up resistance;
when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for
Quad mode.
2.7
HOLD (/HOLD) /RESET /IO3
The /HOLD function is only available when QE=0, which can be configured either as a /HOLD pin
or as a /RESET pin depending on Status Register setting. If QE=1, the /HOLD function is disabled,
the pin acts as dedicated data I/O pin, and the /HOLD or /RESET function is not available.
When QE=0 and HOLD/RES= 0, the /HOLD signal goes low to stop any serial communications
with the device, but doesn’t stop the operation of write status register, programming, or erasing in
progress.
The operation of HOLD, need /CS keep low, and starts on falling edge of the /HOLD signal, with
SCLK signal being low (if SCLK is not being low, HOLD operation will not start until SCLK being
low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is
not being low, HOLD operation will not end until SCLK being low).
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BY25Q256FS
Signal Description
2.8
RESET
The /RESET pin in 16-pin SOP 300mil packages allows the device to be reset by the controller.
2.9
VCC Power Supply
VCC is the supply voltage. It is the single voltage used for all device functions including read,
program, and erase.
2.10 VSS Ground
VSS is the reference for the VCC supply voltage.
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Block/Sector Addresses
BY25Q256FS
3. Block/Sector Addresses
Table 2．Block/Sector Addresses of BY25Q256FS
Memory
Density
Big Block
(4M bit)
Block
(64k byte)
Block
(32k byte)
Half block
0
Block 0
Half block
1
Big Block
0
：
：
Half block
14
Block 7
Half block
15
256Mbi t
：
：
：
Half block
1008
Block 504
Half block
1009
Big Block
63
：
：
Half block
1022
Block 511
Half block
1023
Sector 0
Sector
Size
(KB)
4
0000000h-0000FFFh
：
Sector 7
：
4
：
0007000h-0007FFFh
Sector 8
：
4
4
0008000h-0008FFFh
：
Sector 15
：
4
：
000F000h-000FFFFh
：
Sector 112
4
0070000h-0070FFFh
：
Sector 119
：
4
：
0077000h-0077FFFh
Sector 120
：
4
：
0078000h-0078FFFh
：
Sector 127
：
4
：
007F000h-007FFFFh
：
Sector 8064
：
4
：
1F80000h-1F80FFFh
：
Sector 8071
Sector 8072
4
4
1F87000h-1F87FFFh
1F88000h-1F88FFFh
：
Sector 8079
：
4
：
1F8F000h-1F8FFFFh
：
Sector 8176
：
4
：
1FF0000h-1FF0FFFh
：
：
：
Sector 8183
Sector 8184
4
4
1FF7000h-1FF7FFFh
1FF8000h-1FF8FFFh
：
Sector 8191
：
4
：
1FFF000h-1FFFFFFh
Sector No.
Address range
Notes:
1. Big Block = Uniform Big Block, and the size is 4M bits.
2. Block = Uniform Block, and the size is 64K bytes.
3. Half block = Half Uniform Block, and the size is 32k bytes.
4. Sector = Uniform Sector, and the size is 4K bytes.
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SPI/QPI Operation
BY25Q256FS
4. SPI/QPI Operation
Figure 5. BY25Q256FS Serial Flash Memory Operation Diagram
Power Up
Device Initialization &
Status Register Refresh
(Non-Volatile Cells)
ADP = 0
ADP bit value
3-Byte Address
ADP = 1
4-Byte Address
Enable 4-Byte (B7h)
Hardware
Reset
Standard SPI
Dual SPI
Quad SPI
Enable QPI (38h)
Disable QPI (FFh)
3-Byte Address
Hardware
Reset
QPI
4.1
Disable 4-Byte (E9h)
Standard SPI
Dual SPI
Quad SPI
Enable QPI (38h)
Enable 4-Byte (B7h)
Disable 4-Byte (E9h)
SPI Reset
(66h+99h)
Disable QPI (FFh)
4-Byte Address
QPI
QPI Reset
(66h+99h)
Standard SPI Instructions
The BY25Q256FS features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK),
Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3
are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling
edge of SCLK.
4.2
Dual SPI Instructions
The BY25Q256FS supports Dual SPI operation when using the “3BH”, “3CH”, “BBH”, “BDH”,
“BCH”, and “92H” instructions. These instructions allow data to be transferred to or from the device
at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins
become bidirectional I/O pins: IO0 and IO1.
4.3
Quad SPI Instructions
The BY25Q256FS supports Quad SPI operation when using the “6BH”, “6CH”, “EBH”, “EDH”,
“ECH”, “E7H”, “94H”, “32H”, and “34H” instructions. These instructions allow data to be transferred
to or from the device at four times the rate of the standard SPI. When using the Quad SPI
instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD
December 2020
Rev 1.9
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SPI/QPI Operation
BY25Q256FS
pins become IO2 and IO3. Quad SPI instructions require the non -volatile Quad Enable bit (QE) in
Status Register to be set.
4.4
QPI Instructions
The BY25Q256FS supports Quad Peripheral Interface (QPI) operations only when the device is
switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction.
The typical SPI protocol requires that the byte-long instruction code being shifted into the device
only via SI pin in eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction
code, thus only two serial clocks are required. Standard/Dual/Quad SPI mode and QPI mode are
exclusive. Only one mode can be active at any given time. “Enter QPI (38h)” and “Exit QPI (FFh)”
instructions are used to switch between these two modes. Upon power -up or after a software reset
using “Reset (99h)” instruction or Hardware Reset, the default state of the device is
Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in
Status Register-2 is required to be set. When using QPI instructions, the SI and SO pins become
bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3 respectively. Se e
Figure 5 for the device operation modes.
4.5
3-Byte/4-Byte Address Modes
The BY25Q256FS provides two Address Modes that can be used to specify any byte of data in the
memory array. The 3-Byte Address Mode is backward compatible to older generations of serial
flash memory that only support up to 128M-bit data. To address the 256M-bit or more data in
3-Byte Address Mode, Extended Address Register must be used in addition to the 3 -Byte
addresses.
4-Byte Address Mode is designed to support Serial Flash Memory devices from 256M-bit to
32G-bit. The extended Address Register is not necessary when the 4-Byte Address Mode is
enabled.
Upon power up, the BY25Q256FS can operate in either 3-Byte Address Mode or 4-Byte Address
Mode, depending on the Non-Volatile Status Register Bit ADP (S17) setting. If ADP=0, the device
will operate in 3-Byte Address Mode; if ADP=1, the device will operate in 4-Byte Address Mode.
The factory default value for ADP is 0.
To switch between the 3-Byte and 4-Byte Address Modes, “Enter 4-Byte Address Mode (B7h)” or
“Exit 4-Byte Address Mode (E9h)” instructions must be used. The current address mode is
indicated by the Status Register Bit ADS (S16).
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Rev 1.9
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Operation Features
BY25Q256FS
5. Operation Features
5.1
Supply Voltage
5.1.1 Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within
the specified [VCC(min), VCC(max)] range must be applied (see Electrical Characteristics). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10nF to 100nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and,
for a Write instruction, until the completion of the internal write cycle (tW).
5.1.2 Power-up Conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time,
the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore
recommended to connect the /CS line to VCC via a suitable pull-up resistor.
In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge
sensitive as well as level sensitive: after power-up, the device does not become selected until a
falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must
have been High, prior to going Low to start the first operation.
5.1.3 Device Reset
In order to prevent inadvertent Write operations during power -up (continuous rise of VCC), a
power on reset (POR) circuit is included. At Power-up, the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is lower
than the minimum VCC operating voltage defined in Power-up Timing).
When VCC is lower than VWI , the device is reset.
5.1.4 Power-down
At Power-down (continuous decrease in VCC), as soon as VCC drops from the normal operating
voltage to below the power on reset threshold voltage(VWI ), the device stops responding to any
instruction sent to it. During Power-down, the device must be deselected (Chip Select (/CS) should
be allowed to follow the voltage applied on VCC) and in Standby Power mode (that is there should
be no internal Write cycle in progress).
5.2
Active Power and Standby Power Modes
When Chip Select (/CS) is Low, the device is selected, and in the Active Power mode. The device
consumes ICC.
When Chip Select (/CS) is High, the device is deselected. If a Write cycle is not currently in
progress, the device then goes in to the Standby Power mode, and the device consumption drops
to ICC1.
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Rev 1.9
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Operation Features
5.3
BY25Q256FS
Hold Condition
When QE=0, HOLD/RST=0, the Hold (/HOLD) signal is used to pause any serial communications
with the device without resetting the clocking sequence. During the Hold condition, the Serial Data
Output (SO) is high impedance, and Serial Data Input (SI) and Serial Clock (SCLK) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (/CS) Low. Normally,
the device is kept selected, for the whole duration of the Hold condition. Deselecting the device
while it is in the Hold condition, has the effect of resetting the state of the device, and this
mechanism can be used if it is required to reset any processes that had been in progress.
The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial
Clock (SCLK) already being Low (as shown in Figure 6).The Hold condition ends when the Hold
(HOLD) signal is driven High at the same time as Serial Clock (C) already being Low. Figure 6
also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock
(SCLK) being Low.
Figure 6．Hold condition activation
/CS
SCLK
/HOLD
HOLD
HOLD
December 2020
Rev 1.9
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Operation Features
5.4
BY25Q256FS
Software Reset & Hardware RESET
5.4.1 Software Reset
The BY25Q256FS can be reset to the initial power-on state by a software reset sequence, either in
SPI mode or QPI mode. This sequence must include two consecutive instructions: Enable Reset
(66h) & Reset (99h). If the instruction sequence is successfully accepted, the device will take
approximately 300uS (tRST) to reset. No instruction will be accepted during the reset period.
5.4.2 Hardware Reset (/HOLD pin or /RESET pin)
The BY25Q256FS can also be configured to utilize hardware /RESET pin. The HOLD/RST bit in
the Status Register-3 is the configuration bit for /HOLD pin function or /RESET pin function. When
HOLD/RST=0 (factory default), the pin acts as a /HOLD pin as described above; when
HOLD/RST=1, the pin acts as a /RESET pin. Drive the /RESET pin low for a minimum period of
~1us (tRESET (1)) will reset the device to its initial power-on state. Any on-going Program/Erase
operation will be interrupted and data corruption may happen. While /RESET is low, the device will
not accept any instruction input.
If QE bit is set to 1, the /HOLD or /RESET function will be disabled, the pin will become one of the
four data I/O pin.
For the 16-pin SOP 300mil package, BY25Q256FS provides a dedicated /RESET pin in addition to
the /HOLD/RST (IO3) pin. Drive the /RESET pin low for a minimum period of ~1us (tRESET (1)) will
reset the device to its initial power-on state. The HOLD/RST bit or QE bit in the Status Register will
not affect the function of this dedicated /RESET pin.
Hardware /RESET pin has the highest priority among all the input signals. Drive /RESET low for a
minimum period of ~1us (tRESET (1)) will interrupt any on-going external/internal operations,
regardless the status of other SPI signals (/CS, CLK, IOs, /WP and /HOLD).
Notes:
1.
2.
While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset
the device, a 1us minimum pulse is recommended to ensure reliable operation.
There is an internal pull-up resistor for the dedicated /RESET pin on the 16-pin SOP
300mil package. If the reset function is not used, this pin can be left floating in the
system.
5.4.3 Hardware Reset (JEDEC Standard Hardware Reset)
The BY25Q256FS supports JEDEC Standard Hardware Reset. The JEDEC Standard Hardware
Reset sequence can also be used to reset the device to its power on state without cycling power.
The reset sequence does not use the SCLK pin. The SCLK has to be low (mode 0) or high (mode
3) through the entire reset sequence. This prevents any confusion with a instruction, as no
instruction bits are transferred (clocked).
A reset is commanded when the data on the SI pin is 0101 on four consecutive positive edges of
the /CS pin with no edge on the SCLK pin throughout. The is a sequence where
1.
/CS is driven active low to select the device.
2.
Clock (SCLK) remains stable in either a high or low state.
3.
SI is driven low by the bus master, simultaneously with /CS going active low. No SPI bus
slave drives SI during /CS low before a transition of SCLK i.e.: slave streaming output active
is not allowed until after the first edge of SCLK.
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Rev 1.9
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Operation Features
4.
BY25Q256FS
/CS is driven inactive. The slave captures the state of SI on the rising edge of /CS.
The above steps are repeated 4 times, each time alternating the state of SI.
After the fourth /CS pulse, the slave triggers its internal reset. SI is low on the first /CS, high on the
second, low on the third, high on the fourth. This provides a value of 5H, unlike random noise. Any
activity on SCLK during this time will halt the sequence and a Reset will not be generated. Figure
below illustrates the timing for hardware Reset operation.
Figure 7. JEDEC Standard Hardware Reset
tCH
/CS
tCL
Mode 3
SCLK
Mode 0
SI
SO
High_Z
tRST
Internal Reset
Table 3. JEDEC Standard Hardware Reset Timing Parameters
Parameter
Min.
tCL
tCH
Setup Time
Hold Time
20
20
5
5
December 2020
Typ.
Max.
Unit.
ns
ns
ns
ns
Rev 1.9
17 / 171
Operation Features
5.5
1.
BY25Q256FS
Write Protect Features
Software Protection (Memory array):
- The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory array
that can be read but not change.
- Advanced Block/Sector Protection (Solid and Password Protect): The BY25Q256FS also
provides another Write Protect method using the Advanced Block/Sector Protection. Each
64KB block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector
within the top/bottom blocks (total of 32 sectors) are equipped with the Individual SPB and
DPB bit. When the SPB or DPB bit is 0, the corresponding sector or block can be erased or
programmed; when the SPB or DPB bit is set to 1, Erase or Program instructions issued to
the corresponding sector or block will be ignored.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be
used. When WPS=0 (factory default), the device will only utilize CMP, BP[4:0] bits to protect
specific areas of the array; when WPS=1, the device will utilize the Advanced Block/Sector
Protection for write protection.
2.
Hardware Protection (Status register): /WP going low to protected the writable bits of Status
Register.
3.
Deep Power-Down: In Deep Power-Down Mode, all instructions are ignored except the
Release from deep Power-Down Mode instruction.
4.
Device resets when VCC is below threshold: Upon power-up or at power-down, the
BY25Q256FS will maintain a reset condition while VCC is below the threshold value of VWI .
While reset, all operations are disabled and no instructions are recognized.
5.
Time delay write disable after Power-up: During power-up and after the VCC voltage exceeds
VCC (min), all program and erase related instructions are further disabled for a time delay of
tVSL. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase
and the Write Status Register instructions.
6.
Write Enable: The Write Enable instruction is set the Write Enable Latch bit. The WEL bit will
return to reset by following situation:
-Power –up
-Write Disable
-Write Status Register (Whether the SR is protected, WEL will return to reset)
-Write Extended Address Register (when in 3-Byte Address Mode)
-After some Advanced Block/Sector Protection instructions that need Write Enable
instruction (see Table 18) are executed correctly, WEL bit will return to reset (when
WPS=1)
-Page Program (Whether the program area is protected, WEL will return to reset)
-Sector Erase/Block Erase/Chip Erase (Whether the erase area is protected, WEL will
return to reset)
-Software Reset
-Hardware Reset
7.
One Time Program (OTP) write protection for array and Security Registers using Status
Register.
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Rev 1.9
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Operation Features
5.6
BY25Q256FS
Status Register
5.6.1 Status Register Table
See Table 4 for detail description of the Status Register bits.
Table 4. Status Register
SR3
Default
(1)
S23
HOLD/RST
0
S22
DRV1
0
S21
DRV0
0
S20
S19
Reserved Reserved
×
×
S18
WPS
0
OTP
S17
ADP
0
S16
ADS
0
Read only
S11
LB1
0
OTP
S10
SUS2
0
Read Only
S9
QE
0
S8
SRP1
0
S3
BP1
0
S2
BP0
0
SR2
Default
(1)
S15
SUS1
0
Read Only
S14
CMP
0
S13
LB3
0
OTP
S12
LB2
0
OTP
S7
SRP0
0
S6
BP4
0
S5
BP3
0
S4
BP2
0
SR1
Default
(1)
S1
S0
WEL
WIP
0
0
Read Only Read Only
Notes:
1. The default value is set by Manufacturer during wafer sort, Marked as Default in following
text
December 2020
Rev 1.9
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Operation Features
BY25Q256FS
5.6.2 The Status and Control Bits
5.6.2.1 WIP bit
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write
status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write
status register progress, when WIP bit sets 0, means the device is not in program/erase/write
status register progress.
5.6.2.2 WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set
to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is r eset
and no Write Status Register, Program or Erase, etc. instruction is accepted.
5.6.2.3 BP4, BP3, BP2, BP1, BP0 bits
The Block Protect (BP4, BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against Program and Erase instructions. These bits are written with
the Write Status Register instruction. When WPS=0, and the Block Protect (BP4, BP3, BP2, BP1,
BP0) bits are set to 1, the relevant memory area (as defined in Table 7-Table 8).becomes
protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect
(BP4, BP3, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mod e has
not been set. The Chip Erase instruction is executed, if the Block Protect (BP2, BP1, BP0) bits are
0 and CMP=0 or The Block Protect (BP2, BP1, BP0) bits are 1 and CMP=1.
5.6.2.4 SRP1, SRP0 bits
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status
register. The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable protection.
Table 5. Status Register protect table
SRP1
SRP0
/WP
Status Register
Software
Protected
Hardware
Protected
Hardware
Unprotected
0
0
X
0
1
0
0
1
1
1
0
X
Power Supply
Lock-Down(1)
1
1
X
One Time
Program(2)
Description
The Status Register can be written to after a Write
Enable instruction, WEL=1.(Factory Default)
/WP=0, the Status Register locked and cannot be
written.
/WP=1, the Status Register is unlocked and can be
written to after a Write Enable instruction, WEL=1.
Status Register is protected and cannot be written
to again until the next Power-Down, Power-Up
cycle.
Status Register is permanently protected and
cannot be written to.
Notes:
1. When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to
(0, 0) state.
2. The One time Program feature is available upon special order. Please contact Boya
Microelectronics for details.
December 2020
Rev 1.9
20 / 171
Operation Features
BY25Q256FS
5.6.2.5 QE bit
The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad
operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the
QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (Th e QE bit should never be set to 1
during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or
ground).
QE bit is required to be set to a 1 before issuing an “Enter QPI ( 38h)” to switch the device from
Standard/Dual/Quad SPI to QPI; otherwise the instruction will be ignored. When the device is in
QPI mode, QE bit will remain to be 1. A “Write Status Register” instruction in QPI mode cannot
change QE bit from “1” to “0”.
5.6.2.6 LB3/LB2/LB1 bits
The Security Register Lock (LB3/LB2/LB1) bits are non-volatile One Time Program (OTP) bits in
Status Register (S13–S11) that provide the write protect control and status to the Security
Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1
individually using the Write Register instruction. LB is One Time Programmable, once they are set
to 1, the Security Registers will become read-only permanently.
5.6.2.7 CMP bit
The Complement Protect (CMP) bit is a non-volatile Read/Write bit in the Status Register (S14). It
is used in conjunction the BP4-BP0 bits to provide more flexibility for the array protection. Please
see the Status registers Memory Protection table for details. The default setting is CMP=0.
5.6.2.8 SUS1/SUS2 bits
The Suspend Status (SUS1 and SUS2) bits are read only bits in the status register2 (S15 and S10)
that are set to 1 after executing a Program/Erase Suspend (75H) instruction (The Erase Suspend
will set SUS1 to 1, and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are
cleared to 0 by Program/Erase Resume (7AH) instruction as well as a power-down, power-up
cycle.
5.6.2.9 ADS bit
The Current Address Mode (ADS) bit is a read only bit in the Status Register3 that indicates which
address mode the device is currently operating in. When ADS=0, the device is in the 3 -Byte
Address Mode, when ADS=1, the device is in the 4-Byte Address Mode.
5.6.2.10
ADP bit
The Power-Up Address Mode (ADP) bit is a non-volatile bit that determines the initial address
mode when the device is powered on or reset. This bit is only used during the power on or device
reset initialization period, and it is only writable by the non-volatile Write Status sequence (06h +
11h). When ADP=0 (factory default), the device will power up into 3 -Byte Address Mode, the
Extended Address Register must be used to access memory regions beyond 128Mb. When
ADP=1, the device will power up into 4-Byte Address Mode directly.
December 2020
Rev 1.9
21 / 171
Operation Features
5.6.2.11
BY25Q256FS
HOLD/RST bit
The /HOLD or /RESET Pin Function (HOLD/RST) bit is used to determine whether /HOLD or
/RESET function should be implemented on the hardware pin. When HOLD/RST=0 (factory
default), the pin acts as /HOLD; when HOLD/RST=1, the pin acts as /RESET. Ho wever, /HOLD or
/RESET functions are only available when QE=0. If QE is set to 1, the /HOLD and /RESET
functions are disabled, the pin acts as a dedicated data I/O pin.
5.6.2.12
WPS bit
There are two write memory array protection methods provided on BY25Q256FS：Block Protection
(BP) mode or Advanced Block/Sector Protection mode. The protection modes are mutually
exclusive. The WPS bit selects which protection mode is enabled. Please note that the WPS bit is
an OTP bit. Once WPS is set to “1”, it cannot be programmed back to “0”.
If WPS=0 (factory default), the BP mode is enabled and Advanced Block/Sector Protection mode
is disabled. Please note that if WPS=0, all Advanced Block/Sector Protection instructions
(7.5.1-7.5.18) are not available.
If WPS=1, the Advanced Block/Sector Protection mode is enabled and BP mode is disabled.
Blocks or Sectors are individually protected by their own SPB or DPB. On power -up, all Blocks or
Sectors are write protected by the Dynamic Protection Bits (DPB) by default. The Advanced
Block/Sector Protection instructions (7.5.1-7.5.18) are activated. The CMP, BP[4:0] bits of the
Status Register are disabled and have no effect.
5.6.2.13
DRV1/DRV0 bits
The Output Driver Strength (DRV1&DRV0) bits are used to determine the output driver strength
for the Read instruction.
Table 6．The Output Driver Strength
DRV1,DRV0
00
01
10
11
December 2020
Driver Strength
100%(default)
75%
50%
25%
Rev 1.9
22 / 171
Operation Features
5.7
BY25Q256FS
Array Memory Protection
5.7.1 Block Protect Table (WPS=0)
Table 7．BY25Q256FS Block Memory Protection (WPS=0, CMP=0)
Status Register Content
BP4 BP3 BP2 BP1 BP0
Memory Content
Blocks
Addresses
Density
Portion
X
0
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
511
01FF0000h -01FFFFFFh
64KB
Upper 1/512
0
0
0
1
0
510 to 511
01FE0000h -01FFFFFFh
128KB
Upper 1/256
0
0
0
1
1
508 to 511
01FC0000h -01FFFFFFh
256KB
Upper 1/128
0
0
1
0
0
504 to 511
01F80000h - 01FFFFFFh
512KB
Upper 1/64
0
0
1
0
1
496 to 511
01F00000h - 01FFFFFFh
1MB
Upper 1/32
0
0
1
1
0
480 to 511
01E00000h -01FFFFFFh
2MB
Upper 1/16
0
0
1
1
1
448 to 511
01C00000h -01FFFFFFh
4MB
Upper 1/8
0
1
0
0
0
384 to 511
01800000h - 01FFFFFFh
8MB
Upper 1/4
0
1
0
0
1
256 to 511
01000000h - 01FFFFFFh
16MB
Upper 1/2
1
0
0
0
1
0
00000000h - 0000FFFFh
64KB
Lower 1/512
1
0
0
1
0
0 to 1
00000000h - 0001FFFFh
128KB
Lower 1/256
1
0
0
1
1
0 to 3
00000000h - 0003FFFFh
256KB
Lower 1/128
1
0
1
0
0
0 to 7
00000000h - 0007FFFFh
512KB
Lower 1/64
1
0
1
0
1
0 to 15
00000000h - 000FFFFFh
1MB
Lower 1/32
1
0
1
1
0
0 to 31
00000000h - 001FFFFFh
2MB
Lower 1/16
1
0
1
1
1
0 to 63
00000000h - 003FFFFFh
4MB
Lower 1/8
1
1
0
0
0
0 to 127
00000000h - 007FFFFFh
8MB
Lower 1/4
1
1
0
0
1
0 to 255
00000000h - 00FFFFFFh
16MB
Lower 1/2
X
1
1
0
X
0 to 511
00000000h - 01FFFFFFh
32MB
ALL
X
1
X
1
X
0 to 511
00000000h - 01FFFFFFh
32MB
ALL
December 2020
Rev 1.9
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Operation Features
BY25Q256FS
Table 8．BY25Q256FS Block Memory Protection (WPS=0, CMP=1)
Status Register Content
BP4 BP3 BP2 BP1 BP0
Memory Content
Blocks
Addresses
Density
X
0
0
0
0
ALL
00000000h - 01FFFFFFh
0
0
0
0
1
0 to 510
00000000h - 01FEFFFFh
32,704KB Lower 511/512
0
0
0
1
0
0 to 509
00000000h - 01FDFFFFh
32,640KB Lower 255/256
0
0
0
1
1
0 to 507
00000000h - 01FBFFFFh
32,512KB Lower 127/128
0
0
1
0
0
0 to 503
00000000h - 01F7FFFFh
32,256KB
Lower 63/64
0
0
1
0
1
0 to 495
00000000h - 01EFFFFFh
31MB
Lower 31/32
0
0
1
1
0
0 to 479
00000000h - 01DFFFFFh
30MB
Lower 15/16
0
0
1
1
1
0 to 447
00000000h - 01BFFFFFh
28MB
Lower 7/8
0
1
0
0
0
0 to 383
00000000h - 017FFFFFh
24MB
Lower 3/4
0
1
0
0
1
0 to 255
00000000h - 00FFFFFFh
16MB
Lower 1/2
1
1
0
0
0
0
0
1
1
0
1 to 511
2 to 511
00010000h - 01FFFFFFh
00020000h - 01FFFFFFh
32,704KB Upper 511/512
32,640KB Upper 255/256
1
0
0
1
1
4 to 511
00040000h - 01FFFFFFh
32,512KB Upper 127/128
1
0
1
0
0
8 to 511
00080000h - 01FFFFFFh
32,256KB
Upper 63/64
1
0
1
0
1
16 to 511
00100000h - 01FFFFFFh
31MB
Upper 31/32
1
0
1
1
0
32 to 511
00200000h - 01FFFFFFh
30MB
Upper 15/16
1
0
1
1
1
64 to 511
00400000h - 01FFFFFFh
28MB
Upper 7/8
1
1
0
0
0
128 to 511
00800000h - 01FFFFFFh
24MB
Upper 3/4
1
1
0
0
1
256 to 511
01000000h - 01FFFFFFh
16MB
Upper 1/2
X
1
1
0
X
NONE
NONE
NONE
NONE
X
1
X
1
X
NONE
NONE
NONE
NONE
December 2020
Rev 1.9
ALL
Portion
ALL
24 / 171
Operation Features
BY25Q256FS
5.7.2 Advanced Block/Sector Protection (WPS=1)
Advanced Block/Sector Protection can protect individual 4KB sectors in the bottom and top 64KB
of memory and protect individual 64KB blocks in the rest of memory.
There is one non-volatile Solid Protection Bit (SPB) and one volatile Dynamic Protection Bit (DPB)
assigned to each 4KB sector at the bottom and top 64KB of memory and to each 64KB block in
the rest of memory. A sector or block is write-protected from programming or erasing when its
associated SPB or DPB is set to “1”. The Unprotect Solid Protect Bit (USPB) can temporarily
override and disable the write-protection provided by the SPB bits.
There are two mutually exclusive implementations of Advanced Block/Sector Protection: Solid
Protection mode (factory default) and Password Protection mode. Solid Protection mode permits
the SPB bits to be modified after power-on or a reset. The Password Protection mode requires a
valid password before allowing the SPB bits to be modified.
Please note that if WPS=0, all Advanced Block/Sector Protection instructions (7.5.1-7.5.18) are
not available.
Figure 8．Solid Protection Mode and Password Protection Mode of Advanced Block/Sector
Protection
Power on
Bit 1=1; Bit 2=1
(factory default)
or Bit 1=0
Bit 2=0*
Lock Register?
Solid Protection
Mode
Password Protection
Mode
SPB Lock Bit default
is 1
SPB Lock Bit default
is 0
*The factory default password must be modified
before setting bit 2 of the Lock Register to 0.
Figure 9．Enter Password Protection Mode
Modify the factory default
password
Recommend verify the new
password
Set Lock Register Bit 2=0
Password Protection Mode
December 2020
Rev 1.9
25 / 171
Operation Features
BY25Q256FS
Figure 10．SPB, DPB and USPB protection for Block/Sector Array
SPBLK = 0
SPB Lock Bit
SPB Lock bit locked
ALL SPB can not be
changeable
SPBLK = 1
SPB Lock bit Unlocked
SPB is changeable
Dynamic Protect Bit
Register
(DPB)
DPB = 1
block/sector protect;
DPB = 0
block/sector unprotect
Solid Protection Bit
(SPB)
Temporary Unprotect
SPB bit (USPB)*
SPB = 1 Write Protect
SPB = 0 Write Unprotect
USPB = 0
SPB bits is disabled;
USPB = 1
SPB bits is effective
Block/Sector Array
DPB 0
Sector 0
...
...
DPB 15
DPB 16
Sector 15
Block 1
SPB 0
...
SPB 15
SPB 16
...
...
...
DPB 525
DPB 526
Block 510
Sector 8176
SPB 525
SPB 526
...
...
...
DPB 541
Sector 8191
SPB 541
December 2020
Rev 1.9
USPB
26 / 171
Operation Features
BY25Q256FS
5.7.2.1 Lock Register
The Lock Register is a 16-bit one-time programmable register. Lock Register bits [2:1] select
between Solid Protection mode and Password Protection mode. When both bits are “1” (factory
default), Solid Protection mode is enabled by default. The Lock Register is programmed using the
Write Lock Register instruction. Programming Lock Register bit 1 to “0” permanently selects Solid
Protection mode and permanently disables Password Protection mode. Conversely, programming
bit 2 to “0” permanently selects Password Protection mode and permanently disables Solid
Protection mode. Bits 1 and 2 cannot be programmed to “0” at the same time otherwise the device
will abort the operation. A Write Enable instruction must be executed to set the WEL bit before
sending the Write Lock Register instruction.
A password must be set prior to selecting Password Protection mode. The password can be set by
issuing the Write Password Register instruction.
Table 9．Lock Register
Bit 15-3
Bit 2
Bit 1
Bit0
Reserved
Password Protection Mode Lock Bit
0=Password Protection Mode
Enable
1= Password Protection Mode not
enable (Default =1)
OTP
Solid Protection Mode Lock Bit
0=Solid Protection Mode
Enable
1= Solid Protection Mode not
enable (Default =1)
OTP
Reserved
×
OTP
×
OTP
Notes:
1. Once bit 2 or bit 1 has been programmed to "0", the other bit can't be changed any more.
5.7.2.2 SPB Lock Bit
The SPB Lock Bit (SPBLK) is a volatile bit located in bit 0 of the SPB Lock Register. The SPBLK
bit controls whether the SPB bits can be modified or not. If SPBLK=1, the SPB bits are
unprotected and can be modified. If SPBLK=0, the SPB bits are protected (“locked”) and cannot
be modified. The power-on and reset status of the SPBLK bit is determined by Lock Register bits
[2:1]. Refer to SPB Lock Register for SPBLK bit default power-on status. The Read SPB Lock
Register instruction can be used to read the SPB Lock Register to determine the state of the
SPBLK bit.
In Solid Protection mode, the SPBLK bit defaults to “1” after power-on or reset. When SPBLK=1,
the SPB bits are unprotected (“unlocked”) and can be modified. The SPB Lock Bit Clear instruction
can be used to write the SPBLK bit to “0” and protect the SPB bits. A Write Enable instruction must
be executed to set the WEL bit before sending the SPB Lock Bit Clear instruction. Once the
SPBLK has been written to “0”, there is no instruction (except a software reset) to set the bit back
to “1”. A power-on cycle or reset is required to set the SPB lock bit back to “1”.
In Password Protection mode, the SPBLK bit defaults to “0” after power-on or reset. A valid
password must be provided to set the SPBLK bit to “1” to allow the SPBs to be modified. After the
SPBs have been set to the desired status, use the SPB Lock Bit Clear instruction to clear the
SPBLK bit back to “0” in order to prevent further modification.
Please note that the SPBLK bit will automatically become “0” when entering the Password
Protection mode from Solid Protection mode, even if the original value is “1”.
December 2020
Rev 1.9
27 / 171
Operation Features
BY25Q256FS
Table 10．SPB Lock Register
Bit
7-1
Description
Reserved
Bit Status
×
0
SPBLK (SPB Lock Bit)
0 = SPBs protected
1= SPBs unprotected
Default
0000000
Solid Protection Mode: 1
Password Protection
Mode: 0
Type
Volatile
Volatile
5.7.2.3 Solid Protection Bits
The Solid Protection Bits (SPBs) are non-volatile bits for enabling or disabling write-protection to
sectors and blocks. The SPB bits have the same endurance as the Flash memory. An SPB is
assigned to each 4KB sector in the bottom and top 64KB of memory and to each 64KB block in the
remaining memory. The factory default state of the SPB bits is “0”, which has the block/sector
write-protection disabled.
When an SPB is set to “1”, the associated sector or block is write-protected. Program and erase
operations on the sector or block will be inhibited. SPBs can be individually set to “1” by the SPB
Program instruction. However, the SPBs cannot be individually cleared to “0”. Issuing the SPB
Erase instruction clears all SPBs to “0”. A Write Enable instruction must be executed to set the
WEL bit before sending the SPB Program or SPB Erase instruction.
The SPBLK bit must be “1” before any SPB can be modified. In Solid Protection mode the SPBLK
bit defaults to “1” after power-on or reset. Under Password Protection mode, the SPBLK bit
defaults to “0” after power-on or reset, and a Password Unlock instruction with a correct password
is required to set the SPBLK bit to “1”.
The SPB Lock Bit Clear instruction clears the SPBLK bit to “0”, locking the SPB bits from further
modification.
The Read SPB Status instruction reads the status of the SPB of a sector or block. The Read SPB
Status instruction returns 00h if the SPB is “0”, indicating write-protection is disabled. The Read
SPB Status instruction returns FFh if the SPB is “1”, indicating write-protection is enabled.
In Solid Protection mode, the Unprotect Solid Protect Bit (USPB) can temporarily mask the SPB
bits and disable the write-protection provided by the SPB bits.
Note: If SPBLK=0, instructions to set or clear the SPB bits will be ignored.
Table 11．Solid Protection Bit
Description
Solid Protection Bit (SPB )
Bit Status
0 = Unprotect Sector / Block
1 = Protect Sector / Block
Default
Type
0
Non-volatile
5.7.2.4 Dynamic Protection Bits
The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enablin g or disabling
write-protection to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top
64KB of memory and to each 64KB block in the rest of the memory. The DBPs can enable
write-protection on a sector or block regardless of the state of the corresponding SPB. However,
the DPB bits can only unprotect sectors or blocks whose SPB bits are “0” (unprotected).
When a DPB is “1”, the associated sector or block will be write-protected, preventing any program
or erase operation on the sector or block. All DPBs default to “1” after power-on or reset. When a
DPB is cleared to “0”, the associated sector or block will be unprotected if the corresponding SPB
is also “0”.
December 2020
Rev 1.9
28 / 171
Operation Features
BY25Q256FS
DPB bits can be individually set to “1” or “0” by the Dynamic Protection Block/Sector Lock/
Dynamic Protection Block/Sector Unlock instruction. The DBP bits can also be globally cleared to
“0” with the Global Block/Sector Unlock instruction or globally set to “1” with the Global
Block/Sector Lock instruction. A Write Enable instruction must be executed to set the WEL bit
before sending the Dynamic Protection Block/Sector Lock, Dynamic Protection Block/Sector
Unlock, Global Block/Sector Lock, or Global Block/Sector Unlock instruction.
The Read DPB Status instruction reads the status of the DPB of a sector or block. The Read DPB
Status instruction returns 00h if the DPB is “0”, indicating write-protection is disabled. The Read
DPB Status instruction returns FFh if the DPB is “1”, indicating write-protection is enabled.
Table 12．Dynamic Protection Bit
Description
Dynamic Protection Bit (DPB)
Bit Status
0 = Unprotect Sector / Block
1 = Protect Sector / Block
Default
Type
1
Volatile
5.7.2.5 Unprotect Solid Protect Bit
The Unprotect Solid Protect Bit (USPB) is a volatile bit that defaults to “1” after power-on or reset.
When USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked and
their write-protected sectors and blocks are temporarily unprotected (as long as their
corresponding DPBs are “0”). The USPB provides a means to temporarily override the SPBs
without having to issue the SPB Erase and SPB Program instructions to clear and set the SPBs.
The USPB can be read as often as needed in Solid Protection mode or Password Protection mode
and can be set or cleared as often as needed in Solid Protection mode or after providing a valid
password in Password Protection mode.
Please refer to Table 13 for the sector state with the protection status of DPB/SPB/USPB bits
Table 13．Block/Sector Protection States Summary Table
DPB
0
0
0
0
1
1
1
1
December 2020
Protection Status
SPB
0
0
1
1
0
0
1
1
USPB
0
1
0
1
0
1
0
1
Rev 1.9
Block/Sector Protection State
Unprotected
Unprotected
Unprotected
Protected
Protected
Protected
Protected
Protected
29 / 171
Operation Features
BY25Q256FS
5.7.2.6 Password Protection Mode
Password Protection mode potentially provides a higher level of security than Solid Protection
mode. In Password Protection mode, the SPBLK bit defaults to “0” after a power -on cycle or reset.
When SPBLK=0, the SPBs are locked and cannot be modified. A 64-bit password must be
provided to unlock the SPBs.
The Password Unlock instruction with the correct password will set the SPBLK bit to “1” and
unlock the SPB bits. After the correct password is given, a wait of tPW1 (typical value is 2us) is
necessary for the SPB bits to unlock. The Status Register WIP bit will clear to “0” upon completion
of the Password Unlock instruction. Once unlocked, the SPB bits can be modified. A Write Enable
instruction must be executed to set the WEL bit before sending the Password Unlock instruction.
Several steps are required to place the device in Password Protection mode. Prior to entering the
Password Protection mode, it is necessary to set the 64-bit password and recommend verify it via
use Read Password Register instruction. The Write Password Register instruction writes the
password and the Read Password Register instruction reads back the password. Password
verification is permitted until the Password Protection Mode Lock Bit has been written to “0”.
Password Protection mode is activated by programming the Password Protection Mode Lock Bit
to “0”. This operation is not reversible. Once the bit is programmed, it cannot be erased. The
device remains permanently in Password Protection mode and the 64-bit password can neither be
retrieved nor reprogrammed.
The password is all “1’s” when shipped from the factory. The Write Password Register instruction
can only program password bits to “0”. The Write Password Register instruction cannot program
“0’s” back to “1’s”. All 64-bit password combinations are valid password options. A Write Enable
instruction must be executed to set the WEL bit before sending the Write Password Register
instruction.
The unlock operation will fail if the password provided by the Password Unlock instruction
does not match the stored password. This will insert a tPW2 (100us ± 20us) delay before
clearing the WIP bit to “0”.
The Password Unlock instruction is prohibited from being executed faster than once every
tPW2 (100us ± 20us). This restriction makes it impractical to attempt all combinations of a
64-bit password (such an effort would take ~58 million years). Monitor the WIP bit to
determine whether the device has completed the Password Unlock instruction.
When a valid password is provided, the Password Unlock instruction does not insert the tPW2
(100us ± 20us) delay before returning the WIP bit to zero. The SPBLK bit will set to “1”.
The factory default password must be modified before enter the Password Protection mode
(setting bit 2 of the Lock Register to 0). Otherwise, the chip will not be able to enter the
Password Protection mode, that is, cannot set bit 2 of the Lock Register to 0.
Table 14．Password Register
Bits
63 to 0
Field Name
PWD
December 2020
Function
Hidden
Passwor
d
Type
OTP
Default
State
Description
FFFFFFFFF
FFFFFFFh
Non-volatile OTP storage of 64
bit password. The password is
no longer readable after the
Password Protection mode is
selected by programming Lock
Register bit 2 to zero.
Rev 1.9
30 / 171
Operation Features
5.8
BY25Q256FS
Extended Address Register
In addition to the Status Registers, the BY25Q256FS also provides a volatile Extended Address
Register that allows the 256M area of the device to be used normally in 3-Byte Address Mode. The
value of the Extended Address Register and the 24-bit address input in the 3-Byte Address Mode
together form the complete start address of the instruction operation. That is, when A24 = 0, the
starting address of the instruction operation selects the lower 128Mb memory array
(00000000h-00FFFFFFh). When A24 = 1, the start address of the instruction operation will select
the high 128Mb memory array (01000000h-01FFFFFFh).
Please note that:
1.
In 3-Byte Address Mode, When A24 = 0/1, the starting address of the instruction operation
selects the lower/ high 128Mb memory array. However, as the instruction operation address
continues to be carried, the address of the instruction operation can enter the high/lower
128Mb memory array. At this time, the value of the Extended Address Register does not
change with the carry of the address, that is, the value of Extended Address Register can only
be modified by the Write Extended Address Register instruction.
2.
In 4-Byte Address Mode, Extended Address Register is not available. The value of Extended
Address Register has no effect on the instruction operation. The device will require 4-Byte
address input for all address related instructions, and the Extended Address Re gister setting
will be ignored. The Read Extended Address Register and Write Extended Address Register
instructions are not available in the 4-Byte Address Mode. At the same time, during the
instruction operation, the same as in the 3-Byte Address Mode, the carry of the address does
not have any effect on the Extended Address Register.
Table 15. Extended Address Register
EA7
A31(1)
EA6
A30(1)
EA5
A29(1)
EA4
A28(1)
EA3
A27(1)
EA2
A26(1)
EA1
A25(1)
EA0
A24(2)
Notes:
1. Reserved for higher densities: 512Mb ~ 32Gb.
2. Address Bit #24:A24=0: Select lower 128Mb; A24=1: Select upper 128Mb.
December 2020
Rev 1.9
31 / 171
Device Identification
BY25Q256FS
6. Device Identification
Three legacy Instructions are supported to access device identification that can indicate the
manufacturer, device type, and capacity (density). The returned data bytes provide the information
as shown in the below table.
Table 16. BY25Q256FS ID Definition table
Operation Code
9FH
90H/92H/94H
M7-M0(SPI)
68
68
ID15-ID8(SPI)
49
ABH
18
Operation Code
9FH
M7-M0(QPI)
68
90H/92H/94H
ABH
68
December 2020
ID7-ID0(SPI)
19
18
ID15-ID8(QPI)
48
ID7-ID0(QPI)
19
18
18
Rev 1.9
32 / 171
Instructions Description
BY25Q256FS
7. Instructions Description
All instructions, addresses and data are shifted in and out of the device, beginning with the most
significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction
code must be shifted in to the device, most significant bit first on SI, each bit being latched on the
rising edges of SCLK.
See Table 17, every instruction sequence starts with a one-byte instruction code. Depending on
the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS
must be driven high after the last bit of the instruction sequence has been shifted in. For the
instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and
Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can
be driven high after any bit of the data-out sequence is being shifted out.
For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register,
Write Enable, Write Disable or Deep Power-Down instruction, etc. /CS must be driven high exactly
at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must
drive high when the number of clock pulses after /CS being driven low is an exact multiple of eight.
For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will
not be reset.
December 2020
Rev 1.9
33 / 171
Instructions Description
BY25Q256FS
Table 17. Instruction Set Table
Instruction Set Table-Standard/Dual/Quad SPI Instructions, 3-Byte & 4-Byte Address
Mode (1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Number
（ 0-7）
（ 8-15）
（ 16-23）
（ 24-31）
（ 32-39）
（ 40-47）
（ 48-55）
Write Enable
Volatile SR Write
Enable
Write Disable
Read Status
Register-1
Write Status
Register(4)
Read Status
Register-2
Write Status
Register-2
Read Status
Register-3
Write Status
Register-3
06h
Chip Erase
Program/ E ras e
Suspen d
Program/ E ras e
Resume
C7h/60h
Deep Power-d o w n
Release
Power-d o w n / ID
Release
Power-d o w n
Manufactu rer/ D evic e
ID
B9h
50h
04h
05h
(S7-S0) (2)
01h
(S7-S0) (4)
35h
(S15-S 8)
(S15-S 8)
(2)
31h
(S15-S 8)
15h
(S23-S 1 6)(2)
11h
(S23-S 1 6)
75h
7Ah
Dummy
Dummy
Dummy
(ID7-ID0)(2)
90h
Dummy
Dummy
00/01h
(MF7-MF0)/
(ID7-ID0)
(ID7-ID0))/
(MF7-MF0)
Read JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)(9)
Read Seri al Flash
Disco v era bl e
Param ete r
5Ah
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D 0)
Enter QPI Mode
38h
Enable Reset
66h
Reset Device
99h
13h
A31-A24
A23-A16
A15-A8
A7-A0
(D7-D0)
0Ch
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
3Ch
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0, …)
(7)
6Ch
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0, …)
(9)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Number
（ 0-7）
（ 8-11）
（ 12-15）
（ 16-19）
（ 20-23）
（ 24-27）
（ 28-31）
Fast Read Dual I/O with
4-By te Addre ss
BCh
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
Read Data
with 4-Byte
Address
Fast Read
with 4-Byte Address
Fast Read Dual Output
with 4-By te Addre ss
ABh
ABH
(D7-D0)
Fast Read Quad
Output with 4-By te
Address
Data Input Output
Cloc k Number
Fast Read Quad I/O
with 4-By te Addre ss
Byte 1
Byte 2
（ 0-7） （ 8-9）
ECh
December 2020
A31-A24
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
（ 10-11）
（ 12-13）
（ 14-15）
（ 16-17）
（ 18-19）
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
Rev 1.9
Byte 8
Byte 9
（ 20-21） （ 22-23）
Dummy
(D7-D0)
34 / 171
Instructions Description
Data Input Output
BY25Q256FS
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
（ 0-7）
Cloc k Number
Page Program with
12h
4-Byte Address
Quad Page Program
34h
with 4-Byte Address
Sector Erase (4KB)
21h
with 4-Byte Address
Block Erase(3 2 K)
5Ch
with 4-Byte Address
Block Erase(6 4 K)
DCh
with 4-Byte Address
（ 8-9）
（ 10-11）
（ 12-13）
（ 14-15）
（ 16-17）
（ 18-19）
A31-A24
A23-A16
A15-A8
A7-A0
(D7-D0)
(D7-D0)(3)
A31-A24
A23-A16
A15-A8
A7-A0
(D7-D0)
A31-A24
A23-A16
A15-A8
A7-A0
A31-A24
A23-A16
A15-A8
A7-A0
A31-A24
A23-A16
A15-A8
A7-A0
Read Lock Register
2Dh
(S7-S0)
Next Byte
Write Lock Register
2Ch
(S7-S0)
(S15-S 8)
SPB Lock Bit Clear
Read SPB Lock
Register
SPB Erase
A6h
(S7-S0)
Next Byte
(S7-S0)
Next Byte
A7h
E4h
Global Block/Sect or
Lock
Global Block/Sect or
Unlock
Read Unprotect
Solid Protect Bit
Unprotect Solid
Protect Bit Set
Unprotect Solid
Protect Bit Clear
Data Input Output
Byte 1
Cloc k Number
（ 0-7）
Read Password
Register
Write Password
Register
Password Unlock
7Eh
98h
AAh
A8h
A9h
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
（ 8-9） （ 10-11） （ 12-13） （ 14-15） （ 16-17） （ 18-19） （ 18-19） （ 18-19） （ 18-19）
27h
(P7-P0)
(P15-P 8
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56) Next Byte
28h
(P7-P0)
(P15-P 8
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56)
29h
(P7-P0)
(P15-P 8
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56)
December 2020
Rev 1.9
35 / 171
Instructions Description
BY25Q256FS
Instruction Set Table-Standard/Dual/Quad SPI Instructions, 3-Byte Address Mode (1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Cloc k Number
（ 0-7）
（ 8-15）
（ 16-23）
（ 24-31）
（ 32-39）
（ 40-55）
Read Uni que ID Numb er
4Bh
Dumm y
Dumm y
Dumm y
Dumm y
(ID127 -ID 0)
Cloc k Number
（ 0-7）
（ 8-15）
（ 16-23）
（ 24-31）
（ 32-39）
（ 40-47）
Page Program
02h
A23-A1 6
A15-A8
A7-A0
(D7-D 0)
(D7-D 0)( 3)
Quad Page Program
32h
A23-A1 6
A15-A8
A7-A0
(D7-D0, …)(9)
(D7-D0, …)(3)
Sector Erase (4KB)
20h
A23-A1 6
A15-A8
A7-A0
Block Erase (32KB)
52h
A23-A1 6
A15-A8
A7-A0
Block Erase (64KB)
D8h
A23-A1 6
A15-A8
A7-A0
Normal Read Data
03h
A23-A1 6
A15-A8
A7-A0
(D7-D 0)
(Next Byte)
Fast Read
0Bh
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D 0)
Dual Output Fast read
3Bh
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D0)( 7)
Quad Output Fast read
6Bh
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D0)( 9)
Erase Security
Registers(5)
Program Security
Registers(5)
Read Security
Registers(5)
44h
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
42h
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
D7-D0
Next Byte
48h
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
Dumm y
D7-D0
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Number
（ 0-7）
（ 8-11）
（ 12-15）
（ 16-19）
（ 20-23）
（ 24-27）
（ 28-31）
Dual I/O Fast read
Mftr./Device ID Dual
I/O
BBh
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D 0)
92h
A23-A1 6
A15-A8
A7-A0
Dumm y
(MF7- M F0 )
Data Input Output
Byte 1
Byte 2
Cloc k Number
（ 0-7）
（ 8-9）
Set Burst With Wrap
77h
Dumm y
Dumm y
Dumm y
W6-W4
Quad I/O Fast read
EBh
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
Dumm y
(D7-D 0)
(D7-D 0)
Word Read Quad I/O
Mftr./Device ID Quad
I/O
E7h
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
(D7-D 0)
(D7-D 0)
(D7-D 0)
94h
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
Dumm y
(MF7- M F0 )
(ID7-ID 0)
Read SPB Status
E2h
A23-A16
A15-A8
A7-A0
(D7-D0)
SPB Progra m
E3h
A23-A16
A15-A8
A7-A0
Read DPB Status
Dynamic Protection
Block/Sect or Lock
Dynamic Protection
Block/Sect or Unlock
Enter 4-Byte Address
Mode
Read Extende d Addr.
Register
Write Extended Addr.
Register
3Dh
A23-A16
A15-A8
A7-A0
36h
A23-A16
A15-A8
A7-A0
39h
A23-A16
A15-A8
A7-A0
(12)
December 2020
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
(ID7-ID 0)
Byte 8
Byte 9
（ 10-1 1） （ 12-13） （ 14-15） （ 16-17） （ 18-19） （ 20-2 1） （ 22-23）
(D7-D0)
B7h
C8h
(EA7-E A 0) (2)
C5h
(EA7-E A 0)
Rev 1.9
36 / 171
Instructions Description
BY25Q256FS
Instruction Set Table-Standard/Dual/Quad SPI Instructions, 4-Byte Address Mode (1)
Data Input
Byte 1
Output
Cloc k Numbe r （ 0-7）
Read Unique ID
Number
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
（ 8-15）
（ 16-23）
（ 24-31）
（ 32-39）
（ 40-47）
（ 48-63）
Dumm y
Dumm y
Dumm y
Dumm y
Dumm y
(ID127 -ID 0)
（ 8-15）
（ 16-23）
（ 24-31）
（ 32-39）
（ 40-47）
（ 48-55）
02h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
(D7-D 0)
(D7-D 0)( 3)
32h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
(D7-D0, …)(9)
(D7-D0, …)(3)
20h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
52h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
D8h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
03h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
(D7-D 0)
(Next Byte)
0Bh
A31-A2 4
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D 0)
3Bh
A31-A2 4
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D0)( 7)
6Bh
A31-A2 4
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D0)( 9)
44h
A31-A2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
42h
A31-A2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
D7-D0
Next Byte
48h
A31-A2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
Dumm y
D7-D0
4Bh
Cloc k Numbe r （ 0-7）
Page Program
Quad Page
Program
Sector Erase
(4KB)
Block Erase
(32KB)
Block Erase
(64KB)
Normal Read
Data
Fast Read
Dual Output Fast
read
Quad Output Fast
read
Erase Security
Registers(5)
Program Security
Registers(5)
Read Security
Registers(5)
Data Input
Output
Cloc k Numbe r
Dual I/O Fast
read
Mftr./Device ID
Dual I/O
Data Input
Output
Cloc k Numbe r
Set Burst With
Wrap
Quad I/O Fast
read
Word Read
Quad I/O(12)
Mftr./Device ID
Quad I/O
Read SPB
Status
SPB Progra m
Read DPB
Status
Dynamic
Protectio n
Block/Sect or
Lock
Dynamic
Protectio n
Block/Sect or
Unlock
Exit 4-Byte
Address Mode
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
（ 0-7）
（ 8-11）
（ 12-15）
（ 16-19）
（ 20-23）
（ 24-27）
（ 28-31）
（ 22-35）
BBh
A31-A2 4
A23-A1 6
A15-A8
A7-A0
Dumm y
(D7-D 0)
(D7-D 0)
92h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
Dumm y
(MF7- M F0 )
(ID7-ID 0)
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
Byte 10
（ 0-7）
（ 8-9）
77h
Dumm y
Dumm y
Dumm y
Dumm y
W6-W4
EBh
A31-A2 4
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
Dumm y
(D7-D 0)
(D7-D 0)
E7h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
(D7-D 0)
(D7-D 0)
(D7-D 0)
94h
A31-A2 4
A23-A1 6
A15-A8
A7-A0
M7-M 0
Dumm y
Dumm y
(MF7- M F0 )
(D7-D 0)
E2h
A31-A2 4
A23-A16
A15-A8
A7-A0
(D7-D0)
E3h
A31-A2 4
A23-A16
A15-A8
A7-A0
3Dh
A31-A2 4
A23-A16
A15-A8
A7-A0
36h
A31-A2 4
A23-A16
A15-A8
A7-A0
39h
A31-A2 4
A23-A16
A15-A8
A7-A0
（ 10-11） （ 12-13） （ 14-1 5） （ 16-17） （ 18-19） （ 20-21） （ 22-23） （ 24-25）
(D7-D0)
E9h
December 2020
Rev 1.9
37 / 171
Instructions Description
BY25Q256FS
Instruction Set Table-QPI Instructions, 3-Byte & 4-Byte Address Mode (14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Cloc k Number
(0-1)
(2-3)
(4- 5)
(6- 7)
(8-9)
(10-11)
(12-13)
(14-15)
Dummy
(D7-D0)
Write Enable
06h
Volatile SR Write Enable
50h
Write Disable
04h
Read Status Register-1
05h
Write Status Register(4)
01h
Read Status Register-2
35h
Write Status Register-2
31h
Read Status Register-3
15h
Write Status Register-3
11h
Chip Erase
C7h/60h
Erase / Progra m Suspend
75h
Erase / Progra m Resume
7Ah
Power-d o w n
B9h
Set Read Paramet ers
C0h
Release Powerdow n / ID
ABh
Manufactu rer/ D evic e ID
90h
JEDEC ID
9Fh
Exit QPI Mode
FFh
Enable Reset
66h
Reset Device
99h
Fast Read Quad I/O with
ECh
4-Byte Address
Read Serial Flash
Discovera ble
5Ah
Paramet er
P a g e P ro gra m w ith 4-B yt e
12h
Address
Sector Erase (4KB) with
21h
4-Byte Address
Block Erase(3 2K) with
5Ch
4-Byte Address
Block Erase(6 4K) with
DCh
4-Byte Address
Read Lock Register
2Dh
Write Lock Register
2Ch
SPB Lock Bit Clear
A6h
Read SPB Lock Register
A7h
SPB Erase
E4h
Read Unprotect Solid
AAh
Protect Bit
Unprotect Solid Protect
A8h
Bit Set
Unprotect Solid Protect
A9h
Bit Clear
Data Input Output
Byte 1
Cloc k Number
(0-1)
Read Password Register
27h
Write Password Register
28h
Password Unlock
29h
December 2020
(S7-S0)(2)
(S7-S0)(4)
(S15-S 8)(2)
(S15-S 8)
(S23-S 16)(2)
(S23-S 16)
(S15-S 8)
P7-P0
Dummy
Dummy
(MF7-MF0)
Dummy
Dummy
(ID15-ID8)
Dummy
00h
(ID7-ID0)
(ID7-ID0)(2)
(MF7-MF0)
(ID7-ID0)
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0(15)
A23-A16
A15-A8
A7-A0
Dummy
(D7-D0)
A31-A24
A23-A16
A15-A8
A7-A0
(D7-D0)
A31-A24
A23-A16
A15-A8
A7-A0
A31-A24
A23-A16
A15-A8
A7-A0
A31-A24
A23-A16
A15-A8
A7-A0
(S7-S0)
(S7-S0)
Next Byte
(S15-S 8)
(S7-S0)
Next Byte
(S7-S0)
Next Byte
Byte 2
(2-3)
(P7-P0)
(P7-P0)
(P7-P0)
Byte 3
(4- 5)
(P15-P 8
(P15-P 8
(P15-P 8
(D7-D0)(3)
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9 Byte 10
(6- 7)
(8-9)
(10-11)
(10-11)
(12-13)
(14-15)
(16-17)
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56) Next Byte
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56)
(P23-P 16) (P31-P 24) (P39-P 32) (P47-P 40) (P55-P 48) (P63-P 56)
Rev 1.9
38 / 171
Instructions Description
BY25Q256FS
Instruction Set Table-QPI Instructions, 3-Byte Address Mode (14)
Data Input Output
Byte 1
Cloc k Number
(0-1)
(2-3)
Page Program
02h
A23-A16
Sector Erase (4KB)
20h
A23-A16
A15-A8
A7-A 0
Block Erase (32KB)
52h
A23-A16
A15-A8
A7-A 0
Block Erase (64KB)
D8h
A23-A16
A15-A8
A7-A 0
Fast Read
0Bh
A23-A16
A15-A8
A7-A 0
0Ch
A23-A16
A15-A8
A7-A 0
(16)
Burst Read with W rap
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
(4-5)
(6-7)
(8-9)
(10-11)
(12-13)
A15-A8
A7-A 0
D7-D0
(9)
(3)
D7-D0
Dummy
(15)
(D7-D0)
Dummy
(15)
(D7-D0)
(15)
Fast Read Quad I/O
EBh
A23-A16
A15-A8
A7-A 0
Read Unique ID Number
4Bh
Dummy
Dummy
Dummy
Dummys*
(ID127-ID0)
Read Security Registers(5)
48h
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
Dumm y
D7-D0
Erase Security Registers
44h
A23-A1 6
(8 )
(8)
(8)
Program Security Registers(5)
42h
A23-A1 6 (8 )
A7-A0 (8)
D7-D0
Next Byte
Dumm y
(D7-D0)
(5)
A15-A8
A7-A0
A15-A8 (8)
M7-M0
Read SPB Status
E2h
A23-A16
A15-A8
A7-A0
SPB Program
E3h
A23-A16
A15-A8
A7-A0
Read DPB Status
Dynamic Protection
Block/Sect or Lock
Dynamic Protection
Block/Sect or Unlock
Enter 4-Byte Address Mode
Read Extended Addr.
Register
Write Extended Addr.
Register
3Dh
A23-A16
A15-A8
A7-A0
36h
A23-A16
A15-A8
A7-A0
39h
A23-A16
A15-A8
A7-A0
Byte 1
Cloc k Number
B7h
C8h
(EA7-E A 0)(2)
C5h
(EA7-E A 0)
Byte 2
Byte 3
Byte 4
Byte 6
Byte 7
Byte 8
(10-11)
(12-13)
(13-14)
(0-1)
(2-3)
(4-5)
(6-7)
(8-9)
02h
A31-A24
A23-A16
A15-A8
A7-A0
Sector Erase (4KB)
20h
A31-A24
A23-A16
A15-A8
A7-A0
Block Erase (32KB)
52h
A31-A24
A23-A16
A15-A8
A7-A0
Block Erase (64KB)
D8h
A31-A24
A23-A16
A15-A8
A7-A0
Fast Read
0Bh
A31-A24
A23-A16
A15-A8
A7-A0
0Ch
A31-A24
A23-A16
A15-A8
A7-A0
Burst Read with W rap
(14)
Byte 5
Page Program
(16)
(D7-D0)
(D7-D0)
Instruction Set Table-QPI Instructions, 4-Byte Address Mode
Data Input Output
Dummy
D7-D0
(9)
D7-D0
(3)
Dummy
(15)
(D7-D0)
Dummy
(15)
(D7-D0)
(15)
EBh
A31-A24
A23-A16
A15-A8
A7-A0
4Bh
Dummy
Dummy
Dummy
Dummy
Dummys*
(ID127-ID0)
48h
A31-A 2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
Dumm y
D7-D0
44h
A31-A 2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
42h
A31-A 2 4
A23-A1 6 (8 )
A15-A8 (8)
A7-A0 (8)
D7-D0
Next Byte
Read SPB Status
E2h
A31-A 2 4
A23-A16
A15-A8
A7-A0
Dumm y
(D7-D0)
SPB Progra m
E3h
A31-A 2 4
A23-A16
A15-A8
A7-A0
Read DPB Status
Dynamic Protection
Block/Sect or Lock
Dynamic Protection
Block/Sect or Unlock
Exit 4-Byte Address
Mode
3Dh
A31-A 2 4
A23-A16
A15-A8
A7-A0
36h
A31-A 2 4
A23-A16
A15-A8
A7-A0
39h
A31-A 2 4
A23-A16
A15-A8
A7-A0
Fast Read Quad I/O
Read Unique ID
Number
Read Security
Registers(5)
Erase Security
Registers(5)
Program Security
Registers(5)
December 2020
M7-M0
Dummy
(D7-D0)
(D7-D0)
E9h
Rev 1.9
39 / 171
Instructions Description
BY25Q256FS
Instruction Set Table-DTR with SPI Instructions, 3-Byte & 4-Byte Address Mode (14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Numbe r(1 -1 -1)
8
4
4
4
6
4
4
DTR Quad I/O Fast Read
with 4- By te Address
EEh
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0
(D7-D0)
Instruction Set Table-DTR with QPI Instructions, 3-Byte & 4-Byte Address Mode
(14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Numbe r(1 -1 -1)
8
4
4
4
6
4
4
DTR Quad I/O Fast Read
with 4- By te Address
EEh
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0
(D7-D0)
Instruction Set Table-DTR with SPI Instructions, 3-Byte Address Mode
(14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Numbe r(1 -1 -1)
8
4
4
4
6
4
4
0Dh
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
DTR Fast Read
Cloc k Numbe r(1 -2 -2)
8
2
2
2
2
4
2
DTR Fast Read Dual I/O
BDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
Cloc k Numbe r(1 -4 -4)
8
1
1
1
1
7
1
DTR Fast Read Quad I/O
EDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
Instruction Set Table-DTR with SPI Instructions, 4-Byte Address Mode (14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Numbe r(1 -1 -1)
8
4
4
4
6
4
4
DTR Fast Read
0Dh
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
2
Cloc k Numbe r(1 -2 -2)
8
2
2
2
2
4
DTR Fast Read Dual I/O
BDh
A31-A16
A15-A0
M7-M0
Dummy
(D7-D0)
Cloc k Numbe r(1 -4 -4)
8
1
1
1
1
7
EDh
A31-A16
A15-A0
M7-M0
Dummy
(D7-D0)
DTR Fast Read Quad I/O
1
Instruction Set Table-DTR with QPI Instructions, 3-Byte Address Mode (14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Cloc k Numbe r(4 -4 -4)
2
1
1
1
8
1
1
0Eh
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
0Dh
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
DTR Read with Wrap
(13)
DTR Fast Read
Cloc k Numbe r(4 -4 -4)
2
1
1
1
1
7
1
DTR Fast Read Quad I/O
EDh
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
Instruction Set Table-DTR with QPI Instructions, 4-Byte Address Mode (14)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
1
Cloc k Numbe r(4 -4 -4)
2
1
1
1
61
8
1
DTR Read with Wrap(13)
0Eh
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
DTR Fast Read
0Dh
A31-A24
A23-A16
A15-A8
A7-A0
Dummy
D7-D0
Cloc k Numbe r(4 -4 -4)
2
1
1
1
1
1
7
1
DTR Fast Read Quad I/O
EDh
A31-A24
A23-A16
A15-A8
A7-A0
M7-M0
Dummy
(D7-D0)
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )”
indicate data output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the
December 2020
Rev 1.9
40 / 171
Instructions Description
BY25Q256FS
instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program
Security Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the
device, the addressing will wrap to the beginning of the page and overwrite previously sent data.
4. When the Write Status Register instruction 01h is followed by 1 byte data, the data will be written
to Status Register-1. When the Write Status Register instruction 01h is followed by 2 bytes of data,
the first byte data will be written to Status Register-1, and the second byte data will be written to
Status Register-2, see Write Status Register (01H or 31H or 11H).
5. Security Register Address:
Security Register 1: A23-16=00h; A15-12=0001; A11-9=000; A8-0=byte
address
Security Register 2: A23-16=00h; A15-12=0010; A11-9=000; A8-0=byte
address
Security Register 3: A23-16=00h; A15-12=0011; A11-9=000; A8-0=byte
address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format:
Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. Word Read Quad I/O data output format:
IO0 = (x, x, D4, D0, D4, D0, D4, D0)
IO1 = (x, x, D5, D1, D5, D1, D5, D1)
IO2 = (x, x, D6, D2, D6, D2, D6, D2)
IO3 = (x, x, D7, D3, D7, D3, D7, D3)
12. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0)
13. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0)
14. QPI Instruction, Address, Data input/output format:
CLK # 0
1
2
3
4
5
6
7
8
9
10 11
IO0
IO1
IO2
IO3
=
=
=
=
C4,
C5,
C6,
C7,
C0,
C1,
C2,
C3,
A20, A16,
A21, A17,
A22, A18,
A23, A19,
A12, A8,
A13, A9,
A14, A10,
A15, A11,
A4, A0,
A5, A1,
A6, A2,
A7, A3,
D4,
D5,
D6,
D7,
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D0
D1
D2
D3
15. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read
with Wrap is controlled by read parameter P7 – P4.
16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
Table 18. Instructions that need to send the Write Enable/Write Enable for Volatile Status
Register instruction
Mode
SPI/QPI
SPI
SPI/QPI
Instruction
Write Status Register
Write Extended Address Register
Erase Security Registers
Program Security Registers
Page Program
Page Program with 4-Byte Address
Quad Page Program
Quad Input Page Program with 4-Byte
Address
Sector Erase
Sector Erase with 4-Byte Address
32KB Block Erase
32KB Block Erase with 4-Byte Address
64KB Block Erase
64KB Block Erase with 4-Byte Address
Chip Erase
Write Lock Register
SPB Lock Bit Clear
SPB Program
SPB Erase
Dynamic Protection Block/Sector Lock
Dynamic Protection Block/Sector Unlock
Unprotect Solid Protect Bit Set
Unprotect Solid Protect Bit Clear
Global Block/Sector Lock
Global Block/Sector Unlock
Write Password Register
Password Unlock
December 2020
Rev 1.9
01h/31h/11h
C5h
44h
42h
02h
12h
32h
Write
06H/50H
06H
06H
06H
06H
06H
06H
34h
06H
20h
21h
52h
5Ch
D8h
DCh
60h/C7h
2Ch
A6h
E3h
E4h
36h
39h
A8h
A9h
7Eh
98h
28h
29h
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
06H
42 / 171
Instructions Description
7.1
BY25Q256FS
Configuration and Status Instructions
7.1.1 Write Enable (06H)
See Figure 11-Figure 12，the Write Enable instruction is for setting the Write Enable Latch bit. The
Write Enable Latch bit must be set prior to every Write Status Register, Program, Erase and some
Advanced Block/Sector Protection instruction (see Table 18). The Write Enable instruction
sequence: /CS goes low sending the Write Enable instruction, /CS goes high.
Please note that the Write Enable instruction sent when the Write Enable for Volatile Status
Register instruction is valid is not accepted. Therefore, when need to send the Write Enable
instruction, but do not know if the Write Enable for Volatile Status Register instruction is valid,
please send the Write Disable instruction first.
Figure 11. Write Enable Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
06H
High_Z
SO
Figure 12. Write Enable Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
06H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
7.1.2 Write Enable for Volatile Status Register (50H)
See Figure 13-Figure 14, the non-volatile Status Register bits can also be written to as volatile bits
(HOLD/RES, DRV1, DRV0, CMP, QE, SRP1, SRP0, BP4, BP3, BP2, BP1, BP0). This gives more
flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register
non-volatile bits. Write Enable for Volatile Status Register instruction will not set the Write Enable
Latch bit, it is only valid for the Write Status Registers instruction to change the volatile Status
Register bit values (After the software/hardware reset or re-powered, the volatile Status Register
bit values will be restored to the default value or the value input by the Write Enable instruction).
Please note that the Write Enable for Volatile Status Register instruction sent when the Write
Enable instruction is valid is not accepted. Therefore, when need to send the Write Enable for
Volatile Status Register instruction, please first determine whether the Write Enable instruction is
not valid.
Figure 13. Write Enable for Volatile Status Register (SPI Mode)
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
50H
High_Z
SO
Figure 14. Write Enable for Volatile Status Register (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
50H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
7.1.3 Write Disable (04H)
See Figure 15-Figure 16, the Write Disable instruction is for resetting the Write Enable Latch bit or
invalidate the Write Enable for Volatile Status Register instruction. The Write Disable instruction
sequence: /CS goes low -> sending the Write Disable instruction -> /CS goes high. The WEL bit is
reset by following condition: Power-up and upon completion of the Write Status Register, Page
Program, Sector Erase, Block Erase and Chip Erase, Program/Erase Security Registers and Reset
instructions.
Figure 15. Write Disable Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
SCLK
Instruction
SI
04H
High_Z
SO
Figure 16. Write Disable Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
04H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
7.1.4 Read Status Register (05H or 35H or 15H)
See Figure 17-Figure 18, the Read Status Register (RDSR) instruction is for reading the Status
Register. The Status Register may be read at any time, even while a Program, Erase or Write
Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write in Progress (WIP) bit before sending a new instruction to the device. It is also
possible to read the Status Register continuously. For instruction code “05H”, the SO will outp ut
Status Register bits S7~S0. The instruction code “35H”, the SO will output Status Register bits
S15~S8, The instruction code “15H”, the SO will output Status Register bits S23~16 .
Figure 17. Read Status Register Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Instruction
SI
05H or 35H or 15H
Register 0/1/2
SO
High_Z
7 6
MSB
5
4
Register 0/1/2
2
3
1
0
7 6
MSB
5
4
3
2
1
0
Figure 18. Read Status Register Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
Mode 0
Instruction
05H/35H/15H
SI
(IO0)
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
7
3
7
3
7
/HOLD
(IO3)
SR-1/2/3
out
December 2020
Rev 1.9
SR-1/2/3
out
46 / 171
Instructions Description
BY25Q256FS
7.1.5 Write Status Register (01H or 31H or 11H)
The Write Status Register instruction allows the Status Registers to be written. The Status
Register-1 can be written by the Write Status Register 01h instruction; The Status Register-2 be
written by the Write Status Register 01h or 31h instruction; Status Register-3 can be written by the
Write Status Register 11h instruction. When the Write Status Register instruction 01h is followed
by 1 byte data, the data will be written to Status Register-1. When the Write Status Register
instruction 01h is followed by 2 bytes of data, the first byte data will be written to Status Register-1,
and the second byte data will be written to Status Register-2; And Write Status Register instruction
31h or 11h can only follow 1 byte data, the data will be written to Status Register-2、Status
Register-3 respectively. The writable Status Register bits include: SRP0, BP[4:0] in Status
Register-1; CMP, LB[3:1], QE, SRP1 in Status Register- 2; ADS, ADP, DRV1, DRV0, Hold/RES in
Status Register- 3. All other Status Register bit locations are read-only and will not be affected
by the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it
cannot be cleared to 0.
The Write Status Register instruction allows new values to be written to the Status Register.
Before it can be accepted, a Write Enable or Write Enable For Volatile SR instruction must
previously have been executed After the Write Enable instruction has been decoded and executed,
the device sets the Write Enable Latch (WEL).
The Write Status Register instruction has no effect on S15 (SUS1), S10 (SUS2), S1 (WEL) and S0
(WIP) of the Status Register. /CS must be driven high after the 8 or 16 bit of the data byte has
been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as
/CS is driven high, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to check
the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed,
the Write Enable Latch (WEL) is reset.
The Write Status Register instruction allows the user to change the values of the Block Protect
(BP4, BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 7 and Table 8. The Write Status Register (WRSR) instruction also
allows the user to set or reset the Status Register Protect (SRP1 and SRP0) bits in accordance
with the Write Protect (/WP) signal. The Status Register Protect (SRP1 and SRP0) bits and Write
Protect (/WP) signal allow the device to be put in the Hardware Protected Mode. The Write Status
Register instruction is not executed once the Hardware Protected Mode is entered.
The sequence of issuing WRSR instruction is: /CS goes low→ sending WRSR instruction code→
Status Register data on SI→/CS goes high.
The /CS must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will
be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as
soon as Chip Select (/CS) goes high. The Write in Progress (WIP) bit still can be checked during
the Write Status Register cycle is in progress. The WIP is set 1 during the tW timing, and is set 0
when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Figure 19. Write Status Register Sequence Diagram-01H 2byte (SPI Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
SO
December 2020
01H
11
12
13
14
15
1
0
16
17
7
MSB
6
5
4
3
2
18
19
20
21
22
23
9
8
Mode 3
Mode 0
Status Register-2 in
Status Register-1 in
Instruction
SI
10
15
14
13
12
11
10
MSB
High_Z
Rev 1.9
47 / 171
Instructions Description
BY25Q256FS
Figure 20. Write Status Register Sequence Diagram-01H 2byte (QPI Mode)
/CS
0
Mode 3
Mode 0
SCLK
1
2
3
4
SR2
SR1
01H
Mode 3
Mode 0
5
IO0
4
0
4
0
IO1
5
1
5
1
IO2
6
2
6
2
IO3
7
3
7
3
Figure 21. Write Status Register Sequence Diagram-01/31/11H 1byte (SPI Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
12
13
14
15
1
0
Mode 3
Mode 0
SR1/SR2/SR3 in
Instruction
SI
11
01H/31H/11H
6
7
MSB
SO
5
4
3
2
High_Z
Figure 22. Write Status Register Sequence Diagram-01/31/11H 1byte (QPI Mode)
/CS
Mode 3
SCLK
0
1
3
Mode 3
Mode 0
Instruction
SI
(IO0)
2
Mode 0
SR1/2/3in
01H/31H/11H
4
0
SO
(IO1)
5
1
/WP
(IO2)
6
2
/HOLD
(IO3)
7
3
7.1.6 Read Extended Address Register (C8H)
When the device is in the 3-Byte Address Mode, the Extended Address Register is used as the 4th
address byte A[31:24] to access memory regions beyond 128Mb. The Read Extended Address
Register instruction is entered by driving /CS low and shifting the instruction code “C8h” into the SI
pin on the rising edge of CLK. The Extended Address Register bits are then shifte d out on the DO
pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 23-Figure
24.
When the device is in the 4-Byte Address Mode, the Extended Address Register is not used.
December 2020
Rev 1.9
48 / 171
Instructions Description
BY25Q256FS
Figure 23. Read Extended Address Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
11 12
13 14 15 16 17 18
19 20
21 22 23
SCLK Mode 0
Instruction
SI
C8H
Extended Addr reg out
SO
High_Z
7 6
MSB
5
4
3
2
1
Extended Addr reg out
0
7 6
MSB
4
5
5
4
3
2
1
0
Figure 24. Read Extended Address Register (QPI Mode)
/CS
Mode 3
SCLK
0
1
Instruction
C8H
December 2020
2
3
Mode 0
Extended Addr Extended Addr
Reg out
Reg out
SI
(IO0)
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
/HOLD
(IO3)
7
3
7
3
7
Rev 1.9
49 / 171
Instructions Description
BY25Q256FS
7.1.7 Write Extended Address Register (C5H)
The Extended Address Register is a volatile register that stores the 4th byte address (A31-A24)
when the device is operating in the 3-Byte Address Mode (ADS=0). To write the Extended Address
Register bits, a Write Enable (06h) instruction must previously have been executed for the device
to accept the Write Extended Address Register instruction (Status Register bit WEL must equal 1).
Once write enabled, the instruction is entered by driving /CS low, sending the instruction code
“C5h”, and then writing the Extended Address Register data byte as illustrated in Figure
25-Figure 26.
Upon power up or the execution of a Software reset, the Extended Address Register bit values will
be cleared to 0.
The Extended Address Register is only effective when the device is in the 3 -Byte Address Mode.
When the device operates in the 4-Byte Address Mode (ADS=1), any instruction with address
input of A31-A24 will replace the Extended Address Register values. It is recommended to check
and update the Extended Address Register if necessary when the device is switched from 4 -Byte
to 3-Byte Address Mode.
Figure 25. Write Extended Address Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
13 14 15 Mode 3
Mode 0
11 12
SCLK Mode 0
Instruction
SI
Ext Add Reg in
7 6
MSB
C5H
5
4
3
2
1
0
High_Z
SO
Figure 26. Write Extended Address Register (QPI Mode)
/CS
Mode 3
SCLK
0
1
December 2020
3
Mode 3
Mode 0
Instruction
SI
(IO0)
2
Mode 0
C5H
Ext Add
Reg in
4
0
SO
(IO1)
5
1
/WP
(IO2)
6
2
/HOLD
(IO3)
7
3
Rev 1.9
50 / 171
Instructions Description
BY25Q256FS
7.1.8 Enter 4-Byte Address Mode (B7H)
The Enter 4-Byte Address Mode instruction (Figure 27-Figure 28) will allow 32-bit address
(A31-A0) to be used to access the memory array beyond 128Mb. The Enter 4-Byte Address Mode
instruction is entered by driving /CS low, shifting the instruction code “B7h” into the SI pin and then
driving /CS high.
Figure 27. Enter 4-Byte Address Mode instruction (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
SCLK Mode 0
7
Mode 3
Mode 0
Instruction
SI
B7H
High_Z
SO
Figure 28. Enter 4-Byte Address Mode instruction (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
B7H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
51 / 171
Instructions Description
BY25Q256FS
7.1.9 Exit 4-Byte Address Mode (E9H)
In order to be backward compatible, the Exit 4-Byte Address Mode instruction (Figure 29-Figure
30) will only allow 24-bit address (A23-A0) to be used to access the memory array up to 128Mb.
The Extended Address Register must be used to access the memory array beyond 128Mb. The
Exit 4-Byte Address Mode instruction is entered by driving /CS low, shifting the instruction code
“E9h” into the SI pin and then driving /CS high.
Figure 29. Exit 4-Byte Address Mode (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
SCLK Mode 0
Mode 3
Mode 0
Instruction
SI
E9H
High_Z
SO
Figure 30. Exit 4-Byte Address Mode (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
E9H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
52 / 171
Instructions Description
BY25Q256FS
7.1.10 Enter QPI Mode (38H)
The BY25Q256FS support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad
Peripheral Interface (QPI). However, SPI mode and QPI mode cannot be used at the same time.
“Enter QPI (38h)” instruction is the only way to switch the device from SPI mode to QPI mode.
Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This
provides full backward compatibility with earlier generations of BoyaMicro serial flash memories.
See Instruction Set Table 17 for all supported SPI instructions. In order to switch the device to QPI
mode, the Quad Enable (QE) bit in Status Register-2 must be set to 1 first, and an “Enter QPI
(38h)” instruction must be issued. If the Quad Enable (QE) bit is 0, the “Enter QPI (38h)”
instruction will be ignored and the device will remain in SPI mode.
When the device is switched from SPI mode to QPI mode, the existing Write Enable and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure 31. Enter QPI Mode (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
SCLK Mode 0
7
Mode 3
Mode 0
Instruction
SI
38H
High_Z
SO
7.1.11 Exit QPI Mode (FFH)
In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, an “Exit QPI (FFh)”
instruction must be issued.
When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL)
and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
Figure 32. Exit QPI Mode (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
FFH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
53 / 171
Instructions Description
BY25Q256FS
7.1.12 Enable Reset (66H) and Reset Device (99H)
Because of the small package and the limitation on the number of pins, the BY25Q256FS provides
a software reset instruction instead of a dedicated RESET pin. Once the software reset instruction
is accepted, any on-going internal operations will be terminated and the device will return to its
default power-on state and lose all the current volatile settings, such as Volatile Status Register
bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Continuous Read Mode bit
setting (M7-M0) and Wrap Bit setting (W6-W4).
To avoid accidental reset, both “Enable Reset (66h)” and “Reset (99h)” instructions mu st be issued
in sequence. Any other instructions other than “Reset (99h)” after the “Enable Reset (66h)”
instruction will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h)” and
“Reset (99h)” is needed to reset the device. Once the Reset instruction is accepted by the device,
the device will take approximately 300us to reset. During this period, no instruction will be
accepted.
The Enable Reset (66h) and Reset (99h) instruction sequence is shown in Figure 33-Figure 34.
Data corruption may happen if there is an on-going or suspended internal Erase or Program
operation when Reset instruction sequence is accepted by the device. It is recommended to check
the BUSY bit and the SUS bit in Status Register before issuing the Reset instruction sequence.
Figure 33. Enable Reset (66h) and Reset (99h) Instruction Sequence (SPI Mode)
/CS
0
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
SCLK
Instruction
SI
Instruction
99h
66H
Figure 34. Enable Reset (66h) and Reset (99h) Instruction Sequence (QPI Mode)
/CS
Mode 3
SCLK
0
0
1
1
Mode 0
Mode 3
Mode 0
Instruction
Instruction
66H
99H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
54 / 171
Instructions Description
7.2
BY25Q256FS
Read Instructions
7.2.1 Read Data (03H)
See Figure 35-Figure 36, the Read Data Bytes (READ) instruction is followed by a 3-byte/4-byte
address (A23/31-A0), each bit being latched-in during the rising edge of SCLK. Then the memory
content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fR,
during the falling edge of SCLK. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. This means
that the entire memory can be accessed with a single instruction as long as the clock continues.
The instruction is completed by driving /CS high. The whole memory can be read with a single
Read Data Bytes (READ) instruction. Any Read Data Bytes (READ) instruction, while an Erase,
Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 35. Read Data Bytes Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
0
1
2
4
3
5
6
7
9
8
10
28 29 30
31 32 33 34 35 36 37 38 39
SCLK
24-Bit Address
Instruction
SI
21
23 22
03H
3
2
1
0
Data Byte1
MSB
High_Z
SO
7 6
MSB
4
5
High_Z
2
3
0
1
Figure 36. Read Data Bytes Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
36 37 38
39 40 41 42 43 44 45 46 47
SCLK Mode 0
32-Bit Address
Instruction
SI
03H
31 30
29
3
2
1
0
Data Out
MSB
SO
December 2020
High_Z
7 6
MSB
Rev 1.9
5
4
3
2
1
0
55 / 171
Instructions Description
BY25Q256FS
7.2.2 Read Data with 4-Byte Address (13H)
The Read Data with 4-Byte Address instruction is similar to the Read Data (03h) instruction.
Instead of 24- bit address, 32-bit address is needed following the instruction code 13h. No matter
the device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Read Data with
4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Read Data with 4-Byte Address instruction sequence is shown in Figure 37. If this instruction
is issued while an Erase, Program or Write cycle is in process (WIP=1) the instruction is ignored
and will not have any effects on the current cycle. The Read Data with 4-Byte Address instruction
allows clock rates from D.C. to a maximum of fR (see AC Electrical Characteristics).
The Read Data with 4-Byte Address (13h) instruction is only supported in Standard SPI mode.
Figure 37. Read Data with 4-Byte Address Sequence Diagram (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
36 37 38
39 40 41 42 43 44 45 46 47
SCLK Mode 0
32-Bit Address
Instruction
SI
13H
31 30
29
3
2
1
0
Data Out
MSB
SO
December 2020
High_Z
7
MSB
Rev 1.9
6
5
4
3
2
1
0
56 / 171
Instructions Description
BY25Q256FS
7.2.3 Fast Read (0BH)
See Figure 38-Figure 41, the Read Data Bytes at Higher Speed (Fast Read) instruction is for
quickly reading data out. It is followed by a 3-byte/4-byte address (A23/31-A0) and a dummy byte,
each bit being latched-in during the rising edge of SCLK. Then the memory content, at that
address, is shifted out on SO, each bit being shifted out, at a Max frequency fc, during the falling
edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out.
Figure 38. Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
9
8
28 29 30
10
31
SCLK Mode 0
Instruction
24-Bit Address
21
23 22
0BH
SI
2
3
1
0
High_Z
SO
/CS
32 33 34 35 36
37 38 39 40 41 42 43 44
45 46 47
SCLK
Dummy Clocks
SI
Data Out
High_Z
SO
6
7
5
4
3
2
1
0
Figure 39. Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
9
8
36 37 38
10
39
SCLK Mode 0
Instruction
0BH
SI
High_Z
32-Bit Address
31 30
MSB
29
3
2
1
0
SO
/CS
40 41 42 43 44
45 46 47 48 49 50 51 52
53 54 55
SCLK
Dummy Clocks
SI
SO
High_Z
Data Out
6
7
MSB
5
4
3
2
1
0
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number
of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a
wide range of applications with different needs for either maximum F ast Read frequency or
minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number
of dummy clocks can be configured as either 4, 4, 6 or 8. The default number of dummy clocks
upon power up or after a Reset instruction is 4.
December 2020
Rev 1.9
57 / 171
Instructions Description
BY25Q256FS
Figure 40. Fast Read Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
14
13
Mode 0
Instruction
0BH
A23-16
A15-8
Dummy* Data Out 1 Data Out 2 Data Out 3
A7-0
SI
(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO
(IO1)
21
17
13
9
5
1
5
1
5
1
5
/WP
(IO2)
22
18
14
10
6
2
6
2
6
2
6
23
19
15
11
7
3
7
3
7
3
/HOLD
(IO3)
MSB
MSB
7
MSB
MSB
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
Figure 41. Fast Read Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mode 0
Instruction
0BH
A31-24
A15-8
A23-16
IOs switch from
Input to Output
Dummy*
A7-0
SI
(IO0)
28
24
20
16
12
8
4
0
4
0
4
SO
(IO1)
29
25
21
17
13
9
5
1
5
1
5
/WP
(IO2)
30
26
22
18
14
10
6
2
6
2
6
31
27
23
19
15
11
7
3
/HOLD
(IO3)
3
7
MSB
MSB
Byte1
7
MSB
Byte2
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
December 2020
Rev 1.9
58 / 171
Instructions Description
BY25Q256FS
7.2.4 DTR Fast Read (0DH)
The DTR Fast Read instruction is similar to the Fast Read instruction except that the 24/32-bit
address input and the data output requires DTR (Double Transfer Rate) operation. This is
accomplished by adding six “dummy” clocks after the 24/32-bit address as shown in Figure
42-Figure 43. The dummy clocks allow the devices internal circuits additional time for setting up
the initial address. During the dummy clocks the data value on the SO pin is a “don’t care”.
Figure 42. DTR Fast Read (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
9
8
19
18
SCLK Mode 0
Instruction
24-Bit Address
23 22
0DH
SI
High_Z
21 20
2
3
1
0
MSB
SO
/CS
20 21 22 23 24
27
26
25
29
28
31
30
SCLK
6 Dummy Clocks
High_Z
SI
Data Out 1
High_Z
SO
7 6
MSB
5
4
3
2
1
Data Out 2
6
5 4
7
0
MSB
Figure 43. DTR Fast Read (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
8
9
31 30
MSB
29 28
7
23
21
SCLK Mode 0
Instruction
32-Bit Address
0DH
SI
High_Z
2
3
1
0
SO
/CS
24 25 26 27 28
30
29
31
33
32
34
35
SCLK
6 Dummy Clocks
High_Z
SI
SO
High_Z
Data Out 1
7
6
5
4
3
2
1
0
7
Data Out 2
6
5 4
MSB
MSB
DTR Fast Read (0Dh) in QPI Mode
The DTR Fast Read instruction is also supported in QPI mode.
December 2020
Rev 1.9
59 / 171
Instructions Description
BY25Q256FS
Figure 44. DTR Fast Read (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
7
11
13
12
Mode 0
Instruction
0DH
A23-16
A15-8
A7-0
Data Out 1 Data Out 2
8 Dummy Clocks
SI
(IO0)
20
16
12
8
4
0
4
0
4
SO
(IO1)
21
17
13
9
5
1
5
1
5
/WP
(IO2)
22
18
14
10
6
2
6
2
6
23 19
MSB
15
11
7
3
/HOLD
(IO3)
3
7
MSB
7
MSB
Figure 45. DTR Fast Read (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
7
12
14
13
Mode 0
Instruction
0DH
A31-24
A23-16
A15-8
A7-0
8 Dummy Clocks
Data Out 1 Data Out 2
SI
(IO0)
28
24
20
16
12
8
4
0
4
0
4
SO
(IO1)
29
25
21
17
13
1
5
1
5
1
5
/WP
(IO2)
30
26
22
18
14
10
6
2
6
2
6
/HOLD
(IO3)
31
MSB
27
23
19
15
11
7
3
December 2020
Rev 1.9
3
7
MSB
7
MSB
60 / 171
Instructions Description
BY25Q256FS
7.2.5 Fast Read with 4-Byte Address (0CH)
The Fast Read with 4-Byte Address (0Ch) instruction is similar to the Fast Read instruction except
that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte
Address Mode or 4-byte Address Mode, the Read Data with 4-Byte Address instruction will always
require 32-bit address to access the entire 256Mb memory.
The Fast Read with 4-Byte Address instruction is only supported in Standard SPI mode. In QPI
mode, the instruction code 0Ch is used for the “Burst Read with Wrap” instruction.
Figure 46. Fast Read with 4-Byte Address
/CS
Mode 3
0
1
2
3
4
5
6
7
9
8
36 37 38
10
39
SCLK Mode 0
Instruction
32-Bit Address
31 30
0CH
SI
29
3
2
1
0
MSB
High_Z
SO
/CS
40 41 42 43 44
45 46 47 48 49 50 51 52
53 54 55
56 57
SCLK
Dummy Clocks
High_Z
SI
SO
High_Z
7
MSB
December 2020
Data Out 2
Data Out 1
6
Rev 1.9
5
4
3
2
1
0
6
7
MSB
61 / 171
Instructions Description
BY25Q256FS
7.2.6 Dual Output Fast Read (3BH)
See Figure 47-Figure 48, the Dual Output Fast Read instruction is followed by 3/4-byte address
(A23/31-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the
memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can
be at any location. The address is automatically incremented to the next higher address after each
byte of data is shifted out.
Figure 47. Dual Output Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
0
1
2
3
4
5
6
7
9
8
28
10
29
30
31
SCLK
Instruction
24-Bit Address
3BH
SI
SO
23
22
21
41
42
43
3
2
1
0
High_Z
/CS
32
33
34
35
36
37
38
39
40
44
45
46
47
0
6
4
2
0
1
7
SCLK
Dummy Clocks
SI
6
2
4
Data Byte 2
Data Byte 1
High_Z
SO
5
7
High_Z
3
5
High_Z
1
3
Figure 48. Dual Output Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
9
8
36
10
37
39
38
SCLK Mode 0
Instruction
32-Bit Address
3BH
SI
SO
31 30
MSB
19
50
51
3
2
54
55
1
0
High_Z
/CS
40
41
42
43
44
45
46
47
48
49
52
53
SCLK
SI
SO
December 2020
Dummy Clocks
High_Z
Data Out 1
Data Out 2
4
2
0
6
4
2
0
5
7
MSB
3
1
7
MSB
5
3
1
6
Rev 1.9
62 / 171
Instructions Description
BY25Q256FS
7.2.7 Fast Read Dual Output with 4-Byte Address (3CH)
The Fast Read Dual Output with 4-Byte Address instruction is similar to the Fast Read Dual Output
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is
operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Dual Output with 4-Byte
Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Dual Output with 4-Byte Address (3Ch) instruction is only supported in Standard
SPI mode.
Figure 49. Fast Read Dual Output with 4-Byte Address
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
8
7
37
9
38
39
Mode 0
Instruction
SI
32-Bit Address
31
3CH
MSB
SO
2
30
1
0
MSB
High_Z
/CS
40
SCLK
Dummy Clocks
Data Out 2
SI
6
Data Out 1
4
2
0
6
4
2
0
SO
7
5
1
7
5
3
1
MSB
December 2020
3
MSB
Rev 1.9
63 / 171
Instructions Description
BY25Q256FS
7.2.8 Quad Output Fast Read (6BH)
See Figure 50-Figure 51, the Quad Output Fast Read instruction is followed by 3/4-byte address
(A23/31-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the
memory contents are shifted out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte
addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register must be
set to enable.
Figure 50. Quad Output Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
7
8
9
28
10
29
30
31
Mode 0
24-Bit Address
Instruction
SI
(IO0)
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
/CS
32
33
34
35
36
37
38
39
40
41
3
2
1
45
46
47
21
23 22
MSB
6BH
42
43
44
0
SCLK
SI
(IO0)
Dummy Clocks
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
MSB
December 2020
Rev 1.9
MSB
MSB
64 / 171
Instructions Description
BY25Q256FS
Figure 51. Quad Output Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
8
7
9
36
10
37
38
39
Mode 0
32-Bit Address
Instruction
SI
(IO0)
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
/CS
40
41
42
43
44
45
46
47
48
49
3
2
1
53
54
55
29
31 30
MSB
6BH
50
51
52
0
SCLK
SI
(IO0)
Dummy Clocks
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
MSB
December 2020
Rev 1.9
MSB
MSB
65 / 171
Instructions Description
BY25Q256FS
7.2.9 Fast Read Quad Output with 4-Byte Address (6CH)
The Fast Read Quad Output with 4-Byte Address instruction is similar to the Fast Read Quad
Output instruction except that it requires 32-bit address instead of 24-bit address. No matter the
device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Quad Output
with 4-Byte Address instruction will always require 32-bit address to access the entire 256Mb
memory.
The Fast Read Quad Output with 4-Byte Address (6Ch) instruction is only supported in Standard
SPI mode.
Figure 52. Fast Read Quad Output with 4-Byte Address
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
8
7
9
37
38
39
32-Bit Address
Instruction
SI
(IO0)
SO
(IO1)
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
40
41
42
43
44
45
46
47
48
49
3
2
1
53
54
55
29
31 30
MSB
6CH
High_Z
/CS
36
10
Mode 0
50
51
52
0
SCLK
SI
(IO0)
Dummy Clocks
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
MSB
December 2020
Rev 1.9
MSB
MSB
66 / 171
Instructions Description
BY25Q256FS
7.2.10 Dual I/O Fast Read (BBH)
See Figure 53-Figure 56, the Dual I/O Fast Read instruction is similar to the Dual Output Fast
Read instruction but with the capability to input the 3/4-byte address (A23/31-0) and a “Continuous
Read Mode” byte 2-bit per clock by SI and SO, each bit being latched in during the rising edge of
SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte
addressed can be at any location. The address is automatically incremented to the next higher
address after each byte of data is shifted out.
Dual I/O Fast Read with “continuous Read Mode”
The Dual I/O Fast Read instruction can further reduce instruction overhead through setting the
“continuous Read Mode” bits (M7-4) after the inputs 3-byte address A23-A0).If the “continuous
Read Mode” bits(M5-4)=(1,0),then the next Dual I/O fast Read instruction (after CS/ is raised and
then lowered) does not require the BBH instruction code. The instruction sequence is shown in the
following Figure 53-Figure 56.If the “continuous Read Mode” bits (M5-4) does not equal (1,0), the
next instruction requires the first BBH instruction code, thus returning to normal operation. A
“continuous Read Mode” Reset instruction can be used to reset (M5-4) before issuing normal
instruction.
Figure 53. Dual I/O Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode ; Initial
instruction or previous (M5-4)≠(1,0))
/CS
0
1
2
3
4
5
6
7
9
8
10 11 12
13 14 15 16 17 18 19 20 21 22 23
SCLK
Instruction
SI
(IO0)
BBH
SO
(IO1)
High_Z
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
A23-16
A15-8
A7-0
M7-0
/CS
SCLK
23 24 25 26
27 28 29 30
31 32 33
34 35 36 37 38 39
SI
(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SO
(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
3
5
Byte 4
1
Byte 1
December 2020
Byte 2
Byte 3
Rev 1.9
High_Z
High_Z
67 / 171
Instructions Description
BY25Q256FS
Figure 54. Dual I/O Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode; Initial
instruction or previous (M5-4)≠(1,0))
/CS
Mode 3
SCLK Mode 0
0
2
1
4
3
5
6
7
Instruction
SI
(IO0)
BBH
SO
(IO1)
High_Z
10 11 12
9
8
A31-24
30 28
31 29
MSB
13 14 15 16 17 18 19 20 21 22 23
A7-0
A15-8
A23-16
26 24 22
20 18 16 14 12 10
8
6
4
2
0
27
21 19 17 15
11
9
7
5
3
1
25 23
13
/CS
SCLK
SI
(IO0)
SO
(IO1)
23 24 25 26
27 28 29 30
Data Out 1
M7-0
6
31 32 33
4
2
0
7 5
MSB
3
1
34 35 36 37 38 39
Data Out 2
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
7 5
MSB
MSB
MSB
Data Out 3
0
4 2
3
1
Figure 55. Dual I/O Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode ;
Previous instruction set (M5-4) =(1,0))
/CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
(IO0)
6
SO
(IO1)
7
/CS
0
6
4
0
6
4
2
0
6
4
2
0
5 3 1
A23-16
7
5 3 1
A15-8
7
5 3
A7-0
1
7
5 3
M7-0
1
4
2
2
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
(IO0)
6
4
2
0
6
4
0
6
4
2
0
6
SO
(IO1)
7
5 3
Byte1
1
7
5 3 1
Byte2
7
5 3
Byte3
1
7
December 2020
2
Rev 1.9
2
0
5 3
Byte4
1
4
68 / 171
Instructions Description
BY25Q256FS
Figure 56. Dual I/O Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode ;
Previous instruction set (M5-4) =(1,0))
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
30 28
SO High_Z
(IO1)
31
6
7
8
A23-16
A31-24
SI High_Z
(IO0)
5
10 11 12
9
23 21
29 27 25
A7-0
A15-8
26 24 22 20 18 16 14 12 10
19 17 15 13
11
13 14 15
8
6
4
2
0
9
7
5
3
1
MSB
/CS
SCLK
15 16 17 18
SI
(IO0)
SO
(IO1)
December 2020
19 20 21 22
23 24 25
Data Out 1
M7-0
Data Out 2
4
2
0
6
4
2
0
7 5
MSB
3
1
7
5
3
1
6
MSB
26 27 28 29 30 31
Data Out 3
6
4
2
0
7
5
3
1
MSB
Rev 1.9
4
2
0
7 5
MSB
3
1
6
69 / 171
Instructions Description
BY25Q256FS
7.2.11 DTR Fast Read Dual I/O (BDH)
The DTR Fast Read Dual I/O (BDh) instruction allows for improved random access while
maintaining two IO pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but
with the capability to input the Address bits (A23/A31-0) two bits per clock.
DTR Fast Read Dual I/O with “Continuous Read Mode”
The DTR Fast Read Dual I/O instruction can further reduce instruction overhead through setti ng the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23/31-0), as shown in Figure
57-Figure 60. The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O
instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits
of the (M3-0) are don’t care (“x”). However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after
/CS is raised and then lowered) does not require the BDh instruction code, as shown in Figure
59-Figure 60. This reduces the instruction sequence by eight clocks and allows the Read address
to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation.
Figure 57. DTR Fast Read Dual I/O (SPI Mode only/3-Byte Address Mode ; Initial instruction
or previous M5-410)
/CS
Mode 3
SCLK Mode 0
0
1
2
3
4
5
6
8
7
Instruction
SI
(IO0)
BDH
SO
(IO1)
High_Z
9
10
A23-16
22 20
23
12
11
A15-8
18 16 14
21 19 17 15
14
13
A7-0
M7-0
12 10
8
6
4
2
0
13
9
7
5
3
1
11
15
4
2
0
7 5
MSB
3
1
6
MSB
/CS
SCLK
15
16
17
18
19
20
0
SO
(IO1)
1
December 2020
22
Data Out 1
Dummy Clocks
SI
(IO0)
21
6
23
Data Out 2
4
2
0
7 5
MSB
3
1
4
2
0
7
5
3
1
Rev 1.9
26
Data Out 3
6
MSB
25
24
Data Out 4
6
4
2
0
7
5
3
1
MSB
27
4
2
0
7 5
MSB
3
1
6
70 / 171
Instructions Description
BY25Q256FS
Figure 58. DTR Fast Read Dual I/O (SPI Mode only/4-Byte Address Mode ; Initial instruction
or previous M5-410)
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
5
6
8
7
Instruction
SI
(IO0)
BDH
SO
(IO1)
High_Z
9
10
A31-24
30 28
26
31 29 27
12
11
14
13
A15-8
A23-16
A7-0
14 12 10
8
25 23 21 19 17 15 13 11
9
24 22 20 18 16
15
4
2
0
7 5
MSB
3
1
6
MSB
/CS
SCLK
15
16
18
17
19
M7-0
20
21
22
0
6
4
2
0
SO
(IO1)
1
7
5
3
1
26
Data Out 2
6
4
2
0
7
5
3
1
27
Data Out 3
6
4
2
0
7
5
3
1
MSB
MSB
MSB
25
24
Data Out 1
Dummy Clocks
SI
(IO0)
23
4
2
0
7 5
MSB
3
1
6
Figure 59. DTR Fast Read Dual I/O (SPI Mode only/3-Byte Address Mode ; Previous
instruction set M5-4=10)
/CS
Mode 3
SCLK Mode 0
0
1
2
A23-16
A15-8
High_Z
SI
22 20 18 16 14 12 10
(IO0)
SO
(IO1)
4
3
5
6
8
6
4
A7-0
2
0
9
7
5
1
7
6
M7-0
4 2
0
7
5
1
High_Z
23 21 19 17
15 13
11
3
MSB
3
MSB
/CS
7
SCLK
9
10
11
12
0
SO
(IO1)
1
13
14
Data Out 1
Dummy Clocks
SI
(IO0)
December 2020
8
Data Out 2
4
2
0
6
4
2
0
7 5
MSB
3
1
7
5
3
1
6
Rev 1.9
15
MSB
71 / 171
Instructions Description
BY25Q256FS
Figure 60. DTR Fast Read Dual I/O (SPI Mode only/4-Byte Address Mode ; Previous
instruction set M5-4=10)
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
A31-24
A23-16
High_Z
SI
30 28 26 24 22 20 18 16
(IO0)
SO
(IO1)
High_Z
31 29 27 25
5
6
A15-8
8
7
A7-0
9
M7-0
14 12 10
8
6
4
2
0
23 21 19 17 15 13 11
9
7
5
3
1
4
2
0
7 5
MSB
3
1
6
MSB
/CS
9
SCLK
10
11
12
13
14
0
SO
(IO1)
1
December 2020
16
17
2
0
6
4
2
0
7 5
MSB
3
1
7
5
3
1
Rev 1.9
MSB
19
Data Out 3
4
6
18
Data Out 2
Data Out 1
Dummy Clocks
SI
(IO0)
15
4
2
0
7 5
MSB
3
1
6
72 / 171
Instructions Description
BY25Q256FS
7.2.12 Fast Read Dual I/O with 4-Byte Address (BCH)
The Fast Read Dual I/O with 4-Byte Address instruction is similar to the Fast Read Dual I/O
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is
operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Dual I/O with 4-Byte
Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Fast Read Dual I/O with 4-Byte Address (BCh) instruction is only supported in Standard SPI
mode.
Figure 61. Fast Read Dual I/O with 4-Byte Address(SPI Mode only; Initial instruction or
previous M5-410)
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
5
6
7
Instruction
SI
(IO0)
BCH
SO
(IO1)
High_Z
10 11 12
9
8
A31-24
13 14 15 16 17 18 19 20 21 22 23
26
31 29
27 25 23
24 22 20
14 12 10
8
6
4
2
0
17 15 13 11
9
7
5
3
1
18 16
21 19
A7-0
A15-8
A23-16
30 28
MSB
/CS
SCLK
SI
(IO0)
SO
(IO1)
23 24 25 26
27 28 29 30
4
2
0
7 5
MSB
3
1
December 2020
6
4
2
0
7
5
3
1
MSB
34 35 36 37 38 39
Data Out 2
Data Out 1
M7-0
6
31 32 33
Data Out 3
6
4
2
0
7
5
3
1
MSB
4
2
0
7 5
MSB
3
1
6
Rev 1.9
73 / 171
Instructions Description
BY25Q256FS
Figure 62. Fast Read Dual I/O with 4-Byte Address(SPI Mode only; Initial instruction or
previous M5-4=10)
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
30 28
SO High_Z
(IO1)
31
6
7
8
A23-16
A31-24
SI High_Z
(IO0)
5
26 24 22 20
29 27 25
23 21
10 11 12
9
13 14 15
A7-0
A15-8
18 16 14 12 10
8
6
4
2
0
19 17 15 13
9
7
5
3
1
11
MSB
/CS
SCLK
15 16 17 18
SI
(IO0)
SO
(IO1)
December 2020
19 20 21 22
23 24 25
Data Out 1
M7-0
Data Out 2
4
2
0
6
4
2
0
7 5
MSB
3
1
7
5
3
1
6
MSB
26 27 28 29 30 31
6
4
2
0
7
5
3
1
MSB
Rev 1.9
Data Out 2
6
4 2
7 5
MSB
3
0
1
74 / 171
Instructions Description
BY25Q256FS
7.2.13 Quad I/O Fast Read (EBH)
See Figure 63-Figure 66, the Quad I/O Fast Read instruction is similar to the Dual I/O Fast Read
instruction but with the capability to input the 3/4-byte address (A23/31-0) and a “Continuous Read
Mode” byte and 4-dummy clock 4-bit per clock by IO0, IO1, IO3, IO4, each bit being latched in
during the rising edge of SCLK, then the memory contents are shifted o ut 4-bit per clock cycle
from IO0, IO1, IO2, IO3. The first byte addressed can be at any location. The address is
automatically incremented to the next higher address after each byte of data is shifted out. The
Quad Enable bit (QE) of Status Register must be set to enable for the Quad I/O Fast read
instruction, as shown in Figure 63-Figure 70.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), If the “Continuous Read
Mode” bits (M5-4 )= (1,0), then the next Fast Read Quad I/O instruction(after /CS is raised and
then lowered) does not require the EBH instruction code. If the “Continuous Read Mode” bits M5-4
do not equal to (1,0), the next instruction requires the first EBH instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M5-4)
before issuing normal instruction.
Figure 63. Quad I/O Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode; Initial
instruction or previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
7
9
8
10
11
12
13
14
15
Mode 0
Instruction
SI
(IO0)
EBH
High_Z
SO
(IO1)
A23-16
A15-8
20
16
12
8
A7-0
4
0
21
17
13
9
5
1
5
1
22
18
14
10
6
2
6
2
23 19
MSB
15
11
7
3
7
3
M7-0
4
0
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
MSB
/CS
16
17
18
19
20
21
22
23
24
25
26
27
SCLK
Dummy Clocks
SI
(IO0)
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
High_Z
MSB
December 2020
MSB
Rev 1.9
MSB
75 / 171
Instructions Description
BY25Q256FS
Figure 64. Quad I/O Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode; Initial
instruction or previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
3
2
1
4
6
5
7
9
8
10
12
11
14
13
15
16
17
Mode 0
Instruction
SI
(IO0)
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
1
30
26
22
18
14
10
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
MSB
3
EBH
High_Z
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
M7-0
4
0
/CS
18
19
20
21
22
23
25
24
26
27
28
29
SCLK
Dummy Clocks
Data Out 1 Data Out 2 Data Out 2 Data Out 4
4
0
0
4
0
4
0
4
SI
(IO0)
SO
(IO1)
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
/HOLD
(IO3)
MSB
MSB
MSB
Figure 65. Quad I/O Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode; Initial
instruction or previous (M5-4=(1,0)))
/CS
0
SCLK
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
1
3
4
6
5
7
8
9
10 11 12 13 14 15
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7 3
Byte1
A23-16
December 2020
2
A15-8
A7-0
M7-0
Rev 1.9
Dummy
7 3
Byte2
76 / 171
Instructions Description
BY25Q256FS
Figure 66. Quad I/O Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode; Initial
instruction or previous (M5-4=(1,0)))
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
10
11
12
13
14
15
16
17
19
20
21
22
Mode 0
SI
(IO0)
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
Dummy Clocks
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
4
4
4
0
0
0
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
30
26
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
MSB
3
7
3
7
3
7
3
7
MSB
3
M7-0
4
0
MSB
MSB
MSB
Quad I/O Fast Read with “8/16/32/64-Byte Wrap Around”
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77H) instruction prior to EBH. The “Set Burst with Wrap” (77H)
instruction can either enable or disable the “Wrap Around” feature for the following EBH
instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an
8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address
specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 -byte section,
the output will wrap around to the beginning boundary automatically u ntil /CS is pulled high to
terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64 -byte) of data without issuing
multiple read instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the
wrap around section within a page.
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 67-Figure
70. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read
Parameters (C0h)” instruction to accommodate a wide range of applications with d ifferent needs
for either maximum Fast Read frequency or minimum data access latency. Depending on the
Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 4, 4,
6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 4. In QPI
mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default
setting, the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction.
Please refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform
a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with
Wrap” (0Ch) instruction must be used.
December 2020
Rev 1.9
77 / 171
Instructions Description
BY25Q256FS
Figure 67. Quad I/O Fast Read Sequence Diagram (QPI Mode/3-Byte Address Mode ; Initial
instruction or previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
3
2
1
4
6
5
7
9
8
10
11
12
13
15
14
16
17
Mode 0
Instruction
A23-16
EBH
M7-0 * Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
4
0
0
4
4
0
0
0
4
A7-0
4
0
SI
(IO0)
SO
(IO1)
20
16
A15-8
12
8
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
23 19
MSB
15
11
7
3
7
MSB
3
7
MSB
3
7
3
7
3
7
3
/HOLD
(IO3)
MSB
MSB
MSB
* = “Set Read Parameters”Instruction (C0H) can set
the number of dummy clocks
Figure 68. Quad I/O Fast Read Sequence Diagram (QPI Mode/4-Byte Address Mode ; Initial
instruction or previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
1
3
2
4
6
5
7
9
8
10
11
12
13
15
14
17
16
19
20
Mode 0
Instruction
EBH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
A31-24
A23-16
A15-8
A7-0
M7-0 *
Data Out 1 Data Out 2 Data Out 3 Data Out 4
28
24
20
16
12
8
4
0
4
0
4
0
4
0
4
0
4
0
29
25
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
30
26
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
3
7
3
7
3
7
3
7
MSB
3
MSB
MSB
MSB
MSB
* = “Set Read Parameters”Instruction (C0H) can set
the number of dummy clocks
Figure 69. Quad I/O Fast Read Sequence Diagram (QPI Mode/3-Byte Address Mode; Initial
instruction or previous (M5-4=(1,0)))
/CS
0
SCLK
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
1
3
4
6
5
7
8
9
10 11 12 13 14 15
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7 3
Byte1
A23-16
December 2020
2
A15-8
A7-0
M7-0
Rev 1.9
Dummy
7 3
Byte2
78 / 171
Instructions Description
BY25Q256FS
Figure 70. Quad I/O Fast Read Sequence Diagram (QPI Mode/4-Byte Address Mode; Initial
instruction or previous (M5-4=(1,0)))
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
10
11
12
13
14
15
16
17
19
20
21
22
Mode 0
SI
(IO0)
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
Dummy Clocks
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
4
4
4
0
0
0
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
30
26
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
MSB
3
7
3
7
3
7
3
7
MSB
3
December 2020
M7-0
4
0
MSB
Rev 1.9
MSB
MSB
79 / 171
Instructions Description
BY25Q256FS
7.2.14 DTR Fast Read Quad I/O(EDH)
The DTR Fast Read Quad I/O (EDh) instruction is similar to the Fast Read Dual I/O (BBh) instruction
except that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four
Dummy clocks are required in SPI mode prior to the data output, as shown in Figure 71-Figure 78.
The Quad Enable bit (QE) of Status Register must be set to enable .
DTR Fast Read Quad I/O with “Continuous Read Mode ”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23/A31-0). The upper nibble of the
(M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion
of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO
pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EDh instruction code. This reduces the instruction
sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted
low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after /CS is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
Figure 71. DTR Fast Read Quad I/O (SPI Mode/3-Byte Address Mode; Initial instruction or
previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK Mode 0
0
1
2
4
3
5
6
7
10
9
8
12 13
11
17 18
19
21
20
Instruction
A23-16
A15-8
A7-0
M7-0
SI
(IO0)
EDH
20 16
12
8
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
High_Z
21 17 13
9
5
1
5
1
5
1
5
1
5
1
22 18 14 10
6
2
6
2
6
2
6
2
6
2
23 19 15
MSB
7
3
7 Dummy Clocks
Data Out 1 Data Out 2 Data Out 3
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
11
7 3
MSB
7
3
MSB
7
3
MSB
3
7
MSB
Figure 72. DTR Fast Read Quad I/O (SPI Mode/4-Byte Address Mode; Initial instruction or
previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK Mode 0
0
1
2
3
4
Instruction
SI
(IO0)
EDH
SO
(IO1)
High_Z
/WP
(IO2)
/HOLD
(IO3)
December 2020
5
6
7
8
10
9
11
12
13 14
18
19
20
21
22
A31-24 A23-16
A15-8
A7-0
28 24
12
8
4
0
4
0
29 25 21 17 13
9
5
1
5
1
5
1
5
1
5
1
30 26 22 18 14
10
6
2
6
2
6
2
6
2
6
2
31 27 23 19 15
MSB
11
7
3
20 16
M7-0
7 Dummy Clocks
Data Out 1 Data Out 2 Data Out 3
0
4
4
0
0
4
High_Z
High_Z
Rev 1.9
7 3
MSB
7
3
MSB
7
3
MSB
3
7
MSB
80 / 171
Instructions Description
BY25Q256FS
Figure 73. DTR Fast Read Quad I/O (SPI Mode/3-Byte Address Mode; Initial instruction or
previous (M5-4=(1,0)))
/CS
SCLK
Mode 3
Mode 0
SI
(IO0)
High_Z A23-16 A15-8
20 16 12 8
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
1
0
2
3
A7-0
4
0
4
0
10
7 Dummy Clocks
M7-0
4
9
5
11
12
13
Data Out 1 Data Out 2 Data Out 3
0
4
4
0
0
4
17 13
9
5
1
5
1
5
1
5
1
5
1
22 18 14
10
6
2
6
2
6
2
6
2
6
2
23 19 15 11
MSB
7
3
21
7 3
MSB
3
7
MSB
7
3
MSB
7
3
MSB
Figure 74. DTR Fast Read Quad I/O (SPI Mode/4-Byte Address Mode; Initial instruction or
previous (M5-4=(1,0)))
/CS
SCLK
Mode 3
Mode 0
SI
(IO0)
High_Z A31-24 A23-16
28 24 20 16
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
0
2
1
3
4
5
6
10
7 Dummy Clocks
11
12
13
14
A15-8
A7-0
12
8
4
0
4
0
17 13
9
5
1
5
1
5
1
5
1
5
1
14 10
6
2
6
2
6
2
6
2
6
2
31 27 23 19 15 11
MSB
7
3
29 25 21
30 26 22 18
M7-0
7 3
MSB
Data Out 1 Data Out 2 Data Out 3
0
4
4
0
0
4
7
3
MSB
7
3
MSB
3
7
MSB
DTR Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) instruction prior to EDh. The “Set Burst with Wrap” (77h) instruction
can either enable or disable the “Wrap Around” feature for the following EDh instructions. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches
the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning
boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page.
DTR Fast Read Quad I/O (EDh) in QPI Mode
December 2020
Rev 1.9
81 / 171
Instructions Description
BY25Q256FS
The DTR Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 75-Figure
78. In QPI mode, the “Continuous Read Mode” can further reduce instruction overhead through setting
the “Continuous Read Mode” bits (M7-0) after the input Address bits (A23/31-0). Please refer to the
description on previous pages. If the “Continuous Read Mode” bits (M5-4 )= (1,0), then the next Fast
Read Quad I/O instruction(after /CS is raised and then lowered) does not require the EDH instruction
code, The instruction sequence is shown in the followed Figure. If the “Continuous Read Mode” bits
M5-4 do not equal to (1,0), the next instruction requires the first EDH instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M5-4) before
issuing normal instruction.
Figure 75. DTR Fast Read Quad I/O (QPI Mode/3-Byte Address Mode; Initial instruction or
previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
11
7
13
12
Mode 0
Instruction
EDH
A23-16
A15-8
M7-0
A7-0
Data Out 1 Data Out 2
7 Dummy Clocks
SI
(IO0)
20
16
12
8
4
0
4
0
4
0
4
SO
(IO1)
21
17
13
9
5
1
5
1
5
1
5
/WP
(IO2)
22
18
14
10
6
2
6
2
6
2
6
23 19
MSB
15
11
7
3
/HOLD
(IO3)
7
3
MSB
3
7
MSB
7
MSB
Figure 76. DTR Fast Read Quad I/O (QPI Mode/4-Byte Address Mode; Initial instruction or
previous (M5-4≠(1,0)))
/CS
Mode 3
SCLK
0
1
2
3
4
5
7
6
8
12
13
14
Mode 0
Instruction
A23-16
A15-8
A7-0
SI
(IO0)
28
24
20
16
12
8
4
0
4
0
4
0
4
SO
(IO1)
29
25
21
17
13
9
5
1
5
1
5
1
5
/WP
(IO2)
30
26
22
18
14
10
6
2
6
2
6
2
6
31 27
MSB
23
19
15
11
7
3
EDH
/HOLD
(IO3)
December 2020
A31-24
M7-0
7
3
MSB
Rev 1.9
7 Dummy Clocks
Data Out 1 Data Out 2
3
7
MSB
7
MSB
82 / 171
Instructions Description
BY25Q256FS
Figure 77. DTR Fast Read Quad I/O (QPI Mode/3-Byte Address Mode; Initial instruction or
previous (M5-4=(1,0)))
/CS
SCLK
Mode 3
Mode 0
SI
(IO0)
High_Z A23-16 A15-8
20 16 12 8
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
1
0
2
3
A7-0
4
0
4
0
10
7 Dummy Clocks
M7-0
4
9
5
11
12
13
Data Out 1 Data Out 2 Data Out 3
0
4
4
0
0
4
17 13
9
5
1
5
1
5
1
5
1
5
1
22 18 14
10
6
2
6
2
6
2
6
2
6
2
23 19 15 11
MSB
7
3
21
7 3
MSB
3
7
MSB
7
3
MSB
7
3
MSB
Figure 78. DTR Fast Read Quad I/O (QPI Mode/4-Byte Address Mode; Initial instruction or
previous (M5-4=(1,0)))
/CS
SCLK
Mode 3
Mode 0
SI
(IO0)
High_Z A31-24 A23-16
28 24 20 16
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
0
2
1
4
5
6
10
7 Dummy Clocks
11
12
13
14
A15-8
A7-0
12
8
4
0
4
0
17 13
9
5
1
5
1
5
1
5
1
5
1
14 10
6
2
6
2
6
2
6
2
6
2
31 27 23 19 15 11
MSB
7
3
29 25 21
30 26 22 18
December 2020
3
M7-0
7 3
MSB
Rev 1.9
Data Out 1 Data Out 2 Data Out 3
0
4
4
0
0
4
7
3
MSB
7
3
MSB
3
7
MSB
83 / 171
Instructions Description
BY25Q256FS
7.2.15 Fast Read Quad I/O with 4-Byte Address (ECH)
The Fast Read Quad I/O with 4-Byte Address instruction is similar to the Quad I/O Fast Read
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is
operating in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Quad I/O with
4-Byte Address instruction will always require 32-bit address to access the entire 256Mb memory.
The Quad Enable bit (QE) of Status Register must be set to enable .
Figure 79. Fast Read Quad I/O with 4-Byte Address (SPI Mode; Initial instruction or previous
M5-4≠10)
/CS
Mode 3
SCLK
0
3
2
1
4
6
5
7
9
8
10
11
12
13
14
15
16
17
Mode 0
Instruction
SI
(IO0)
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
1
30
26
22
18
14
10
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
3
ECH
High_Z
SO
(IO1)
M7-0
4
0
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
MSB
/CS
18
19
20
22
21
23
24
25
26
27
28
29
SCLK
Dummy Clocks
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
SI
(IO0)
SO
(IO1)
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
/HOLD
(IO3)
MSB
MSB
MSB
Figure 80. Fast Read Quad I/O with 4-Byte Address (SPI Mode; Initial instruction or previous
M5-4=10)
/CS
Mode 3
SCLK
Mode 0
SI
(IO0)
High_Z
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
0
1
2
3
4
5
6
7
9
8
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
M7-0
4
0
29
25
21
17
13
9
5
1
5
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
10
11
12
Dummy Clocks
13
14
15
16
17
19
20
21
22
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
4
0
4
0
4
0
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
7
MSB
3
7
3
7
3
7
3
7
MSB
3
MSB
MSB
MSB
Fast Read Quad I/O with 4-Byte Address with “8/16/32/64-Byte Wrap Around” in Standard
SPI mode
December 2020
Rev 1.9
84 / 171
Instructions Description
BY25Q256FS
The Fast Read Quad I/O with 4-Byte Address instruction can also be used to access a specific portion
within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to ECh. The “Set Burst with Wrap”
(77h) instruction can either enable or disable the “Wrap Around” feature for the following ECh instructions.
When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte
section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it
reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning
boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page.
Fast Read Quad I/O with 4-Byte Address (ECh) in QPI Mode
The Fast Read Quad I/O with 4-Byte Address instruction is also supported in QPI mode, as shown
in Figure 81-Figure 82. When QPI mode is enabled, the number of dummy clocks is configured
by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applications with
different needs for either maximum Fast Read frequency or minimum dat a access latency.
Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be
configured as either 4, 4, 6 or 8. The default number of dummy clocks upon power up or after a
Reset instruction is 4. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as
dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits
immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O with 4-Byte
Address instruction. Please refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O with 4-Byte Address
instruction. To perform a read operation with fixed data length wrap around in QPI mode, a
dedicated “Burst Read with Wrap” (0Ch) instruction must be used.
Figure 81. Fast Read Quad I/O with 4-Byte Address (QPI Mode; Initial instruction or
previous M5-4≠10)
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
7
8
9
Instruction
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
SI
(IO0)
10
11
12
13
14
15
16
17
18
19
20
22
21
23
Mode 0
ECh
/HOLD
(IO3)
Dummy Clocks*
Data Out 1 Data Out 2 Data Out 3 Data Out 4
M7-0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
MSB
3
MSB
MSB
MSB
3
7
MSB
* = “Set Read Parameters”Instruction (C0H) can set
the number of dummy clocks
December 2020
Rev 1.9
85 / 171
Instructions Description
BY25Q256FS
Figure 82. Fast Read Quad I/O with 4-Byte Address (QPI Mode; Initial instruction or
previous M5-4= 10)
/CS
Mode 3
SCLK
Mode 0
SI
(IO0)
High_Z
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
0
1
3
2
4
5
6
7
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
December 2020
9
8
M7-0
4
0
10
11
12
Dummy Clocks
13
14
15
16
17
19
20
21
22
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
4
0
4
0
4
0
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
7
MSB
3
7
3
7
3
7
3
7
MSB
3
MSB
Rev 1.9
MSB
MSB
86 / 171
Instructions Description
BY25Q256FS
7.2.16 DTR Quad I/O Fast Read with 4- Byte Address (EEH)
The DTR Quad I/O Fast Read with 4- Byte Address (EEh) instruction is similar to the Fast Read Dual I/O
(BBh) instruction except that address and data bits are input and output through four pins IO0, IO1, IO2
and IO3 and four Dummy clocks are required in SPI mode prior to the data output, as shown in Figure
83-Figure 86. The Quad Enable bit (QE) of Status Register must be set to enable .
DTR Fast Read Quad I/O with “Continuous Read Mode”
The DTR Quad I/O Fast Read with 4-Byte Address instruction can further reduce instruction overhead
through setting the “Continuous Read Mode” bits (M7-0) after the input Address bits (A31-0) The upper
nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the inclusion
or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”).
However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next DTR Quad I/O Fast Read with 4- Byte
Address instruction (after /CS is raised and then lowered) does not require the EEh instruction code, as
shown in Figure 84. This reduces the instruction sequence by eight clocks and allows the Read
address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4
do not equal to (1,0), the next instruction (after /CS is raised and then lowered) requires the first byte
instruction code, thus returning to normal operation.
Figure 83. DTR Quad I/O Fast Read with 4- Byte Address (SPI Mode; Initial instruction or
previous M5-4≠10)
/CS
0
1
2
3
4
5
6
10
9
8
7
13 19
12
11
20
21
SCLK
SI
(IO0)
Instruction
EEH
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
December 2020
4
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
6
2
3
7 3 7
A31-24 A23-16
Rev 1.9
7 3
A15-8
7 3
A7-0
7 3
M7-0
7 3
7
Dummy Byte1
7 3
Byte2
87 / 171
Instructions Description
BY25Q256FS
Figure 84. DTR Quad I/O Fast Read with 4- Byte Address (SPI Mode; Initial instruction or
previous M5-4= 10)
/CS
2
1
0
5
4
3
11
13
12
SCLK
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
/HOLD
(IO3)
3
7 3 7
A31-24 A23-16
7 3
A15-8
7 3
A7-0
7 3
M7-0
7 3
7
Dummy Byte1
7 3
Byte2
DTR Quad I/O Fast Read with 4- Byte Address with “8/16/32/64-Byte Wrap Around” in
Standard SPI mode
The DTR Quad I/O Fast Read with 4- Byte Address instruction can also be used to access a specific
portion within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to EEh. The “Set Burst
with Wrap” (77h) instruction can either enable or disable the “Wrap Around” feature for the following EEh
instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16,
32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the
instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap
around to the beginning boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and
then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page.
DTR Quad I/O Fast Read with 4- Byte Address (EEh) in QPI Mode
“Continuous Read Mode” feature is also available in QPI mode for DTR Quad I/O Fast Read with
4- Byte Address instruction.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a
read operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap”
(0Ch) instruction must be used.
December 2020
Rev 1.9
88 / 171
Instructions Description
BY25Q256FS
Figure 85. DTR Quad I/O Fast Read with 4- Byte Address (QPI Mode; Initial instruction or
previous M5-4≠10)
/CS
Mode 3
SCLK
0
2
3
4
5
A31-24
A23-16
A15-8
A7-0
1
12
6
13
14
15
Mode 0
Instruction
EEH
8 Dummy Clocks
Data Out 1 Data Out 2
4
4
0
0
SI
(IO0)
SO
(IO1)
28
24
20
16
12
8
4
0
29
25
21
17
13
9
5
1
5
1
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
3
7
3
/HOLD
(IO3)
MSB
MSB
Figure 86. DTR Quad I/O Fast Read with 4- Byte Address (QPI Mode; Initial instruction or
previous M5-4= 10)
/CS
2
1
0
5
4
3
11
13
12
SCLK
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
/HOLD
(IO3)
December 2020
3
7 3 7
A31-24 A23-16
7 3
A15-8
7 3
A7-0
Rev 1.9
7 3
M7-0
7 3
7
Dummy Byte1
7 3
Byte2
89 / 171
Instructions Description
BY25Q256FS
7.2.17 Quad I/O Word Fast Read (E7H)
The Quad I/O Word Fast Read instruction is similar to the Quad Fast Read instruction except that
the lowest address bit (A0) must equal 0 and 2-dummy clock. The instruction sequence is shown
in the followed Figure 87-Figure 90, the first byte addressed can be at any location. The address
is automatically incremented to the next higher address after each byte of data is shifted out. The
Quad Enable bit (QE) of Status Register (S9) must be set to enable for the Quad I/O Word Fast
Read instruction. The Quad Enable bit (QE) of Status Register must be set to enable.
Quad I/O Word Fast Read with “Continuous Read Mode”
The Quad I/O Word Fast Read instruction can further reduce instruction overhead through setting
the “Continuous Read Mode” bits (M7-0) after the input 3-byte Address bits (A23-0). If the
“Continuous Read Mode” bits (M5-4) = (1, 0), then the next Quad I/O Fast Read instruction (after
/CS is raised and then lowered) does not require the E7H instruction code, the instruction
sequence is shown in the followed Figure 89-Figure 90. If the “Continuous Read Mode” bits M5-4
do not equal to (1,0), the next instruction requires the first E7H instruction code, thus returning to
normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset (M5-4)
before issuing normal instruction.
Figure 87. Quad I/O Word Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode;
Initial instruction or previous (M5-4)≠(1,0))
/CS
0
1
2
3
4
6
5
10 11 12 13 14 15 16 17 18 19 20 21 22 23
9
8
7
SCLK
SI
(IO0)
Instruction
E7H
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
4
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7 3 7
3
A23-16 A15-8
7 3
A7-0
7 3
M7-M0 Dummy
7
3
Byte1
7 3
Byte3
7
3
Byte2
Figure 88. Quad I/O Word Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode;
Initial instruction or previous (M5-4)≠(1,0))
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
10
11
13
12
14
15
16
17
18
19
20
21
Mode 0
Instruction
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
E7H
High_Z
Dummy
Clocks
28
24
20
16
12
8
29
25
21
17
13
9
5
1
5
1
5
1
30
26
22
18
14
10
6
2
6
2
6
2
31
27
23
19
15
11
7
3
7
3
7
3
A23-16
M7-0
4
0
Data Out 1
4
0
High_Z
High_Z
MSB
December 2020
A15-8
A7-0
4
0
A31-24
MSB
Rev 1.9
MSB
90 / 171
Instructions Description
BY25Q256FS
Figure 89. Quad I/O Word Fast Read Sequence Diagram (SPI Mode/3-Byte Address Mode;
Initial instruction or previous (M5-4)=(1,0))
/CS
0
SCLK
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
1
2
3
4
6
5
8
7
10 11 12 13 14 15
9
4
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
A15-8
A23-16
A7-0
7 3
Dummy Byte1
M7-0
7 3
Byte3
7 3
Byte2
Figure 90. Quad I/O Word Fast Read Sequence Diagram (SPI Mode/4-Byte Address Mode;
Initial instruction or previous (M5-4)=(1,0))
/CS
Mode 3
SCLK
Mode 0
SI
(IO0)
High_Z
SO
(IO1)
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
High_Z
0
1
3
2
4
5
6
7
9
8
10
11
12
13
14
15
16
17
19
20
Dummy
Data Out 1 Data Out 2 Data Out 3 Data Out 4
Clocks
4
0
4
4
4
0
0
0
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
29
25
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
30
26
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
31 27
MSB
23
19
15
11
7
3
7
MSB
3
7
3
7
3
7
3
7
MSB
3
M7-0
4
0
MSB
MSB
MSB
Quad I/O Word Fast Read with “8/16/32/64-Byte Wrap Around” in standard SPI mode
The Quad I/O Fast Read instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77H) instruction prior to E7H. The “Set Burst with Wrap” (77H)
instruction can either enable or disable the “Wrap Around” feature for the following E7H
instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an
8, 16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address
specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section,
the output will wrap around to the beginning boundary automatically until /CS is pulled high to
terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64 -byte) of data without issuing
multiple read instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the
wrap around section within a page.
December 2020
Rev 1.9
91 / 171
Instructions Description
BY25Q256FS
7.2.18 Set Burst with Wrap (77H)
See Figure 91-Figure 92, The Set Burst with Wrap instruction is used in conjunction with “EBH”,
“EDH”, “ECH”, “EEH” and “E7H” instructions to access a fixed length of 8/16/32/64-byte section
within a 256-byte page, in standard SPI mode.
The Set Burst with Wrap instruction sequence:/CS goes low ->Send Set Burst with Wrap
instruction ->Send24 Dummy bits ->Send 8 bits” Wrap bits”->/CS goes high.
If W6-4 is set by a Set Burst with Wrap instruction, all the following “EBH”, “EDH”, “ECH”, “EEH”
and “E7H” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst
with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1.
W4 = 0
W4 =1 (DEFAULT)
W6 , W5
Wrap Around
Wrap Length
Wrap Around
Wrap Length
0
0
Yes
8-byte
No
N/A
0
1
Yes
16-byte
No
N/A
1
1
0
1
Yes
Yes
32-byte
64-byte
No
No
N/A
N/A
Figure 91. Set Burst with Wrap Sequence Diagram (SPI Mode only/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
3
2
1
4
5
6
7
9
8
10
12
11
14
13
15 Mode 3
Mode 0
Mode 0
Instruction
SI
(IO0)
X
X
X
X
X
X
W4
X
X
X
X
X
X
X
W5
X
X
X
X
X
X
X
W6
X
X
X
X
X
X
X
X
X
77H
High_Z
SO
(IO1)
High_Z
High_Z
High_Z
High_Z
/WP
(IO2)
High_Z
/HOLD
(IO3)
byte1
byte2
byte3
High_Z
byte4
Figure 92. Set Burst with Wrap Sequence Diagram (SPI Mode only/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
10
11
12
13
15
14
16
17 Mode 3
Mode 0
Mode 0
Instruction
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
77H
High_Z
X
X
X
X
X
X
x
x
W4
X
X
X
X
X
X
X
x
x
W5
X
X
X
X
X
X
X
x
x
W6
X
X
X
byte1
X
X
X
X
X
x
X
X
High_Z
High_Z
High_Z
High_Z
High_Z
Rev 1.9
byte2
byte3
byte4
High_Z
byte5
92 / 171
Instructions Description
BY25Q256FS
7.2.19 Set Read Parameters (C0H)
In QPI mode, to accommodate a wide range of applications with different needs for either
maximum read frequency or minimum data access latency, “Set Read Parameters (C0h)”
instruction can be used to configure the number of dummy clocks for “0BH”, “EBH”, “ECH”, “0CH”,
“4BH”, “48H”, “5AH” and “E2H” instructions, as shown in Table 19, and to configure the number of
bytes of “Wrap Length” for the “0CH” and “0EH” instruction.
Table 19. Instructions that configurable dummy number
Mode
Instruction
Fast Read
Fast Read Quad I/O
Fast Read Quad I/O with 4-Byte Address
Burst Read with Wrap
Read Unique ID Number
Read Security Registers
Read Serial Flash Discoverable Parameter
Read SPB Status
QPI
0Bh
EBh
ECh
0Ch
4Bh
48h
5Ah
E2h
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy
clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer
to the Instruction Table 17 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with
Wrap (77h)” instruction. This setting will remain unchanged when the device is switched from
Standard SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 4. The number of dummy clocks is only programmable for “0BH”, “EBH”, “ECH”,
“0CH”, “4BH”, “48H”, “5AH” and “E2H”instructions in the QPI mode. Whenever the device is
switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to
any “0BH”, “EBH”, “ECH”, “0CH”, “4BH”, “48H”, “5AH” and “E2H” instructions.
P5 – P4
DUMMY
CLOCKS
MAXIMUM
READ
FREQ.
MAXIMUM
READ FREQ.
(A[1:0]=0,0
VCC=2.7V~2.9V)
MAXIMUM
READ
FREQ.
(A[1:0]=0,0
VCC=3.0V~3.6V)
P1 – P0
WRAP
LENGTH
0
0
4
55MHz
80MHz
80MHz
0
0
8-byte
0
1
4
55MHz
80MHz
80MHz
0
1
16-byte
1
0
6
80MHz
80MHz
100MHz
1
0
32-byte
1
1
8
80MHz
80MHz
100MHz
1
1
64-byte
December 2020
Rev 1.9
93 / 171
Instructions Description
BY25Q256FS
Figure 93. Burst Read with Wrap (QPI Mode only)
/CS
Mode 3
SCLK
0
1
2
3
Mode 3
Mode 0
Mode 0
Instruction
COH
SI
(IO0)
Read
Paramters
P4
P0
SO
(IO1)
P5
P1
/WP
(IO2)
P6
P2
/HOLD
(IO3)
P7
MSB
P3
7.2.20 Burst Read with Wrap (0CH)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read
operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)”
instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the
beginning boundary of the “Wrap Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read
Parameters (C0h)” instruction
Figure 94. Burst Read with Wrap (QPI Mode only/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mode 0
Instruction
A23-16
0CH
SI
(IO0)
A15-8
A7-0
IOs switch from
Input to Output
Dummy*
4
0
4
0
4
0
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
/HOLD
(IO3)
7
MSB
3
7
MSB
3
7
MSB
3
7
3
MSB
Byte1
3
7
7
MSB
MSB
Byte3
Byte2
*”Set Read Paraments” instruction(C0h)can
set the number of dummy clocks.
December 2020
Rev 1.9
94 / 171
Instructions Description
BY25Q256FS
Figure 95. Burst Read with Wrap (QPI Mode only/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mode 0
Instruction
A31-24
A23-16
0CH
SI
(IO0)
A15-8
IOs switch from
Input to Output
Dummy*
A7-0
4
0
4
0
4
0
4
0
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
/HOLD
(IO3)
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
*”Set Read Paraments” instruction(C0h)can
set the number of dummy clocks.
December 2020
Rev 1.9
7
3
MSB
Byte1
3
7
MSB
Byte2
7
MSB
Byte3
95 / 171
Instructions Description
BY25Q256FS
7.2.21 DTR Burst Read with Wrap (0EH)
The “DTR Burst Read with Wrap (0Eh)” instruction provides an alternative way to perform the read
operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)”
instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the
beginning boundary of the “Wrap Length” once the ending boundary is reached.
The “Wrap Length” can be configured by the “Set Read Parameters (C0h)” instruction .
Figure 96. DTR Burst Read with Wrap (QPI Mode only/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
2
1
3
4
A15-8
A7-0
5
6
12
13
14
Mode 0
Instruction
A23-16
0EH
SI
(IO0)
IOs switch from
Input to Output
8 Dummy Clocks
4
0
4
0
4
0
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
/HOLD
(IO3)
7
MSB
3
7
MSB
3
7
MSB
3
7
3
MSB
Byte1
3
7
MSB
Byte2
7
MSB
Byte3
Figure 97. DTR Burst Read with Wrap (QPI Mode only/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
2
3
4
5
A31-24
A23-16
A15-8
A7-0
1
6
7
13
14
15
Mode 0
Instruction
SI
(IO0)
0EH
IOs switch from
Input to Output
8 Dummy Clocks
4
0
4
0
4
0
4
0
4
0
4
0
4
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
/HOLD
(IO3)
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
December 2020
Rev 1.9
7
3
MSB
Byte1
3
7
MSB
Byte2
7
MSB
Byte3
96 / 171
Instructions Description
7.3
BY25Q256FS
ID and Security Instructions
7.3.1 Read Manufacture ID/ Device ID (90H)
See Figure 98-Figure 99, The Read Manufacturer/Device ID instruction is an alternative to the
Release from Power-Down/Device ID instruction that provides both the JEDEC assigned
Manufacturer ID and the specific Device ID.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “90H”
followed by a 24-bit address (A23-A0) of 000000H, regardless of the 3-byte or 4-byte Address
Mode. If the 24-bit address is initially set to 000001H, the Device ID will be read first.
Figure 98. Read Manufacture ID/ Device ID Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Instruction
SI
24-Bit Address
3 2
21
22
23
90H
High_Z
SO
1
0
/CS
32 33 34 35 36
37 38 39 40 41 42
43 44 45 46 47
SCLK
SI
SO
7
6
Manufacturer ID
5 4
3 2
1
0
7
6
Device ID
3 2
5 4
0
1
Figure 99. Read Manufacture ID/ Device ID Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11
Mode 0
Instruction
A23-16
A15-8
IOs switch from
Input to Output
A7-0
90H
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
/HOLD
(IO3)
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
MFR ID
December 2020
Rev 1.9
Device ID
97 / 171
Instructions Description
BY25Q256FS
7.3.2 Dual I/O Read Manufacture ID/ Device ID (92H)
See Figure 100-Figure 101, the Dual I/O Read Manufacturer/Device ID instruction is an
alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC
assigned Manufacturer ID and the specific Device ID by Dual I/O.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92H”
followed by a 24/32-bit address (A23/31-A0) of 000000/00000000H. If the 24/32-bit address is
initially set to 000001/00000001H, the Device ID will be read first.
Figure 100. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram (SPI Mode/3-Byte
Address Mode)
/CS
0
2
1
4
3
5
6
7
10 11 12
9
8
13 14 15 16 17 18 19 20 21 22 23
SCLK
Instruction
SI
(IO0)
92H
SO
(IO1)
High_Z
6
A23-16
4
2
0
7
5
1
3
MSB
6
A15-8
4 2
0
7
5
1
3
MSB
6
A7-0
4 2
0
7
5
1
3
MSB
6
Dummy
4 2 0
7
5
3
1
MSB
/CS
SCLK
23 24 25 26
39
31 32
27 28 29 30
44 45 46 47
40 41 42 43
IOs switch from
Input to Output
SI
(IO0)
6
4
0
2
4
6
2
6
0
2
4
6
0
2
4
High_Z
0
High_Z
SO
(IO1)
7 5 3 1 7 5 3 1
MSB
MSB
MFR ID
Device ID
MFR and Device ID
(repeat)
7
3 1
5 3 1 7 5
MSB
MSB
Device ID(repeat)
MFR ID(repeat)
Figure 101. Dual I/O Read Manufacture ID/ Device ID Sequence Diagram (SPI Mode/4-Byte
Address Mode)
/CS
0
2
1
4
3
5
6
7
9
8
10
11
12
13
14
15
16
17
18
21
20
19
22
23
SCLK
Instruction
SI
(IO0)
A31-24
92H
A23-16
6
4
2
0
7
5
3
1
A7-0
A15-8
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
46
47
High_Z
SO
(IO1)
MSB
MSB
MSB
MSB
/CS
24
26
25
27
28
29
30
31
32
33
34
35
36
40
43
41
42
44 45
SCLK
IOs switch from
Input to Output
Dummy
High_Z
SI
(IO0)
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SO
(IO1)
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
High_Z
MSB
MSB
MSB
MFR ID
December 2020
Device ID
MFR and Device ID (repeat) MSB
MFR ID(repeat)
Rev 1.9
MSB
Device ID(repeat)
98 / 171
Instructions Description
BY25Q256FS
7.3.3 Quad I/O Read Manufacture ID/ Device ID (94H)
See Figure 102-Figure 103, the Quad I/O Read Manufacturer/Device ID instruction is an
alternative to the Release from Power-Down/Device ID instruction that provides both the JEDEC
assigned Manufacturer ID and the specific Device ID by quad I/O. The Quad Enable bit (QE) of
Status Register must be set to enable.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94H”
followed by a 24/32-bit address (A23/31-A0) of 000000H and 6 dummy clocks. If the 24/32-bit
address is initially set to 000001/00000001H, the Device ID will be read first.
Figure 102. Quad I/O Read Manufacture ID/ Device ID Sequence Diagram (SPI Mode/3-Byte
Address Mode)
/CS
0
1
2
3
4
5
6
7
9
8
10 11 12
13 14 15 16 17 18 19 20 21
SCLK
Instruction
SI
(IO0)
94H
SO
(IO1)
High_Z
WP
(IO2)
High_Z
HOLD
(IO3)
High_Z
A7-0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
7 3 7 3 7 3
MSB
MSB
MSB
23 24 25 26
27 28 29 30
dummy
7 3 7
3
MSB
MSB
MFR ID Device ID
31
SI
(IO0)
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
WP
(IO2)
6
2
6
2
6
2
6
2
HOLD
(IO3)
IOs switch from
Input to Output
A23-16 A15-8
/CS
SCLK
22 23
7 3 7 3 7 3 7
3
MSB
MSB
MSB
MSB
High_Z
High_Z
High_Z
High_Z
MFR ID DID ID MFR ID DID ID
(repeat) (repeat) (repeat) (repeat)
December 2020
Rev 1.9
99 / 171
Instructions Description
BY25Q256FS
Figure 103. Quad I/O Read Manufacture ID/ Device ID Sequence Diagram (SPI Mode/3-Byte
Address Mode)
/CS
0
1
2
3
4
5
6
7
9
8
10 11 12
13 14 15 16 17 18 19 20 21
22 23 24
SCLK
Instruction
SI
(IO0)
94H
SO
(IO1)
High_Z
WP
(IO2)
High_Z
HOLD
(IO3)
High_Z
A7-0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
6
2
29 30 31 32
dummy
7 3 7
3
MSB
MSB
MFR ID Device ID
33
SI
(IO0)
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
WP
(IO2)
6
2
6
2
6
2
6
2
HOLD
(IO3)
dummy
7 3 7 3 7 3 7
3 7 3
MSB
MSB
MSB
MSB
MSB
25 26 27 28
IOs switch from
Input to Output
A31-24 A23-16 A15-8
/CS
SCLK
25
7 3 7 3 7 3 7
3
MSB
MSB
MSB
MSB
High_Z
High_Z
High_Z
High_Z
MFR ID DID ID MFR ID DID ID
(repeat) (repeat) (repeat) (repeat)
7.3.4 Read JEDEC ID (9FH)
The JEDEC ID instruction allows the 8-bit manufacturer identification to be read, followed by two
bytes of device identification. The device identification indicates the memory type in the first byte,
and the memory capacity of the device in the second byte. JEDEC ID instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
The JEDEC ID instruction should not be issued while the device is in Deep Power-Down Mode.
See Figure 104-Figure 105, the device is first selected by driving /CS to low. Then, the 8-bit
instruction code for the instruction is shifted in. This is followed by the 24 -bit device identification,
stored in the memory, being shifted out on Serial Data Output, each bit being shifted out during the
falling edge of Serial Clock. The JEDEC ID instruction is terminated by driving /CS to high at any
time during data output. When /CS is driven high, the device is put in the Standby Mode. Once in
the Standby Mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
December 2020
Rev 1.9
100 / 171
Instructions Description
BY25Q256FS
Figure 104. JEDEC ID Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
8
10 11 12 13
9
14 15
SCLK
9FH
Instruction
SI
Manufacturer ID
/CS
6
7
MSB
SO
5
16 17 18 19 20 21 22 23 24 25 26
4
3
2
1
0
27 28 29 30 31
SCLK
SI
SO
7
Memory Type ID15-ID8
1
6 5 4 3 2
0
Capacity ID7-ID0
6 5 4 3 2 1
7
MSB
0
MSB
Figure 105. JEDEC ID Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
Mode 0
IOs switch from
Input to Output
Instruction
9FH
SI
(IO0)
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
/HOLD
(IO3)
December 2020
3
7
MSB
MFR ID
Rev 1.9
7
3
7
3
MSB
MSB
MT ID Capacity
ID
101 / 171
Instructions Description
BY25Q256FS
7.3.5 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 128-bit number that is
unique to each BY25Q256FS device. The ID number can be used in conjunction with user
software methods to help prevent copying or cloning of a system. The Read Unique ID instruction
is initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by four or five
bytes of dummy clocks in SPI mode. In QPI mode, it contains 3/4 bytes dummy and some dummy
that can be configured by the “Set Read Parameters (C0h)” instruction. After which, the 128-bit ID
is shifted out on the falling edge of SCLK as
Figure 106. Read Unique ID Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
0
Mode 3
Mode 0
SCLK
1
2
3
4
5
6
7
8
9
10
Instruction
SI
11
12
13
14
15
16
17
18
Dummy Byte 1
19
20
21
22
23
Dummy Byte 2
4BH
SO
High_Z
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
164 165 166 167
41
SCLK
Dummy Byte 3
Mode 3
Mode 0
Dummy Byte 4
SI
High_Z
SO
127
2
126
MSB
1
0
128-bit Unique
Serial Number
Figure 107. Read Unique ID Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
2
3
4
5
6
7
8
9
10
Instruction
SI
11
12
13
14
15
16
17
Dummy Byte 1
18
19
20
21
22
23
Dummy Byte 2
4BH
SO
High_Z
/CS
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SCLK
Dummy Byte 3
Dummy Byte 4
41
42
43
44
45
46
47
48
49
172 173 174 175
Mode 3
Mode 0
Dummy Byte 5
SI
SO
High_Z
127
MSB
December 2020
Rev 1.9
126
2
1
0
128-bit Unique
Serial Number
102 / 171
Instructions Description
BY25Q256FS
Figure 108．Read Unique ID Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
Instruction
4BH
SI
(IO0)
2
3
4
Dummy
Byte 1
5
Dummy
Byte 2
6
7
8
9
Dummy
Byte 3
Dummy
*
10
11
86
87
88
89
IOs switch from
Input to Output
4
0
4
0
4
0
4
0
124
120
12
8
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
125
121
13
9
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
126
122
14
10
6
2
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
127
123
15
11
7
3
/HOLD
(IO3)
Mode 3
Mode 0
MSB
128-bit Unique
Serial Number
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
Figure 109．Read Unique ID Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
Instruction
4BH
SI
(IO0)
2
3
4
Dummy
Byte 1
5
Dummy
Byte 2
6
7
8
9
10
11
Dummy
Byte 3
Dummy
Byte 4
Dummy
*
12
13
88
89
90
91
IOs switch from
Input to Output
4
0
4
0
4
0
4
0
4
0
124
120
12
8
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
125
121
13
9
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
126
122
14
10
6
2
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
127
123
15
11
7
3
/HOLD
(IO3)
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
Mode 3
Mode 0
MSB
128-bit Unique
Serial Number
7.3.6 Deep Power-Down (B9H)
Although the standby current during normal operation is relatively low, standby current can be
further reduced with the Deep Power-down instruction. The lower power consumption makes the
Deep Power-down (DPD) instruction especially useful for battery powered applications (see ICC1
and ICC2). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“B9h” as shown in Figure 110-Figure 111
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Deep
Power down instruction will not be executed. After /CS is driven high, the power -down state will
entered within the time duration of tDP. While in the power-down state only the Release from Deep
Power-down/Device ID instruction, software reset sequence or hardware reset sequence, which
restores the device to normal operation, will be recognized. All other Instructions are ignored. This
includes the Read Status Register instruction, which is always available during normal operation.
December 2020
Rev 1.9
103 / 171
Instructions Description
BY25Q256FS
Ignoring all but one instruction also makes the Power Down state a useful condition for securing
maximum write protection. The device always powers-up in the normal operation with the standby
current of ICC1.
Figure 110. Deep Power-Down Sequence Diagram (SPI Mode)
/CS
0
1
2
3 4
5
6
tDP
7
SCLK
Instruction
SI
B9H
Stand-by mode
Power-down mode
Figure 111. Deep Power-Down Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
tDP
1
Mode 0
Mode 3
Mode 0
Instruction
B9H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
Stand-by mode
December 2020
Rev 1.9
Power_down mode
104 / 171
Instructions Description
BY25Q256FS
7.3.7 Release from Deep Power-Down/Read Device ID (ABH)
The Release from Power-Down or Device ID instruction is a multi-purpose instruction. It can be
used to release the device from the Power-Down state or obtain the devices electronic
identification (ID) number.
See Figure 112-Figure 113, to release the device from the Power-Down state, the instruction is
issued by driving the /CS pin low, shifting the instruction code “ABH” and driving /CS high Release
from Power-Down will take the time duration of tRES1 (See AC Characteristics) before the device
will resume normal operation and other instruction are accepted. The /CS pin must remain high
during the tRES1 time duration.
When used only to obtain the Device ID while not in the Power -Down state, the instruction is
initiated by driving the /CS pin low and shifting the instr uction code “ABH” followed by 3-dummy
byte. The Device ID bits are then shifted out on the falling edge of SCLK with most significant bit
(MSB) first as shown in Figure 114-Figure 115. The Device ID value for the BY25Q256FS is listed
in Manufacturer and Device Identification table. The Device ID can be read continuously. The
instruction is completed by driving /CS high.
When used to release the device from the Power-Down state and obtain the Device ID, the
instruction is the same as previously described, and shown in Figure 114-Figure 115, except that
after /CS is driven high it must remain high for a time duration of tRES2 ( See AC Characteristics).
After this time duration the device will resume normal operation and other instruction will be
accepted. If the Release from Power-Down/Device ID instruction is issued while an Erase,
Program or Write cycle is in process (when WIP equal 1) the instruction is ignored and will not
have any effects on the current cycle.
Figure 112. Release Power-Down Sequence Diagram (SPI Mode)
/CS
0
1
2
3 4
5
6
7
tRES1
SCLK
Instruction
SI
ABH
Power-down mode
December 2020
Rev 1.9
Stand-by mode
105 / 171
Instructions Description
BY25Q256FS
Figure 113. Release Power-Down Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
tRES1
1
Mode 3
Mode 0
Mode 0
Instruction
ABH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
Power_down mode
Stand-by mode
Figure 114. Release Power-Down/Read Device ID Sequence Diagram (SPI Mode)
/CS
0
1
2
3
4
5
6
7
8
9
29
31 32
30
33
34
35
36
37
38
39
SCLK
Instruction
SI
ABH
SO
High_Z
3 Dummy Bytes
23 22
2
1
MSB
tRES2
0
7
MSB
6
Device ID
3
4
5
2
1
0
Deep Power-down mode
Stand-by mode
Figure 115. Release Power-Down/Read Device ID Sequence Diagram (QPI Mode)
/CS
tRES2
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
Mode 3
Mode 0
Mode 0
Instruction
3 Dummy Byte
ABH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
IOs switch from
Input to Output
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
Device ID
Power-down current Stand-by current
December 2020
Rev 1.9
106 / 171
Instructions Description
BY25Q256FS
7.3.8 Read Security Registers (48H)
See Figure 116-Figure 119, the instruction is followed by a 3/4-byte address (A23/31-A0) and the
dummy byte. In QPI mode, the number of dummy can be configured by the “C0h” instruction. Each
bit being latched-in during the rising edge of SCLK. Then the memory content, at that address, is
shifted out on SO, each bit being shifted out, at a Max frequency fC, during the falling edge of
SCLK. The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. Once the A8-A0 address reaches
the last byte of the register (Byte FFH), it will reset to 000H, the instruction is completed by driving
/CS high.
ADDRESS
A23/31-A16
A15-12
A11-9
A8-0
Security Register #1
00H/0000H
0 00 1
0 00
Byte Address
Security Register #2
00H/0000H
0 01 0
0 00
Byte Address
Security Register #3
00H/0000H
0 01 1
0 00
Byte Address
Figure 116. Read Security Registers instruction Sequence Diagram (SPI Mode/3-Byte
Address Mode)
/CS
Mode 3
SCLK Mode 0
1
0
2
3
5
4
6
7
8
Instruction
SI
48H
SO
High_Z
28 29 30 31
9
24-Bit Address
3
23 22
MSB
2
1
0
/CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Mode 3
Mode 0
Dummy Byte
SI
SO
7 6
MSB
December 2020
5
4
3
2
1
0
Data Byte 1
7 6
MSB
Rev 1.9
5
4
3
2
1
0
107 / 171
Instructions Description
BY25Q256FS
Figure 117. Read Security Registers instruction Sequence Diagram (SPI Mode/4-Byte
Address Mode)
/CS
1
0
Mode 3
SCLK Mode 0
2
3
5
4
7
6
8
Instruction
SI
48H
SO
High_Z
36 37 38 39
9
32-Bit Address
3
31 30
MSB
2
1
0
/CS
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
SCLK
Dummy Byte
SI
SO
7 6
MSB
5
4
3
2
1
0
Data Byte 1
7 6
MSB
5
4
3
2
1
0
Figure 118. Read Security Registers instruction Sequence Diagram (QPI Mode/3-Byte
Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
Mode 0
Instruction
A15-8
Dummy*
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
20
16
12
8
A7-0
4
0
SO
(IO1)
21
17
13
9
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
22
18
14
10
6
2
6
2
6
2
6
2
6
2
23 19
MSB
15
11
7
3
7
3
7
3
7
MSB
3
SI
(IO0)
/HOLD
(IO3)
48h
A23-16
MSB
MSB
3
7
MSB
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
December 2020
Rev 1.9
108 / 171
Instructions Description
BY25Q256FS
Figure 119. Read Security Registers instruction Sequence Diagram (QPI Mode/4-Byte
Address Mode)
/CS
Mode 3
SCLK
0
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mode 0
Instruction
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
/WP
(IO2)
30
26
22
18
14
10
31 27
MSB
23
19
15
11
48h
SI
(IO0)
/HOLD
(IO3)
Dummy* Data Out 1
Data Out 2 Data Out 3 Data Out 4
4
0
4
0
4
0
4
0
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
MSB
3
MSB
MSB
3
7
MSB
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
7.3.9 Erase Security Registers (44H)
The BY25Q256FS provides three 512-byte Security Registers which can be erased and
programmed individually. These registers may be used by the system manufacturers to store
security and other important information separately from the main memory array.
See Figure 120-Figure 123, the Erase Security Registers instruction is similar to Block/Sector
Erase instruction. A Write Enable instruction must previously have been executed to set the Write
Enable Latch bit.
The Erase Security Registers instruction sequence: /CS goes low sending Erase Security
Registers instruction /CS goes high. /CS must be driven high after the eighth bit of the instruct ion
code has been latched in otherwise the Erase Security Registers instruction is not executed. As
soon as /CS is driven high, the self-timed Erase Security Registers cycle (whose duration is tSE) is
initiated. While the Erase Security Registers cycle is in progress, the Status Register may be read
to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during
the self-timed Erase Security Registers cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch bit is reset. The Security Registers
Lock Bit (LB) in the Status Register can be used to OTP protect the security registers. Once the LB
bit is set to 1, the Security Registers will be permanently locked; the Er ase Security Registers
instruction will be ignored.
ADDRESS
A23/31-A16
A15-12
A11-9
A8-0
Security Register #1
00H/0000H
0 00 1
0 00
Byte Address
Security Register #2
00H/0000H
0 01 0
0 00
Byte Address
Security Register #3
00H/0000H
0 01 1
0 00
Byte Address
December 2020
Rev 1.9
109 / 171
Instructions Description
BY25Q256FS
Figure 120. Erase Security Registers instruction Sequence Diagram (SPI Mode/3-Byte
Address Mode)
CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
29 30
31 Mode 3
Mode 0
Mode 0
Instruction
SI
24-Bit Address
23 22
MSB
44H
2
1
0
Figure 121. Erase Security Registers instruction Sequence Diagram (SPI Mode/4-Byte
Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
37
38
39
Mode 0
Mode 3
Mode 0
Instruction
SI
32-Bit Address
31 30
MSB
44H
2
1
0
Figure 122. Erase Security Registers instruction Sequence Diagram (QPI Mode/3-Byte
Address Mode)
/CS
Mode 3
SCLK
0
1
4
5
6
7 Mode 3
Mode 0
Instruction
A23-16
A15-8
20
16
12
8
A7-0
4
0
SO
(IO1)
21
17
13
9
5
1
/WP
(IO2)
22
18
14
10
6
2
23 19
MSB
15
11
7
3
SI
(IO0)
/HOLD
(IO3)
December 2020
3
2
Mode 0
44h
Rev 1.9
110 / 171
Instructions Description
BY25Q256FS
Figure 123. Erase Security Registers instruction Sequence Diagram (QPI Mode/4-Byte
Address Mode)
/CS
Mode 3
SCLK
0
1
Instruction
4
5
6
7
8
9 Mode 3
Mode 0
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
SI
(IO0)
/HOLD
(IO3)
December 2020
3
2
Mode 0
44h
Rev 1.9
111 / 171
Instructions Description
BY25Q256FS
7.3.10 Program Security Registers (42H)
See Figure 124-Figure 127, the Program Security Registers instruction is similar to the Page
Program instruction. It allows from one byte to 512 bytes of security register data to be
programmed by two times (one time program 256 bytes). A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit before sending the Program
Security Registers instruction. The Program Security Registers instruction is entered by driving
/CS Low, followed by the instruction code (42H), 3/4-byte address and at least one data byte on SI.
As soon as /CS is driven high, the self-timed Program Security Registers cycle (whose duration is
tPP) is initiated. While the Program Security Registers cycle is in progress, the Status Register
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch bit is rese t.
If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be
permanently locked. Program Security Registers instruction will be ignored.
ADDRESS
A23/31-A16
A15-12
A11-9
A8-0
Security Register #1
00H/0000H
0 00 1
0 00
Byte Address
Security Register #2
00H/0000H
0 01 0
0 00
Byte Address
Security Register #3
00H/0000H
0 01 1
0 00
Byte Address
Figure 124. Program Security Registers instruction Sequence Diagram (SPI Mode/3-Byte
Address Mode)
/CS
Mode 3
SCLK Mode 0
0
4
3
2
1
5
6
7
8
Instruction
SI
9
10
28
29 30
31 32 33 34 35 36 37 38 39
24-Bit Address
23 22 21
MSB
42H
3
Data Byte 1
1
2
0
7
MSB
6
5
4
3
2
1
0
/CS
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
2073 2074 2075 2076 2077 2078 2079
SCLK
Data Byte 2
SI
7
6
5
MSB
December 2020
4
3
2
1
0
7
MSB
6
Data Byte 3
5 4 3 2
Rev 1.9
1
0
7
MSB
6
Data Byte 256
3 2
5 4
1
Mode 3
Mode 0
0
112 / 171
Instructions Description
BY25Q256FS
Figure 125. Program Security Registers instruction Sequence Diagram (SPI Mode/4-Byte
Address Mode)
/CS
Mode 3
SCLK Mode 0
0
4
3
2
1
5
6
7
9
8
10
Instruction
39 40 41 42 43 44 45 46 47
32-Bit Address
31 30 29
MSB
42H
SI
37 38
36
3
Data Byte 1
1
2
0
6
7
MSB
4
5
3
2
1
0
/CS
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2080 2081 2082 2083 2084 2085 2086 2087
SCLK
Data Byte 2
7
SI
6
5
4
2
3
1
0
MSB
Data Byte 3
5 4 3 2
6
7
MSB
1
7
MSB
0
Data Byte 256
3 2
5 4
6
1
Mode 3
Mode 0
0
Figure 126. Program Security Registers instruction Sequence Diagram (QPI Mode/3-Byte
Address Mode)
/CS
Mode 3
SCLK
0
3
2
1
4
6
5
7
9
8
10
518 519 Mode 3
Mode 0
11
Mode 0
Instruction
A23-16
A15-8
28
24
12
8
A7-0 Data byte 1 Data byte 2
4
0
4
0
4
0
SO
(IO1)
29
25
13
9
5
1
5
1
5
1
5
1
/WP
(IO2)
30
26
14
10
6
2
6
2
6
2
6
2
31 27
MSB
15
11
7
3
7
3
7
3
42h
SI
(IO0)
/HOLD
(IO3)
MSB
Data byte 256
4
0
3
7
MSB
MSB
Figure 127. Program Security Registers instruction Sequence Diagram (QPI Mode/4-Byte
Address Mode)
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
7
8
9
10
12
11
13
Mode 0
Instruction
A31-24
A23-16
A15-8
28
24
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
/WP
(IO2)
30
26
22
18
14
10
31 27
MSB
23
19
15
11
SI
(IO0)
/HOLD
(IO3)
42h
Data byte 1 Data byte 2
520 521 Mode 3
Mode 0
Data byte 256
4
0
4
0
4
0
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7
3
7
3
7
3
MSB
MSB
3
7
MSB
7.3.11 Read Serial Flash Discoverable Parameter (5AH)
See Figure 128-Figure 129,The Serial Flash Discoverable Parameter (SFDP) standard provides
a consistent method of describing the functional and feature capabilities of serial flash devices in a
December 2020
Rev 1.9
113 / 171
Instructions Description
BY25Q256FS
standard set of internal parameter tables. These parameter tables can be interrogated by host
system software to enable adjustments needed to accommodate divergent features from multiple
vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68
on CFI. SFDP is a standard of JEDEC Standard No.216.
The Read SFDP instruction is initiated by driving the /CS pin low and shif ting the instruction code
“5Ah” followed by a 24-bit address (A23-A0) into the SI pin, regardless of the 3-byte or 4-byte
Address Mode. Eight “dummy” clocks are also required in SPI mode. In QPI mode，the number of
dummy clocks can be configured by the “Set Read Parameters (C0h)” instruction.
Figure 128. Read Serial Flash Discoverable Parameter instruction Sequence Diagram (SPI
Mode)
/CS
1
0
2
3
5
4
7
6
8
28 29 30 31
9
SCLK
Instruction
SI
5AH
SO
High_Z
23 22
MSB
24-Bit
Address
3 2
1
0
/CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
IOs switch from
Input to Output
Dummy Byte
7 6
MSB
SI
SO
5
4
3
2
1
0
Data Byte 1
5 4 3 2
7 6
MSB
1
0
Figure 129. Read Serial Flash Discoverable Parameter instruction Sequence Diagram (QPI
Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
16
Mode 0
Instruction A23-16
5Ah
20 16
SI
(IO0)
A15-8
A7-0
12
8
4
0
Dummy*
Data Out 1 Data Out 2 Data Out 3 Data Out 4
4
0
0
4
0
4
0
4
SO
(IO1)
21
17
13
9
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
22
18
14
10
6
2
6
2
6
2
6
2
6
2
23 19
MSB
15
11
7
3
7
3
7
3
7
MSB
3
/HOLD
(IO3)
MSB
MSB
3
7
MSB
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
December 2020
Rev 1.9
114 / 171
Instructions Description
7.4
BY25Q256FS
Program and Erase Instructions
7.4.1 Page Program (02H)
The Page Program instruction is for programming the memory. A Write Enable instruction must
previously have been executed to set the Write Enable Latch bit before sending the Page Program
instruction.
See Figure 130-Figure 133, the Page Program instruction is entered by driving /CS Low, followed
by the instruction code, 3-byte address and at least one data byte on SI. If the 8 least significant
address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current
page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). /CS must be driven low for the entire duration of the sequence.
The Page Program instruction sequence: /CS goes low-> sending Page Program instruction
->3-byte/4-byte address on SI ->at least 1 byte data on SI-> /CS goes high.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last
256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256
data bytes are sent to device, they are correctly programmed at the requested addresses without
having any effects on the other bytes of the same page. /CS must be driven high after the eighth
bit of the last data byte has been latched in; otherwise the Page Progr am instruction is not
executed.
As soon as /CS is driven high, the self-timed Page Program cycle (whose duration is tPP) is
initiated. While the Page Program cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the
self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch bit is reset.
A Page Program instruction applied to a page which is protected by the Block Protect (BP4, BP3,
BP2, BP1, BP0) bits (see Table 7-Table 8)、SPB and DPB are not executed.
Figure 130. Page Program Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
4
3
2
1
5
6
7
9
8
10
Instruction
31 32 33 34 35 36 37 38 39
24-Bit Address
23 22
MSB
02H
SI
29 30
28
21
3
Data Byte 1
1
2
0
7 6
MSB
5
4
3
2
1
0
/CS
40 41 42 43 44 45 46 47 48 49 50 51 52
53 54
55
2072 2073
2074 2075 2076 2077 2078 2079 Mode
3
Mode 0
SCLK
Data Byte 2
SI
7
6
5
MSB
December 2020
4
3
2
1
0
7 6
MSB
Data Byte 3
4 3 2
5
Rev 1.9
1
0
7 6
MSB
Data Byte 256
3 2
5 4
1
0
115 / 171
Instructions Description
BY25Q256FS
Figure 131. Page Program Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
4
3
2
1
5
6
7
9
8
10
Instruction
32-Bit Address
31 30 29
MSB
02H
SI
39 40 41 42 43 44 45 46 47
37 38
36
3
Data Byte 1
1
2
0
7 6
MSB
4
5
2
3
1
0
/CS
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
2080
2086 2087 Mode
3
Mode 0
2081 2082 2083 2084 2085
SCLK
Data Byte 2
7
SI
6
5
4
2
3
1
0
MSB
Data Byte 3
4 3 2
1
5
7 6
MSB
7 6
MSB
0
Data Byte 256
3 2
5 4
0
1
Figure 132. Page Program Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
0
Mode 3
Mode 0
SCLK
1
2
3
4
5
6
7
8
Instruction
A23-16
02H
SI
(IO0)
A15-8
9
10
Byte 1
A7-0
11
Byte 2
12
13
Byte 3
516 517 518 519
Byte 256
Byte 255
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
/HOLD
(IO3)
MSB
MSB
MSB
MSB
MSB
MSB
Mode 3
Mode 0
MSB
MSB
Figure 133. Page Program Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
Instruction
11
Byte 1
A7-0
12
13
Byte 2
516 517 518 519
A31-24
A23-16
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
SI
(IO0)
/HOLD
(IO3)
December 2020
02H
MSB
MSB
A15-8
MSB
MSB
MSB
Rev 1.9
MSB
Byte 255
MSB
Mode 3
Mode 0
Byte 256
MSB
116 / 171
Instructions Description
BY25Q256FS
7.4.2 Page Program with 4-Byte Address (12H)
The Page Program with 4-Byte Address instruction is similar to the Page Program instruction
except that it requires 32-bit address instead of 24-bit address. No matter the device is operating
in 3-Byte Address Mode or 4-byte Address Mode, the Page Program with 4-Byte Address
instruction will always require 32- bit address to access the entire 256Mb memory.
Figure 134. Page Program with 4-Byte Address (SPI Mode)
/CS
Mode 3 0
SCLK Mode 0
4
3
2
1
5
6
7
9
8
10
Instruction
39 40 41 42 43 44 45 46 47
32-Bit Address
31 30 29
MSB
12H
SI
37 38
36
Data Byte 1
1
2
3
0
7 6
MSB
5
4
2
3
1
0
/CS
2080 2081 2082 2083 2084 2085 2086 2087Mode
3
Mode 0
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
SCLK
Data Byte 2
SI
7
6
5
4
2
3
1
0
7 6
MSB
MSB
Data Byte 3
4 3 2
5
1
7 6
MSB
0
Data Byte 256
3 2
5 4
1
0
Figure 135. Page Program with 4-Byte Address (QPI Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
7
9
8
10
11
518 519 Mode 3
Mode 0
SI
(IO0)
Mode 0
Instruction
A31-24
12h
28 24
A23-16
Data byte 1
12
8
A15-8
4
0
4
0
4
0
A7-0
Data byte 256
4
0
SO
(IO1)
29
25
13
9
5
1
5
1
5
1
5
1
/WP
(IO2)
30
26
14
10
6
2
6
2
6
2
6
2
31 27
MSB
15
11
7
3
7
3
7
3
/HOLD
(IO3)
December 2020
MSB
Rev 1.9
3
7
MSB
117 / 171
Instructions Description
BY25Q256FS
7.4.3 Quad Page Program (32H)
The Quad Page Program instruction is for programming the memory using for pins: IO0, IO1, IO2
and IO3. To use Quad Page Program the Quad enable in status register Bit9 must be set (QE=1).
A Write Enable instruction must previously have been executed to set the Write Enable Latc h bit
before sending the Page Program instruction. The Quad Page Program instruction is entered by
driving /CS Low, followed by the instruction code (32H), three address bytes and at least one data
byte on IO pins. The Quad Enable bit (QE) of Status Register must be set to enable.
The instruction sequence is shown in Figure 136-Figure 137. If more than 256 bytes are sent to
the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be
programmed correctly within the same page. If less than 256 data bytes are sent to device, they
are correctly programmed at the requested addresses without having any effects on the other
bytes of the same page. /CS must be driven high after the eighth bit of the last data byte has been
latched in; otherwise the Quad Page Program instruction is not executed.
As soon as /CS is driven high, the self-timed Quad Page Program cycle (whose duration is tPP) is
initiated. While the Quad Page Program cycle is in progress, the Status Register may be read to
check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Quad Page Program cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch bit is reset. A Quad Page Program
instruction applied to a page which is protected by the Block Protect ( BP4, BP3, BP2, BP1, BP0)
bits (see Table 7-Table 8) is not executed
Figure 136. Quad Page Program Sequence Diagram (SPI Mode only/3-Byte Address Mode)
/CS
Mode 0 0
SCLK Mode 3
1
2
3
4
5
6
7
30 31 32 33 34 35 36 37 38 39
8
Instruction
SI
(IO0)
24-bits address
32H
23 22
0
1
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
MSB
SO
(IO1)
High_Z
WP
(IO2)
High_Z
HOLD
(IO3)
High_Z
7 3 7 3 7 3
7 3
MSB
MSB
MSB
MSB
Byte4
Byte1 Byte2 Byte3
/CS
SCLK
40 41 42
43 44 45 46
47 48
535 536 537 538 539 540 541 542 543
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7 3 7 3 7 3 7 3
MSB
MSB
MSB
MSB
Byte 5
Byte 6 Byte 7 Byte 8
7
3
7
3
7
3
7
3
Mode 0
Mode 3
High_Z
High_Z
High_Z
High_Z
HOLD
(IO3)
December 2020
MSB
MSB
MSB
MSB
Byte 253 Byte 254 Byte 255 Byte 256
Rev 1.9
118 / 171
Instructions Description
BY25Q256FS
Figure 137. Quad Page Program Sequence Diagram (SPI Mode only/4-Byte Address Mode)
/CS
Mode 0 0
SCLK Mode 3
1
2
3
4
5
6
7
38 39 40 41 42 43 44 45 46 47
8
Instruction
SI
(IO0)
32H
SO
(IO1)
High_Z
WP
(IO2)
High_Z
HOLD
(IO3)
High_Z
32-bits address
31 30
MSB
0
1
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
7 3 7 3 7 3
7 3
MSB
MSB
MSB
MSB
Byte1 Byte2 Byte3
Byte4
/CS
SCLK
48 49 50
51 52 53 54
55 56
545 546 545 546 547 548 549 550 551
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
Mode 0
Mode 3
High_Z
High_Z
High_Z
High_Z
HOLD
(IO3)
7 3 7 3 7 3 7 3
MSB
MSB
MSB
MSB
Byte 5
Byte 6 Byte 7 Byte 8
3 7 3
7 3 7
MSB
MSB
MSB
MSB
Byte 253 Byte 254 Byte 255 Byte 256
7
3
7.4.4 Quad Input Page Program with 4-Byte Address (34H)
The Quad Input Page Program with 4-Byte Address instruction is similar to the Quad Input Page
Program instruction except that it requires 32-bit address instead of 24-bit address. No matter the
device is operating in 3-Byte Address Mode or 4-byte Address Mode, the Quad Input Page
Program with 4-Byte Address instruction will always require 32-bit address to access the entire
256Mb memory. The Quad Enable bit (QE) of Status Register must be set to enable .
December 2020
Rev 1.9
119 / 171
Instructions Description
BY25Q256FS
Figure 138. Quad Page Program with 4-Byte Address Sequence Diagram (SPI Mode only)
/CS
Mode 0 0
SCLK Mode 3
1
2
3
4
5
6
7
38 39 40 41 42 43 44 45 46 47
8
Instruction
SI
(IO0)
32-bits address
34H
31 30
SO
(IO1)
High_Z
WP
(IO2)
High_Z
HOLD
(IO3)
High_Z
0
1
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
MSB
7 3 7 3 7 3
MSB
MSB
MSB
Byte1 Byte2 Byte3
7 3
MSB
Byte4
/CS
SCLK
48 49 50
51 52 53 54
55 56
545 546 545 546 547 548 549 550 551
SI
(IO0)
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
WP
(IO2)
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
Mode 0
Mode 3
High_Z
High_Z
High_Z
High_Z
HOLD
(IO3)
December 2020
3 7 3
7 3 7
MSB
MSB
MSB
MSB
Byte 253 Byte 254 Byte 255 Byte 256
7 3 7 3 7 3 7 3
MSB
MSB
MSB
MSB
Byte 5
Byte 6 Byte 7 Byte 8
7
Rev 1.9
3
120 / 171
Instructions Description
BY25Q256FS
7.4.5 Sector Erase (20H)
The Sector Erase instruction is for erasing the all data of the chosen sector. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The Sector
Erase instruction is entered by driving /CS low, followed by th e instruction code, and 3-address
byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. /CS
must be driven low for the entire duration of the sequence.
See Figure 139-Figure 142, The Sector Erase instruction sequence: /CS goes low-> sending
Sector Erase instruction-> 3-byte/4-byte address on SI ->/CS goes high. /CS must be driven high
after the eighth bit of the last address byte has been latched in; otherwise the Sector Erase
instruction is not executed. As soon as /CS is driven high, the self-timed Sector Erase cycle
(whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status
Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the Write Enable Latch bit is reset. A Sector Erase
instruction applied to a sector which is protected by the Block Protect ( BP4, BP3, BP2, BP1, BP0)
bits (see Table 7-Table 8) is not executed.
Figure 139．Sector Erase Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
Instruction
SI
8
9
29 30 31 Mode 3
Mode 0
24-Bit Address
23 22
MSB
20H
2
1
0
Figure 140．Sector Erase Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
Instruction
SI
December 2020
7
8
9
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
20H
Rev 1.9
2
1
0
121 / 171
Instructions Description
BY25Q256FS
Figure 141．Sector Erase Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
Instruction
20H
SI
(IO0)
2
3
A23-16
4
5
6
A15-8
7
A7-0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
7
MSB
3
7
MSB
3
7
MSB
3
/HOLD
(IO3)
Mode 3
Mode 0
Figure 142．Sector Erase Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
Instruction
SI
(IO0)
20H
2
3
A31-24
4
5
A23-16
6
7
8
A15-8
9
A7-0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
7
MSB
3
7
3
7
3
7
3
/HOLD
(IO3)
December 2020
MSB
Rev 1.9
MSB
Mode 3
Mode 0
MSB
122 / 171
Instructions Description
BY25Q256FS
7.4.6 Sector Erase with 4-Byte Address (21H)
The Sector Erase with 4-Byte Address instruction is similar to the Sector Erase instruction except
that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte
Address Mode or 4-byte Address Mode, the Sector Erase with 4-Byte Address instruction will
always require 32-bit address to access the entire 256Mb memory.
Figure 143. Sector Erase with 4-Byte Address (SPI Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
8
Instruction
SI
9
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
21H
2
1
0
Figure 144. Sector Erase with 4-Byte Address (QPI Mode)
/CS
Mode 3
SCLK
SI
(IO0)
0
1
2
3
4
5
6
7
8
9
Mode 0
Instruction
A31-24
21h
28 24
A23-16
A15-8
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
/HOLD
(IO3)
December 2020
Rev 1.9
Mode 3
Mode 0
123 / 171
Instructions Description
BY25Q256FS
7.4.7 32KB Block Erase (52H)
The 32KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The 32KB Block
Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte/4-byte
address on SI. Any address inside the block is a valid address for the 32KB Block Erase
instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 145-Figure 148, the 32KB Block Erase instruction sequence: /CS goes low ->sending
32KB Block Erase instruction ->3-byte/4-byte address on SI ->/CS goes high. /CS must be driven
high after the eighth bit of the last address byte has been latched in; otherwise the 32KB Block
Erase instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle
(whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register
may be read to check the value of the Write in Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch bit is reset. A 32KB Block Erase
instruction applied to a block which is protected by the Block Protect ( BP4, BP3, BP2, BP1, BP0)
bits (see Table 7-Table 8) is not executed.
Figure 145. 32KB Block Erase Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
8
Instruction
SI
9
29 30 31 Mode 3
Mode 0
24-Bit Address
23 22
MSB
52H
2
1
0
Figure 146. 32KB Block Erase Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
Instruction
SI
December 2020
7
8
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
52H
Rev 1.9
2
1
0
124 / 171
Instructions Description
BY25Q256FS
Figure 147. 32KB Block Erase Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
Instruction
52H
SI
(IO0)
2
3
A23-16
4
5
6
A15-8
7
A7-0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
7
MSB
3
7
MSB
3
7
MSB
3
/HOLD
(IO3)
Mode 3
Mode 0
Figure 148. 32KB Block Erase Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
Instruction
SI
(IO0)
52H
2
2
3
A31-24
3
A23-16
4
5
A15-8
6
7
A7-0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
/HOLD
(IO3)
December 2020
Rev 1.9
Mode 3
Mode 0
125 / 171
Instructions Description
BY25Q256FS
7.4.8 32KB Block Erase with 4-Byte Address (5CH)
The 32KB Block Erase with 4-Byte Address instruction is similar to the 32KB Block Erase
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is
operating in 3-Byte Address Mode or 4-byte Address Mode, the 32KB Block Erase with 4-Byte
Address instruction will always require 32-bit address to access the entire 256Mb memory.
Figure 149. 32KB Block Erase with 4-Byte Address (SPI Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
8
Instruction
SI
9
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
5CH
1
0
8
9
2
Figure 150. 32KB Block Erase with 4-Byte Address (QPI Mode)
/CS
Mode 3
SCLK
SI
(IO0)
0
1
2
3
4
5
6
7
Mode 0
Instruction
A31-24
5Ch
28 24
A23-16
A15-8
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
/HOLD
(IO3)
December 2020
Rev 1.9
Mode 3
Mode 0
126 / 171
Instructions Description
BY25Q256FS
7.4.9 64KB Block Erase (D8H)
The 64KB Block Erase instruction is for erasing the all data of the chosen block. A Write Enable
instruction must previously have been executed to set the Write Enable Latch bit. The 64KB Block
Erase instruction is entered by driving /CS low, followed by the instruction code, and 3-byte/4-byte
address on SI. Any address inside the block is a valid address for the 64KB Block Erase
instruction. /CS must be driven low for the entire duration of the sequence.
See Figure 151-Figure 154, the 64KB Block Erase instruction sequence: /CS goes low sending
64KB Block Erase instruction 3-byte/4-byte address on SI /CS goes high. /CS must be driven high
after the eighth bit of the last address byte has been latched in; otherwise the 64KB Block Erase
instruction is not executed. As soon as /CS is driven high, the self-timed Block Erase cycle (whose
duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be
read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1
during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time
before the cycle is completed, the Write Enable Latch bit is reset. A 64KB Block Erase instruction
applied to a block which is protected by the Block Protect ( BP4, BP3, BP2, BP1, BP0) bits (see
Table 7-Table 8) is not executed.
Figure 151. 64KB Block Erase Sequence Diagram (SPI Mode/3-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
8
Instruction
SI
9
29 30 31 Mode 3
Mode 0
24-Bit Address
23 22
MSB
D8H
2
1
0
Figure 152. 64KB Block Erase Sequence Diagram (SPI Mode/4-Byte Address Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
Instruction
SI
December 2020
8
9
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
D8H
Rev 1.9
2
1
0
127 / 171
Instructions Description
BY25Q256FS
Figure 153. 64KB Block Erase Sequence Diagram (QPI Mode/3-Byte Address Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
Instruction
D8H
SI
(IO0)
2
3
A23-16
4
5
6
A15-8
7
A7-0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
7
MSB
3
7
MSB
3
7
MSB
3
/HOLD
(IO3)
Mode 3
Mode 0
Figure 154. 64KB Block Erase Sequence Diagram (QPI Mode/4-Byte Address Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
Instruction
SI
(IO0)
D8H
2
4
3
A31-24
5
A23-16
6
7
A15-8
8
9
A7-0
4
0
4
0
4
0
4
0
SO
(IO1)
5
1
5
1
5
1
5
1
/WP
(IO2)
6
2
6
2
6
2
6
2
7
MSB
3
7
MSB
3
7
MSB
3
7
MSB
3
/HOLD
(IO3)
December 2020
Rev 1.9
Mode 3
Mode 0
128 / 171
Instructions Description
BY25Q256FS
7.4.10 64KB Block Erase with 4-Byte Address (DCH)
The 64KB Block Erase with 4-Byte Address instruction is similar to the 64KB Block Erase
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is
operating in 3-Byte Address Mode or 4-byte Address Mode, the 64KB Block Erase with 4-Byte
Address instruction will always require 32-bit address to access the entire 256Mb memory.
Figure 155. 64KB Block Erase with 4-Byte Address (SPI Mode)
/CS
Mode 3 0
SCLK Mode 0
1
2
3
4
5
6
7
8
Instruction
SI
9
37 38 39 Mode 3
Mode 0
32-Bit Address
31 30
MSB
DCH
2
1
0
Figure 156. 64KB Block Erase with 4-Byte Address (QPI Mode)
/CS
Mode 3
SCLK
SI
(IO0)
1
2
3
4
5
6
7
8
9
Mode 0
Instruction
A31-24
DCh
28 24
A23-16
A15-8
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
/HOLD
(IO3)
December 2020
0
Rev 1.9
Mode 3
Mode 0
129 / 171
Instructions Description
BY25Q256FS
7.4.11 Chip Erase (60/C7H)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A
Write Enable instruction must be executed before the device will accept the Chip Erase Instruction
(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and
shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in
Figure 157-Figure 158.
The /CS pin must be driven high after the eighth bit has been latched. If this i s not done the Chip
Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase
instruction will commence for a time duration of tCE. While the Chip Erase cycle is in progress, the
Read Status Register instruction may still be accessed to check the status of the WIP bit.
The WIP bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is
ready to accept other Instructions again. After the Chip Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction is executed only
if all Block Protect (BP2, BP1, and BP0) bits are 0.The Chip Erase instruction is ignored if one or
more sectors are protected.
Figure 157. Chip Erase Sequence Diagram (SPI Mode)
/CS
SCLK
0
Mode 3
Mode 0
1
2
3
4
5
6
7
Mode 3
Mode 0
Instruction
SI
60H or C7H
SO
High_Z
Figure 158. Chip Erase Sequence Diagram (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
60H/C7H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
December 2020
Rev 1.9
130 / 171
Instructions Description
BY25Q256FS
7.4.12 Program/Erase Suspend (75H)
The Program/Erase Suspend instruction “75h” allows the system to interrupt a Page Program or a
Sector/32K/64K Block Erase operation (The time between the Program/Erase instruction and the
Program/Erase Suspend instruction is tPS/tES). After the program operation has entered the
suspended state, the memory array can be read or erase except for the page being programmed.
And after the erase operation has entered the suspended state, the memory array can be read or
programed except for the big block being erased. Write status register operation can't b e
suspended. The Program/Erase Suspend instruction sequence is shown in Figure 159-Figure
160.
Table 20. Readable or Erasable Area of Memory While a Program Operation is Suspended
Readable or Erasable Region
Of Memory Array
All but the Page being programmed
All but the Page being programmed
All but the Page being programmed
All but the Page being programmed
Suspended operation
Page Program
Page Program with 4-Byte Address
Quad Page Program
Quad Page Program with 4-Byte Address
Table 21. Readable or Programmable Area of Memory While an Erase Operation is
Suspended
Sector Erase(4KB)
Sector Erase with 4-Byte Address (4KB)
Block Erase(32KB)
Block Erase with 4-Byte Address (32KB)
Block Erase(64KB)
Readable Region or Programmable
Of Memory Array
All but the Big Block being Erased
All but the Big Block being Erased
All but the Big Block being Erased
All but the Big Block being Erased
All but the Big Block being Erased
Block Erase with 4-Byte Address (64KB)
All but the Big Block being Erased
Suspended operation
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL
before the Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after
which the device is ready to accept one of the instructions listed in "Table Acceptable
Instructions During Program/Erase Suspend after tPSL/tESL" (e.g. FAST READ). Refer to " AC
Characteristics" for tPSL and tESL timings. "Table Acceptable instructions During Suspend
(tPSL/tESL not required)" lists the Instructions for which the tPSL and tESL latencies do not
apply. For example, “05h”, “66h” and “99h” can be issued at any time after the Suspend
instruction.
Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The
SUS2 (Program Suspend Bit) sets to “1” when a program instruction is suspended. The SUS1
(Erase Suspend Bit) sets to “1” when an erase operation is suspended. The SUS2 or SUS1
clears to “0” when the program or erase instruction is resumed.
Table 22. Acceptable instructions During Program/Erase Suspend after tPSL/tESL
Instruction Name
Suspend Type
Instruction
code
Program Suspend Erase Suspend
Write Enable
Write Disable
06h
04h
*
*
*
*
Read Extended Address Register
C8H
*
*
December 2020
Rev 1.9
131 / 171
Instructions Description
Instruction Name
Write Extended Address Register
BY25Q256FS
Suspend Type
Instruction
code
Program Suspend Erase Suspend
C5H
*
*
Enter 4-Byte Address Mode
B7h
*
*
Exit 4-Byte Address Mode
E9h
*
*
Enter QPI Mode
38h
*
*
Exit QPI Mode
FFh
*
*
Read Extended Address Register
C8h
*
*
Read Data
03h
*
*
Read Data with 4-Byte Address
13h
*
*
Fast Read
0Bh
*
*
DTR Fast Read
0Dh
*
*
Fast Read with 4-Byte Address
0Ch
*
*
Dual Output Fast Read
Fast Read Dual Output with 4-Byte
Address
Quad Output Fast Read
Fast Read Quad Output with 4-Byte
Address
Dual I/O Fast Read
3Bh
*
*
3Ch
*
*
6Bh
*
*
6Ch
*
*
BBh
*
*
DTR Fast Read Dual I/O
BDh
*
*
Fast Read Dual I/O with 4-Byte Address
BCh
*
*
Quad I/O Fast Read
EBh
*
*
DTR Fast Read Quad I/O
Fast Read Quad I/O with 4-Byte
Address
DTR Quad I/O Fast Read with 4- Byte
Address
Quad I/O Word Fast Read
EDh
*
*
ECh
*
*
EEh
*
*
E7h
*
*
Set Burst with Wrap
77h
*
*
Set Read Parameters
Read Mftr./Device ID
C0h
90h
*
*
*
*
Dual IO Read Mftr./Device ID
92h
*
*
Quad IO Read Mftr./Device ID
94h
*
*
Read JEDEC ID
9Fh
*
*
Read Unique ID Number
4Bh
*
*
Release Powen-down/Device ID
ABh
*
*
Read Securty Registers
Read SFDP
48h
5Ah
*
*
*
*
Page Program
02h
*
Page Program with 4-Byte Address
12h
*
Quad Page Program
32h
*
December 2020
Rev 1.9
132 / 171
Instructions Description
BY25Q256FS
Suspend Type
Instruction
code
Program Suspend Erase Suspend
Instruction Name
Quad Input Page Program with 4-Byte
Address
Sector Erase
34h
*
20h
*
Sector Erase with 4-Byte Address
21h
*
32KB Block Erase
52h
*
32KB Block Erase with 4-Byte Address
64KB Block Erase
5Ch
D8h
*
*
64KB Block Erase with 4-Byte Address
DCh
*
Program/Erase Resume
7Ah
*
*
Read Lock Register
2Dh
*
*
Read SPB Lock Register
A7h
*
*
Read SPB Status
E2h
*
*
Read DPB Status
3Dh
*
*
Read Unprotect Solid Protect Bit
AAh
*
*
Read Password Register
27H
*
*
Table 23. Acceptable Instructions During Suspend（tPSL/tESL not required）
Suspend Type
Instruction
code
Program Suspend Erase Suspend
Instruction Name
Read Status Register-1
05H
*
*
Read Status Register-2
35H
*
*
Read Status Register-3
15H
*
*
Enable Reset
66H
*
*
Reset Device
99H
*
tPSL: Program Suspend Latency; tESL: Erase Suspend Latency.
*
Figure 159. Program/Erase Suspend Instruction Sequence (SPI Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
2
3
4
5
6
7
tPSL/tESL
Mode 3
Mode 0
Instruction
SI
75H
SO
High_Z
Accept instructions
December 2020
Rev 1.9
133 / 171
Instructions Description
BY25Q256FS
Figure 160. Program/Erase Suspend Instruction Sequence (QPI Mode)
/CS
tPSL/tESL
Mode 3
SCLK
0
1
Mode 3
Mode 0
Mode 0
Instruction
75H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
Accept instructions
December 2020
Rev 1.9
134 / 171
Instructions Description
BY25Q256FS
7.4.13 Program/Erase Resume (7AH)
The Program/Erase Resume instruction “7Ah” must be written to resume the Sector or Block
Erase operation or the Page Program operation after an Program/Erase Suspend. The Resume
instruction “7AH” will be accepted by the device only if the SUS bit in the Status Register equa ls to
1 and the WIP bit equals to 0.
After the Resume instruction is issued the SUS bit will be cleared from 1 to 0 immediately, the WIP
bit will be set from 0 to 1 within 200 ns and the Sector or Block will complete the erase operation or
the page will complete the program operation. If the SUS bit equals to 0 or the WIP bit equals to 1,
the Resume instruction “7Ah” will be ignored by the device. The Program/Erase Resume
instruction sequence is shown in Figure 161-Figure 162.
Figure 161. Program/Erase Resume Instruction Sequence (SPI Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction
SI
7AH
SO
High_Z
Figure 162. Program/Erase Resume Instruction Sequence (QPI Mode)
/CS
SCLK
Mode 3
Mode 0
0
1
Mode 3
Mode 0
Instruction
SI
(IO0)
7AH
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
Resume previously
suspended Program or
Erase
December 2020
Rev 1.9
135 / 171
Instructions Description
7.5
BY25Q256FS
Advanced Block/Sector Protection Instructions
7.5.1 Read Lock Register (2DH)
The Read Lock Register (2Dh) instruction is used to read the Lock Register. The Lock Register is
a 16-bit one-time programmable register. Lock Register bits [2:1] select between Solid Protection
mode and Password Protection mode.
See Figure 163-Figure 164, to read out the bit value of the Lock Register, the Read Lock Register
(2Dh) instruction must be issued by driving /CS low, shifting the instruction code “2Dh” into the
Data Input (SI or IO0-IO3) pin on the rising edge of CLK. The Lock Register value will be shifted
out on the SO or IO0-IO3 pin at the falling edge of CLK with most significant bit (MSB) first as
shown in Figure.
Figure 163. Read Lock Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
16 17 18 19 20 21 22 23
13 14 15
10 11 12
9
SCLK Mode 0
Instruction
SI
2DH
Register Out
SO
High_Z
7 6
MSB
5
4
2
3
Register Out
1
0
15 14 13 12 11 10
MSB
9
8
7
Figure 164. Read Lock Register (QPI Mode)
/CS
Mode 3
SCLK
0
2
1
3
4
5
6
4
Mode 0
Instruction Register
Out
2DH
4
0
Register
Out
12
8
5
1
13
9
5
/WP
(IO2)
6
2
14
10
6
/HOLD
(IO3)
7
3
15
11
7
SI
(IO0)
SO
(IO1)
MSB
MSB
MSB
7.5.2 Write Lock Register (2CH)
The Write Lock Register (2Ch) instruction is used to write the Lock Register. The Lock Register is
a 16-bit one-time programmable register. Lock Register bits [2:1] select between Solid Protection
mode and Password Protection mode. Programming Lock Register bit 1 to “0” permanently
selects Solid Protection mode and permanently disables Password Protection mode. Conversely,
programming bit 2 to “0” permanently selects Password Protection mode and permanently
disables Solid Protection mode. Bits 1 and 2 cannot be programmed to “0” at the same time
otherwise the device will abort the operation.
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Write
Lock Register (2Ch) instruction.
See Figure 165-Figure 166, to write the Lock Register, the Write Lock Register (2Ch) instruction
must be issued by driving /CS low, shifting the instruction code “ 2Ch” into the Data Input (SI or
IO0-IO3) pin on the rising edge of CLK, followed by the value of Lock Register bit 7-0 and bit 15-8,
and then driving /CS high.
Figure 165. Write Lock Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
9
8
10 11 12
SCLK Mode 0
Instruction
SI
6
7
2CH
5
4
3
16 17 18 19 20 21 22 23 Mode 3
Mode 0
Lock Register In
13 14 15
2
1
0
15 14 13 12 11 10
9
8
MSB
SO
High_Z
Figure 166. Write Lock Register (QPI Mode)
/CS
Mode 3
SCLK
0
2
1
3
4
5
Mode 0
Mode 0
Instruction Register
In
2CH
4
0
Register
In
12
8
5
1
13
9
/WP
(IO2)
6
2
14
10
/HOLD
(IO3)
7
3
15
11
SI
(IO0)
SO
(IO1)
Mode 3
MSB
MSB
7.5.3 SPB Lock Bit Clear (A6H)
The SPB Lock Bit Clear (A6h) instruction can be used to write the SPB Lock Bit to “0” and protect
the SPB bits.
In Solid Protection mode, once the SPB Lock Bit has been written to “0”, there is no instruction
(except a software reset) to set the bit back to “1”. A power-on cycle or reset is required to set the
SPB lock bit back to “1”.
In Password Protection mode, the SPB Lock Bit defaults to “0” after power -on or reset. A valid
password must be provided to set the SPB Lock Bit to “1” to allow the SPBs to be modified. After
the SPBs have been set to the desired status, use the SPB Lock Bit Clear instruction to clear the
SPB Lock Bit back to “0” in order to prevent further modification.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the SPB Lock
Bit Clear instruction.
December 2020
Rev 1.9
137 / 171
Instructions Description
BY25Q256FS
See Figure 167-Figure 168, the instruction must be issued by driving /CS low, shifting the
instruction code “A6h” into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK, and then
driving /CS high.
Figure 167. SPB Lock Bit Clear (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
SCLK Mode 0
Mode 3
Mode 0
Instruction
SI
A6H
High_Z
SO
Figure 168. SPB Lock Bit Clear (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
A6H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.4 Read SPB Lock Register (A7H)
The Read SPB Lock Register (A7h) instruction is used to read the SPB Lock Register. The SPB
Lock Bit is a volatile bit located in bit 0 of the SPB Lock Register.
See Figure 169-Figure 170, to read out the bit value of the SPB Lock Bit, the Read SPB Lock
Register (A7h) instruction must be issued by driving /CS low, shifting the instruction code “ A7h”
into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK. The SPB Lock Register value will
be shifted out on the SO or IO0-IO3 pin at the falling edge of CLK with most significant bit (MSB)
first.
December 2020
Rev 1.9
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Instructions Description
BY25Q256FS
Figure 169. Read SPB Lock Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
16 17 18 19 20 21 22 23
13 14 15
10 11 12
9
SCLK Mode 0
Instruction
SI
A7H
Register Out
SO
High_Z
7 6
MSB
5
4
2
3
Register Out
1
7 6
MSB
0
5
4
3
2
1
0
7
Figure 170. Read SPB Lock Register (QPI Mode)
/CS
Mode 3
SCLK
0
2
1
3
4
5
6
4
Mode 0
Instruction Register
Out
A7H
4
0
Register
Out
4
0
5
1
5
1
5
/WP
(IO2)
6
2
6
2
6
/HOLD
(IO3)
7
3
7
3
SI
(IO0)
SO
(IO1)
MSB
MSB
7
MSB
7.5.5 Read SPB Status (E2H)
The Read SPB Status (E2h) instruction reads the status of the SPB of a sector or block. The Solid
Protection Bits (SPBs) are non-volatile bits for enabling or disabling write-protection to sectors and
blocks. An SPB is assigned to each 4KB sector in the bottom and top 64KB of memory and to
each 64KB block in the remaining memory. The factory default state of the SPB bits is “0”, which
has the block/sector write-protection disabled.
The Read SPB Status instruction returns 00h if the SPB is “0”, indicating write-protection is
disabled. The Read SPB Status instruction returns FFh if the SPB is “1”, indicating write-protection
is enabled.
See Figure 171-Figure 174, to read out the SPB Bit value of a specific block or sector, the Read
SPB Status (E2h) instruction must be issued by driving /CS low, shifting the instruction code “ E2h”
into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK, followed by a 24/32-bit address.
In QPI mode, the number of dummy clocks can be configured by the “Set Read Parameters (C0h)”
instruction. The SPB Bit value will be shifted out on the SO or IO0-IO3 pin at the falling edge of
CLK with most significant bit (MSB) first as shown in Figure, and then driving /CS high. Please
note that if not driven /CS high, the SPB Bit value will be repeatedly output.
December 2020
Rev 1.9
139 / 171
Instructions Description
BY25Q256FS
Figure 171. Read SPB Status (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
9
8
28 29 30
10
SCLK Mode 0
24-Bit Address
Instruction
SI
31 32 33 34 35 36 37 38 39 Mode 3
Mode 0
23 22
E2H
21
3
2
1
0
MSB
High_Z
SO
7 6
MSB
Data Out
4 3 2
5
1
0
Figure 172. Read SPB Status (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
9
8
36 37 38
10
SCLK Mode 0
32-Bit Address
Instruction
SI
39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
31 30
E2H
29
3
2
1
0
MSB
High_Z
SO
7 6
MSB
5
Data Out
4 3 2
1
0
Figure 173. Read SPB Status (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
8
7
9
10
11
Mode 0
Mode 0
Instruction
E2H
A23-16
A7-0
4
0
SI
(IO0)
SO
(IO1)
20
16
A15-8
12
8
21
17
13
9
5
/WP
(IO2)
22
18
14
10
23 19
MSB
15
11
/HOLD
(IO3)
Mode 3
Dummy*
4
0
4
0
1
5
1
5
1
6
2
6
2
6
2
7
3
7
3
7
3
Data Out
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
December 2020
Rev 1.9
140 / 171
Instructions Description
BY25Q256FS
Figure 174. Read SPB Status (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
3
2
4
5
6
8
7
9
10
11
12
13
Mode 0
Mode 3
Mode 0
Instruction
E2H
28
24
20
16
A15-8
12
8
29
25
21
17
13
9
5
/WP
(IO2)
30
26
22
18
14
10
31 27
MSB
23
19
15
11
A31-24
/HOLD
(IO3)
A23-16
Dummy*
A7-0
4
0
SI
(IO0)
SO
(IO1)
4
0
4
0
1
5
1
5
1
6
2
6
2
6
2
7
3
7
3
7
3
Data Out
* = “Set Read Parameters”Instruction (C0H)
can set the number of dummy clocks
7.5.6 SPB Program (E3H)
The SPB Program (E3h) instruction set SPBs to “1”. SPBs can be individually set to “1” by the SPB
Program instruction. The Solid Protection Bits (SPBs) are non-volatile bits for enabling or disabling
write-protection to sectors and blocks. An SPB is assigned to each 4KB sector in the bottom and
top 64KB of memory and to each 64KB block in the remaining memory. The factory default state of
the SPB bits is “0”, which has the block/sector write-protection disabled. When an SPB is set to “1”,
the associated sector or block is write-protected. Program and erase operations on the sector or
block will be inhibited.
The SPB Lock Bit must be “1” before any SPB can be modified. In Solid Protection mode the SPB
Lock Bit defaults to “1” after power-on or reset. Under Password Protection mode, the SPB Lock
Bit defaults to “0” after power-on or reset, and a Password Unlock instruction with a correct
password is required to set the SPB Lock Bit to “1”.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the SPB
Program instruction.
See Figure 175-Figure 178, to set SPB to “1”, the SPB Program (E3h) instruction must be issued
by driving /CS low, shifting the instruction code “E3h” into the Data Input (SI or IO0-IO3) pin on the
rising edge of CLK, followed by a 24/32-bit address, and then driving /CS high.
Figure 175. SPB Program (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28 29 30
SCLK Mode 0
24-Bit Address
Instruction
SI
E3H
31 Mode 3
Mode 0
23 22
21
3
2
1
0
MSB
SO
December 2020
High_Z
Rev 1.9
141 / 171
Instructions Description
BY25Q256FS
Figure 176. SPB Program (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
8
9
36 37 38
10
SCLK Mode 0
32-Bit Address
Instruction
SI
39 Mode 3
Mode 0
29
31 30
E3H
3
2
1
0
MSB
High_Z
SO
Figure 177. SPB Program (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
Mode 3
Mode 0
Mode 0
Instruction
A23-16
E3H
20 16
SI
(IO0)
A15-8
12
8
A7-0
4
0
SO
(IO1)
21
17
13
9
5
1
/WP
(IO2)
22
18
14
10
6
2
23 19
MSB
15
11
7
3
/HOLD
(IO3)
Figure 178. SPB Program (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
SI
(IO0)
0
1
2
3
4
5
6
7
8
9
Mode 0
Mode 0
Instruction
A31-24
E3H
28 24
A23-16
A15-8
20
16
12
8
A7-0
4
0
SO
(IO1)
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
/HOLD
(IO3)
December 2020
Mode 3
Rev 1.9
142 / 171
Instructions Description
BY25Q256FS
7.5.7 SPB Erase (E4H)
The SPB Erase (E4h) instruction clears all SPBs to “0”. The SPBs cannot be individually cleared to
“0”. The SPB Lock Bit must be “1” before any SPB can be modified. In Solid Protection mode the
SPB Lock Bit defaults to “1” after power-on or reset. Under Password Protection mode, the SPB
Lock Bit defaults to “0” after power-on or reset, and a Password Unlock instruction with a correct
password is required to set the SPB Lock Bit to “1”.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the SPB
Erase instruction.
See Figure 179-Figure 180, to clear all SPBs to “0”, the SPB Erase (E4h) instruction must be
issued by driving /CS low, shifting the instruction code “E4h” into the Data Input (SI or IO0-IO3),
and then driving /CS high.
Figure 179. SPB Erase (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
SCLK Mode 0
Mode 3
Mode 0
Instruction
SI
E4H
High_Z
SO
Figure 180. SPB Erase (QPI Mode)
/CS
Mode 3
SCLK
0
1
Mode 0
Mode 3
Mode 0
Instruction
E4H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.8 Read DPB Status (3DH)
The Read DPB Status (3Dh) instruction reads the status of the DPB of a sector or block. The Read
DPB Status instruction returns 00h if the DPB is “0”, indicating write-protection is disabled. The
Read DPB Status instruction returns FFh if the DPB is “1”, indicating write-protection is enabled.
The Dynamic Protection Bits (DPBs) are volatile bits for quickly and easily enab ling or disabling
write-protection to sectors and blocks. A DPB is assigned to each 4KB sector in the bottom and top
December 2020
Rev 1.9
143 / 171
Instructions Description
BY25Q256FS
64KB of memory and to each 64KB block in the rest of the memory. When a DPB is “1”, the
associated sector or block will be write-protected, preventing any program or erase operation on
the sector or block. All DPBs default to “1” after power-on or reset. When a DPB is cleared to “0”,
the associated sector or block will be unprotected if the corresponding SPB is also “0”.
See Figure 181-Figure 184, to read out the DPB Bit value of a specific block or sector, the Read
DPB Status (3Dh) instruction must be issued by driving /CS low, shifting the instruction code “3Dh”
into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK, followed by a 24/32-bit address.
The DPB Bit value will be shifted out on the SO or IO0-IO3 pin at the falling edge of CLK with most
significant bit (MSB) first as shown in Figure, and then driving /CS high. Please note that if not
driven /CS high, the DPB Bit value will be repeatedly output.
Figure 181. Read DPB Status (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
8
9
28 29 30
10
SCLK Mode 0
24-Bit Address
Instruction
SI
31 32 33 34 35 36 37 38 39 Mode 3
Mode 0
23 22
3DH
21
3
2
1
0
MSB
High_Z
SO
7 6
MSB
5
Data Out
4 3 2
1
0
Figure 182. Read DPB Status (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
36 37 38
10
SCLK Mode 0
32-Bit Address
Instruction
SI
39 40 41 42 43 44 45 46 47 Mode 3
Mode 0
31 30
3DH
29
3
2
1
0
MSB
High_Z
SO
7 6
MSB
5
Data Out
4 3 2
9
Mode 3
1
0
Figure 183. Read DPB Status (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
8
7
Mode 0
Mode 0
Instruction
3DH
A23-16
A7-0
4
0
4
0
5
1
5
1
10
6
2
6
2
11
7
3
7
3
SI
(IO0)
SO
(IO1)
20
16
A15-8
12
8
21
17
13
9
/WP
(IO2)
22
18
14
23 19
MSB
15
/HOLD
(IO3)
Data
Out
December 2020
Rev 1.9
144 / 171
Instructions Description
BY25Q256FS
Figure 184. Read DPB Status (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
3
2
1
4
5
6
8
7
9
10
11
Mode 0
Mode 3
Mode 0
Instruction
3DH
A7-0
4
0
4
0
5
1
5
1
10
6
2
6
2
11
7
3
7
3
SI
(IO0)
SO
(IO1)
A31-24
28 24
A23-16
20 16
A15-8
12
8
29
25
21
17
13
9
/WP
(IO2)
30
26
22
18
14
31 27
MSB
23
19
15
/HOLD
(IO3)
Data
Out
7.5.9 Dynamic Protection Block/Sector Lock (36H)
The Dynamic Protection Block/Sector Lock (36h) instruction can individually set DPB bits to “1”.
When a DPB is “1”, the associated sector or block will be write-protected, preventing any program
or erase operation on the sector or block. All DPBs default to “1” after power-on or reset. When a
DPB is cleared to “0”, the associated sector or block will be unprotected if the corresponding SPB
is also “0”.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Dynamic
Protection Block/Sector Lock instruction.
See Figure 185-Figure 188, to set DPB to “1”, the Dynamic Protection Block/Sector Lock (36h)
instruction must be issued by driving /CS low, shifting the instruction code “ 36h” into the Data Input
(SI or IO0-IO3) pin on the rising edge of CLK, followed by a 24/32-bit address, and then driving
/CS high.
Figure 185. Dynamic Protection Block/Sector Lock (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
28 29 30
SCLK Mode 0
24-Bit Address
Instruction
SI
36H
31 Mode 3
Mode 0
23 22
21
3
2
1
0
MSB
SO
December 2020
High_Z
Rev 1.9
145 / 171
Instructions Description
BY25Q256FS
Figure 186. Dynamic Protection Block/Sector Lock (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
9
8
36 37 38
10
SCLK Mode 0
32-Bit Address
Instruction
SI
39 Mode 3
Mode 0
29
31 30
36H
3
2
1
0
MSB
High_Z
SO
Figure 187. Dynamic Protection Block/Sector Lock (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
6
5
Mode 3
7
Mode 0
Mode 0
Instruction
A23-16
36H
A7-0
4
0
SI
(IO0)
SO
(IO1)
20
16
A15-8
12
8
21
17
13
9
5
1
/WP
(IO2)
22
18
14
10
6
2
23 19
MSB
15
11
7
3
/HOLD
(IO3)
Figure 188. Dynamic Protection Block/Sector Lock (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
9
8
Mode 0
Mode 3
Mode 0
Instruction
36H
A31-24
A23-16
A7-0
4
0
SI
(IO0)
SO
(IO1)
28
24
20
16
A15-8
12
8
29
25
21
17
13
9
5
1
/WP
(IO2)
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
/HOLD
(IO3)
7.5.10 Dynamic Protection Block/Sector Unlock (39H)
The Dynamic Protection Block/Sector Unlock (39h) instruction can individually set DPB bits to “0”.
When a DPB is cleared to “0”, the associated sector or block will be unprotected if the
corresponding SPB is also “0”.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Dynamic
Protection Block/Sector Unlock instruction.
December 2020
Rev 1.9
146 / 171
Instructions Description
BY25Q256FS
See Figure 189-Figure 192, to set DPB to “0”, the Dynamic Protection Block/Sector Unlock (39h)
instruction must be issued by driving /CS low, shifting the instruction code “ 39h” into the Data Input
(SI or IO0-IO3) pin on the rising edge of CLK, followed by a 24/32-bit address, and then driving
/CS high.
Figure 189. Dynamic Protection Block/Sector Unlock (SPI Mode/3-Byte Address Mode)
/CS
Mode 3
2
1
0
3
4
5
6
7
9
8
31 Mode 3
Mode 0
28 29 30
10
SCLK Mode 0
24-Bit Address
Instruction
SI
21
23 22
39H
3
2
1
0
MSB
High_Z
SO
Figure 190. Dynamic Protection Block/Sector Unlock (SPI Mode/4-Byte Address Mode)
/CS
Mode 3
0
1
2
4
3
5
6
7
9
8
36 37 38
10
SCLK Mode 0
32-Bit Address
Instruction
SI
39 Mode 3
Mode 0
29
31 30
39H
3
2
1
0
MSB
High_Z
SO
Figure 191. Dynamic Protection Block/Sector Unlock (QPI Mode/3-Byte Address Mode)
/CS
Mode 3
SCLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
Mode 0
Instruction
39H
A7-0
4
0
20
16
A15-8
12
8
21
17
13
9
5
1
/WP
(IO2)
22
18
14
10
6
2
23 19
MSB
15
11
7
3
/HOLD
(IO3)
December 2020
A23-16
SI
(IO0)
SO
(IO1)
Rev 1.9
147 / 171
Instructions Description
BY25Q256FS
Figure 192. Dynamic Protection Block/Sector Unlock (QPI Mode/4-Byte Address Mode)
/CS
Mode 3
SCLK
0
3
2
1
4
5
6
7
8
9
Mode 0
Mode 3
Mode 0
Instruction
39H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
A31-24
A23-16
28
24
20
16
A15-8
12
8
29
25
21
17
13
9
5
1
30
26
22
18
14
10
6
2
31 27
MSB
23
19
15
11
7
3
A7-0
4
0
7.5.11 Read Unprotect Solid Protect Bit (AAH)
The Read Unprotect Solid Protect Bit (AAh) instruction can read the value of Unprotect Solid
Protect Bit. The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or
reset. When USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked
and their write-protected sectors and blocks are temporarily unprotected (as long as their
corresponding DPBs are “0“).
The USPB can be read, set or cleared as often as needed in Solid Protection mode or after
providing a valid password in Password Protection mode.
See Figure 193-Figure 194, to read out the bit value of the Unprotect Solid Protect Bit, the Read
Unprotect Solid Protect Bit (AAh) instruction must be issued by driving /CS low, shifting the
instruction code “AAh” into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK. The
Unprotect Solid Protect Bit value will be shifted out on the SO or IO0-IO3 pin at the falling edge of
CLK with most significant bit (MSB) first.
Figure 193. Read Unprotect Solid Protect Bit (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
13 14 15
10 11 12
16 17 18 19 20 21 22 23
SCLK Mode 0
Instruction
SI
AAH
Register Out
SO
December 2020
High_Z
X X
MSB
X
X
X
Rev 1.9
X
Register Out
X
0
X X
MSB
X
X
X
X
X
0
X
148 / 171
Instructions Description
BY25Q256FS
Figure 194. Read Unprotect Solid Protect Bit (QPI Mode)
/CS
Mode 3
SCLK
0
2
1
3
4
5
6
X
Mode 0
Instruction Register
Out
AAH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
X
0
Register
Out
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MSB
X
MSB
MSB
7.5.12 Unprotect Solid Protect Bit Set (A8H)
The Unprotect Solid Protect Bit Set (A8h) instruction can set the Unprotect Solid Protect Bit can be
to 1. The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or reset.
When USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked and
their write-protected sectors and blocks are temporarily unprotected (as long as their
corresponding DPBs are “0“).
The USPB can be read, set or cleared as often as needed in Solid Protection mode or after
providing a valid password in Password Protection mode.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Unprotect
Solid Protect Bit Set instruction.
See Figure 195-Figure 196, the instruction must be issued by driving /CS low, shifting the
instruction code “A8h” into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK, and then
driving /CS high.
Figure 195. Unprotect Solid Protect Bit Set (SPI Mode)
/CS
Mode 3
0
1
2
3
4
SCLK Mode 0
5
6
7
Mode 3
Mode 0
Instruction
SI
SO
December 2020
A8H
High_Z
Rev 1.9
149 / 171
Instructions Description
BY25Q256FS
Figure 196. Unprotect Solid Protect Bit Set (QPI Mode)
/CS
0
Mode 3
SCLK
1
Mode 0
Mode 3
Mode 0
Instruction
A8H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.13 Unprotect Solid Protect Bit Clear (A9H)
The Unprotect Solid Protect Bit Clear (A9h) instruction can set the Unprotect Solid Protect Bit to 0.
The Unprotect Solid Protect Bit is a volatile bit that defaults to “1” after power-on or reset. When
USPB=1, the SPBs have their normal function. When USPB=0 all SPBs are masked and their
write-protected sectors and blocks are temporarily unprotected (as long as their corresponding
DPBs are “0“).
The USPB can be read, set or cleared as often as needed in Solid Protection mode or after
providing a valid password in Password Protection mode.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Unprotect
Solid Protect Bit Clear instruction.
See Figure 197-Figure 198, the instruction must be issued by driving /CS low, shifting the
instruction code “A9h” into the Data Input (SI or IO0-IO3) pin on the rising edge of CLK, and then
driving /CS high.
Figure 197. Unprotect Solid Protect Bit Clear (SPI Mode)
/CS
Mode 3
0
1
2
3
4
SCLK Mode 0
5
6
7
Mode 3
Mode 0
Instruction
SI
SO
December 2020
A9H
High_Z
Rev 1.9
150 / 171
Instructions Description
BY25Q256FS
Figure 198. Unprotect Solid Protect Bit Clear (QPI Mode)
/CS
0
Mode 3
1
Mode 3
Mode 0
SCLK
Mode 0
Instruction
A9H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.14 Global Block/Sector Lock (7Eh)
The Global Block/Sector Lock (7Eh) instruction can set all Dynamic Protection Bits (DPBs) to 1.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Global
Block/Sector Lock instruction.
See Figure 199-Figure 200, to set all DPBs to “1”, the Global Block/Sector Lock (7Eh) instruction
must be issued by driving /CS low, shifting the instruction code “7Eh” into the Data Input (SI or
IO0-IO3) pin on the rising edge of CLK, and then driving /CS high.
Figure 199. Global Block/Sector Lock (SPI Mode)
/CS
Mode 3
0
1
2
3
4
SCLK Mode 0
5
6
7
Mode 3
Mode 0
Instruction
SI
SO
December 2020
7EH
High_Z
Rev 1.9
151 / 171
Instructions Description
BY25Q256FS
Figure 200. Global Block/Sector Lock (QPI Mode)
/CS
0
Mode 3
1
Mode 3
Mode 0
SCLK
Mode 0
Instruction
7EH
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.15 Global Block/Sector Unlock (98h)
The Global Block/Sector Unlock (98h) instruction can set all Dynamic Protection Bits (DPBs) to 0.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Global
Block/Sector Unlock instruction.
See Figure 201-Figure 202, to set all DPBs “0”, the Global Block/Sector Unlock (98h) instruction
must be issued by driving /CS low, shifting the instruction code “ 98h” into the Data Input (SI or
IO0-IO3) pin on the rising edge of CLK, and then driving /CS high.
Figure 201. Global Block/Sector Unlock (SPI Mode)
/CS
Mode 3
0
1
2
3
4
SCLK Mode 0
5
6
7
Mode 3
Mode 0
Instruction
SI
SO
December 2020
98H
High_Z
Rev 1.9
152 / 171
Instructions Description
BY25Q256FS
Figure 202. Global Block/Sector Unlock (QPI Mode)
/CS
0
Mode 3
1
Mode 0
SCLK
Mode 3
Mode 0
Instruction
98H
SI
(IO0)
SO
(IO1)
/WP
(IO2)
/HOLD
(IO3)
7.5.16 Read Password Register (27H)
The Read Password Register (27H) instruction can reads back the 64-bit password. Password
Protection mode potentially provides a higher level of security than Solid Protection mode.
See Figure 203-Figure 204, to reads back the password, the Read Password Register (27H)
instruction must be issued by driving /CS low, shifting the instruction code “ 27h” into the Data Input
(SI or IO0-IO3) pin on the rising edge of CLK. The 64-bit password will be shifted out on the SO or
IO0-IO3 pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure.
Figure 203. Read Password Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
10
69
70
71 72
73
SCLK Mode 0
Instruction
SI
27H
Data Out 1
SO
December 2020
High_Z
7 6
MSB
Rev 1.9
5
Data Out 2
58 57 56
7 6
MSB
5
153 / 171
Instructions Description
BY25Q256FS
Figure 204. Read Password Register (QPI Mode)
/CS
Mode 3
SCLK
0
3
2
1
17
18
Mode 0
Instruction
Data Out 1
27H
SI
(IO0)
SO
(IO1)
Data Out 2
4
0
56
4
5
1
57
5
/WP
(IO2)
6
2
58
6
/HOLD
(IO3)
7
3
59
7
MSB
MSB
7.5.17 Write Password Register (28H)
The Write Password Register (28H) instruction writes the password. The Password Protection
mode potentially provides a higher level of security than Solid Protection mode.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Write
Password Register instruction.
See Figure 205-Figure 206, to write the password, the Write Password Register (28H) instruction
must be issued by driving /CS low, shifting the instruction code “ 28h” into the Data Input (SI or
IO0-IO3) pin on the rising edge of CLK followed by the 64-bit password, and then driving /CS high.
Figure 205. Write Password Register (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
69 70
10
SCLK Mode 0
Instruction
SI
28H
71 Mode 3
Mode 0
Password
7
6
5
58 57 56
MSB
SO
December 2020
High_Z
Rev 1.9
154 / 171
Instructions Description
BY25Q256FS
Figure 206. Write Password Register (QPI Mode)
/CS
Mode 3
SCLK
0
3
2
1
17 Mode 3
Mode 0
Mode 0
Instruction
Password
28H
SI
(IO0)
SO
(IO1)
4
0
56
5
1
57
/WP
(IO2)
6
2
58
/HOLD
(IO3)
7
3
59
MSB
7.5.18 Password Unlock (29H)
The Password Unlock (29H) instruction with the correct password will set the SPB Lock Bit to “1”
and unlock the SPB bits.
Password Protection mode potentially provides a higher level of security than Sol id Protection
mode. In Password Protection mode, the SPB Lock Bit defaults to “0” after a power-on cycle or
reset. When SPB Lock Bit=0, the SPBs are locked and cannot be modified. A 64-bit password
must be provided to unlock the SPBs. After the correct password is given, a wait of 2us is
necessary for the SPB bits to unlock. The Status Register WIP bit will clear to “0” upon completion
of the Password Unlock instruction. Once unlocked, the SPB bits can be modified.
A Write Enable (06h) instruction must be executed to set the WEL bit before sending the Password
Unlock instruction.
See Figure 207-Figure 208, to give the correct password, the Password Unlock (29H) instruction
must be issued by driving /CS low, shifting the instruction code “ 29h” into the Data Input (SI or
IO0-IO3) pin on the rising edge of CLK followed by the 64-bit password, and then driving /CS high.
Figure 207. Password Unlock (SPI Mode)
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
69 70
10
SCLK Mode 0
Instruction
SI
29H
71 Mode 3
Mode 0
Password
7
6
5
58 57 56
MSB
SO
December 2020
High_Z
Rev 1.9
155 / 171
Instructions Description
BY25Q256FS
Figure 208. Password Unlock (QPI Mode)
/CS
Mode 3
SCLK
0
2
1
3
Mode 0
17 Mode 3
Mode 0
Instruction
Password
29H
SI
(IO0)
SO
(IO1)
4
0
56
5
1
57
/WP
(IO2)
6
2
58
/HOLD
(IO3)
7
3
59
MSB
December 2020
Rev 1.9
156 / 171
Electrical Characteristics
BY25Q256FS
8. Electrical Characteristics
8.1
Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage
VCC
Voltage Applied to Any Pin
VIO
Transient Voltage on any Pin
VIOT
Storage Temperature
TSTG
Electrostatic Discharge Voltage
VESD
Conditions
Range
Unit.
–0.5 to 4
V
Relative to Ground
–0.5 to 4
V
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