ADM3232EARNZ

UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers FEATURES ■ Meets true EIA/TIA-232-F Standards from a +3.0V to +5.5V power supply ■ Minimum 120Kbps Data Rate Under Full Load ■ 1µA Low-Power Shutdown with Receivers Active (ADM3222A) ■ Enhanced ESD Specifications: ±15kV Human Body Model ±15kV IEC1000-4-2 Air Discharge ±8kV IEC1000-4-2 Contact Discharge EN 18 SHDN 1 17 VCC C1+ 2 V+ 3 16 GND C1- 4 15 T1OUT C2+ 5 14 R1IN C2- 6 13 R1OUT 12 T1IN ADM3222A V- 7 T2OUT 8 11 T2IN R2IN 9 10 R2OUT SOP-18 DESCRIPTION The ADM3222A/3232E series is an RS-232 transceiver solution intended for portable or handheld applications such as notebook or palmtop computers. The ADM3222A/3232E series has a high-efficiency, charge-pump power supply that requires only 0.1µF capacitors in 3.3V operation.This charge pump allows the ADM3222A/3232E series to deliver true RS-232 performance from a single power supply ranging from +3.3V to +5.0V.The ADM3222A/3232E are 2-driver/2-receiver devices. This series is ideal for portable or handheld applications such as notebook or palmtop computers.The ESD tolerance of the ADM3222A/3232E devices are over ±15kV for both Human Body Model and IEC1000-4-2 Air discharge test methods.The ADM3222A device has a low-power shutdown mode where the devices' driver outputs and charge pumps are disabled.During shutdown, the supply current falls to less than 1µA. SELECTION TABLE MODEL Power Supplies RS-232 Drivers RS-232 Receivers External Components Shutdown TTL 3-State No. of Pins ADM3222A +3.0V to +5.5V 2 2 4 Yes Yes 18 ADM3232E +3.0V to +5.5V 2 2 4 No No 16 www.umw-ic.com 1 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers Input Voltages TxIN, EN ................................................... -0.3V to +6.0V RxIN .......................................................................... ±15V ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability and cause permanent damage to the device. Output Voltages TxOUT ...................................................................... ±15V RxOUT ........................................... -0.3V to (VCC + 0.3V) Short-Circuit Duration TxOUT ............................................................ Continuous VCC................................................................-0.3V to +6.0V V+ (NOTE 1)................................................-0.3V to +7.0V V- (NOTE 1)................................................+0.3V to -7.0V V+ + |V-| (NOTE 1)....................................................+13V Storage Temperature .............................. -65°C to +150°C Power Dissipation Per Package 18-pin SOP (derate 15.7mW/oC above +70oC) ... 1260mW 16-pin SOP (derate 13.57mW/°C above +70°C) .. 1086mW ICC (DC VCC or GND current).................................±100mA NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V. ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with TAMB = TMIN to TMAX PARAMETER MIN. TYP. MAX. UNITS CONDITIONS Supply Current 0.3 1.0 mA no load, TAMB = +25oC, VCC = 3.3V Shutdown Supply Current 1.0 10 µA SHDN = GND, TAMB = +25oC, VCC = +3.3V 0.8 V TxIN, EN, SHDN, Note 2 V VCC = 3.3V, Note 2 VCC = 5.0V, Note 2 DC CHARACTERISTICS LOGIC INPUTS AND RECEIVER OUTPUTS Input Logic Threshold LOW Input Logic Threshold HIGH 2.0 2.4 Input Leakage Current ± 0.01 ± 1. 0 µA TxIN, EN, SHDN, TAMB = +25oC Output Leakage Current ± 0.05 ± 10 µA receivers disabled 0. 4 Output Voltage LOW V IOUT = 1.6mA VCC-0.6 VCC-0.1 V IOUT = -1.0mA Output Voltage Swing ± 5.0 ± 5. 4 V 3kΩ load to ground at all driver outputs, TAMB = +25oC Output Resistance 300 Ω VCC = V+ = V- = 0V, TOUT = +2V Output Voltage HIGH DRIVER OUTPUTS Output Short-Circuit Current Output Leakage Current www.umw-ic.com ± 35 ± 70 ± 60 ± 100 mA mA VOUT = 0V VOUT = +15V ± 25 µA VOUT = +12V,VCC= 0V to 5.5V,drivers disabled 2 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers ELECTRICAL CHARACTERISTICS Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.0V with TAMB = TMIN to TMAX. Typical Values apply at VCC = +3.3V or +5.0V and TAMB = 25oC. PARAMETER MIN. TYP. MAX. UNITS +15 V CONDITIONS RECEIVER INPUTS Input Voltage Range -15 Input Threshold LOW 0.6 0.8 1.2 1.5 Input Threshold HIGH 1.5 1.8 Input Hysteresis 0.3 Input Resistance 2.4 2.4 V VCC=3.3V VCC=5.0V V VCC=3.3V VCC=5.0V V 3 5 7 kΩ 120 235 kbps Driver Propagation Delay 1.0 1.0 µs µs tPHL, RL = 3KΩ, CL = 1000pF tPLH, RL = 3KΩ, CL = 1000pF Receiver Propagation Delay 0.3 0.3 µs tPHL, RxIN to RxOUT, CL=150pF tPLH, RxIN to RxOUT, CL=150pF Receiver Output Enable Time 200 ns Receiver Output Disable Time 200 ns Driver Skew 100 500 ns | tPHL - tPLH |, TAMB = 25oC Receiver Skew 200 1000 ns | tPHL - tPLH | 30 V/µs TIMING CHARACTERISTICS Maximum Data Rate Transition-Region Slew Rate RL=3kΩ, CL=1000pF, one driver switching VCC = 3.3V, RL = 3KΩ, TAMB = 25oC, measurements taken from -3.0V to +3.0V or +3.0V to -3.0V NOTE 2: Driver input hysteresis is typically 250mV. www.umw-ic.com 3 友台半导体有限公司 R UMW ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120kbps data rates, all drivers loaded with 3kΩ, 0.1µF charge pump capacitors, and TAMB = +25°C. 14 12 4 10 Vout+ Vout- 2 Slew Rate [V/µs] Transmitter Output Voltage [V] 6 0 0 500 1000 1500 2000 -2 8 6 4 +Slew -Slew -4 2 -6 0 Load Capacitance [pF] 0 Figure 1. Transmitter Output Voltage VS. Load Capacitance for the ADM3222 and the ADM3232 500 1000 1500 Load Capacitance [pF] 2000 2330 Figure 2. Slew Rate VS. Load Capacitance for the ADM3222 and the ADM3232 50 118KHz 60KHz 10KHz 45 40 Supply Current [mA] 35 30 25 20 15 10 5 0 0 500 1000 1500 2000 2330 Load Capacitance [pF] Figure 3. Supply Current VS. Load Capacitance when Transmitting Data for the ADM3222 and the ADM3232 www.umw-ic.com 4 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers PIN NUMBER NAME FUNCTION ADM3222A ADM3232E EN Receiver Enable. Apply logic LOW for normal operation. Apply logic HIGH to disable the receiver outputs (high-Z state). 1 - C1+ Positive terminal of the voltage doubler charge-pump capacitor. 2 1 V+ +5.5V generated by the charge pump. 3 2 C1- Negative terminal of the voltage doubler charge-pump capacitor. 4 3 C2+ Positive terminal of the inverting charge-pump capacitor. 5 4 C2- Negative terminal of the inverting charge-pump capacitor. 6 5 V- -5.5V generated by the charge pump. 7 6 T1OUT RS-232 driver output. 15 14 T2OUT RS-232 driver output. 8 7 R1IN RS-232 receiver input. 14 13 R2IN RS-232 receiver input. 9 8 R1OUT TTL/CMOS reciever output. 13 12 R2OUT TTL/CMOS reciever output. 10 9 T1IN TTL/CMOS driver input. 12 11 T2IN TTL/CMOS driver input. 11 10 GND Ground. 16 15 +3.0V to +5.5V supply voltage 17 16 Shutdown Control Input. Drive HIGH for normal device operation. Drive LOW to shutdown the drivers (high-Z output) and the onboard power supply. 18 - - - VCC SHDN N.C. No Connect. Table 1. Device Pin Description www.umw-ic.com 5 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers EN 18 SHDN 1 C1+ 2 17 VCC V+ 3 16 GND C1- 4 15 T1OUT C2+ 5 14 R1IN C2- 6 13 R1OUT V- 7 12 T1IN T2OUT 8 11 T2IN R2IN 9 10 ADM3222A R2OUT SOP-18 Figure 4. Pinout Configurations for the ADM3222A 16 VCC C1+ 1 V+ 2 15 GND C1- 3 C2+ 4 C2- 5 12 R1OUT V- 6 11 T1IN T2OUT 7 10 R2IN 8 9 14 T1OUT ADM3232E 13 R1IN T2IN R2OUT SOP-16 Figure 5. Pinout Configuration for the ADM3232E www.umw-ic.com 6 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers VCC C5 C1 + + 17 VCC 0.1µF 2 C1+ 0.1µF V+ + 0.1µF LOGIC INPUTS ADM3222A C4 + 6 C212 T1IN T1OUT 15 11 T2IN T2OUT 8 R1IN 14 R2IN 9 0.1µF RS-232 OUTPUTS 5kΩ 10 R2OUT 0.1µF 7 V- SOP-18 13 R1OUT LOGIC OUTPUTS + *C3 4 C15 C2+ C2 3 RS-232 INPUTS 5kΩ 1 EN SHDN 18 GND *can be returned to either VCC or GND 16 Figure 6. ADM3222A Typical Operating Circuits VCC C5 C1 + + 1 C1+ 0.1µF C2 LOGIC INPUTS 0.1µF V+ *C3 ADM3232E V- C4 11 T1IN T1OUT 14 10 T2IN T2OUT 7 R1IN 13 R2IN 8 5kΩ 9 R2OUT + 0.1µF 6 5 C2- 12 R1OUT LOGIC OUTPUTS 2 3 C14 C2+ + 16 VCC 0.1µF + 0.1µF RS-232 OUTPUTS RS-232 INPUTS 5kΩ GND 15 *can be returned to either VCC or GND Figure 7. ADM3232E Typical Operating Circuit www.umw-ic.com 7 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers DESCRIPTION The slew rate of the driver output is internally limited to a maximum of 30V/µs in order to meet the EIA standards (EIA RS-232D 2.1.7, Paragraph 5). The transition of the loaded output from HIGH to LOW also meets the monotonicity requirements of the standard. The ADM3222A/3232E transceivers meet the EIA/ TIA-232 and V.28/V.24 communication protocols and can be implemented in battery-powered, portable, or hand-held applications such as notebook or palmtop computers. The ADM3222A/ 3232E devices all feature proprietary on-board charge pump circuitry that generates 2 x VCC for RS-232 voltage levels from a single +3.0V to +5.5V power supply. This series is ideal for +3.3V-only systems, mixed +3.3V to +5.5V systems, or +5.0V-only systems that require true RS-232 performance. The ADM3222A/ 3232E series have drivers that operate at a typical data rate of 235Kbps fully loaded. The ADM3222A/3232E drivers can maintain high data rates up to 235Kbps fully loaded. Figure 8 shows a loopback test circuit used to test the RS-232 drivers. Figure 9 shows the test results of the loopback circuit with all drivers active at 120Kbps with RS-232 loads in parallel with 1000pF capacitors. Figure 10 shows the test results where one driver was active at 235Kbps and all drivers loaded with an RS-232 receiver in parallel with a 1000pF capacitor. A solid RS-232 data transmission rate of 120Kbps provides compatibility with many designs in personal computer peripherals and LAN applications. The ADM3222A and ADM3232E are 2-driver/2-receiver devices ideal for portable or hand-held applications.The ADM3222A features a 1µA shutdown mode that reduces power consumption and extends battery life in portable systems. Its receivers remain active in shutdown mode, allowing external devices such as modems to be monitored using only 1µA supply current. The ADM3222A driver's output stages are turned off (tri-state) when the device is in shutdown mode. When the power is off, the ADM3222A device permits the outputs to be driven up to ±12V. The driver's inputs do not have pull-up resistors.Designers should connect unused inputs to VCC or GND. THEORY OF OPERATION The ADM3222A/3232E series are made up of three basic circuit blocks: 1. Drivers, 2. Receivers, and 3. the Sipex proprietary charge pump. In the shutdown mode, the supply current falls to less than 1µA, where SHDN = LOW. When the ADM3222A device is shut down, the device's driver outputs are disabled (tri-stated) and the charge pumps are turned off with V+ pulled down to VCC and V- pulled to GND. The time required to exit shutdown is typically 100µs. Connect SHDN to VCC if the shutdown mode is not used. SHDN has no effect on RxOUT or RxOUTB. As they become active, the two driver outputs go to opposite RS-232 levels where one driver input is HIGH and the other LOW. Note that the drivers are enabled only when the magnitude of V- exceeds approximately 3V. Drivers The drivers are inverting level transmitters that convert TTL or CMOS logic levels to ±5.0V EIA/TIA-232 levels inverted relative to the input logic levels. Typically, the RS-232 output voltage swing is ±5.5V with no load and at least ±5V minimum fully loaded. The driver outputs are protected against infinite short-circuits to ground without degradation in reliability. Driver outputs will meet EIA/TIA-562 levels of ±3.7V with supply voltages as low as 2.7V. The drivers typically can operate at a data rate of 235Kbps. The drivers can guarantee a data rate of 120Kbps fully loaded with 3KΩ in parallel with 1000pF, ensuring compatibility with PC-to-PC communication software. www.umw-ic.com 8 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers VCC C5 C1 + + 0.1µF VCC C1+ V+ 0.1µF + 0.1µF C3 C1- + C2 ADM3222A ADM3232E C2+ 0.1µF VC4 + C2TxOUT TxIN LOGIC INPUTS RxIN RxOUT LOGIC OUTPUTS 0.1µF 5kΩ EN *SHDN VCC GND 1000pF * ADM3222A only Figure 8. ADM3222A/3232E Driver Loopback Test Circuit [ T ] [ T T1 IN 1 T1 OUT 2 T T T T R1 OUT 3 R1 OUT 3 Ch1 5.00V Ch3 5.00V Ch2 5.00V M 5.00µs Ch1 Ch1 5.00V Ch3 5.00V 0V Figure 9. Driver Loopback Test Results at 120kbps www.umw-ic.com ] T T1 IN 1 T1 OUT 2 T Ch2 5.00V M 2.50µs Ch1 0V Figure 10. Driver Loopback Test Results at 235kbps 9 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers Receivers The receivers convert EIA/TIA-232 levels to TTL or CMOS logic output levels. All receivers have an inverting tri-state output. These receiver outputs (RxOUT) are tri-stated when the enable control EN = HIGH. In the shutdown mode, the receivers can be active or inactive. EN has no effect on TxOUT. The truth table logic of the ADM3222A/3232E driver and receiver outputs can be found in Table 2. Since receiver input is usually from a transmission line where long cable lengths and system interference can degrade the signal, the inputs have a typical hysteresis margin of 300mV. This ensures that the receiver is virtually immune to noisy transmission lines. Should an input be left unconnected, a 5kΩ pulldown resistor to ground will commit the output of the receiver to a HIGH state. Charge Pump The charge pump uses a unique approach compared to older less–efficient designs. The charge pump still requires four external capacitors, but uses a four–phase voltage shifting technique to attain symmetrical 5.5V power supplies. The internal power supply consists of a regulated dual charge pump that provides output voltages 5.5V regardless of the input voltage (VCC) over the +3.0V to +5.5V range. SHDN EN TxOUT RxOUT 0 0 Tri-state Active 0 1 Tri-state Tri-state 1 0 Active Active 1 1 Active Tri-state Table 2. Truth Table Logic for Shutdown and Enable Control www.umw-ic.com In most circumstances, decoupling the power supply can be achieved adequately using a 0.1µF bypass capacitor at C5 (refer to Figures 6 and 7). In applications that are sensitive to power-supply noise, decouple VCC to ground with a capacitor of the same value as charge-pump capacitor C1. Physically connect bypass capacitors as close to the IC as possible. The charge pumps operate in a discontinuous mode using an internal oscillator. If the output voltages are less than a magnitude of 5.5V, the charge pumps are enabled. If the output voltage exceed a magnitude of 5.5V, the charge pumps are disabled. This oscillator controls the four phases of the voltage shifting. A description of each phase follows. Phase 1 — VSS charge storage — During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. Cl+ is then switched to GND and the charge in C1– is transferred to C2–. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2 times VCC. Phase 2 — VSS transfer — Phase two of the clock connects the negative terminal of C2 to the VSS storage capacitor and the positive terminal of C2 to GND. This transfers a negative generated voltage to C3. This generated voltage is regulated to a minimum voltage of -5.5V. Simultaneous with the transfer of the voltage to C3, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND. Phase 3 — VDD charge storage — The third phase of the clock is identical to the first phase — the charge transferred in C1 produces –VCC in the negative terminal of C1, which is applied to the negative side of capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2 times VCC. 10 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers Phase 4 — VDD transfer — The fourth phase of the clock connects the negative terminal of C2 to GND, and transfers this positive generated voltage across C2 to C4, the VDD storage capacitor. This voltage is regulated to +5.5V. At this voltage, the internal oscillator is disabled. Simultaneous with the transfer of the voltage to C4, the positive side of capacitor C1 is switched to VCC and the negative side is connected to GND, allowing the charge pump cycle to begin again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. potential to store electro-static energy and discharge it to an integrated circuit. The simulation is performed by using a test model as shown in Figure 17. This method will test the IC’s capability to withstand an ESD transient during normal handling such as in manufacturing areas where the ICs tend to be handled frequently. The IEC-1000-4-2, formerly IEC801-2, is generally used for testing ESD on equipment and systems. For system manufacturers, they must guarantee a certain amount of ESD protection since the system itself is exposed to the outside environment and human presence. The premise with IEC1000-4-2 is that the system is required to withstand an amount of static electricity when ESD is applied to points and surfaces of the equipment that are accessible to personnel during normal usage. The transceiver IC receives most of the ESD current when the ESD source is applied to the connector pins. The test circuit for IEC1000-4-2 is shown on Figure 18. There are two methods within IEC1000-4-2, the Air Discharge method and the Contact Discharge method. Since both V+ and V– are separately generated from VCC; in a no–load condition V+ and V– will be symmetrical. Older charge pump approaches that generate V– from V+ will show a decrease in the magnitude of V– compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 0.1µF with a 16V breakdown voltage rating. ESD Tolerance With the Air Discharge Method, an ESD voltage is applied to the equipment under test (EUT) through air. This simulates an electrically charged person ready to connect a cable onto the rear of the system only to find an unpleasant zap just before the person touches the back panel. The high energy potential on the person discharges through an arcing path to the rear panel of the system before he or she even touches the system. This energy, whether discharged directly or through air, is predominantly a function of the discharge current rather than the discharge voltage. Variables with an air discharge such as approach speed of the object carrying the ESD potential to the system and humidity will tend to change the discharge current. For example, the rise time of the discharge current varies with the approach speed. The ADM3222A/3232E series incorporates ruggedized ESD cells on all driver output and receiver input pins. The ESD structure is improved over our previous family for more rugged applications and environments sensitive to electro-static discharges and associated transients.The improved ESD tolerance is at least ±15kV without damage nor latch-up. There are different methods of ESD testing applied: a) MIL-STD-883, Method 3015.7 b) IEC1000-4-2 Air-Discharge c) IEC1000-4-2 Direct Contact The Human Body Model has been the generally accepted ESD testing method for semiconductors. This method is also specified in MIL-STD883, Method 3015.7 for ESD testing. The premise of this ESD test is to simulate the human body’s www.umw-ic.com 11 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers VCC = +5V C4 +5V + C1 C2 – –5V + – – + VDD Storage Capacitor + – VSS Storage Capacitor C3 –5V Figure 12. Charge Pump — Phase 1 VCC = +5V C4 + C1 C2 – + – – + VDD Storage Capacitor + – VSS Storage Capacitor C3 –10V Figure 13. Charge Pump — Phase 2 [ T ] +6V a) C2+ T GND 1 GND 2 b) C2- T -6V Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 5.48V Figure 14. Charge Pump Waveforms VCC = +5V C4 +5V C1 + –5V – – + + C2 – + – VDD Storage Capacitor VSS Storage Capacitor C3 –5V Figure 15. Charge Pump — Phase 3 VCC = +5V C4 +10V C1 + – C2 + – – + + – VDD Storage Capacitor VSS Storage Capacitor C3 Figure 16. Charge Pump — Phase 4 www.umw-ic.com 12 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers R RSS R RC C SW2 SW2 SW1 SW1 Device Under Test C CSS DC Power Source Figure 17. ESD Test Circuit for Human Body Model The Contact Discharge Method applies the ESD current directly to the EUT. This method was devised to reduce the unpredictability of the ESD arc. The discharge current rise time is constant since the energy is directly transferred without the air-gap arc. In situations such as hand held systems, the ESD charge can be directly discharged to the equipment from a person already holding the equipment. The current is transferred on to the keypad or the serial port of the equipment directly and then travels through the PCB and finally to the IC. The circuit models in Figures 17 and 18 represent the typical ESD testing circuits used for all three methods. The CS is initially charged with the DC power supply when the first switch (SW1) is on. Now that the capacitor is charged, the second switch (SW2) is on while SW1 switches off. The voltage stored in the capacitor is then applied through RS, the current limiting resistor, onto the device under test (DUT). In ESD tests, the SW2 switch is pulsed so that the device under test receives a duration of voltage. Contact-Discharge Module RSS RC C SW2 SW1 DC Power Source RV Device Under Test CSS RS and RV add up to 330Ω for IEC1000-4-2. Figure 18. ESD Test Circuit for IEC1000-4-2 www.umw-ic.com 13 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers I➙ For the Human Body Model, the current limiting resistor (RS) and the source capacitor (CS) are 1.5kΩ an 100pF, respectively. For IEC-1000-4-2, the current limiting resistor (RS) and the source capacitor (CS) are 330Ω an 150pF, respectively. 30A 15A The higher CS value and lower RS value in the IEC1000-4-2 model are more stringent than the Human Body Model. The larger storage capacitor injects a higher voltage to the test point when SW2 is switched on. The lower current limiting resistor increases the current charge onto the test point. 0A t=0ns t➙ t=30ns Figure 19. ESD Test Waveform for IEC1000-4-2 Device Pin Tested Human Body Model Air Discharge Driver Outputs Receiver Inputs ±15kV ±15kV ±15kV ±15kV IEC1000-4-2 Direct Contact ±8kV ±8kV Level 4 4 Table 3. Transceiver ESD Tolerance Levels www.umw-ic.com 14 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers PACKAGE: SOP-18 UNIT: mm D SYMBOL A2 A 0.25 L A1 MILLIMETER MILLIMETER MIN MIN NOM NOM MAX MAX A 2.65 A1 0.10 A2 2.20 b 0.35 c 0.25 D 11.35 11.45 11.55 E 10.10 10.30 10.50 E1 7.40 7.50 7.60 e L 0.30 2.30 2.40 0.43 0.29 1.27BSC 0.70 1.00 E1 E e b PACKAGE: SOP-16 UNIT: mm L E E1 b e c SYMBOL MILLIMETER MIN NOM MAX A 1.80 A1 0.10 0.15 0.25 A2 1.25 1.45 1.65 b 0.33 c 0.17 0.25 D 9.50 10.20 E 5.80 E1 3.70 e L 0.51 6.00 6.20 4.10 1.27BSC 0.45 0.60 0.80 D A2 A A1 www.umw-ic.com 15 友台半导体有限公司 UMW R ADM3222A/3232E True +3.0V to +5.5V RS-232 Transceivers Ordering information Order code UMW ADM3222ARWZ Package SOP-18 Baseqty 2000 Deliverymode Tape and reel UMW ADM3232EARNZ SOP-16 2500 Tape and reel www.umw-ic.com 16 Operating temperature range -40°- +85° 友台半导体有限公司