ESD9B5VDA-2/TR

ESD9B5VDA ESD9B5VDA 1-Line, Low capacitance, Bi-directional http//:www.sh-willsemi.com Transient Voltage Suppressors Descriptions The ESD9B5VDA is a transient voltage suppressor (TVS) which provide a very high level protection for sensitive electronic components that may be subjected SOD-923 to electrostatic discharge (ESD). It is designed to replace multilayer equipment varistors applications (MLV) in as mobile such consumer phone, notebook, PAD, STB, LCD TV etc. The ESD9B5VDA may be used to provide ESD Circuit Diagram protection up to ±20kV (contact and air discharge) according to IEC61000-4-2 and withstand peak pulse current up to 5A (8/20μs) according to IEC61000-4-5. 9C The ESD9B5VDA is available in SOD-923 package. Standard products are Pb-free and Halogen-free. 9C Features  Reverse stand-off voltage: ±5V Max.  Transient protection for each line according to = Device code Marking Order information IEC61000-4-2 (ESD): ±20kV (Contact and Air) IEC61000-4-4 (EFT): 40A (5/50ns) IEC61000-4-5 (surge): 5A (8/20μs)  Capacitance: CJ = 13pF typ.  Leakage current: IR < 1µA typ.  Low clamping voltage  Small Package SOD-923 Device ESD9B5VDA-2/TR Package Shipping SOD-923 10000/Tape&Reel Applications  Mobile phone  PAD  Notebook  LCD TV  Other electronics equipment Will Semiconductor Ltd. 1 Revision 2.2, 2018/01/08 ESD9B5VDA Absolute maximum ratings Parameter Symbol Rating Unit Peak pulse power (tp = 8/20μs) Ppk 50 W Peak pulse current (tp = 8/20μs) IPP 5 A ESD according to IEC61000-4-2 air discharge ±20 VESD KV ESD according to IEC61000-4-2 contact discharge ±20 TJ 125 o Operating temperature TOP -40~85 o Lead temperature TL 260 o TSTG -55~150 o Junction temperature Storage temperature C C C C Electronics characteristics (TA = 25 oC, unless otherwise noted) Parameter Symbol Condition Reverse stand-off voltage VRWM Reverse leakage current IR VRWM = 5V Reverse breakdown voltage Min. Unit ±5 V 1 µA 9.0 V VBR IBR = 1mA Clamping voltage VCL IPP = 16A, tp = 100ns 10 V Clamping voltage 2) VCL VESD = 8kV 11 V Clamping voltage 3) VCL 1) Junction capacitance Ipp = 1A, tp = 8/20μs 7.5 V Ipp = 5A, tp = 8/20μs 10 V RDYN CJ 7.5 Max. 1) Dynamic resistance 5.8 Typ. Ω 0.2 VR = 0V, f = 1MHz 13 16 pF Notes: 1) TLP parameter: Z0 = 50Ω, tp = 100ns, tr = 2ns, averaging window from 60ns to 80ns. RDYN is calculated from 4A to 16A. 2) Contact discharge mode, according to IEC61000-4-2. 3) Non-repetitive current pulse, according to IEC61000-4-5. Will Semiconductor Ltd. 2 Revision 2.2, 2018/01/08 ESD9B5VDA o 100 90 Front time: T1= 1.25 T = 8s 100 90 Time to half-value: T2= 20s Current (%) Peak pulse current (%) Typical characteristics (Ta=25 C, unless otherwise noted) 50 T2 10 10 0 0 tr = 0.7~1ns Time (s) T1 8/20μs waveform per IEC61000-4-5 C - Junction capacitance (pF) VC - Clamping voltage (V) Pulse waveform: tp=8/20us 10 8 6 0 1 2 3 4 5 Time (ns) Contact discharge current waveform per IEC61000-4-2 12 4 t 60ns 30ns 20 T 20 15 10 5 f = 1MHz VAC = 50mV 0 6 0 1 2 3 4 Ipp - Peak pulse current (A) VR - Reverse voltage (V) Clamping voltage vs. Peak pulse current Capacitance vs. Reverse voltage 5 1000 % of Rated power Peak Pulse Power (W) 100 100 10 1 80 60 40 20 0 1 10 100 Pulse Time(μs) 1000 25 50 75 100 125 150 o TA - Ambient temperature ( C) Non-repetitive peak pulse power vs. Pulse time Will Semiconductor Ltd. 0 Power derating vs. Ambient temperature 3 Revision 2.2, 2018/01/08 ESD9B5VDA o Typical characteristics (Ta=25 C, unless otherwise noted) ESD clamping ESD clamping (+8kV contact discharge per IEC61000-4-2) (-8kV contact discharge per IEC61000-4-2) 20 TLP current (A) 16 12 8 4 0 -4 -8 Z0 = 50 -12 tr = 2ns -16 tp = 100ns -20 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 TLP voltage (V) TLP Measurement Will Semiconductor Ltd. 4 Revision 2.2, 2018/01/08 ESD9B5VDA Package outline dimensions SOD-923  b D R E E1 A1 c A Symbol θ Dimensions in millimeter Min. Typ. Max. A - 0.42 0.45 A1 0.00 - 0.05 b 0.15 0.20 0.25 c 0.07 0.12 0.17 D 0.55 0.60 0.65 E 0.95 1.00 1.05 E1 0.75 0.80 0.85 o θ R Recommend PCB Layout (Unit: mm) 0.60 6 Ref. - - 0.12 0.30 0.40 Notes: This recommended land pattern is for reference purposes only. Please consult your manufacturing group to ensure your PCB design guidelines are met. Will Semiconductor Ltd. 5 Revision 2.2, 2018/01/08