Embedded Nano SD NAND Flash
MKDNXXXCL-XX
Commercial Grade Specification
Preliminary
Ver.1.0
Oct.2020
-1-
Nano SD NAND
Revision History
Date
Rev.
2020/10/31
1.0
Description
Original version
-2-
Nano SD NAND
CONTENTS
1. Introduction............................................................................................................................................................. . - 1 2. Product List ............................................................................................................................................................. - 1 3. Features........................................................................................................................................................................ 1
4. Physical Characteristics..............................................................................................................................................2
4.1. Temperature.......................................................................................................................................................2
5. Pin Assignments(SD Mode& SPI Mode)................................................................................................................. 2
6. Usage.............................................................................................................................................................................3
6.1 SD Bus Mode protocol...................................................................................................................................... 3
6.2. Card Initialize.....................................................................................................................................................5
6.3 DC Characteristics............................................................................................................................................7
7. Internal Information......................................................................................................................................................8
7.1 Registers............................................................................................................................................................. 8
7.1.1 OCR Register..................................................................................................................................................9
7.1.2. CID Register.................................................................................................................................................10
7.2.3. CSD Register............................................................................................................................................... 11
7.1.4. RCA Register............................................................................................................................................... 12
7.1.5. DSR Register............................................................................................................................................... 12
8. Power Scheme........................................................................................................................................................... 13
8.1. Power Up......................................................................................................................................................... 13
8.2 Power Up Time................................................................................................................................................ 13
8.2.1 Power On or Power Cycle...........................................................................................................................14
8.2.2 Power Supply Ramp Up.............................................................................................................................. 14
8.2.3 Power Supply Ramp Up.............................................................................................................................. 14
9. Package Dimensions.................................................................................................................................................15
10. Reference Design.................................................................................................................................................... 16
-3-
Nano SD NAND
Preliminary
1. Introduction
MK Nano SD NAND is an embedded storage solution designed in a LGA package form. The
operation of SD is similar to an SD card which is an commercial standard.
Nano SD NAND consists of NAND flash and a high performance controller. 3.3V supply voltage is
required for the NAND area (VCC).
Nano SD NAND is fully compliant with SD3.0 interface, which allows most of general CPU to utilize.
Nano SD NAND has high performance at a competitive cost, high quality and low power
consumption.
2. Product List
Part No.
Capacity
Package
Size
MKDN032GCL-AA
MKDN064GCL-AA
MKDN128GCL-AA
MKDN128GCL-ZA
MKDN256GCL-ZA
MKDN512GCL-ZA
32Gb
64Gb
128Gb
128Gb
256Gb
512Gb
LGA-8
LGA-8
LGA-8
LGA-8
LGA-8
LGA-8
9x12.5mm
9x12.5mm
9x12.5mm
9x12.5mm
9x12.5mm
9x12.5mm
3. Features
Support up to 208MHz clock frequency
SD-protocol compatible
Supports SPI Mode
Built-in HW ECC Engine and highly reliable NAND management mechanism
Write speed up to class 10
Smaller package LGA-8
-1-
Nano SD NAND
4. Physical Characteristics
4.1. Temperature
1) Operation Conditions
Temperature Range:
Ta = -25 to 85 degrees centigrade
2) Storage Conditions
Temperature Range: Tstg = −55 to 150 degrees centigrade
5. Pin Assignments(SD Mode& SPI Mode)
TOP VIEW
a. Type Key: S=power supply; I= input; O=output using push-pull drivers; PP=I/O using push-pull drivers.
b. The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after the
SET_BUS_WIDTH Type Key: S=power supply; I=input; O=output using push-pull drivers; PP=I/O using push-pull
drivers.
c. At power up this line has a 50 kilohm pull-up enabled in the card. This resistor serves two functions: Card
detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select
SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that
the line is pulled high. This pull-up should be disconnected by the user, during regular data transfer, with
SET_CLR_CARD_DETECT (ACMD42) command.
2
Nano SD NAND
6. Usage
6.1 SD Bus Mode protocol
The SD bus allows the dynamic configuration of the number of data line from 1 to 4 Bi-directional data
signal. After power up by default, the SD card will use only DAT0. After initialization, host can change
the bus width.
Multiplied SD cards connections are available to the host. Common VDD, VSS and CLK signal
connections are available in the multiple connections. However, Command, Respond and Data lined
(DAT0-DAT3) shall be divided for each device from host.
This feature allows easy trade off between hardware cost and system performance. Communication
over the SD bus is based on command and data bit stream initiated by a start bit and terminated by
stop bit.
Command: Commands are transferred serially on the CMD line. A command is a token to starts an
operation from host to the device. Commands are sent to an addressed single card (addressed
Command) or to all connected cards (Broad cast command).
Response:Responses are transferred serially on the CMD line.
A response is a token to answer to a previous received command. Responses are sent from an
addressed single card or from all connected cards.
Data:Data can be transfer from the card to the host or vice versa. Data is transferred via the data
lines.
3
Nano SD NAND
SD NAND (A)
CLK
CMD
DAT0 - DAT3
VDD
VSS
Host card Clock signal
Bi-directional Command/ Response Signal
4 Bi-directional data signal
Power supply
GND
4
Nano SD NAND
6.2. Card Initialize
To initialize the SD NAND, follow the following procedure is recommended example.
1) Supply Voltage forinitialization.
Host System can apply the Operating Voltage from initialization to the card. Apply more than 74
cycles of Dummy-clock to the SD card.
2) Select operation mode (SD mode or SPI mode)
In case of SPI mode operation, host should drive 1 pin (CD/DAT3) of SD Card I/F to “Low” level.
Then, issue CMD0. In case of SD mode operation, host should drive or detect 1 pin of SD Card I/F
(Pull up register of 1 pin is pull up
to “High” normally).
Card maintain selected operation mode except re-issue of CMD0 or power on below is SD mode
initialization procedure.
3) Send the ACMD41 with Arg = 0 and identify the operating voltage range of the Card.
4) Apply the indicated operating voltage to the card.
Reissue ACMD41 with apply voltage storing and repeat ACMD41 until the busy bit is cleared. (Bit 31
Busy = 1) If response time out occurred, host can recognize not SD Card.
5) Issue the CMD2 and get the Card ID (CID).
Issue the CMD3 and get the RCA. (RCA value is randomly changed by access, not equal zero)
6) Issue the CMD7 and move to the transfer state.
If necessary, Host may issue the ACMD42 and disabled the pull up resistor for Card detect.
7) Issue the ACMD13 and poll the Card status as SD Memory Card. Check SD_CARD_TYPE value.
If significant 8 bits are “all zero”, that means SD Card. If it is not, stop initialization.
8) Issue CMD7 and move to standby state. Issue CMD9 and get CSD.
Issue CMD10 and get CID.
9) Back to the Transfer state with CMD7.
Issue ACMD6 and choose the appropriate bus-width.
Then the Host can access the Data between the SD card as a storage device.
5
Nano SD NAND
Normal SD initial flow
Power-on
CMD0
No Response
CMD8
Card returns response
Ver2.00 or later
SD Memory Card
Ver2.00 or later SD Memory Card
(voltage mismatch)
Or Ver1.X SD Memory Card
Or not SD Memory Card
ACMD41
with HCS=0
No Response
Valid
Response ?
Card returns
busy
Card with compatible
Voltage range
Card is
ready ?
Cards with non compatible
voltage range(card goes to
‘ina’ state) or timeout (no
responseorbusy)occurs Card returnsready
Unusable
Card
Compatible voltage range
and check pattern is correct
If host supports high capacity,
HCS is set to 1
ACMD41
with HCS=0 or 1
Card returns
busy
Unusable
Card
Non-compatible voltage range
or check pattern is not correct
Cards with non compatible voltage range
or time out ( no response or busy ) occurs
Unusable
Card
Card is
ready ?
Card returns ready
CCS in
ready ?
Not SD Memory
Card
CCS=0
Ver2.00 or later
Standard Capacity
SD Memory Card
Ver1.X Standard
Capacity SD
Memory Card
No
CCS=1
Ver2.00 or later
High Capacity
SD Memory Card
CMD2
Get CID
CMD3
Get RCA
CMD7
Choose card with RCA
ACMD42
Disable the Pull-up Resister
(If necessary)
ACMD3
Get SD status
Memory
Card ?
Yes
Other SD Card
(SD IO or Others)
CMD7
Idle state with RCA=0000
CMD9
Get CSD
CMD10
Get CID
CMD7
Choose card with RCA
ACMD6
Choose Data Bus Width
Transfer mode
SD card Initialize Procedure
6
Data Access Enable
Nano SD NAND
7.1.4. RCA Register
SD3.0 initial flow for UHS-I(IO 1.8v) switch
7
Nano SD NAND
6.3 DC Characteristics
Item
Symbol
VDD
Supply Voltage
High Level VIH
Input
VIL
Voltage Low Level
V
OH
High Level
Output
V
OL
Voltage Low Level
Standby Current
ICC1
Operation Write
Current (*) Read
Input Voltage Setup Time
ICC2
Vrs
DC Characteristics
MIN.
MAX.
2.7
3.6
VDD+0.3
VDD×0.625
VSS-0.3
VDD×0.25
VDD×0.75
－
－
VDD×0.125
－
0.25 (32Gb)
0.05
－
30 (32Gb)
28 (32Gb)
250
－
－
－
Unit
V
V
V
V
V
mA
mA
Note
IOH = -2mA , VDD=VDD min
IOL = 2mA , VDD=VDD min
VDD = 3.6V , Clock 25MHz
VDD = 3.3V, Clock STOP,
Ta=25℃
3.3V / 25MHz, 50MHz
ms From 0V to VDD min
*) Peak Current: RMS value over a 10usec period
Item
Symbol
Peak voltage on all lines
Input Leakage Current
for all pins
Output Leakage
Current for all outputs
Item
Pull up Resistance
Total bus capacitance
for each signal line
Card capacitance
for signal pin
Pull up Resistance
inside card ( pin1)
Capacity Conneted to
Power line
Symbol
RCMD
RDAT
CL
Peak Voltage and Leak Current
Min.
Max.
Unit
-0.3
VDD+0.3
V
-10
10
-10
10
Signal Capacitance
Min.
Max.
uA
uA
Unit
10
100
kΩ
─
40
pF
CCAR
D
RDAT3
─
10
pF
10
90
CC
kΩ
─
5
uF
7
Note
Note
1 card
CHOST+CBUS≦30pF
Nano SD NAND
7. Internal Information
7.1 Registers
The Nano SD NAND has six registers and SD Status information: OCR, CID, CSD, RCA,
DSR, SCR and SD Status. DSR IS NOT SUPPORTED in this card.
There are two types of register groups.
MMC compatible registers: OCR, CID, CSD, RCA, DSR, and SCR SD card Specific: SD Status
Resister
Name Bit Width
OCR
32
CID
128
CSD
128
RCA
16
DSR
16
SCR
64
SD Status 512
SD card Registers
Description
Operation Conditions (VDU Voltage Profile and Busy Status
Card Identification information
Card specific information
Relative Card Address
Not Implemented (Programmable Card Driver): Driver Stage Register
SD Memory Card‟s special features
Status bits and Card features
8
Nano SD NAND
7.1.1 OCR Register
This 32-bit register describes operating voltage range and status bit in the power supply.
OCR register definition
OCR
bit
31
VDD voltage window
Card power up status bit(busy)
Initial
32Gb
64Gb
“0” = busy
“1” =
“0”= SD Memory
Card
All „0‟
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
All „0‟
30
Card Capacity Status
29-25 reserved
24
Switching to 1.8V Accepted(S18A)
23
3.6 - 3.5
22
3.5 - 3.4
21
3.4 - 3.3
20
3.3 - 3.2
19
3.2 - 3.1
18
3.1 - 3.0
17
3.0 - 2.9
16
2.9 - 2.8
15
2.8 - 2.7
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
Reserved
7
Reserved for Low Voltage Range
6
Reserved
5
Reserved
4
Reserved
3-0
reserved
bit 23-4: Describes the SD Card Voltage
bit 31 indicates the card power up status. Value “1” is set after power up and initialization procedure
has been completed.
9
Nano SD NAND
7.1.2. CID Register
The CID (Card Identification) register is 128-bit width. It contains the card identification information.
(Refer Appendix 3. for the detail) The Value of CID Register is vender specific.
Table 11: CID
Register
Initial Value
32Gb
64Gb
MID
8
[127:120]
TB
OID
16 [119:104]
TBD
PNM
40 [103:64] TBD
TBD
TBD
-PRV
8
[63:56]
TB
PSN
32 [55:24]
(a) (Product serial number)
4
[23:20]
All “0b”
MDT
12 [19:8]
(a) (Manufacture date)
CRC
7
[7:1]
(b) (CRC)
1
[0:0]
1b
(a) : Depends on the SD Card. Controlled by Production Lot.
(b) Depends on the CIDRegister
Field
Width CID-slice
10
Nano SD NAND
7.2.3. CSD Register
CSD is Card-Specific Data register provides information on 128bit width. Some field of this register
can writable by PROGRAM_CSD (CMD27).
Field
CSD_STRUCTURE
TAAC
NSAC
TRAN_SPEED
CCC
READ_BL_LEN
READ_BL_PARTIAL
WRITE_BLK_MISALIG
READ_BLK_MISALIGN
DSR_IMP
C_SIZE
ERASE_BLK_EN
SECTOR_SIZE
WP_GRP_SIZE
WP_GRP_ENABLE
R2W_FACTOR
WRITE_BL_LEN
WRITE_BL_PARTIAL
FILE_FORMAT_GRP
COPY
PERM_WRITE_PROTE
TMP_WRITE_PROTEC
FILE_FORMAT
CRC
-
CSD Register
Initial Value
Cell
CSD
Width
32Gb
64Gb
Slice
Type
2
R
[127:126]
01b
6
R
[125:120]
All “0b”
8
R
[119:112]
0_0001_110b (1ms)
8
R
[111:104]
00000000
8
R
[103:96]
0_0110_010b
12
R
[95:84]
0101_1011_0101
4
R
[83:80]
1001b
1
R
[79:79]
0b
1
R
[78:78]
0b
1
R
[77:77]
0b
1
R
[76:76]
0b
6
R
[75:70]
All “0b”
22
R
[69:48]
TBD
TBD
TBD
1
R
[47:47]
0b
1
R
[46:46]
1b
7
R
[45:39]
11_1111_1
7
R
[38:32]
000_0000
1
R
[31:31]
0b
2
R
[30:29]
00b
3
R
[28:26]
010b
4
R
[25:22]
1001b
1
R
[21:21]
0b
2
R
[20:16]
All “0b”
R
1
(1 [15:15]
0b
R/W
1
0b
(1 [14:14]
1
R/W [13:13]
0b
1
R/W [12:12]
0b
2
R
[11:10]
00b
2
R
[9:8]
All “0b”
7
R/W [7:1]
(CRC)
1
[0:0]
1b
(1)
R/W: Writable and Readable, R/W : One-time Writable / Readable
--
Cell Type: R: Read Only,
Note: Erase of one data block is not allowed in this card. This information is indicated by “ERASE_BLK_EN”.
Host System should refer this value before one data block size erase.
11
Nano SD NAND
7.1.4. RCA Register
The writable 16bit relative card address register carries the card address in SD Card mode.
7.1.5. DSR Register
This register is not implemented on this car
12
Nano SD NAND
8. Power Scheme
8.1. Power Up
'Power up time' is defined as voltage rising time from 0 volt to VDD min.
'Supply ramp up time' provides the time that the power is built up to the operating level
(Host Supply Voltage) and the time to wait until the Nano SD NAND can accept the first
command,
The host shall supply power to the card so that the voltage is reached to Vdd_min within
250ms and start to supply at least 74 SD clocks to the Nano SD NAND with keeping CMD
line to high.
8.2 Power Up Time
Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up.
13
Nano SD NAND
8.2.1 Power On or Power Cycle
Followings are requirements for Power on and Power cycle to assure a reliable Tailor™ SD
hard reset.
(1) Voltage level shall be below 0.5V
(2) Duration shall be at least 1ms.
8.2.2 Power Supply Ramp Up
The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage
which is stable between VDD(min.) and VDD(max.) and host can supply SDCLK.
Followings are recommendation of Power ramp up:
(1) Voltage of power ramp up should be monotonic as much as possible.
(2) The minimum ramp up time should be 0.1ms.
(3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply.
8.2.3 Power Supply Ramp Up
When the host shuts down the power, the VDD shall be lowered to less than 0.5Volt for a minimum
period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to
logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines.
If the host needs to change the operating voltage, a power cycle is required. Power cycle means
the power is turned off and supplied again. Power cycle is also needed for accessing cards that are
already in Inactive State. To create a power cycle the host shall follow the power down description
before power up the card (i.e. the VDD shall be once lowered to less than 0.5Volt for a minimum
period of 1ms).
14
Nano SD NAND
9. Package Dimensions
15
Nano SD NAND
10. Reference Design
RDAT and RCMD (10K~100 kΩ) are pull-up resistors protecting the CMD and the
DAT lines against bus floating when Nano SD NAND is in a high-impedance mode.
The host shall pull-up all DAT0-3 lines by RDAT, even if the host uses the Nano SD
NAND as 1 bit mode-only in SD mode. It is recommended to have 2.2uF capacitance on
VDD.
Rclk reference 0~120 Ω
16
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