SCT51240TWBR

SILICON CONTENT TECHNOLOGY SCT51240 Rev 1.0 - 2018 Up to 24V Supply, 4-A Single Channel High Speed Low Side Driver FEATURES             DESCRIPTION Wide Supply Voltage Range: 4.5V - 24V 4A Peak Source Current and 4A Peak Sink Current Dual Input Configuration: Non-Inverting (IN+) or Inverting (IN-) Input Negative Input Voltage Capability: Down to -5V TTL Input-Logic Threshold Propagation Delay: 12ns Fast Rising and Falling Time: 9ns and 6ns Low Quiescent Current: 38uA Under Voltage Lock Out Protection of Supply Voltage Output Low When Input Floating Thermal Shutdown Protection: 170°C Available in TSOT23-5L Package APPLICATIONS      The SCT51240 is a wide supply, single channel, high speed, low side gate driver for power MOSFET, IGBT, and wide band-gap device such as GaN. The 24V power supply rail enhances the driver output ringing endurance during the power device transition. The capability to switch below 5V power supply makes the SCT51240 work well for the low voltage threshold power device. The SCT51240 can source and sink 4A peak current along with rail-to-rail output driving capability. The minimum 12ns input to output propagation delay enables it suitable for high frequency power converter application. The SCT51240 features wide input hysteresis that is compatible for TTL low voltage logic. The SCT51240 has the capability to handle negative input down to -5V, which enhances the input noise immunity. The IN+ and IN- input provides the flexibility to configure the SCT51240 either as non-inverting or inverting driver. The SCT51240 has very low quiescent current that reduces the stand by power loss in the power converter. The SCT51240 gate driver adopts nonoverlap driver design to avoid the shoot-through of output stage. Power MOSFET Gate Driver IGBT Gate Driver GaN Device Gate Driver Switching Power Supply Motor Control, Solar Power The SCT51240 features 170°C thermal shut down protection and operates over a wide temperature range -40°C to 150°C. The SCT51240 is available in TSOT23-5L package. TYPICAL APPLICATION SCT51240 Typical Application RG VDD VDD C1 Application Waveform OUT C2 GND IN+ IN- For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 1 SCT51240 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Revision 1.0 Released to Production. DEVICE ORDER INFORMATION PART NUMBER PACKAGE MARKING PACKAGE DISCRIPTION SCT51240TWB 1240 TSOT23-5 1）For Tape & Reel, Add Suffix R (e.g. SCT51240TWBR). ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Over operating free-air temperature unless otherwise noted(1) Top View: TSOT23-5pin Plastic DESCRIPTION MIN MAX UNIT IN+, IN- -5 26 V VDD 1 OUT -0.3 26 V GND 2 VDD -0.3 26 V IN+ 3 Operating junction temperature TJ (2) -40 150 °C Storage temperature TSTG -65 150 °C (1) (2) 5 OUT 4 IN- Stresses beyond those listed under Absolut Maximum Rating may cause device permanent damage. The device is not guaranteed to function outside of its Recommended Operation Conditions. The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will reduce lifetime PIN FUNCTIONS NAME 2 NO. VDD 1 GND 2 IN+ 3 IN- 4 OUT 5 PIN FUNCTION Power supply of gate driver, must be decoupled by ceramic cap. A 0.1uF, and 1uF or 10uF are recommended. Power ground. Must be soldered directly to ground planes for improved thermal performance and electrical contact. Non-inverting logic input, TTL compatible. Floating logic low. In Non-Inverting configuration, apply PWM signal on IN+. In inverting configuration, connect IN+ to VDD. Inverting logic input, TTL compatible. Floating logic low. In Non-Inverting configuration, connect IN- to GND. In inverting configuration, apply PWM signal on IN-. Gate driver output. For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved SCT51240 RECOMMENDED OPERATING CONDITIONS Over operating free-air temperature range unless otherwise noted PARAMETER VDD VIN+,INTJ DEFINITION Supply voltage range Input voltage range Operating junction temperature MIN MAX UNIT 4.5 -5 -40 24 24 150 V V °C MIN MAX UNIT -2 +2 kV -1 +1 kV ESD RATINGS PARAMETER VESD (1) DEFINITION Human Body Model (HBM), per ANSI-JEDEC-JS-0012014 specification, all pins (1) Charged Device Model (CDM), per ANSI-JEDEC-JS-0022014 specification, all pins (1) HBM and CDM stressing are done in accordance with the ANSI/ESDA/JEDEC JS-001-2014 specification THERMAL INFORMATION PARAMETER THERMAL METRIC TSOT23-5 RθJA Junction to ambient thermal resistance (1) 89 RθJC Junction to case thermal resistance (1) 39 UNIT °C/W (1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit board (PCB) on which the SCT51240 is mounted, and external environmental factors. The PCB board is a heat sink that is soldered to the leads and thermal pad of the SCT51240. Changing the design or configuration of the PCB board changes the efficiency of the heat sink and therefore the actual RθJA and RθJC. For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 3 SCT51240 ELECTRICAL CHARACTERISTICS VDD=12V, TJ=-40°C~125°C, typical values are tested under 25°C. SYMBOL PARAMETER TEST CONDITION Power Supply and Output VDD Operating supply voltage MIN TYP 4.5 4.5 V mV uA Quiescent current INPUTS VIN+ Input+ logic high threshold VIN+ Input+ logic low threshold VIN+_Hys Hysteresis 1.1 VIN-_H Input- logic high threshold 2.1 VIN-_L Input- logic low threshold VIN-_Hys Hysteresis OUTPUTS VDD_VOH Output High Voltage (only PMOS ON) IOUT=10mA 150 mV VOL Output Low Voltage IOUT=10mA 10 mV ISINK/SRC CLoad=10nF, Fsw=1kHz ROL Output Sink/Source peak current Output pull high resistance (only PMOS ON) Output pull low resistance Timing TR Output rising time CLoad=1nF 9 20 ns Output falling time IN+ to output propagation delay, Rising edge IN+ to output propagation delay, Falling edge IN- to output propagation delay, Rising IN- to output propagation delay, Falling Minimum input pulse width CLoad=1nF 6 20 ns 12 25 ns 12 25 ns 12 25 ns 12 25 ns CLoad=1nF 20 30 ns Thermal shutdown threshold TJ rising 170 °C 25 °C TD_INTMIN_ON 120 V IQ TD_IN+ IN+=IN-=GND, VDD=12V 24 Input UVLO Hysteresis TF IN+=IN-=GND, VDD=3.5V 4.2 300 38 UNIT VDD_UVLO ROH VDD rising MAX 2.1 0.8 uA 2.4 1.0 0.8 V V V 2.4 V 1.0 V 1.1 V 4 A IOUT= - 10mA 8.5 Ω IOUT= 10mA 0.6 Ω Protection TSD 4 Hysteresis For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved SCT51240 TYPICAL CHARACTERISTICS 4.5 200.0 4.4 180.0 VDD=3.5V 160.0 VDD=12V 4.3 Start up Current (uA) Supply Voltage (v) VDD=12V, TA= 25°C. 4.2 4.1 4.0 3.9 3.8 3.7 UVLO_Rise 3.6 UVLO_Fall 140.0 120.0 100.0 80.0 60.0 40.0 3.5 20.0 -50 0 50 100 150 -50 0 Temperature (ºC) Figure 1. UVLO Vs Temperature 100 150 Figure 2. Start-up current Vs Temperature 20.0 2.5 18.0 Delay Time (ns) 2.0 IN Voltage (v) 50 Temperature (ºC) 1.5 1.0 IN+ High IN+ Low 0.5 16.0 14.0 12.0 Input to Output High 10.0 Input to Output Low 0.0 8.0 -50 0 50 100 150 -50 0 Figure 3. IN Threshold Vs Temperature 9.0 Falling Time (ns) 9.0 Rising Time (ns) 10.0 8.0 7.0 6.0 COUT=1nF 0 50 150 100 COUT=1nF 8.0 7.0 6.0 5.0 4.0 -50 100 Figure 4. Input to Output Propagation Delay vs Temperature 10.0 5.0 50 Temperature (ºC) Temperature (ºC) 150 4.0 -50 Temperature (ºC) Figure 5. Output Rising Time Vs Temperature 0 50 100 150 Temperature (ºC) Figure 6. Output Falling Time Vs Temperature For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 5 SCT51240 2.0 Pull Down Resistance (Ω) Pull Up Resistance (Ω) 15.0 13.0 11.0 9.0 7.0 ROH 1.5 1.0 0.5 ROL 0.0 5.0 -50 0 50 100 150 -50 Temperature (ºC) Figure 7. ROH vs Temperature 6 For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 0 50 100 Temperature (ºC) Figure 8. ROL Vs Frequency All Rights Reserved 150 SCT51240 FUNCTIONAL BLOCK DIAGRAM VDD 400k IN- 4 UVLO 1 VDD 5 OUT Thermal Sensor IN+ 2 1M 500k GND 3 For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 7 SCT51240 OPERATION Overview The SCT51240 is a up to 24V wide supply, single channel, high speed, low side gate driver for power MOSFET and IGBT. The SCT51240 can source and sink 4A peak current along with the minimum propagation delay 12ns from input to output. The ability to handle -5V DC input increases the driver input stage noise immunity, the 24V rail-to-rail output improves the SCT51240 output stage robustness during the switching load fast transition. The SCT51240 features a dual-input design by implementing both inverting (IN– pin) and non-inverting (IN+ pin) configuration in the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The internal pull-up or pull-down resistors on the input pins ensure that output is held low when the input pins are in floating condition. As a result, the unused input pin must be biased properly to ensure that driver output is enabled for normal operation. Table 1 is the device logic truth table. Table 1: the SCT51240 Device Logic. IN+ IN- OUT L L L H H L H L H H H L Floating Any L Any Floating L VDD Power Supply The SCT51240 operates under a supply voltage range between 4.5V to 24V. For the best high-speed circuit performance, two VDD bypass capacitors in parallel are recommended to prevent noise problems on supply VDD. A 0.1-μF surface mount ceramic capacitor must be located as close as possible to the VDD to GND pins of the SCT51240. In addition, a larger capacitor (such as 1μF or 10uF) with relatively low ESR must be connected in parallel, in order to help avoid the unexpected VDD supply glitch. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in the application. Under Voltage Lock Out (UVLO) The SCT51240 Under Voltage Lock Out (UVLO) rising threshold is typically 4.2 V with 300-mV typical hysteresis. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output low regardless of the status of the inputs. The hysteresis prevents output bouncing when low VDD supply voltages have noise impact from the power supply. The capability to operate at low power supply voltage below 5 V is especially suited for driving wide band gap power device like GaN. For example, during power up, the driver output remains low until the VDD voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with VDD till steady state VDD reached. The non-inverting operation in Figure 9 shows that the output remains low till the UVLO threshold reached, and then the output is in-phase with the input. 8 For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved SCT51240 VDD UVLO IN+ OUT Figure 9. SCT51240 Output Vs VDD Input Stage The input of SCT51240 is compatible on TTL logic that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically low threshold = 1.0 V, the logic level thresholds are conveniently driven by PWM control signals derived from 3.3-V and 5-V digital power-controller devices. Wider hysteresis offers enhanced noise immunity compared to traditional TTL logic implementation, where the hysteresis is typically less than 0.5 V. SCT51240 also features tight control of the input threshold voltage that ensures stable operation across temperature. The low input capacitance on the input pins increases switching speed and reduces the propagation delay. The SCT51240 features a dual-input configuration with two input pins available to control the state of the output. The user has the flexibility to configure the device by using either a non-inverting input pin (IN+) or an inverting input pin (IN–). The state of the output pin depends on the bias on both the IN+ and IN– pins. Refer to the input/output logic truth table (Table 1) and the Typical Application Diagrams Figure 11. When any of the input pin is in a floating condition, the driver output is held low state to guarantee the system robustness. There is a 500kOhm ground pulldown resistor on IN+ pin and a 400kOhm VDD pull-up resistor on IN- pin. To achieve the proper output, the IN+ and IN- pin must be properly biased. 1. To configure the SCT51240 as a non-inverting driver, apply the PWM input signal on IN+ pin and bias the INpin with ground or VDD, where the IN- pin can be used as an enable pin. 2. To configure the SCT51240 as an inverting driver, apply the PWM input signal on IN- pin and bias the IN+ pin can be used as an enable pin, where the IN+ can be used as an enable pin. Output Stage The SCT51240 output stage features the pull up structure with P-type MOSFET PM1 and N-type MOSFET NM1 in parallel, as shown in Figure 10. PM1 provides the pull up capability when OUT approaches VDD and the NM1 holds off state, which guarantees the driver output is up to VDD rail. The measurable on-resistance ROH in steady state is the conduction resistance of PM1. NM1 provides a narrow instant peak sourcing current up to 4A to eliminate the turn on time and delay. During the output turn on transition, the equivalent hybrid pull on transient resistance is 1.5xROL, which is much lower than the ROH. The N-type MOSFET NM2 composes the output stage pull down structure; the R OL is the DC measurement and represents the pull down impedance. The output stage of SCT51240 provides rail-to-rail operation, and is able to supply 4A sourcing and 4A sinking current. The presence of the MOSFET-body diodes also offers low impedance path to damp overshoots and undershoots. The outputs of the dual channel drivers are designed to withstand 500For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 9 SCT51240 mA reverse current without either damaging the device or causing the logic malfunction. VDD+5V 6 VDD 5 OUT VDD BootStrap NM1 Input Logic Anti-shoot through and Dead time PM1 ROH 1M NM2 ROL Figure 10. SCT51240 Output Stage Thermal Shutdown Once the junction temperature in the SCT51240 exceeds 170ºC, the thermal sensing circuit stops switching until the junction temperature falling below 145ºC, and the device restarts. Thermal shutdown prevents the damage on device during excessive heat and power dissipation condition. 10 For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved SCT51240 APPLICATION INFORMATION Typical Application RG VDD VDD C1 C2 GND IN+ IN- RG VDD C1 OUT VDD OUT C2 GND IN+ IN- Figure 11. Single Channel Driver Non-Inverting and Inverting Application Driver Power Dissipation Generally, the power dissipated in the SCT51240 depends on the gate charge required of the power device (Qg), Switching frequency, and use of external gate resistors. The SCT51240 features very low quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, their effect on the power dissipation within the gate driver is negligible. For the pure capacitive load, the power loss of SCT51240 is: 2 𝑃𝐺 = 𝐶𝐿𝑜𝑎𝑑 ∗ 𝑉𝐷𝐷 ∗ 𝑓𝑆𝑊 (1) Where  VDD is supply voltage  CLoad is the output capacitance  fSW is the switching frequency For the switching load of power MOSFET, the power loss of the driver is shown in equation (1), where charging a capacitor is determined by using the equivalence Qg = CLOADVDD. The gate charge includes the effect of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Manufacturers provide specifications with the typical and maximum gate charge, in nC, to switch the device under specified conditions. For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 11 SCT51240 𝑃𝐺 Where    = 𝑄𝑔 ∗ 𝑉𝐷𝐷 ∗ 𝑓𝑆𝑊 (2) Qg is the gate charge of the power device fSW is the switching frequency VDD is the supply voltage If RG applied between driver and gate of power device to slow down the power device transition, the power dissipation of the driver shows as below: 1 𝑅𝑂𝐿 𝑅𝑂𝐻 𝑃𝐺 = ∗ 𝑄𝑔 ∗ 𝑉𝐷𝐷 ∗ 𝑓𝑆𝑊 ∗ （ + ） 2 𝑅𝑂𝐿 + 𝑅𝐺 𝑅𝑂𝐻 + 𝑅𝐺 (3) Where  ROH is the equivalent pull up resistance of SCT51240  ROL is the pull down resistance of SCT51240  RG is the gate resistance between driver output and gate of power device. Application Waveforms 12 Figure 12. IN+ Switching ON Figure 13. IN+ Switching OFF Figure 14. IN- Switching ON Figure 15. IN- Switching OFF For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved SCT51240 Layout Guideline The SCT51240 provides the 4A output driving current and features very short rising and falling time at the power devices gate. The high di/dt causes driver output unexpected ringing when the driver output loop is not optimized. The regulator could suffer from malfunction and EMI noise if the power device gate has serious ringing. Below are the layout recommendations with using SCT51240 and Figure 16 is the layout example. Put the SCT51240 as close as possible to the power device and minimize the gate driving loop including the driver output and power device gate. The power supply decoupling capacitors needs to be close to the VDD pin and GND pin to reduce the supply ripple. Star-point grounding is recommended to minimize noise coupling from one current loop to the other. The GND of the driver connects to the other circuit node such as source of power MOSFET or ground of PWM controller at single point. The connected paths must be as short as possible to reduce parasitic inductance. A ground plane provides noise shielding and thermal dissipation as well. VDD 1 GND 2 IN+ 3 5 OUT G D 4 INS NMOS Figure 16. SCT51240 PCB Layout Example Thermal Considerations The maximum IC junction temperature should be restricted to 170°C under normal operating conditions. Calculate the maximum allowable dissipation, PD(max) , and keep the actual power dissipation less than or equal to P D(max) . The maximum-power-dissipation limit is determined using Equation (4). 𝑃𝐷(𝑀𝐴𝑋) = 150 − 𝑇𝐴 𝑅θJA (4) where  TA is the maximum ambient temperature for the application.  RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table. The real junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout, and environmental factor. Soldering the ground pin to a large ground plate enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom layer around the IC without solder mask also improves the thermal capability. For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 13 SCT51240 PACKAGE INFORMATION TOP VIEW BOTTOM VIEW SYMBOL SIDE VIEW NOTE: 1. 2. 3. 4. 5. 6. 14 Drawing proposed to be made a JEDEC package outline MO220 variation. Drawing not to scale. All linear dimensions are in millimeters. Thermal pad shall be soldered on the board. Dimensions of exposed pad on bottom of package do not include mold flash. Contact PCB board fabrication for minimum solder mask web tolerances between the pins. A A1 A2 b c D E E1 e e1 L ɵ For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 Unit: Millimeter MIN TYP MAX ----0.9 0.02 --0.09 0.7 --0.8 0.35 --0.5 0.08 --0.2 2.82 3.02 2.65 2.95 1.6 1.7 0.95 (BSC) 1.90 (BSC) 0.3 0.6 0° 8° All Rights Reserved SCT51240 TAPE AND REEL INFORMATION Feeding Direction For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. All Rights Reserved Product Folder Links: SCT51240 15 SCT51240 TYPICAL APPLICATION SCT52240 Typical Application RGA ENA INA GND INB ENB OUTA VDD VDD RGB OUTB C1 C2 RELATED PARTS PART NUMBERS SCT52240 DESCRIPTION Up to 24V Supply, 4-A Dual Channel High Speed Low Side Driver COMMENTS   Stackable Output Application -5V Input Capability NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any application. SCT will not assume any legal responsibility for any said applications 16 For more information www.silicontent.com © 2018 Silicon Content Technology Co., Ltd. Product Folder Links: SCT51240 All Rights Reserved