W5100S
(W5100S-L & W5100S-Q)
Version 1.0.0
http://www.wiznet.io/
© Copyright 2018 WIZnet Co., Ltd. All rights reserved.
W5100S
W5100S designed with Hardwired TCP/IP, WIZnet technology, is an embedded Internet
Controller Chip. W5100S supporting Full Hardwired, Ethernet MAC (Media Access Control), and
10Base-T/100Base-TX Ethernet PHY is Internet Connectivity One-chip Solution for Internet
Protocol (TCP/IP).
With W5100S, Host (User MCU) simply handles variety Internet Protocol such as IPv4, TCP,
UDP, ICMP, IGMP, ARP, PPPoE and etc. And W5100S supports each 8KB Memory for Transmit
and Receive to minimize using memory on Low-end level Host. Host also independently uses 4
Hardwired SOCKETs to develop vary Internet Applications in each Hardwired SOCKETs.
W5100S supports SPI and Parallel System BUS Interface for Host Interface. It also provides Low
Power / Low Heat design, WOL (Wake On LAN), Ethernet PHY Power Down Mode and etc.
W5100S is Low-cost chip that improves on W5100. Any Firmware using on W5100 can be used
on W5100S without any modification. Also, W5100S has 48 Pin LQFP & QFN Lead-Free
Package, smaller than W5100 for product miniaturization.
2 / 109
W5100S Datasheet Version1.0.0
Features
-
Support Hardwired Internet protocols
: TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
-
Support 4 independent SOCKETs simultaneously
-
Support SOCKET-less command
: ARP-Request, PING-Request
-
Support Ethernet Power down mode & Main Clock gating for power save
-
Support Wake on LAN over UDP
-
Support Serial & Parallel Host Interface
: High Speed SPI (MODE 0/3), System Bus with 2 Address signal & 8bit Data
-
Internal 16Kbytes Memory for TX/ RX Buffers
-
10BaseT/100BaseTX Ethernet PHY Integrated
-
Support Auto Negotiation (Full and half duplex, 10 and 100-based )
-
Support Auto-MDIX only when Auto-Negotiation mode
-
Not support IP Fragmentation
-
3.3V operation with 5V I/O signal tolerance
-
Network Indicator LEDs (Full/Half duplex, Link, 10/100 Speed, Active)
-
48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)
Target Applications
W5100S is well-suited for many embedded applications, including:
-
User product based on W5100 : No modify firmware
-
Home Network Devices: Set-Top Boxes, PVRs, Digital Media Adapters
-
Serial-to-Ethernet: Access Controls, LED displays, Wireless AP relays, etc.
-
Parallel-to-Ethernet: POS / Mini Printers, Copiers
-
USB-to-Ethernet: Storage Devices, Network Printers
-
GPIO-to-Ethernet: Home Network Sensors
-
Security Systems: DVRs, Network Cameras, Kiosks
-
Factory, Building, Home Automations
-
Medical Monitoring Equipment
-
Embedded Servers
-
Internet of Thing (IoT) Devices
-
IoT Cloud Devices
W5100S Datasheet Version1.0.0
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Block Diagram
Figure 1 Block Diagram
4 / 109
W5100S Datasheet Version1.0.0
Contents
1 PIN Description ........................................................................................ 11
1.1
PIN Description ............................................................................. 12
2 Memory Map ............................................................................................ 16
2.1
W5100S Registers........................................................................... 18
2.1.1
Common registers .................................................................... 18
2.1.2
SOCKET Registers .................................................................... 20
3 Register Descriptions ................................................................................. 22
3.1
Common Registers ......................................................................... 24
3.1.1
MR (Mode Register) .................................................................. 24
3.1.2
GWR (Gateway IP Address Register) .............................................. 24
3.1.3
SUBR (Subnet Mask Register) ...................................................... 24
3.1.4
SHAR (Source Hardware Address Register) ...................................... 25
3.1.5
SIPR (Source IP Address Register) ................................................. 25
3.1.6
INTPTMR (Interrupt Pending Time Register) .................................... 25
3.1.7
IR (Interrupt Register)............................................................... 25
3.1.8
IMR (Interrupt Mask Register) ...................................................... 26
3.1.9
RTR (Retransmission Time Register) .............................................. 27
3.1.10
RCR (Retransmission Count Register) ............................................. 27
3.1.11
RMSR (RX Memory Size Register) .................................................. 27
3.1.12
TMSR (TX Memory Size Register) .................................................. 28
3.1.13
IR2 (Interrupt Register 2) ........................................................... 28
3.1.14
IMR2 (Interrupt Mask Register 2) .................................................. 29
3.1.15
PTIMER (PPP Link Control Protocol Request Timer Register) ................ 29
3.1.16
PMAGIC (PPP Link Control Protocol Magic number Register) ................. 29
3.1.17
UIPR (Unreachable IP Address Register) ......................................... 30
3.1.18
UPORTR (Unreachable Port Register) ............................................ 30
3.1.19
MR2 (Mode Register 2) .............................................................. 30
3.1.20
PHAR (Destination Hardware Address Register on PPPoE) .................... 32
3.1.21
PSIDR (Session ID Register on PPPoE) ............................................. 32
3.1.22
PMRUR (PPPoE Maximum Receive Unit Register) ............................... 32
3.1.23
PHYSR (PHY Status Register) ....................................................... 32
3.1.24
PHYRAR (PHY Register Address Register) ........................................ 33
3.1.25
PHYDIR (PHY Data Input Register) ................................................ 34
3.1.26
PHYDOR (PHY Data Output Register) ............................................. 34
3.1.27
PHYACR (PHY Access Control Register) .......................................... 34
3.1.28
PHYDIVR (PHY Division Register) .................................................. 34
3.1.29
PHYCR0 (PHY Control Register 0) ................................................. 34
W5100S Datasheet Version1.0.0
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3.2
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3.1.30
PHYCR1 (PHY Control Register 1) ................................................. 35
3.1.31
SLCR (SOCKET-less Command Register) .......................................... 36
3.1.32
SLRTR (SOCKET-less Retransmission Time Register) ........................... 36
3.1.33
SLRCR (SOCKET-less Retransmission Count Register) .......................... 37
3.1.34
SLPIPR (SOCKET-less Peer IP Address Register) ................................. 37
3.1.35
SLPHAR (SOCKET-less Peer Hardware Address Register) ...................... 37
3.1.36
PINGSEQR (PING Sequence-number Register) ................................... 37
3.1.37
PINGIDR (PING ID Register) ......................................................... 38
3.1.38
SLIMR (SOCKET-less Interrupt Mask Register) ................................... 38
3.1.39
SLIR (SOCKET-less Interrupt Register) ............................................ 38
3.1.40
CLKLCKR (Clock Lock Register) .................................................... 39
3.1.41
NETLCKR (Network Lock Register) ................................................ 39
3.1.42
PHYLCKR (PHY Lock Register) ..................................................... 39
3.1.43
VERR (Version Register) ............................................................. 39
3.1.44
TCNTR (Ticker Counter Register) ................................................. 39
3.1.45
TCNTCLR (Ticker Counter Clear Register) ....................................... 40
SOCKET Register ............................................................................ 41
3.2.1
Sn_MR (SOCKET n Mode Register) ................................................. 41
3.2.2
Sn_CR (SOCKET n Command Register)............................................ 42
3.2.3
Sn_IR (SOCKET n Interrupt Register) ............................................. 44
3.2.4
Sn_SR (SOCKET n Status Register) ................................................ 45
3.2.5
Sn_PORTR (SOCKET n Source Port Register) .................................... 46
3.2.6
Sn_DHAR (SOCKET n Destination Hardware Address Register) ............... 46
3.2.7
Sn_DIPR (SOCKET n Destination IP Address Register) .......................... 47
3.2.8
Sn_DPORTR (SOCKET n Destination Port Register) ............................. 47
3.2.9
Sn_MSS (SOCKET n Maximum Segment Size Register) ......................... 47
3.2.10
Sn_PROTOR (SOCKET n IP Protocol Register) ................................... 48
3.2.11
Sn_TOS (SOCKET n IP Type Of Service Register) ............................... 48
3.2.12
Sn_TTL (SOCKET n IP Time To Live Register) ................................... 48
3.2.13
Sn_RXBUF_SIZE (SOCKET n RX Buffer Size Register) ........................... 48
3.2.14
Sn_TXBUF_SIZE (SOCKET n TX Buffer Size Register) ........................... 49
3.2.15
Sn_TX_FSR (SOCKET n TX Free Size Register) ................................... 49
3.2.16
Sn_TX_RD (SOCKET n TX Read Pointer Register) ............................... 49
3.2.17
Sn_TX_WR (SOCKET n TX Write Pointer Register) .............................. 50
3.2.18
Sn_RX_RSR (SOCKET n RX Received Size Register) ............................. 50
3.2.19
Sn_RX_RD (SOCKET n RX Read Pointer Register) ............................... 50
3.2.20
Sn_RX_WR (SOCKET n RX Write Pointer Register) .............................. 51
3.2.21
Sn_IMR (SOCKET n Interrupt Mask Register) ..................................... 51
3.2.22
Sn_FRAGR (SOCKET n Fragment Offset in IP Header Register) .............. 51
W5100S Datasheet Version1.0.0
3.2.23
Sn_MR2 (SOCKET n Mode register 2) .............................................. 51
3.2.24
Sn_KPALVTR (SOCKET n Keep Alive Timer Register) ........................... 53
3.2.25
Sn_RTR (SOCKET n Retransmission Time Register) ............................. 53
3.2.26
Sn_RCR (SOCKET n Retransmission Count Register) ........................... 53
4 Functional Description ............................................................................... 54
4.1
W5100S RESET .............................................................................. 54
4.2
Initialization ................................................................................ 54
4.3
4.4
4.2.1
Basic Setting .......................................................................... 54
4.2.2
Network Information Setting....................................................... 54
4.2.3
SOCKET TX/RX Buffer Setting ...................................................... 55
TCP ........................................................................................... 56
4.3.1
TCP Server ............................................................................ 57
4.3.2
TCP Client ............................................................................. 65
4.3.3
Other Functions ...................................................................... 67
UDP ........................................................................................... 68
4.4.1
UDP Unicast ........................................................................... 68
4.4.2
UDP Broadcast ........................................................................ 71
4.4.3
UDP Multicast ......................................................................... 72
4.4.4
Other Functions ...................................................................... 74
4.5
IPRAW ........................................................................................ 75
4.6
MACRAW ..................................................................................... 78
4.7
SOCKET-less Command (SLCR) ........................................................... 81
4.8
4.9
4.7.1
ARP Request (SLCR [ARP] = ‘1’) ................................................... 81
4.7.2
PING Command (SLCR [PING] = ‘1’)............................................... 83
Retransmission .............................................................................. 86
4.8.1
ARP & PING Retransmission ........................................................ 86
4.8.2
TCP Retransmission .................................................................. 86
Others Function ............................................................................ 88
4.9.1
System Clock(SYS_CLK) Switching ................................................ 88
4.9.2
Ethernet PHY Operation Mode Configuration ................................... 88
4.9.3
Ethernet PHY Parallel Detection .................................................. 89
4.9.4
Ethernet PHY Auto MDIX ............................................................ 89
4.9.5
Ethernet PHY Power Down Mode .................................................. 90
4.9.6
Ethernet PHY’s Registers Control ................................................. 91
5 HOST Interface Mode ................................................................................. 92
5.1
SPI Mode ..................................................................................... 92
5.1.1
SPI Frame .............................................................................. 93
5.1.2
SPI Write ............................................................................... 93
5.1.3
SPI Read ............................................................................... 94
W5100S Datasheet Version1.0.0
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5.2
Parallel Bus Mode .......................................................................... 95
5.2.1
Parallel Bus Data Write ............................................................. 95
5.2.2
Parallel Bus Data Write ............................................................. 96
6 Clock & Transformer Requirements ............................................................... 97
6.1
Quartz Crystal requirements. ............................................................ 97
6.2
Oscillator requirements. .................................................................. 98
6.3
Transformer Characteristics ............................................................. 98
7 Electrical Specification .............................................................................. 99
7.1
Absolute Maximum ratings................................................................ 99
7.2
Absolute Maximum ratings (Electrical Sensitivity) ................................... 99
7.3
DC Characteristics ......................................................................... 99
7.4
AC Characteristics ........................................................................ 100
7.5
7.4.1
Reset Timing ......................................................................... 100
7.4.2
BUS ACCESS TIMING ................................................................. 102
7.4.3
SPI ACCESS TIMING .................................................................. 103
7.4.4
Transformer Characteristics ...................................................... 104
7.4.5
MDIX ................................................................................... 104
POWER DISSPATION ....................................................................... 104
8 Package Information ................................................................................ 106
8.1
LQFP48 ...................................................................................... 106
8.2
QFN48 ....................................................................................... 107
9 Document Revision History ....................................................................... 109
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W5100S Datasheet Version1.0.0
List of Figures
Figure 1 Block Diagram ...........................................................................4
Figure 2 W5100S Pin Layout .................................................................. 11
Figure 3 Memory Map ........................................................................... 16
Figure 4 State Diagram ......................................................................... 46
Figure 5 TCP SERVER and TCP CLIENT ...................................................... 56
Figure 6 TCP Server Operation Flow ........................................................ 57
Figure 7 TCP Client Operation Flow ......................................................... 65
Figure 8 UDP Operation Flow ................................................................. 68
Figure 9 Received UDP DATA in SOCKETn RX Buffer Block ............................. 69
Figure 10 IPRAW Operation Flow ............................................................ 75
Figure 11 Received Data in IPRAW Mode SOCKET RX Buffer Block ................... 76
Figure 12 MACRAW Operation Flow ......................................................... 78
Figure 13 Received DATA Format in MACRAW ............................................ 79
Figure 14 SOCKET-less Command Operation Flow ....................................... 81
Figure 15 SCSn controlled by Host ........................................................... 92
Figure 16 SPI Mode 0 & Mode 3 ............................................................... 92
Figure 17 SPI Frame ............................................................................. 93
Figure 18 W5100 Mode Write SPI Frame ................................................... 94
Figure 19 W5100 Mode Read SPI Frame .................................................... 94
Figure 20 Direct & Indirect Mode Control by Host ....................................... 95
Figure 21 Parallel Bus N-Bytes Data Write ................................................. 96
Figure 22 Indirect Mode Continuous Read Access ........................................ 96
Figure 23 Quartz Crystal Model .............................................................. 97
Figure 24 Transformer Type .................................................................. 98
Figure 25 Reset Timing ....................................................................... 101
Figure 26 Bus Read Timing .................................................................. 102
Figure 27 BUS Write Timing ................................................................. 102
Figure 28 SPI Read Timing ................................................................... 103
Figure 29 SPI Write Timing .................................................................. 103
Figure 30 Transformer Type ................................................................ 104
W5100S Datasheet Version1.0.0
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List of Tables
Table 1 Pin Type Notation ..................................................................... 11
Table 2 PIN Description ........................................................................ 12
Table 3 Common Registers .................................................................... 18
Table 4 Socket Registers ....................................................................... 20
Table 5 Internet Protocol Supported In IPRAW Mode .................................... 75
Table 6 W5100 Mode SPI Command ......................................................... 93
Table 7 Indirect Mode Address Value ....................................................... 95
Table 8 Quartz Crystal .......................................................................... 97
Table 9 Crystal Recommendation Characteristics ........................................ 97
Table 10 Oscillator Characteristics .......................................................... 98
Table 11 Transformer Characteristics ...................................................... 98
Table 12 Absolute Maximum ratings......................................................... 99
Table 13 Electro Static Discharge (ESD) .................................................... 99
Table 14 Latch up Test ......................................................................... 99
Table 15 DC Characteristics ................................................................... 99
Table 16 Reset Table ......................................................................... 101
Table 17 BUS Read Timing ................................................................... 102
Table 18 BUS Write timing ................................................................... 103
Table 19 SPI Read Timing .................................................................... 103
Table 20 SPI Write Timing ................................................................... 104
Table 21 Transformer Characteristics .................................................... 104
Table 22 Power Dissipation .................................................................. 104
Table 23 LQFP48 VARIATIONS (ALL DEMINSIONS SHOWN IN MM) ................... 106
Table 24 QFN48 VARIATIONS (ALL DEMINSIONS SHOWN IN MM) ..................... 107
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W5100S Datasheet Version1.0.0
MISO
MOSI
1V2D
SCLK
CSn
MOD3
MOD2
MOD1
33
32
31
30
29
28
27
26
MOD0
RDn
34
25
WRn
DAT1
35
37
3V3D
DAT0
36
PIN Description
24
3V3D
38
23
GND
DAT2
39
22
1V2D
DAT3
40
21
COLn
DAT4
41
20
ACTn
DAT5
42
19
DPXn
DAT6
43
18
SPDn
DAT7
44
17
LNKn
1V2D
45
16
GNDA
GND
46
15
3V3A
INTn
47
14
1V2O
RSTn
48
13
1V2D
W5100S
5
6
7
8
9
10
11
12
RXIN
RXIP
GNDA
3V3A
RSET_BG
GND
XSCO
XSCI
3
TXOP
4
2
TXON
1V2A
1
LOT Number
Weekly Code
GNDA
1
Figure 2 W5100S Pin Layout
Table 1 Pin Type Notation
Type
Description
I
Input
O
Output
M
Alternate (Multi-function) Signal
U
Internal pulled-up 75KΩ resistor
D
Internal pulled-down 75KΩ resistor
A
Analog
P
Power & Ground
W5100S Datasheet Version1.0.0
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1.1
PIN Description
Table 2 PIN Description
PIN #
Symbol
Type
Description
1
GNDA
AP
Analog Ground
2
TXON
AO
Differential Transmitted Signal Pair
3
TXOP
AO
4
1V2A
AP
5
RXIN
AI
6
RXIP
AI
7
GNDA
AP
Analog Ground
8
3V3A
AP
Analog 3.3V Power
Differential Data is transmitted to Media via TXOP/TXON
signal pair on MDI Mode.
Analog 1.2V Power
Supplied from 1V20 voltage source
Differential Received Signal Pair
Differential Data is received from Media via RXIP/RXIN
signal pair on MDI Mode.
Off-chip Bias Resistor
9
RSET_BG
AO
Must be connected to analog Ground through external
12.3KΩ, error 1% Resistance.
10
GND
AP
Digital Ground
11
XSCO
AO
25MHz Clock
25MHz Crystal Oscillator (TXAL) or Oscillator (OSC) are
used for Internal oscillator stabilization.
W5100S uses 25MHz (Low Frequency Mode) or 100MHz
12
XSCI
AI
(Normal Mode) as Internal Clock from External 25MHz
Clock Source.
If OSC is used, 25MHz@1.2V must be used and only XSCI
must be connected and XSCO must be floated.
For more information, refer to Clock Selection Guide.
13
1V2D
P
Digital 1.2V Power
Supplied from 1V20 voltage source
Internal Regulator 1.2V Power Output
Internal Regulator for W5100S needs Max 150mA for 1.2V
Power Output.
Make sure to supply 1V2D and 1V2A for External
14
1V2O
PO
Capacitor 3.3uF stabilization.
1V2O must use Ferrite Bead. 1V2D and 1V2A must be
separated and be supplied.
This power is only for W5100S. It must not be used for
other device.
12 / 109
W5100S Datasheet Version1.0.0
15
3V3A
AP
Analog 3.3V Power
16
GNDA
AP
Analog Ground
Link Status LED It is valid on SPI and Parallel Bus Mode.
17
LNKn
OU
Low : Link up
High : Link down
Link Speed LEDIt is valid on SPI and Parallel Bus Mode.
18
SPDn
OU
Low : 100Mbps
High : 10Mbps
Link Duplex LED
It is valid on SPI and Parallel Bus Mode.
19
DPXn
OU
Low : Full-Duplex
High : Half-Duplex
Link Activity LED
It is valid on SPI and Parallel Bus Mode.
20
ACTn
OU
No Flash : Link up state without TX/RX
Flash : Link up state with TX/RX data
High : Link-down state
Link Collision Detect LED
It is valid on SPI and Parallel Bus Mode.
21
COLn
OU
It indicates a collision during Data transmission.
Low : Collision Detected
High : No Collision
Digital 1.2V Power
22
1V2D
P
23
GND
P
Digital Ground
24
3V3D
P
Digital 3.3V power
25
MOD[0]
ID
W5100S Interface Mode Selection
26
MOD[1]
ID
Interface Mode is selected by MOD [3:0].
27
MOD[2]
ID
28
MOD[3]
ID
29
CSn
IU
W5100S Datasheet Version1.0.0
Supplied from 1V20 voltage source.
“0000” : SPI Mode
“010X” : Parallel Bus Mode
W5100S Chip Select
13 / 109
Low : Select
High : No Select
SPI Clock
30
SCLK
ID
On SPI Mode, it is used to SPI Clock.
But on Parallel Bus Mode, it must be connected to GND
or be floated.
31
32
33
1V2D
MOSI
/ADDR0
MISO
/ADDR1
P
Digital 1.2V Power
Supplied from 1V20 voltage source.
SPI Master Output Slave Input / Address 0
IDM
MOSI
: On SPI Mode, SPI Data is received from HOST.
ADDR0 : On Parallel Bus Mode, it is used to Address 0.
SPI Master Input Slave Output / Address 1
IOPM
MISO
: On SPI Mode, SPI Data is transmitted to HOST.
ADDR1 : On Parallel Bus Mode, It is used to Address 1.
Read Strobe
34
RDn
IU
On Parallel Bus Mode, it indicates Read Operation.
On SPI Mode, it must be connected to 3V3D or be floated.
Write Strobe
35
WRn
IU
36
3V3D
P
37
DAT0
IOU
8 Bits Data Bus
38
DAT1
IOU
On Parallel Bus Mode, DAT [7:0] receives Data from HOST
39
DAT2
IOU
or W5100S.
40
DAT3
IOU
41
DAT4
IOU
42
DAT5
IOU
43
DAT6
IOU
44
DAT7
IOU
45
1V2D
P
Digital 1.2V Power
46
GND
P
Digital Ground
On Parallel Bus Mode, it indicates Write Operation.
Digital 3.3V Power
On SPI Mode, DAT [7:0] must be floated.
Interrupt
When the event occurs during W5100S Ethernet
Communication, INTn notices to HOST.
47
INTn
OP
Low : Interrupt Occurred
High : No Interrupt
Refer to IEN (Interrupt pin Enable) in MR2 (Mode Register
2), INTPTMR (Interrupt Pending Time Register), IMR
14 / 109
W5100S Datasheet Version1.0.0
(Interrupt Mask Register), IMR2 (Interrupt Mask Register
2), SLIMR (SOCKET-less Interrupt Mask Register)
Reset
RSTn initializes W5100S. RSTn must be asserted to Low
longer than 500ns. After asserted RSTn, W5100S spends
48
RSTn
IP
60.3ms for initialization. (Ref 7.4.1 Reset Timing)
Low : W5100S initialized.
High : Normal Operation.
W5100S Datasheet Version1.0.0
15 / 109
2
Memory Map
W5100S has the same Memory Map as W5100 for compatibility and additional Common
Register for improved functionality. The below Figure 3 shows W5100S Memory Map.
Figure 3 Memory Map
16 / 109
W5100S Datasheet Version1.0.0
Figure 3 shows the Address Offset of Common & SOCKET Register Block and TX/RX Memory
Block. At W5100S Reset, each SOCKET n TX/RX Buffer are assigned with 2KB/2KB from TX/RX
Memory Block.
After W5100S Reset, each SOCKET n TX/RX Buffer Size are set by TMSR (TX Memory Size
Register) and RMSR (RX Memory Size Register) or by SOCKET n TX/RX Buffer Size Register
(Sn_TXBUF_SIZE / Sn_RXBUF_SIZE). The total Buffer Size of SOCKET n TX/RX must not be
exceeded by 8 Kbytes.
W5100S Datasheet Version1.0.0
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2.1
W5100S Registers
2.1.1 Common registers
Table 3 Common Registers
Address
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
0x0010
0x0011
0x0012
0x0013
0x0014
Register
Mode (MR)
Gateway Address
Interrupt2 (IR2)
(GAR1)
Interrupt2 Mask (IMR2)
(GAR2)
0x0022
(GAR3)
~
Subnet Mask Address
(SUBR0)
(SUBR1)
(SUBR2)
(SUBR3)
Source Hardware Address
(SHAR0)
(SHAR1)
(SHAR2)
(SHAR4)
(SHAR5)
Source IP Address
0x001B
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Reserved
0x0027
0x0028
0x0029
0x002A
0x002B
0x002C
0x002D
(SHAR3)
0x002E
0x002F
PPP LCP Request Timer
(PTIMER)
PPP LCP Magic Number
(PMAGIC)
Unreachable IP Address
(UIPR0)
(UIPR1)
(UIPR2)
(UIPR3)
Unreachable Port
(UPORTR0)
(UPORTR1)
(SIPR0)
0x0030
Mode2 (MR2)
(SIPR1)
0x0031
Reserved
(SIPR2)
Destination Hardware Address
(SIPR3)
0x0032
on PPPoE
Interrupt Pending Time
0x0033
(PHAR0)
(INTPTMR0)
0x0034
(PHAR1)
(INTPTMR1)
0x0035
(PHAR2)
0x0036
(PHAR3)
0x0037
(PHAR4)
Interrupt Mask (IMR)
0x001A
Reserved
0x0021
0x0016
0x0019
~
0x001F
0x0020
Interrupt (IR)
0x0018
0x001C
(GAR0)
0x0015
0x0017
Register
(PHAR5)
Retransmission Time
(RTR0)
(RTR0)
0x0038
0x0039
Retransmission Time
(RCR)
RX Memory Size
0x003A
0x003B
(RMSR)
TX Memory Size
(TMSR)
0x003C
Session ID on PPPoE
(PSIDR0)
(PSIDR1)
Maximum Receive Unit on PPPoE
(PMRUR0)
(PMRUR1)
PHY Status
(PHYSR0)
W5100S Datasheet Version1.0.0
Address
Register
0x003E
PHY Address Value (PHYAR)
0x003F
PHY Register Address (PHYRAR)
0x0040
0x0041
PHY Data Input
(PHYDIR0)
(PHYDIR1)
PHY Data Output
Address
0x005E
0x005F
Register
SOCKET-less Interrupt
Mask (SLIMR)
SOCKET-less Interrupt (SLIR)
0x0060
~
Reserved
0x006A
0x0070
Clock Lock (CLKLCKR)
0x0071
Network Lock (NETLCKR)
(PHYDOR1)
0x0072
PHY Lock (PHYLCKR)
0x0044
PHY Access (PHYACR)
0x0073
0x0045
PHY Division (PHYDIVR)
0x0042
0x0043
0x0046
0x0047
(PHYDOR0)
0x007F
(PHYCR0)
0x0080
Chip Version (VERR)
(PHYCR1)
0x0081
Reserved
Reserved
0x0082
0x0083
0x004B
0x004C
0x004D
0x004E
0x004F
0x0050
0x0051
0x0052
0x0053
0x0054
0x0055
0x0056
0x0057
0x0058
0x0059
0x005A
0x005B
0x005C
0x005D
Reserved
PHY Control
0x0048
~
~
SOCKET-less Command (SLCR)
SOCKET-less Retransmission Time
(SLRTR0)
(SLRTR1)
100us Tick Counter
(TCNTR0)
(TCNTR1)
0x0084
~
Reserved
0x0087
0x0088
TCNTCLR
SOCKET-less Retransmission Count
(SLRCR)
SOCKET-less Peer IP Address
(SLPIPR0)
(SLPIPR1)
(SLPIPR2)
(SLPIPR3)
SOCKET-less Peer Hardware Address
(SLPHAR0)
(SLPHAR1)
(SLPHAR2)
(SLPHAR3)
(SLPHAR4)
(SLPHAR5)
PING Sequence Number
(PINGSEQR0)
(PINGSEQR1)
PING ID
(PINGIDR0)
(PINGIDR1)
W5100S Datasheet Version1.0.0
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2.1.2 SOCKET Registers
Table 4 Socket Registers
Symbol
Sn_MR
Sn_CR
Sn_IR
Sn_SR
Description
SOCKET n
Mode
SOCKET n
Command
SOCKET n
Interrupt
SOCKET n
Status
Address
Sn_
S0_
S1_
S2_
S3_
0x0400+(0x0100 x n)
0x0400
0x0500
0x0600
0x0700
0x0401+(0x0100 x n)
0x0401
0x0501
0x0601
0x0701
0x0402+(0x0100 x n)
0x0402
0x0502
0x0602
0x0702
0x0403+(0x0100 x n)
0x0403
0x0503
0x0603
0x0703
Sn_PORTR0
SOCKET n
0x0404+(0x0100 x n)
0x0404
0x0504
0x0604
0x0704
Sn_PORTR1
Source Port
0x0405+(0x0100 x n)
0x0405
0x0505
0x0605
0x0705
Sn_DHAR0
0x0406+(0x0100 x n)
0x0406
0x0506
0x0606
0x0706
Sn_DHAR1
0x0407+(0x0100 x n)
0x0407
0x0507
0x0607
0x0707
0x0408+(0x0100 x n)
0x0408
0x0508
0x0608
0x0708
0x0409+(0x0100 x n)
0x0409
0x0509
0x0609
0x0709
Sn_DHAR4
0x040A+(0x0100 x n)
0x040A
0x050A
0x060A
0x070A
Sn_DHAR5
0x040B+(0x0100 x n)
0x040B
0x050B
0x060B
0x070B
Sn_DIPR0
0x040C+(0x0100 x n)
0x040C
0x050C
0x060C
0x070C
0x040D+(0x0100 x n)
0x040D
0x050D
0x060D
0x070D
0x040E+(0x0100 x n)
0x040E
0x050E
0x060E
0x070E
0x040F+(0x0100 x n)
0x040F
0x050F
0x060F
0x070F
Sn_DHAR2
Sn_DHAR3
Sn_DIPR1
Sn_DIPR2
SOCKET n
Destination
Hardware Address
SOCKET n
Destination IP
Address
Sn_DIPR3
Sn_DPORTR0
SOCKET n
0x0410+(0x0100 x n)
0x0410
0x0510
0x0610
0x0710
Sn_DPORTR0
Destination Port
0x0411+(0x0100 x n)
0x0411
0x0511
0x0611
0x0711
SOCKET n
0x0412+(0x0100 x n)
0x0412
0x0512
0x0612
0x0712
0x0413+(0x0100 x n)
0x0413
0x0513
0x0613
0x0713
0x0414+(0x0100 x n)
0x0414
0x0514
0x0614
0x0714
0x0415+(0x0100 x n)
0x0415
0x0515
0x0615
0x0715
0x0416+(0x0100 x n)
0x0416
0x0516
0x0616
0x0716
Sn_MSS0
Sn_MSS1
Sn_PROTOR
Sn_TOS
Sn_TTL
Maximum
Segment Size
SOCKET n
IP Protocol
SOCKET n
IP Type Of Service
SOCKET n
IP Time To Live
Reserved
Reserved
0x0417+(0x0100 x n)
0x0417
0x0517
0x0617
0x0717
Reserved
Reserved
0x041D+(0x0100 x n)
0x041D
0x051D
0x061D
0x071D
0x041E+(0x0100 x n)
0x041E
0x051E
0x061E
0x071E
0x041F+(0x0100 x n)
0x041F
0x051F
0x061F
0x071F
0x0420+(0x0100 x n)
0x0420
0x0520
0x0620
0x0720
Sn_RXBUF_SIZE
Sn_TXBUF_SIZE
Sn_TX_FSR0
20 / 109
SOCKET n
RX Buffer Size
SOCKET n
TX Buffer Size
SOCKET n
W5100S Datasheet Version1.0.0
Sn_TX_FSR1
TX Free Size
0x0421+(0x0100 x n)
0x0421
0x0521
0x0621
0x0721
Sn_TX_RD0
SOCKET n
0x0422+(0x0100 x n)
0x0422
0x0522
0x0622
0x0722
Sn_TX_RD1
TX Read Pointer
0x0423+(0x0100 x n)
0x0423
0x0523
0x0623
0x0723
Sn_TX_WR0
SOCKET n
0x0424+(0x0100 x n)
0x0424
0x0524
0x0624
0x0724
Sn_TX_WR1
TX Write Pointer
0x0425+(0x0100 x n)
0x0425
0x0525
0x0625
0x0725
Sn_RX_RSR0
SOCKET n
0x0426+(0x0100 x n)
0x0426
0x0526
0x0626
0x0726
Sn_RX_RSR1
RX Received Size
0x0427+(0x0100 x n)
0x0427
0x0527
0x0627
0x0727
Sn_RX_RD0
SOCKET n
0x0428+(0x0100 x n)
0x0428
0x0528
0x0628
0x0728
Sn_RX_RD1
RX Read Pointer
0x0429+(0x0100 x n)
0x0429
0x0529
0x0629
0x0729
Sn_RX_WR0
SOCKET n
0x042A+(0x0100 x n)
0x042A
0x052A
0x062A
0x072A
Sn_RX_WR1
RX Write Pointer
0x042B+(0x0100 x n)
0x042B
0x052B
0x062B
0x072B
0x042C+(0x0100 x n)
0x042C
0x052C
0x062C
0x072C
0x042D+(0x0100 x n)
0x042D
0x052D
0x062D
0x072D
0x042E+(0x0100 x n)
0x042E
0x052E
0x062E
0x072E
0x042F+(0x0100 x n)
0x042F
0x052F
0x062F
0x072F
0x0430+(0x0100 x n)
0x0430
0x0530
0x0630
0x0730
0x0432+(0x0100 x n)
0x0432
0x0532
0x0632
0x0732
0x0433+(0x0100 x n)
0x0433
0x0533
0x0633
0x0733
0x0434+(0x0100 x n)
0x0434
0x0534
0x0634
0x0734
Sn_IMR
Sn_FRAGR0
Sn_FRAGR1
Sn_MR2
Sn_KPALVTR
Sn_RTR0
Sn_RTR1
SOCKET n
Interrupt Mask
SOCKET n
Fragment Offset
in IP Header
SOCKET n Mode 2
SOCKET n
Keep-alive Timer
SOCKET n
Retransmission
Time
SOCKET n
Sn_RCR
Retransmission
Count
W5100S Datasheet Version1.0.0
21 / 109
3
Register Descriptions
Register Notation
* Register Symbol (Register full Name)
- [Register Type][Address Offset][Reset Value]
Register Description….
7
6
5
4
3
2
1
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit Type
Bit Type
Bit Type
Bit Type
Bit Type
Bit Type
Bit Type
Bit Type
Sn_IR [3: 0] indicates a Register Symbol [Upper Bit: Lower Bit].
Sn_IR [3: 0] = '0001' indicates Sn_IR [3] = '0', Sn_IR [2] = '0', Sn_IR [1] = '0', Sn_IR [0] = '1'.
[Register/Bit Type]: Type of Register and Bit.
-
[RW] : Both reading and writing are possible.
-
[R=W] : The value read and written are the same.
-
[RO] : Read Only
-
[WO] : Write Only
-
[W] : Write Only
-
[WC] : Cleared by written ‘1’.
-
[W0] : Must be written only ‘0’.
-
[W1] : Must be written only ‘1’.
-
[AC] : Auto Clear
-
[1] : Always read ‘1’
-
[0] : Always read ‘0’
-
[-] : Not available
[Address Offset]: Register Address Offset
[Reset Value]: Default Value.
Ex1)
3.1.1 MR ( Mode Register)
[RW][0x0000][0x03]
MR is abbreviation for Mode Register. This Register is possible to be read and written.
The Register Address Offset is ‘0x0000’ and it is set to ‘0x03’ after Reset.
7
6
5
4
3
2
1
0
RST
-
-
PB
PPPoE
-
AI
IND
AC
W0
W0
R=W
R=W
-
1
1
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W5100S Datasheet Version1.0.0
Ex2) MR [RST]
MR [RST] means RST Bit in MR.
Ex3) MR [7:0]
MR [7:0] means the Bits from 7th to 0th bit in MR.
W5100S Datasheet Version1.0.0
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3.1
Common Registers
3.1.1 MR (Mode Register)
[RW][0x0000] [0x03]
MR is used for Reset, PING Block and PPPoE Enable
7
6
5
4
3
2
1
0
RST
-
-
PB
PPPoE
-
-
-
Bit
Symbol
Description
Reset
7
RST
If this Bit is ‘1’, All W5100S Registers will be initialized.
It will be automatically cleared as ‘0’ after 3 SYS_CLK
[6:5]
-
Reserved
PING Response Block
4
PB
If this Bit is ‘1’, it blocks the Response to a ping request.
1 : Disable PING Response
0 : Enable PING Response
PPPoE Enable
3
PPPoE
1 : Enable PPPoE
0 : Disable PPPoE
[2:0]
-
Reserved
3.1.2 GWR (Gateway IP Address Register)
[R=W] [0x0001-0x0004] [0x00]
GWR configures the Gateway Address when NETLCKR (Network Lock Register) is on Unlock
Mode.
Ex) GWR = “192.168.0.1”
GWR0(0x0001)
GWR1(0x0002)
GWR2(0x0003)
GWR3(0x0004)
192 (0xC0)
168 (0xA8)
0 (0x00)
1 (0x01)
3.1.3 SUBR (Subnet Mask Register)
[R=W] [0x0005–0x0008] [0x00]
SUBR configures the Subnet Mask Address when NETLCKR (Network Lock Register) is on Unlock
Mode.
Ex) SUBR = “255.255.255.255”
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W5100S Datasheet Version1.0.0
SUBR0(0x0005)
SUBR0(0x0006)
SUBR0(0x0007)
SUBR0(0x0008)
255 (0xFF)
255 (0xFF)
255 (0xFF)
255 (0xFF)
3.1.4 SHAR (Source Hardware Address Register)
[R=W] [0x0009-0x000E] [0x00]
SHAR configures the Source MAC Address when NETLCKR (Network Lock Register) is on Unlock
Mode.
Ex) SHAR = “11:22:33:AA:BB:CC”
SHAR0(0x0009)
SHAR1(0x000A)
SHAR2(0x000B)
0x11
0x22
0x33
SHAR3(0x000C)
SHAR4(0x000D)
SHAR5(0x000E)
0xAA
0xBB
0xCC
3.1.5 SIPR (Source IP Address Register)
[R=W] [0x000F-0x0012] [0x00]
SIPR configures the Source IP Address when NETLCKR (Network Lock Register) is on Unlock
Mode.
Ex) SIPR = “192.168.0.100”
SIPR0(x000F)
SIPR1(0x0010)
SIPR2(0x0011)
SIPR3(0x0012)
192 (0xC0)
168 (0xA8)
0 (0x00)
100(0x64)
3.1.6 INTPTMR (Interrupt Pending Time Register)
[RW][0x0013-0x0014][0x0000]
INTPTMR sets internal Interrupt Pending Timer Count. When INTn is de-asserted to High,
Timer Count is initialized to INTPTMR and decreased by 1 from initial value to ‘0’ every
SYS_CLK x 4. When Interrupt occurs and the corresponding Interrupt Mask is set and INTPTMR
is ‘0’, INTn is asserted to Low.
Ex) INTPTMR = 1000(0x03EB)
INTPTMR0(0x0013)
INTPTMR1(0x0014)
0x03
0xEB
3.1.7 IR (Interrupt Register)
[RW] [0x0015] [0x00]
When W5100S or SOCKET n Event occurs, the corresponding Bit in IR is set to ‘1’. If the Event
occurs and the corresponded Interrupt Mask Bit in IMR is set to ‘1’ and internal Interrupt
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Pending Timer Counter is ‘0’, INTn is asserted to Low. When the Event is cleared or the
corresponding Mask Bit is set to ‘0’, INTn is de-asserted to High.
7
6
5
4
3
2
1
0
CONFLICT
UNREACH
PPPTERM
-
S3_INT
S2_INT
S1_INT
S0_INT
WC
WC
WC
-
AC
AC
AC
AC
Bit
Symbol
Description
IP Conflict
7
CONFLICT
Read 1 : IP Conflict
Read 0 : Destination Port Unreachable
When receiving the ICMP (Destination port unreachable) packet, this
Bit is set as ‘1’. And Destination Information, IP Address and Port
6
UNREACH
Number, is written on UIPR & UPORTR.
Read 1 : Unreachable Packet receive
Read 0 : PPPoE Terminated
5
PPPTERM
Read 1 : Received PPPT or LCPT Packet only on PPPoE
Read 0 : -
4
-
Reserved
SOCKET n Interrupt
[3:0]
Sn_INT
Read 1 : Each n-th Bit describes SOCKET n-th Interrupt.
Read 0 : When Sn_IR is 0x00, Sn_INT bit is Auto-Clear as ‘0’
3.1.8 IMR (Interrupt Mask Register)
[R=W] [0x0016] [0x00]
IMR is used for the corresponding IR Bit Mask.
7
6
5
4
3
CNFT
UNREACH
PPPTERM
-
S3_INT
R=W
R=W
R=W
R=W
Bit
Symbol
2
1
0
S2_INT
S1_INT
S0_INT
R=W
R=W
R=W
Description
IP Conflict Interrupt Mask
7
CNFT
1 : Enable IP Conflict Interrupt
0 : Disable IP Conflict Interrupt
6
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UNREACH
Destination Port Unreachable Interrupt Mask
W5100S Datasheet Version1.0.0
1 : Enable Destination Port Unreachable Interrupt
0 : Disable Destination Port Unreachable Interrupt
PADT/LCPT Interrupt Mask
5
PPPTERM
1 : Enable PADT/LCPT Interrupt
0 : Disable PADT/LCPT Interrupt
4
-
Reserved
SOCKET 3 Interrupt Mask
3
S3_INT
1 : Enable SOCKET 3 Interrupt
0 : Disable SOCKET 3 Interrupt
SOCKET 2 Interrupt Mask
2
S2_INT
1 : Enable SOCKET 2 Interrupt
0 : Disable SOCKET 2 Interrupt
SOCKET 1 Interrupt Mask
1
S1_INT
1 : Enable SOCKET 1 Interrupt
0 : Disable SOCKET 1 Interrupt
SOCKET 0 Interrupt Mask
0
S0_INT
1 : Enable SOCKET 0 Interrupt
0 : Disable SOCKET 0 Interrupt
3.1.9 RTR (Retransmission Time Register)
[R=W] [0x0017-0x0018] [0x07D0]
RTR sets initial value of Sn_RTR (SOCKET n Retransmission Time Register). The unit is 100us.
RTR and RCR (Retransmission Counter Register) set ARP & TCP Retransmission. (Ref 4.8
Retransmission)
Ex) RTR = 5000 (0x1388)
5000*100us = 0.5s
RTR0(0x0017)
RTR1(0x0018)
0x13
0x88
3.1.10 RCR (Retransmission Count Register)
[R=W] [0x0019] [0x08]
RCR sets initial value of Sn_RCR (SOCKET n Retransmission Count Register). RTR and RCR set
ARP & TCP Retransmission. (Ref 4.8 Retransmission)
3.1.11 RMSR (RX Memory Size Register)
[R=W] [0x001A] [0x55]
RMSR configures each SOCKET n RX Buffer Size. And the Sum of SOCKET n RX Buffer Size must
not exceeded 8 Kbytes. (Ref Sn_RXBUF_SIZE (SOCKET n RX Buffer Size Register))
W5100S Datasheet Version1.0.0
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7
6
5
SOCKET 3
S1
4
3
SOCKET 2
S0
S1
2
1
SOCKET 1
S0
S1
0
SOCKET 0
S0
S1
S0
Each SOCKET n RX Buffer Size is set by S0 and S1.
Buffer Size
S1
S0
1 KB
0
0
2 KB
0
1
4 KB
1
0
8 KB
1
1
3.1.12 TMSR (TX Memory Size Register)
[R=W] [0x001B] [0x55]
TMSR configures each SOCKET n TX Buffer Block Size. And the sum of SOCKET n TX Buffer
Block Size must not be exceeded 8 Kbytes. (Ref Sn_TXBUF_SIZE (SOCKET n TX Buffer Size
Register))
7
6
5
SOCKET 3
S1
4
3
SOCKET 2
S0
S1
2
1
SOCKET 1
S0
S1
0
SOCKET 0
S0
S1
S0
Each SOCKET n TX Buffer Block Size is set by S0 and S1.
Buffer Size
S1
S0
1 KB
0
0
2 KB
0
1
4 KB
1
0
8 KB
1
1
3.1.13 IR2 (Interrupt Register 2)
[RW] [0x0020] [0x00]
When WOL Event occurs, IR2 [WOL] is set to ‘1’. If the Event occurs and IMR2 [WOL] is set to
‘1’ and internal Interrupt Pending Timer Counter is ‘0’, INTn is asserted to Low. When the
Event is cleared or IMR2 [WOL] is set to ‘0’, INTn is de-asserted to High.
7
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6
5
4
3
2
1
0
W5100S Datasheet Version1.0.0
-
-
-
-
-
-
-
WOL
-
-
-
-
-
-
-
WC
Bit
Symbol
[7:1]
-
Description
Reserved
WOL MAGIC Packet Interrupt
0
WOL
1 : Received UDP based WOL Magic Packet.
0:-
3.1.14 IMR2 (Interrupt Mask Register 2)
[R=W] [0x0021] [0x00]
IMR2 is used for the corresponding IR2 Bit Mask.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
WOL
-
-
-
-
-
-
-
R=W
Bit
Symbol
[7:1]
-
Description
Reserved
WOL MAGIC Packet Interrupt Mask
0
WOL
1 : Enable WOL MAGIC Packet Interrupt
0 : Disable WOL MAGIC Packet Interrupt
3.1.15 PTIMER (PPP Link Control Protocol Request Timer
Register)
[R=W] [0x0028] [0x28]
PTIMER configures the sending period for LCP Echo Request. The unit is 25ms.
Ex) PTIMER = 200 (0xC8),
200 * 25ms = 5s
3.1.16 PMAGIC (PPP Link Control Protocol Magic number
Register)
[R=W] [0x0029] [0x00]
PMAGIC configures 4 Bytes Magic Number for LCP Echo Request.
Ex) PMAGIC = 0x01
PMAGIC(0x0029)
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0x01
LCP Magic Number = 0x01010101
3.1.17 UIPR (Unreachable IP Address Register)
[RO] [0x002A-0x002D] [0x0000]
When W5100S received Unreachable Packet (IR [UNR] = ‘1’), Peer IP Address in the Packet is
written on UIPR.
Ex) UIPR = “192.169.0.21”
UIPR0(0x002A)
UIPR1(0x002B)
UIPR2(0x002C)
UIPR3(0x002D)
192(0xC0)
168(0xA8)
0(0x00)
21(0x15)
3.1.18 UPORTR (Unreachable Port Register)
[RO] [0x002E-0x002F] [0x0000]
When W5100S received Unreachable Packet (IR [UNR] = ‘1’), Peer PORT Number in the Packet
is written on UPORTR.
Ex) UPORTR = 3000 (0x0BB8)
UPORTR0(0x002E)
UPORTR1(0x002F)
0x0B
0xB8
3.1.19 MR2 (Mode Register 2)
[R=W] [0x0030] [0x40]
MR2 configures System Operation Clock (SYS_CLK), Interrupt Activation, TCP & UDP Scan
Prevention, WOL (Wake On LAN) and Force ARP.
7
6
5
4
3
2
1
0
CLKSEL
IEN
NOTCPRST
UDPURB
WOL
-
FARP
-
R=W
R=W
R=W
R=W
R=W
W0
R=W
W0
Bit
Symbol
Description
System Operation Clock(SYS_CLK) Select
When CLKLCKR (Clock Lock Register) is Unlock, this bit can only set.
7
CLKSEL
(Ref to 3.1.40
CLKLCKR (Clock Lock Register)
[WO] [0x0070] [0x00])
1 : 25MHz
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W5100S Datasheet Version1.0.0
0 : Depends on PHYCR1[PWDN]
SYS_CLK selected by PHCR1 configuration.
PHYCR1[PWDN]
SYS_CLK
0
100 MHz
1
25 MHz
INTn Enable / Disable
6
IEN
1 : INTn Enable
0 : INTn Disable (INTn is Always High)
TCP RST Packet Block
If Peer transmits TCP Packet to a Port that does not exist on W5100S.
W5100S automatically transmits RST Packet. But it could be the target
for Port Scan Attack.
5
NOTCPRST
But if this Bit is set as ‘1’, W5100S does not transmit RST Packet against
Peer TCP Packet having wrong port.
1 : Block sending RST Packet
0 : Normal
UDP Port Unreachable Packet Block
If Peer transmits UDP Packet to a Port that does not exist on W5100S.
W5100S automatically transmits ICMP Packet (Destination Port
Unreachable) to Peer. But it could be the target for Port Scan Attack.
4
UDPURB
But if this Bit is set as ‘1’, W5100S does not transmit ICMP Packet
(Destination Port Unreachable).
1 : Block sending ICMP Packet (Destination Port Unreachable Message)
0 : Normal
Wake On LAN
This Bit decides receiving WOL Packet.
3
WOL
1 : Receive WOL
0 : No Receive WOL
2
-
Reserved
Force ARP
UDP Mode SOCKET transmits ARP Request once before the first UDP
Data Packet when it sends Data continuously to the same Peer. But if
1
FARP
this Bit is set to ‘1’, it sends ARP Request for every UDP Data Packet.
1 : Transmit ARP Request for every UDP Data Packet
0 : Normal
W5100S Datasheet Version1.0.0
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0
-
Reserved
3.1.20 PHAR (Destination Hardware Address Register on PPPoE)
[R=W] [0x0032-0x0037] [0x0000]
PHAR configures PPPoE Server Hardware Address only on PPPoE.
Ex) PHAR = “11:22:33:AA:BB:CC”
PHAR0(0x0032)
PHAR1(0x0033)
PHAR2(0x0034)
0x11
0x22
0x33
PHAR3(0x0035)
PHAR4(0x0036)
PHAR5(0x0037)
0xAA
0xBB
0xCC
3.1.21 PSIDR (Session ID Register on PPPoE)
[R=W] [0x0038-0x0039] [0x0000]
PSID configures PPPoE Sever Session ID on PPPoE.
Ex) PSIDR = 0x1234
PSIDR0(0x0038)
PSIDR1(0x0039)
0x12
0x34
3.1.22 PMRUR (PPPoE Maximum Receive Unit Register)
[R=W] [0x003A-0x003B] [0xFFFF]
PMRUR configures MRU (Maximum Receive Unit) on PPPoE and the value must not be
exceeded 1472. If it is set bigger than 1472, it is configured 1472. And also PMRUR must be
configured before SOCKET OPEN (Sn_CR [OPEN] = ’1’).
Ex) PMUR = 1000 (0x03E8)
PMUR0(0x0038)
PMUR1(0x0039)
0x03
0xE8
3.1.23 PHYSR (PHY Status Register)
[RO] [0x003C] [0x00]
PHYSR indicates PHY Operation Mode and LINK status configured by PHYCR0 (PHY Control
Register 0)
7
6
5
4
3
2
1
0
CABOFF
-
AUTO
SPD
DPX
FDPX
FSPD
LINK
RO
RO
RO
RO
RO
RO
RO
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W5100S Datasheet Version1.0.0
Bit
Symbol
Description
Cable OFF Bit
7
CABOFF
1 : Cable Unplugged
0 : Cable Plugged
6
-
Reserved
Auto Negotiation Bit configured by PHYCR0[2]
5
AUTO
1 : Disable Auto Negotiation
0 : Enable Auto Negotiation
Speed Bit configured by PHYCR0[1]
4
SPD
1 : 10Mbps
0 : 100Mbps
Duplex Bit configured by PHYCR0[0]
3
DPX
1 : Half Duplex
0 : Full Duplex
Flag Duplex Bit (When Link up)
2
FDPX
1 : Half Duplex
0 : Full Duplex
Flag Speed Bit (When Link up)
1
FSPD
1 : 10Mbps
0 : 100Mbps
Flag Link Bit
0
LNK
1 : Link Up
0 : Link Down
3.1.24 PHYRAR (PHY Register Address Register)
[R=W] [0x003F] [0x00]
PHYRAR configures PHY Register Address of Internal Ethernet PHY.
7
6
5
4
3
2
1
0
-
-
-
A4
A3
A2
A1
A0
R=W
R=W
R=W
R=W
R=W
Bit
Symbol
Description
7
-
Reserved
6
-
Reserved
5
-
Reserved
[4:0]
A[4:0]
PHY Register Address
W5100S Datasheet Version1.0.0
33 / 109
3.1.25 PHYDIR (PHY Data Input Register)
[R=W] [0x0040-0x0041] [0x0000]
PHTDIR writes PHY Register specified by PHYAR.
Ex) PHYDIR = 0x1234
PHYDIR0(0x0040)
PHYDIR1(0x0041)
0x34
0x12
3.1.26 PHYDOR (PHY Data Output Register)
[RO] [0x0042-0x0043] [0x0000]
PHYDOR reads the PHY Register specified by PHYAR
Ex) PHYDOR = 0x1234
PHYDOR0(0x0042)
PHYDPR1(0x0043)
0x34
0x12
3.1.27 PHYACR (PHY Access Control Register)
[AC] [0x0044] [0x00]
PHYACR configures Access Type of PHY Register specified by PHYAR
Access Type
Value
Write
0x01
Read
0x02
3.1.28 PHYDIVR (PHY Division Register)
[R=W] [0x0045] [0x01]
Internal Ethernet PHY uses the divided Clock of System Operation Clock (SYS_CLK). And this
divided Clock must not be exceeded 2.5MHz.
Value
Divider
SYS_CLK=100MHz
SYS_CLK=25MH
0x00
1/32
3.125MHz (N/A)
781.25KHz
0x01
1/64
1.5625MHz
390.625KHz
others
1/128
781.25KHz
195.3125KHz
3.1.29 PHYCR0 (PHY Control Register 0)
[WO] [0x0046] [0x00]
PHYCR configures Ethernet PHY Operation Mode such as Auto Negotiation, Speed and Duplex.
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W5100S Datasheet Version1.0.0
Before set PHYCR, PHYLCKR (PHY Lock Register) must be on Unlock Mode.
7
6
5
4
3
2
1
0
-
-
-
-
-
AUTO
SPD
DPX
WO
WO
WO
Bit
Symbol
[7:3]
-
Description
Reserved
Auto Negotiation
If AUTO is set to ‘1’, SPD and DPX are ignored.
2
AUTO
1 : Disable Auto Negotiation
0 : Enable Auto Negotiation
10/100 Speed
When AUTO is ‘0’ , it can configures 10Mbps or 100Mbps
1
SPD
1 : 10 Mbps
0 : 100 Mbps
Full/Half Duplex
When AUTO is ‘0’ , it can configures Half Duplex or Full Duplex
0
DPX
1 : HDX
0 : FDX
3.1.30 PHYCR1 (PHY Control Register 1)
[R=W] [0x0047] [0x41]
PHYCR configures Ethernet PHY Operation Mode such as PHY Power Down Mode, PHY Reset.
Before set PHYCR, PHYLCKR (PHY Lock Register) must be on Unlock Mode.
7
6
5
4
3
2
1
0
-
-
PWDN
-
-
-
-
Reset
W0
W0
R=W
W0
W0
W0
W0
AC
Bit
Symbol
[7:6]
-
Description
Reserved
PHY Power Down
5
PWDN
1 : Enable Power Down Mode and SYS_CLK switching 25MHz
0 : Disable Power Down Mode and SYS_CLK selected by MR2[CLKSEL]
W5100S Datasheet Version1.0.0
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MR2[CLKSEL]
SYS_CLK
0
100 MHz
1
25 MHz
(Ref 7.4.1 Reset Timing)
[4:1]
-
Reserved
PHY Reset
When PHY Reset Bit is set to ‘0’, SYS_CLK is switched to 25MHz. After
PHY Reset completed, this Bit is automatically cleared and SYS_CLK is
0
RST
turn back to the previous clock. (Ref 7.4.1 Reset Timing)
1 : Normal
0 : PHY H/W Reset
3.1.31 SLCR (SOCKET-less Command Register)
[RW] [0x004C] [0x00]
SLCR configures ARP and PING Request Transmission Command. Each Command must not be
executed at the same time and not configured before SLCR cleared. The results of each
Command is shown via SLIR (SOCKET-less Interrupt Register)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
ARP
PING
-
-
-
-
-
-
AC
AC
Bit
Symbol
[7:2]
-
Description
Reserved
ARP Request Transmission Command
1
ARP
1 :Transmit ARP packet
0 : Ready
PING Request Transmission Command
0
PING
1: Transmit PING Request
0 : Ready
3.1.32 SLRTR (SOCKET-less Retransmission Time Register)
[R=W] [0x004D-0x004E] [0x07D0]
SLRTR sets SLCR Retransmission Time. The unit is 100us. If there is no Response for ARP or
PING Request Packet transmitted by SLCR, W5100S automatically retransmits Request Packet
every SLRTR. (Ref 4.8 Retransmission)
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W5100S Datasheet Version1.0.0
Ex) SLRTR = 5000 (0x1388),
5000 * 100us = 0.5s
SLRTR0(0x004D)
SLRTR1(0x004E)
0x013
0x88
3.1.33 SLRCR (SOCKET-less Retransmission Count Register)
[R=W] [0x004F] [0x00]
SLRCR sets SLCR Retransmission Number. If the number of Retransmission exceeds SLRCR,
SOCKET-less Timeout (SLIR [TIMEOUT] = ‘1’) occurs. (Ref 4.8 Retransmission)
3.1.34 SLPIPR (SOCKET-less Peer IP Address Register)
[R=W] [0x0050-0x0053] [0x00000000]
SLPIPR configures Peer IP Address for ARP or Ping Request Packet transmitted by SLCR.
Ex) SLPIPR = “192.169.0.21”
SLPIPR0(0x0050)
SLPIPR1(0x0051)
SLPIPR2(0x0052)
SLPIPR3(0x0053)
192(0xC0)
168(0xA8)
0(0x00)
21(0x15)
3.1.35 SLPHAR (SOCKET-less Peer Hardware Address Register)
[RO] [0x0054-0x0059] [0x000000000000]
If W5100S received ARP Reply against SLCR [ARP] and SLIPR [ARP] is set to ‘1’, Peer Hardware
Address from ARP Reply is written on SLPHAR.
Ex) SLPHAR = “11:22:33:AA:BB:CC”
SLPHAR0(0x0054)
SLPHAR1(0x0055)
SLPHAR2(0x0056)
0x11
0x22
0x33
SLPHAR3(0x0057)
SLPHAR4(0x0058)
SLPHAR5(0x0059)
0xAA
0xBB
0xCC
3.1.36 PINGSEQR (PING Sequence-number Register)
[R=W] [0x005A-0x005B] [0x0000]
PINGSEQR configures Sequence Number for PING Request Packet and it is not automatically
increased.
Ex) PINGSEQR = 1000 (0x03E8)
PINGSEQR0(0x005A)
PINGSEQR1(0x005B)
0x03
0xE8
W5100S Datasheet Version1.0.0
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3.1.37 PINGIDR (PING ID Register)
[R=W] [0x005C-0x005D] [0x0000]
PINGIDR configures ID for PING Request Packet.
Ex) PINGIDR = 256 (0x0100)
PINGIDR0(0x005C)
PINGIDR1(0x005D)
0x01
0x00
3.1.38 SLIMR (SOCKET-less Interrupt Mask Register)
[R=W] [0x005E] [0x00]
SLIMR is used for corresponding SLIR (SOCKET-less Interrupt Register) Bit Mask.
7
6
5
4
3
2
1
0
-
-
-
-
-
TIMEOUT
ARP
PING
-
-
-
-
-
R=W
R=W
R=W
Bit
Symbol
[7:3]
-
Description
Reserved
TIMEOUT Interrupt Mask
2
TIMEOUT
1 : Enable TIMEOUT Interrupt
0 : Disable TIMEOUT Interrupt
ARP Interrupt Mask
1
ARP
1 : Enable ARP Interrupt
0 : Disable ARP Interrupt
PING Interrupt Mask
0
PING
1 : Enable PING Interrupt
0 : Disable PING Interrupt
3.1.39 SLIR (SOCKET-less Interrupt Register)
[RW] [0x005F] [0x00]
When SOCKET-less Event occurs, the corresponding Bit in SLIR is set to ‘1’. If the Event occurs
and the corresponded Interrupt Mask Bit in SLIMR is set to ‘1’ and internal Interrupt Pending
Timer Counter is ‘0’, INTn is asserted to Low. When the Event is cleared or the corresponding
Mask Bit is set to ‘0’, INTn is de-asserted to High.
7
6
5
4
3
2
1
0
-
-
-
-
-
TIMEOUT
ARP
PING
-
-
-
-
-
WC
WC
WC
38 / 109
W5100S Datasheet Version1.0.0
Bit
Symbol
[7:3]
-
2
TIMEOUT
1
ARP
0
PING
Description
Reserved
TIMEOUT Interrupt
When TIMEOUT occurs, this Bit is set to ‘1’.
ARP Interrupt
When ARP Reply received, this Bit is set to ‘1’.
PING Interrupt
When PING Reply received, this Bit is set to ‘1’.
3.1.40 CLKLCKR (Clock Lock Register)
[WO] [0x0070] [0x00]
CLKLCKR status must be Unlock to set MR2 [CLKSEL]. Before HOST changes CLKLCKR status,
CLKLCKR has the previous status.
Unlock
Lock
0xCE
Others
3.1.41 NETLCKR (Network Lock Register)
[WO] [0x0071] [0x00]
NETLCKR status must be Unlock to set GWR, SUBR, SHAR and SIPR. Before HOST changes
NETLCKR status, LETLCKR has the previous status.
Unlock
Lock
0xC5
0x3A
3.1.42 PHYLCKR (PHY Lock Register)
[WO] [0x0072] [0x00]
PHYLCKR status must be Unlock to set PHYCR0 and PHYCR1. Before HOST changes PHYLCKR
status, PHYLCKR has the previous status.
Unlock
Lock
0x53
Others
3.1.43 VERR (Version Register)
-
[RO] [0x0080] [0x51]
VERR shows W5100S Version.
3.1.44 TCNTR (Ticker Counter Register)
[RO][0x0082-0x0083][0x0000]
W5100S Datasheet Version1.0.0
39 / 109
TCNTR is W5100S Internal Counter, it has automatically increased since SYS_CLK operating.
The unit is 100us.
3.1.45 TCNTCLR (Ticker Counter Clear Register)
[WO][0x0088][0x00]
With TCNTCLR Write Access, TCNTR Counter value is initialized.
40 / 109
W5100S Datasheet Version1.0.0
3.2
SOCKET Register
3.2.1 Sn_MR (SOCKET n Mode Register)
[R=W] [0x0000+0x0100*(n+4)] [0x00]
Sn_MR configures SOCKET Mode and Option. Sn_MR must be set before SOCKET OPEN (Sn_CR
[OPEN] = ‘1’).
7
6
5
4
3
2
1
0
MULTI
MF
ND / MC
-
P3
P2
P1
P0
R=W
R=W
R=W
-
R=W
R=W
R=W
R=W
Bit
Symbol
Description
UDP Multicast
This Bit is valid only on UDP Mode. (Ref 4.4.3 UDP Multicast)
7
MULTI
1 : Enable UDP Multicast
0 : Disable UDP Multicast
MAC Filter Enable
This Bit is valid only on MACRAW Mode.
If This Bit is set to ‘1’, W5100S block all Packets without Multicast,
6
MF
Broadcast and the Packets no having Source MAC (SHAR).
1 : Enable MAC Filter.
0 : Disable MAC Filter
No Delayed ACK (ND)
This Bit is valid only on TCP Mode.
If this Bit is set to ‘1’, TCP Mode SOCKET transmits ACK Packet without
waiting RTR after receiving Data Packet from Peer.
1 : Enable No Delayed ACK
0 : Disable No Delayed ACK
5
ND / MC
Ref) After Sn_CR[RECV] Command operating, If TCP Mode SOCKET
Window Size is smaller than MSS, it sends ACK packet immediately. (no
concerned with ND Bit)
Multicast IGMP Version (MC)
This Bit is valid only on UDP Multicast Mode (Sn_MR[3:0] = ‘UDP’ &
Sn_MR[MULTI] = ‘1’)
W5100S Datasheet Version1.0.0
41 / 109
0 : Using IGMP version 2
1 : Using IGMP version 1
4
-
Reserved
Protocol Mode
This Bits set SOCKET Protocol Mode. MACRAW Mode is used only with
SOCKET 0.
[3:0]
P[3:0]
P3
P2
P1
P0
Protocol Mode
0
0
0
0
SOCKET Closed
0
0
0
1
TCP
0
0
1
0
UDP
0
0
1
1
IPRAW
0
1
0
0
MACRAW
3.2.2 Sn_CR (SOCKET n Command Register)
[RW][AC] [0x0001+0x0100*(n+4)] [0x00]
Sn_CR configures SOCKET n Command. After W5100S executes SOCKET Command, the
corresponding Sn_CR Bit is automatically cleared. Next SOCKET Command must be configured
after previous SOCKET Command Bit cleared.
Value
Symbol
Description
SOCKET OPEN Command
Before OPEN Command, HOST must be set SOCKET Mode with Sn_MR.
After OPEN Command done, Sn_SR shows SOCKET Status.
0x01
OPEN
Sn_MR (P[3:0])
Sn_MR_CLOSE
(‘0000’)
Sn_SR
SOCK_CLOSED (0x00)
Sn_MR_TCP
(‘0001’)
SOCK_INIT (0x13)
Sn_MR_UDP
(‘0010’)
SOCK_UDP (0x22)
Sn_MR_IPRAW
(‘0011’)
S0_MR_MACRAW
(‘0100’)
SOCK_IPRAW (0x32)
SOCK_MACRAW (0x42)
TCP LISTEN Command
0x02
LISTEN
After LISTEN Command, TCP Mode SOCKET waits for SYN Packet from
Peer for TCP Connection in SOCK_INIT (Sn_SR = ‘0x13’).
(Ref 4.3.1 TCP Server)
TCP CONNECT Command
0x04
CONNECT
After CONNECT Command, TCP Mode SOCKET transmits SYN Packet to
Peer for TCP Connection in SOCK_INIT (Sn_SR = ‘0x13’).
42 / 109
W5100S Datasheet Version1.0.0
(Ref 4.3.2 TCP Client)
TCP DISCON Command
0x08
DISCON
After DISCON Command, TCP Mode SOCKET transmits FIN Packet to Peer
for TCP Disconnection in SOCK_ESTABLESHED (Sn_SR = ‘0x17’) or
SOCK_CLOSE_WAIT (Sn_SR = ‘0x1C’).
SOCKET CLOSE Command
0x10
CLOSE
After CLOSE Command, SOCKET is closed (Sn_SR = ‘0x00’).
*Caution : Sn_SR is changed to SOCK_CLOSE without FIN Packet sending in TCP
Mode
SOCKET SEND Command
After SEND Command, SOCKET sends Data as much as the calculated size
between Sn_TX_WR (SOCKET n TX Write Point Register) and Sn_TX_RD
(SOCKET n RX Read Pointer Register). The Sent Data must not be
exceeded Sn_RX_FSR (SOCKET n TX Free Buffer Size Register). HOST
must execute next SEND Command after Sn_IR [SENDOK] is set to ‘1’.
On TCP and UDP Mode, if the calculated size is over MSS (Maximum
Segment Size), Data is separated by MSS and sent.
0x20
SEND
On the other hands, on IPRAW and MACRAW Mode, if Data is over MSS,
HOST must separate it by less than MSS.
On TCP Mode, if Peer receives Data (It means TCP Mode SOCKET receives
ACK Packet from Peer), Sn_RX_FSR is automatically increased by sent
Data Size. But if not, Sn_IR [TIMEOUT] is set to ‘1’ and Sn_SR is changed
to SOCK_CLOSED.
On UDP, IPRAW and MACRAW Mode, Sn_TX_FSR is increased by sent Data
Size after Sn_IR [SENDOK] is set to ‘1’.
SOCKET SEND_MAC Command
SEND_MAC Command is used only on UDP and IPRAW Mode. Only the
0x21
SEND_MAC
different with SEND Command is that it skips ARP Process. Before using
SEND_MAC Command, HOST must set Sn_DHAR (SOCKET n Destination
Hardware Address Register) with Peer MAC Address.
SOCKET SEND_KEEP Command
SEND_KEEP Command is used only on TCP Mode. Before using SEND_KEEP
0x22
SEND_KEEP
Command, TCP Mode SOCKET must send more than 1 byte Data to Peer.
After SEND_KEEP Command, TCP Mode SOCKET continues to send Keep
alive (KA) Packet and check the TCP connection. If there is no Peer
W5100S Datasheet Version1.0.0
43 / 109
response, KA Packet is retransmitted. After Retransmission Time, Sn_IR
[TIMEOUT] is set to ‘1’ and Sn_SR is changed to SOCK_CLOSED.
(Ref 4.3.3.2 Keep AliveKeep )
SOCKET RECV Command
After reading received Data from SOCKET n RX Buffer Block, HOST
updates Sn_RX_RD (SOCKET n Read Pointer Register) with RECV
Command.
0x40
RECV
(Ref 오류! 참조 원본을 찾을 수 없습니다. 오류! 참조 원본을 찾을
수 없습니다., 3.2.19 Sn_RX_RD (SOCKET n RX Read Pointer Register) and
오류! 참조 원본을 찾을 수 없습니다. 오류! 참조 원본을 찾을 수
없습니다.)
3.2.3 Sn_IR (SOCKET n Interrupt Register)
[RW] [0x0002+0x0100*(n+4)] [0x00]
When Sn_IR Event occurs, the corresponding Interrupt Bit is set to ‘1’.
7
6
5
4
3
2
1
0
-
-
-
SENDOK
TIMEOUT
RECV
DISCON
CON
WC
WC
WC
WC
WC
Bit
Symbol
[7:5]
-
Description
Reserved
SEND OK Interrupt
4
SENDOK
1 : When SEND Command is completed
0 : When others
TIMEOUT Interrupt
3
TIMEOUT
1 : When the number of retransmission is exceeded Sn_RCR (SOCKET
Retransmission Count Register) in ARP or TCP communication.
0 : When others
RECEIVED Interrupt
2
RECV
1 : When SOCKET received Data or Data still remained in SOCKET n RX
Buffer Block after Sn_CR [RECV]
0 : When others
DISCONNECTED Interrupt
1
DISCON
1: When FIN Packet sent and disconnection completed, or When FIN
Packet received or RST Packet received.
0 : When others
0
44 / 109
CON
CONNECTED Interrupt
W5100S Datasheet Version1.0.0
1 : When TCP Connection is successfully done. (Sn_MR [3:0]=’TCP)
0 : When others
3.2.4 Sn_SR (SOCKET n Status Register)
[RO] [0x0003+0x0100*(n+4)] [0x00]
Sn_SR describes the Status of SOCKET. Sn_SR is set by Sn_CR or Data transmit/receive.
Value
Symbol
Description
0x00
SOCK_CLOSED
0x13
SOCK_INIT
0x14
SOCK_LISTEN
0x17
SOCK_ESTABLISHED
SOCKET is TCP Mode and TCP Connection is done
0x1C
SOCK_CLOSE_WAIT
SOCKET is TCP Mode and received disconnection request
0x22
SOCK_UDP
0x32
SOCK_IPRAW
0x42
SOCK_MACRAW
SOCKET Closed
SOCKET Opened as TCP Mode
SOCKET is TCP Mode and wait for Peer Connection
SOCKET Opened as UDP Mode
SOCKET Opened as IPRAW Mode
SOCKET Opened as MACRAW Mode
The below table shows a temporary status indicated during changing the status of SOCKET n.
Value
Symbol
0x15
SOCK_SYNSENT
SOCKET n sent the Connect request
0x16
SOCK_SYNRECV
SOCKET n received the Connect request
0x18
SOCK_FIN_WAIT
0X1B
SOCK_TIME_WAIT
0X1D
SOCK_LAST_ACK
W5100S Datasheet Version1.0.0
Description
SOCKET n is in SOCKET Closed
45 / 109
SNED/SEND_MAC/RECV
SOCK_IPRAW
: Status
(when Sn_MR[3:0]='IPRAW')
SEND/SEND_MAC/RECV
: Command
: SEND/RECV packet
or Timeout
OPEN CLOSE
OPEN
SOCK_UDP
(when Sn_MR[3:0]='UDP')
CLOSE
SOCK_CLOSED
CLOSE
SOCK_MACRAW
OPEN
(START/END)
(when Sn_MR[3:0]='MACRAW')
RECV ACK
OPEN CLOSE
SOCK_INIT
CLOSE
SOCK_LAST_ACK
(when Sn_MR[3:0]='TCP')
LISTEN
SOCK_LISTEN
SEND SYN/ACK
RECV ACK
RECV FIN
or
Timeout
CONNECT
Timeout
SOCK_SYNSENT
RECV SYN
SOCK_SYNRECV
SEND/RECV
Timeout
RECV SYN/ACK
SEND ACK
CLOSE DISCON
SOCK_FIN_WAIT
SOCK_TIME_WAIT
Timeout
CLOSE
SOCK_CLOSE_WAIT
DISCON
SOCK_ESTABLISHED
SEND/RECV
RECV FIN
SEND/RECV
Figure 4 State Diagram
3.2.5 Sn_PORTR (SOCKET n Source Port Register)
[R=W] [0x0004+0x0100*(n+4), 0x0005+0x0100*(n+4)] [0x0000]
Sn_PORTR configures Source Port Number of SOCKET n.
Ex) S0_PORTR = 5000 (0x1388)
S0_PORTR0(0x0404)
S0_PORTR1(0x0405)
0x013
0x88
3.2.6 Sn_DHAR (SOCKET n Destination Hardware Address
Register)
[RW] [0x0006+0x0100*(n+4), 0x0007+0x0100*(n+4), 0x0008+0x0100*(n+4),
0x0009+0x0100*(n+4), 0x000A+0x0100*(n+4), 0x000B+0x0100*(n+4)]
[0x000000000000]
Peer MAC Address in Peer Packet is written on Sn_DHAR. On TCP Mode, Sn_DHAR is valid after
CONNECT Command. On UDP and IPRAW Mode, Sn_DHAR is valid after SEND Command.
If HOST uses SEND_MAC Command, Sn_DHAR must be set with Peer MAC Address before
Command. On UDP Multicast Mode, Sn_DHAR must be configured with Multicast Group MAC
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W5100S Datasheet Version1.0.0
Address. (Ref 4.4.3 UDP Multicast)
Ex) S0_DHAR = “11:22:33:AA:BB:CC”
S0_DHAR0(0x0406)
S0_DHAR1(0x0407)
S0_DHAR2(0x0408)
0x11
0x22
0x33
S0_DHAR3(0x0409)
S0_DHAR4(0x040A)
S0_DHAR5(0x040B)
0xAA
0xBB
0xCC
3.2.7 Sn_DIPR (SOCKET n Destination IP Address Register)
[RW] [0x000C+0x0100*(n+4), 0x000D+0x0100*(n+4), 0x000E+0x0100*(n+4),
0x000F+0x0100*(n+4)] [0x00000000]
Sn_DIPR is set with Peer IP Address. On TCP Mode, Sn_DIPR must be set with Peer IP Address
before Connection, or indicates IP Address of connected Peer. On UDP and IPRAW Mode,
Sn_DIPR must be set with Peer IP Address before sending Data.
On UDP Multicast Mode, Sn_DIPR must be configured with Multicast Group IP Address. (Ref
4.4.3 UDP Multicast)
On UDP, UDP Multicast and IPRAW Mode, Peer IP Address is stored with Data in SOCKET n RX
Buffer.
Ex) S0_DIPR = “192.168.0.11”
S0_DIPR0(0x040C)
S0_DIPR1(0x040D)
S0_DIPR2(0x040E)
S0_DIPR3(0x040F)
192 (0xC0)
168 (0xA8)
0 (0x00)
11 (0x0B)
3.2.8 Sn_DPORTR (SOCKET n Destination Port Register)
[R=W] [0x0010+0x0100*(n+4), 0x0011+0x0100*(n+4)] [0x0000]
Sn_DPORTR is set with Peer Port Number. On TCP Mode, Sn_DPORTR must be set with Peer
Port Number before Connection, or indicates Port Number of connected Peer. On UDP and
IPRAW Mode, Sn_DPORTR must be set with Peer Port Number before sending Data.
On UDP Multicast Mode, Sn_DPORTR must be configured with Multicast Group Port Number.
(Ref 4.4.3 UDP Multicast)
On UDP, UDP Multicast and IPRAW Mode, Peer Port Number is stored with Data in SOCKET n
RX Buffer.
Ex) S0_DPORTR = 5000 (0x1388),
S0_DPORTR0(0x0410)
S0_DPORTR1(0x0411)
0x13
0x88
3.2.9 Sn_MSS (SOCKET n Maximum Segment Size Register)
[R=W] [0x0012+0x0100*(n+4), 0x0013+0x0100*(n+4] [0xFFFF]
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Sn_MSS sets SOCKET n MSS and it must be set before Sn_CR [OPEN]. Sn_MSS must not be
exceeded specified size as below table.
Mode
Normal (MR [PPPoE]=’0’) Range
PPPoE (MR [PPPoE]=’1’) Range
TCP
1~1460
1~1452
UDP
1~1472
1~1464
IPRAW
1480
1472
MACRAW
1514
Ex) S0_MSS = 1460 (0x05B4),
S0_MSS0(0x0412)
S0_MSS1(0x0413)
0x05
0xB4
3.2.10 Sn_PROTOR (SOCKET n IP Protocol Register)
[R=W] [0x0014+0x0100*(n+4)] [0x0000]
Sn_PROTOR configures Protocol Number (Ref IANA_Protocol Number) of IP Header except for
TCP (0x06), UDP (0x11) and IGMP (0x01).
On IPRAW Mode, only the Protocol configured in Sn_PROTR can be transmitted and received.
Ex) ICMP (Internet Control Message Protocol) = 0x01
3.2.11 Sn_TOS (SOCKET n IP Type Of Service Register)
[R=W] [0x0015+0x0100*(n+4)] [0x00]
Sn_TOS configures the TOS (Type Of Service) of IP Header. (Ref IANA_IP Parameters)
3.2.12 Sn_TTL (SOCKET n IP Time To Live Register)
[R=W] [0x0016+0x0100*(n+4)] [0x80]
Sn_TTL configures TTL (Time To Live) of IP header. (Ref IANA_IP Parameters)
3.2.13 Sn_RXBUF_SIZE (SOCKET n RX Buffer Size Register)
[RW] [0x001E+0x0100*(n+4)] [0x02]
Sn_RXBUF_SIZE configures SOCKET n RX Buffer Size as 0, 1, 2, 4 and 8 Kbytes. RX Memory is
sequentially allocated from SOCKET 0 to SOCKET 3. The total sum of Sn_RXBUF_SIZE must not
be exceeded 8 Kbytes. Sn_RXBUF_SIZE can also be configured by RMSR.
Value (Dec)
0
1
2
4
8
Buffer size
0KB
1KB
2KB
4KB
8KB
Ex) S0_RXBUF_SIZE = 8KB
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W5100S Datasheet Version1.0.0
S0_RXBUF_SIZE(0x041E)
0x08
3.2.14 Sn_TXBUF_SIZE (SOCKET n TX Buffer Size Register)
[RW] [0x001F+0x0100*(n+4)] [0x02]
Sn_TXBUF_SIZE configures SOCKET n TX Buffer Size as 0, 1, 2, 4 and 8 Kbytes. TX Memory is
sequentially allocated from SOCKET 0 to SOCKET 3. The total sum of Sn_TXBUF_SIZE must not
be exceeded 8 Kbytes. Sn_TXBUF_SIZE can also be configured by RMSR.
Value (Dec)
0
1
2
4
8
Buffer size
0KB
1KB
2KB
4KB
8KB
Ex) S0_TXBUF_SIZE= 4KB
S0_TXBUF_SIZE(0x041F)
0x04
3.2.15 Sn_TX_FSR (SOCKET n TX Free Size Register)
[RO] [0x0020+0x0100*(n+4), 0x0021+0x0100*(n+4)] [0x0800]
Sn_TX_FSR indicates SOCKET n TX Free Buffer Size.
In UDP, IPRAW and MACRAW mode,
Sn_TX_FSR = | Sn_TX_WR(1) – Sn_TX_RD(2) | + 1
In TCP mode,
Sn_TX_FSR = | Sn_TX_WR – Internal Pointer(3) | + 1
(1) SOCKET n TX Write Pointer Register
(2) SOCKET n TX Read Pointer Register
(3) TCP ACK Pointer managed by W5100S
Data to be stored in SOCKET n TX Buffer must not be bigger than Sn_TX_FSR.
Ex) S0_TX_FSR = 1024 (0x0400)
S0_TX_FSR0(0x0420)
S0_TX_FSR1(0x0421)
0x04
0x00
3.2.16 Sn_TX_RD (SOCKET n TX Read Pointer Register)
[RO] [0x0022+0x0100*(n+4), 0x0023+0x0100*(n+4)] [0x0000]
Sn_TX_RD indicates the last Data Address in SOCKET n TX Buffer Block after transmitting.
Sn_TX_RD is initialized by Sn_CR [OPEN]. On TCP Mode, Sn_TX_RD is re-configured in TCP
Connection Process. By Sn_CR [SEND] and Sn_CR [SEND_MAC], Sn_TX_WR (SOCKET n TX Write
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Pointer Register) is increased to Data Size. After transmitting Data, Sn_TX_RD increases by
Sn_TX_WR and Sn_IR [SENDOK] occurs.
Ex) S0_TX_RD = 0xd4b3
S0_TX_RD0(0x0422)
S0_TX_RD1(0x0423)
0xd4
0xb3
3.2.17 Sn_TX_WR (SOCKET n TX Write Pointer Register)
[RW] [0x0024+0x0100*(n+4), 0x0025+0x0100*(n+4)] [0x0000]
Sn_TX_WR indicates the last stored Data Address in SOCKET n TX Buffer Block. Sn_TX_RD is
initialized by Sn_CR [OPEN]. On TCP Mode, Sn_TX_RD is re-configured in TCP Connection
Process. Before Sn_CR [SEND] and Sn_CR [SEND_MAC], Sn_TX_WR must be set as transmitting
Data Size.
Ex) S0_TX_WR = 0x0800
S0_TX_WR0(0x0424)
S0_TX_WR1(0x0425)
0x08
0x00
3.2.18 Sn_RX_RSR (SOCKET n RX Received Size Register)
[RO] [0x0026+0x0100*(n+4), 0x0027+0x0100*(n+4)] [0x0000]
Sn_RX_RSR indicates received Data Size in SOCKET n RX Buffer Block.
In TCP, UDP, IPRAW and MACRAW mode,
Sn_RX_RSR = | Sn_RX_WR(1) – Sn_RX_RD(2) |
(1) SOCKET n RX Write Pointer Register
(2) SOCKET n RX Read Pointer Register
Ex) S0_RX_RSR = 2048 (0x0800)
S0_RX_RSR0(0x0426)
S0_RX_RSR1(0x0427)
0x08
0x00
3.2.19 Sn_RX_RD (SOCKET n RX Read Pointer Register)
[RW] [0x0028+0x0100*(n+4), 0x0029+0x0100*(n+4)] [0x0000]
Sn_RX_RD is the last Data Address read by HOST in SOCKET n RX Buffer Block. HOST is
available to read Data from Sn_RX_RD to Sn_RX_WR in SOCKET n RX Buffer Block. After
setting Sn_RX_RD as much as Data read, HOST must set Sn_CR [RECV] to update Sn_RX_RD.
Ex) S0_RX_RD =1536(0x0600)
S0_RX_RD0(0x0428)
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S0_RX_RD1(0x0429)
W5100S Datasheet Version1.0.0
0x06
0x00
3.2.20 Sn_RX_WR (SOCKET n RX Write Pointer Register)
[RO] [0x002A+0x0100*(n+4), 0x002B+0x0100*(n+4)] [0x0000]
Sn_RX_WR is the last received Data Address in SOCKET n RX Buffer Block. If received Data is
smaller than Sn_RX_RSR, it is stored in SOCKET n RX Buffer Block and Sn_RX_WR increases by
stored Data Size.
Ex) S0_RX_WR = 1536(0x0600)
S0_RW_WR0(0x042A)
S0_RW_WR1(0x042B)
0x06
0x00
3.2.21 Sn_IMR (SOCKET n Interrupt Mask Register)
[R=W] [0x002C+0x0100*(n+4)] [0xFF]
Sn_IMR is used for the corresponding Sn_IR Bit Mask.
7
6
5
4
3
2
1
0
-
-
-
SENDOK
TIMEOUT
RECV
DISCON
CON
-
-
-
R=W
R=W
R=W
R=W
R=W
Bit
Symbol
Description
[7:5]
-
4
SENDOK
Sn_IR[SENDOK] Interrupt Mask
3
TIMEOUT
Sn_IR[TIMEOUT] Interrupt Mask
2
RECV
1
DISCON
0
CON
Reserved
Sn_IR[RECV] Interrupt Mask
Sn_IR[DISCON] Interrupt Mask
Sn_IR[CON] Interrupt Mask
3.2.22 Sn_FRAGR (SOCKET n Fragment Offset in IP Header
Register)
[R=W] [0x002D+0x0100*(n+4), 0x002E+0x0100*(n+4)] [0x4000]
Sn_FRAGR configures Fragment Offset in IP Header.
Ex) S0_FRAG0 = 0x0000 (Don’t Fragment)
S0_FRAGR0(0x042D)
S0_FRAGR1(0x042E)
0x00
0x00
3.2.23 Sn_MR2 (SOCKET n Mode register 2)
[R=W] [0x002F+0x0100*(n+4)] [0x00]
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Sn_MR2 configures SOCKET n Option. Sn_MR2 must be set before Sn_CR[OPEN] = ‘1’.
7
6
5
4
3
2
1
0
-
MBBLK
MMBLK
IPV6BLK
-
-
BRDB
UNIB
-
R=W
R=W
R=W
-
-
R=W
R=W
Bit
Symbol
7
-
Description
Reserved
Broadcast Blocking on MACRAW Mode
On MACRAW Mode, this Bit is set to ‘1’ to block Broadcast Packet.
6
MBBLK
0 : Disable Broadcast Blocking
1 : Enable Broadcast Blocking
Multicast Blocking on MACRAW Mode
On MACRAW Mode, this Bit is set to ‘1’ to block Multicast Packet.
5
MMBLK
0 : Disable Multicast Blocking
1 : Enable Multicast Blocking
IPv6 Packet Blocking on MACRAW Mode
On MACRAW Mode, this Bit is set ‘1’ to block IPv6 Packet.
4
IPV6BLK
0 : Disable IPv6 Blocking
1 : Enable IPv6 Blocking
[3:2]
-
Reserved
Broadcast Blocking on UDP Mode/ Force PSH on TCP Mode
*Broadcast Blocking on UDP Mode
On UDP Mode, this Bit is set ‘1’ to block UDP Broadcast Packet.
0 : Disable Broadcast Blocking
1 : Enable Broadcast Blocking
1
BRDB
* Force PSH on TCP Mode
On TCP Mode, this Bit is set to ‘1’ to set PSH Flag in all transmitting
Data Packet.
1: Force PSH Flag
0: No Force PSH Flag
0
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UNIB
Unicast Blocking on UDP Multicast Mode
W5100S Datasheet Version1.0.0
On UDP Multicast Mode, this Bit is set to ‘1’ to block UDP Unicast
Packet.
0 : Disable Unicast Blocking
1 : Enable Unicast Blocking
3.2.24 Sn_KPALVTR (SOCKET n Keep Alive Timer Register)
[RO] [0x0030+0x0100*(n+4)] [0x00]
Sn_KPALVTR sets ‘Keep Alive (KA)’ Packet transmission time. The unit is 5 sec. TCP Mode
SOCKET transmits KA Packet every Sn_KPALVTR. Before transmitting KA Packet, SOCKET must
transmit Data (over 1 Byte) Packet at least once. By Sn_CR [SENDKEEP], KA Packet is
transmitted without Sn_KPALVTR setting.
Ex) S0_KPALVTR = 10 (0x0A),
10 * 5s = 50s
S0_KPALVRT(0x0430)
0x0A
3.2.25 Sn_RTR (SOCKET n Retransmission Time Register)
[R=W] [0x0032+0x0100*(n+4), 0x0033+0x0100*(n+4)] [0x0000]
Sn_RTR sets SOCKET n Retransmission Time. If Sn_RTR is zero, SOCKET n Retransmission Time
is set by RTR. (Ref 4.8 Retransmission)
Ex) S0_RTR = 5000 (0x1388),
5000 * 100us = 0.5s
S0_RTR0(x0432)
S0_RTR1(0x0433)
0x013
0x88
3.2.26 Sn_RCR (SOCKET n Retransmission Count Register)
[R=W] [0x0034+0x0100*(n+4)] [0x00]
Sn_RCR sets SOCKET n Retransmission Counter. If Sn_RCR is zero, SOCKET n Retransmission
Counter is set by RCR. (Ref 4.8 Retransmission)
W5100S Datasheet Version1.0.0
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4
Functional Description
W5100S provides Internet Connectivity with simple register control. In this chapter, the
Initialization of W5100S, Data Communication method according to each TCP, UDP, IPRAW,
MACRAW Mode and the additional functions are described step by step based on the pseudo
code.
4.1
W5100S RESET
Set Hardware before Reset. (Ref 7.4.1 Reset Timing)
Set HOST Interface Mode with MOD [3:0] pin.
Supply the Reset signal longer than 500ns on RSTn pin for Hardware Reset.
Wait for TSTA (Ref 7.4.1 Reset Timing)
4.2
Initialization
The Network Information and SOCKET n TX / RX buffer are set in the W5100S Initialization
Process.
4.2.1 Basic Setting
To operate the W5100S properly, set the following Registers according to User’s Application.
Mode Register (MR)
Interrupt Mask Register (IMR)
Retransmission Time Register (RTR)
Retransmission Count Register (RCR)
More Information for the above registers can be found in each Register Descriptions.
4.2.2 Network Information Setting
Set the basic Network Information for Internet Communication.
NETWORK SETTING:
{
/* W5100S MAC Address, 11:22:33:AA:BB:CC */
SHAR[0:5] = { 0x11, 0x22, 0x33, 0xAA, 0xBB, 0xCC };
/* W5100S Gateway IP address, 192.168.0.1 */
GAR[0:3] = { 0xC0, 0xA8, 0x00, 0x01 };
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W5100S Datasheet Version1.0.0
/* W5100S Subnet MASK Address, 255.255.255.0 */
SUBR[0:3] = { 0xFF, 0xFF,, 0xFF, 0x00};
/* W5100S IP Address, 192.168.0.100 */
SIPR[0:3] = {0xC0, 0xA8,0x00, 0x64};
}
4.2.3 SOCKET TX/RX Buffer Setting
Determine SOCKET n TX/RX Buffer Size using TMSR/RMSR or Sn_TXBUF_SIZE/Sn_RXBUF_SIZE.
SOCKET n TX / RX Buffer is a RING-Buffer structure. So, calculation of the base address and
MASK value for SOCKET n TX / RX Buffer control must be required.
Please make sure that the Sum of SOCKET n TX / RX Buffer Size must not be exceed 8 KB.
The pseudo-code for setting the SOCKET n TX/RX Buffer is described below.
In case of, assign 2KB TX/RX memory per SOCKET
{
// set Base Address of TX/RX Memory for SOCKET n
gS0_RX_BASE = 0x8000;
// TX Memory Block Base Address
gS0_RX_BASE = 0xC000;
// RX Memory Block Base Address
TxTotalSize = 0;
// For check the total size of SOCKET n TX Buffer
RxTotalSize = 0;
// For check the total size of SOCKET n RX Buffer
for (n=0; n 8 or RxTotalSize > 8 )
goto ERROR;
// invalid Total Size
} // end for
}
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4.3
TCP
TCP (Transmission Control Protocol) is a bidirectional Data Transmission Protocol based on a
1:1 communication on Transport Layer. It also provides Communication between Applications
by using Port Number.
TCP 1:1 communication needs the Connection Process such as transmitting Connection
Request to Peer or receiving Connection Request from Peer.
In this Connection Process, the side transmitting Connection Request is ‘TCP CLIENT’ and the
other side receiving Connection Request is ‘TCP SERVER’.
TCP also provides reliable, ordered and error-checked delivery of a stream Data between
applications running on hosts communicating by an IP network.
‘TCP SERVER’ and ‘TCP CLIENT’ are maintaining transmit and receive Data until the TCP
connection is terminated.
SERVER
CLIENT
SERVER
OPEN
OPEN
LISTEN
CLIENT
Connect-Request
ESTABLISHED
CONNECT
Connect-Request
ESTABLISHED
Data Communications
Data Communications
Disconnect-Request
Disconnect-Request
Or
Or
Disconnect-Request
Disconnect-Request
CLOSED
CLOSED
“TCP SERVER”
“TCP CLIENT”
Figure 5 TCP SERVER and TCP CLIENT
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W5100S Datasheet Version1.0.0
4.3.1 TCP Server
Figure 6 show ‘TCP SERVER’ Operation Flow.
Figure 6 TCP Server Operation Flow
OPEN
HOST configures SOCKET n to TCP Mode.
{
START :
Sn_MR[3:0] = ‘0001’;
/* set TCP Mode */
Sn_PORTR[0:1] = {0x13,0x88}; /* set PORT Number, 5000(0x1388) */
/* configure SOCKET Option when you need it. */
// Sn_MR[ND] = ‘1’; /* set No Delay ACK */
Sn_CR[OPEN] = ‘1’;
/* set OPEN Command */
while(Sn_CR != 0x00); /* wait until OPEN Command is cleared*/
if(Sn_SR != SOCK_INIT) goto START; /* check SOCKET Status */
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}
LISTEN
SOCKET n is operated as ‘TCP SERVER’ by Sn_CR [LISTEN]. ‘TCP SERVER’ waits for SYN Packet
in Sn_SR (SOCK_LISTEN)
{
Sn_CR = LISTEN; /* set LISTEN Command */
while(Sn_CR != 0x00); /* wait until LISTEN Command is cleared*/
if(Sn_SR != SOCK_LISTEN) goto OPEN; /* check SOCKET Status */
}
ESTABLISHED?
‘TCP SERVER’ keeps Sn_SR (SOCK_LISTEN) until received SYN Packet. If ‘TCP SERVER’ receives
SYN Packet from ‘TCP CLIENT’, it transmits SYN/ACK Packet to ‘TCP CLIENT’ and the
Connection Process between ‘TCP SERVER’ and ‘TCP CLIENT’ is completed.
If there is no response from Peer against of transmitted SYN Packet or SYN/ACK Packet within
the Retransmission Time, Sn_IR [TIMEOUT] is set to ‘1’.
First method :
{
/* check SOCKET Interrupt */
if (Sn_IR[CON]
== ‘1’)
{
/* clear SOCKET Interrupt */
Sn_IR[CON] = ‘1’;
goto Received DATA?;
/* or goto Send DATA?; */
}
else if(Sn_IR[TIMEOUT] == ‘1’)
goto Timeout?;
}
Second method :
{
if (Sn_SR == SOCK_ESTABLISHED)
{
/* clear SOCKET Interrupt */
Sn_IR[CON] = ‘1’;
goto Received DATA?
/* or goto Send DATA?; */
}
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W5100S Datasheet Version1.0.0
else if(Sn_IR[TIMEOUT] == ‘1’) goto Timeout?;
}
Receive DATA?
Whether SOCKET n Data is received is confirmed by Sn_IR [RECV] or Sn_RX_RSR.
First method :
{
/* check SOCKET RX Memory Received Size */
if (Sn_RX_RSR > 0)
goto Receiving Process;
}
Second method :
{
if (Sn_IR[RECV] == ‘1’)
{
/* check SOCKET Interrupt */
Sn_IR[RECV] = ‘1’;
/* clear SOCKET Interrupt */
goto Receiving Process;
}
}
Receiving Process
Received Data is read from SOCKET n RX Buffer Block.
The Read Offset Address of Received Data in RX Memory Block is calculated by gSn_RX_BASE,
gSn_RX_MASK and Sn_RX_RD. (Ref 4.2.3 SOCKET TX/RX Buffer Setting)
After reading received Data, Sn_RX_RD must be increased by Data read Size and Sn_CR [RECV]
must be set to ‘1’. If there is remain Data in SOCKET n RX Buffer Block after Sn_CR [RECV]
Command, Sn_IR [RECV] is set to ‘1’.
When Read Offset Address calculated, it is cautious to over the boundary Address (n=0,1,2 :
gSn_RX_BASE ∼ gSn+1_RX_BASE, n=3 : gS3_RX_BASE ∼ 0xFFFF) of SOCKET n RX Buffer Block.
{
/* get Received Size */
get_size = Sn_RX_RSR;
/* calculate SOCKET n RX Buffer Size & Offset Address */
gSn_RX_MAX = Sn_RXBUF_SIZE * 1024;
get_offset = Sn_RX_RD & gSn_RX_MASK;
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/* calculate Read Offset Address */
get_start_address = gSn_RX_BASE + get_offset;
/* if overflow the upper boundary of SOCKET n RX Buffer */
If( (get_offset + get_size) > gSn_RX_MAX )
{
/* copy upper_size bytes of get_start_address to destination_address
- destination_address is user data memory address */
upper_size = gSn_RX_MAX – get_offset;
memcpy(get_start_address, destination_address, upper_size);
destination_address += upper_size;
/* copy the remained size bytes of gSn_RX_BASE to destination_address */
remained_size = get_size – upper_size;
memcpy(gSn_RX_BASE, destination_address, remained_size);
}
else
{
/* copy get_size of get_start_address to destination_address */
memcpy(get_start_address, destination_address, get_size);
}
/* increase Sn_RX_RD as get_size */
Sn_RX_RD += get_size;
/* set RECV Command */
Sn_CR[RECV] = ‘1’;
while(Sn_CR != 0x00); /* wait until RECV Command is cleared*/
}
Send DATA? / Sending Process
Written Data in SOCKET n TX Buffer Block is transmitted.
The Write Offset Address in TX Memory Block is calculated by gSn_TX_BASE, gSn_TX_MASK and
Sn_TX_WD. (Ref 4.2.3 SOCKET TX/RX Buffer Setting). And Data to be transmitted form the
Write Offset Address is written. After writing Data, Sn_TX_WD must be increased by written
Data Size and the Data is transmitted by Sn_CR [SEND].
Before Sn_IR [SENDOK] = ‘1’, next Data Transmission Process is not executed. How long time
until Sn_IR [SENDOK] = ‘1’ after transmitting Data is depending on SOCKET Count, Data Size
and Network Traffic. Also Sn_IR [TIMEOUT] could be occurred. (Ref 4.8.2 TCP Retransmission)
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W5100S Datasheet Version1.0.0
When Write Offset Address calculated, it is cautious to over the boundary Address (n=0,1,2 :
gSn_TX_BASE ∼ gSn+1_TX_BASE, n=3 : gS3_TX_BASE ∼ 0xC000) of SOCKET n TX Buffer Block.
If there is no response from Peer against of transmitted Data Packet within the
Retransmission Time, Sn_IR [TIMEOUT] is set to ‘1’.
{
/* calculate SOCKETn TX Buffer Size & Offset Address */
gSn_TX_MAX = Sn_TXBUF_SIZE * 1024;
get_offset = Sn_TX_WR & gSn_TX_MASK;
/* check the max size of DATA(send_size) & Free Size of SOCKETn TX
Buffer(Sn_TX_FSR)*/
if( send_size >gSn_TX_MAX ) send_size = gSn_TX_MAX;
while(send gSn_TX_MAX )
{
/* copy upper size bytes of source_address to get_start_address
- source_address is the start address of user data */
upper_size = gSn_TX_MAX – get_offset;
memcpy(source_address, get_start_address, upper_size);
/* copy the Remained Size Bytes of source_address to gSn_TX_BASE */
source_address += upper_size;
remained_size = send_size – upper_size;
memcpy(source_address, gSn_TX_BASE, remained_size);
}
else
{
/* copy send_size bytes of source_address to get_start_address
- source_address is the start address of user data */
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memcpy(source_address, get_start_address, send_size);
}
/* increase Sn_TX_WR as send_size */
Sn_TX_WR += send_size;
/* set SEND Command */
Sn_CR = SEND;
while(Sn_CR != 0x00); /* wait until SEND Command is cleared*/
/* wait until SEND Command is completed or TIMEOUT Interrupt is occurred*/
while(Sn_IR[SENDOK] == ‘0’ and Sn_IR[TIMEOUT] = ‘0’);
/* clear SOCKET Interrupt*/
if(Sn_IR[SENDOK] == ‘1’) Sn_IR[SENDOK] = ‘1’;
else goto Timeout?;
}
Received FIN (Passive Close)
When FIN Packet received from Peer.
First Method:
{
If(Sn_SR == SOCK_CLOSE_WAIT) goto Disconnecting Process;
}
Second Method:
{
If(Sn_IR[DISCON] == ‘1’) goto Disconnecting Process;
}
Disconnected (Active Close)
When FIN Packet transmitted to Peer.
{
/* send FIN Packet */
Sn_CR[DISCON] = ‘1’;
while(Sn_CR != 0x00); /* wait until DISCON Command is cleared*/
goto Disconnecting Process;
}
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W5100S Datasheet Version1.0.0
Disconnecting Process
In Passive Close, if FIN Packet is received from Peer and there is no Data to be transmitted,
SOCKET transmits FIN Packet and it will be closed. If there is no response from Peer against of
transmitted FIN Packet within the Retransmission Time, Sn_IR [TIMEOUT] is set to ‘1’.
In Active Close, if SOCKET transmits FIN Packet to Peer, SOCKET waits for Peer FIN Packet.
SOCKET will be closed after receiving FIN Packet from Peer. If there is no response from Peer
against of transmitted FIN Packet within the Retransmission Time, Sn_IR [TIMEOUT] is set to
‘1’.
Passive Close: /* received FIN Packet from Peer */
{
/* send FIN Packet */
Sn_CR = DISCON;
while(Sn_CR != 0x00); /* wait until DISCON Command is cleared*/
/* wait unit ACK Packet is received*/
while(Sn_IR[DISCON] == ‘0’ and Sn_IR[TIMEOUT] == ‘0’) ;
if (Sn_IR[DISCON] == ‘1’)
{
/* clear Interrupt */
Sn_IR[DISCON] = ‘1’;
goto CLOSED;
}
else
goto Timeout?;
}
Active Close : /* sent FIN Packet to Peer */
{
/* wait until FIN Packet is received*/
while(Sn_IR[DISCON] == ‘0’ and Sn_IR[TIMEOUT] == ‘0’) ;
if (Sn_IR[DISOCN] == ‘1’)
{
/* clear Interrupt */
Sn_IR[DISCON] = ‘1’;
goto CLOSED;
}
else
goto Timeout?;
}
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Timeout?
If there is no response from Peer against of transmitted SYN or SYN/ACK or FIN or Data Packet
within the Retransmission Time, Sn_IR [TIMEOUT] is set to ‘1’. (Ref 4.8.2 TCP Retransmission)
{
/* check TIMEOUT Interrupt */
if(Sn_IR[TIMEOUT] == ‘1’)
{
/* clear Interrupt */
Sn_IR[TIMEOUT] = ‘1’;
goto CLOSE;
}
}
CLOSE
SOCKET n is closed by the Disconnect Process, Sn_IR [TIMEOUT] = ‘1’ and Sn_CR [CLOSE] = ‘1’.
{
/*wait until SOCKET n is closed*/
while(Sn_SR != SOCK_CLOSED);
}
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4.3.2 TCP Client
Figure 7 shows ‘TCP CLIENT’ Operation Flow.
Figure 7 TCP Client Operation Flow
OPEN
Refer to 4.3.1 TCP Server : OPEN
CONNECT
SOCKET n is operated as ‘TCP CLIENT’ by Sn_CR [CONNECT].
SYN Packet is transmitted to ‘TCP SERVER’ by Sn_CR [CONNECT].
{
/* set Destination IP Address, 192.168.0.11 */
Sn_DIPR[0:3] ={ 0xC0, 0xA8, 0x00, 0x0B};
/* set Destination PORT Number, 5000(0x1388) */
Sn_DPORTR[0:1] = {0x13, 0x88};
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/* set CONNECT Command */
Sn_CR = CONNECT;
while(Sn_CR != 0x00); /* wait until CONNECT Command is cleared*/
goto ESTABLISHED?;
}
ESTABLISHED?
‘TCP CLIENT’ is in Sn_SR (SOCK_SYNSENT) until receiving SYN/ACK Packet from ‘TCP SERVER’
against of SYN Packet transmitted. If SYN/ACK Packet is received from ‘TCP SERVER’, the
Connection Process between ‘TCP SERVER’ and ‘TCP CLIENT’ is completed.
If there is no response from Peer against of transmitted SYN Packet within the Retransmission
Time, Sn_IR [TIMEOUT] is set to ‘1’.
(Ref 4.3.1 TCP Server : Received DATA?)
Others flow
Refer to 4.3.1 TCP Server.
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W5100S Datasheet Version1.0.0
4.3.3 Other Functions
4.3.3.1
TCP SOCKET Options
Before Sn_CR [OPEN] is set to ‘1’, SOCKET Option can be set by Sn_MR and Sn_MR2.
No Delayed ACK : Sn_MR [NDACK] = ‘1’
If No Delayed ACK option is set, SOCKET sends ACK Packet against of Peer Data Packet
without Delay.
Delayed ACK : Sn_MR [NDACK] = ‘0’
If No Delayed ACK option is not set, SOCKET sends ACK Packet against of Peer Data Packet
after RTR or TCP Window Size increased.
Force PSH : Sn_MR2 [BRDB ]=’1’
If Force PSH option is set, SOCKET puts PSH flag in every Data Packet to be transmitted.
Auto PSH : Sn_MR2 [BRDB ]=’0’
If Force PSH option is not set, SOCKET puts PSH flag in the last Data Packet to be transmitted.
4.3.3.2
Keep Alive
Keep Alive (KA) is a message sent by Peer to check that the link is operating, or to prevent
the link from being broken. Keep Alive sends the last 1 Byte from the last transmitted Data.
So, Data bigger than 1 Byte must be transmitted before Keep Alive.
If there is no response from Peer against of KA Packet within the Retransmission Time, Sn_IR
[TIMEOUT] is set to ‘1’.
The period of KA Packet transmit is set by Sn_KPALVTR. If Sn_KPALVTR is zero, KA Packet is
able to be transmitted by Sn_CR [SEND_KEEP].
W5100S Datasheet Version1.0.0
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4.4
UDP
UDP (User Datagram Protocol) is a Datagram Communication Protocol and doesn’t guarantee
the stability in Transport Layer above the IP Layer. It also provides Communication between
Applications using Port Numbers. UDP can communicate with more than one Peer and doesn’t
require the Connection Process. On the other hand, UDP has Data Loss and receives Data from
any Peers because UDP has no guarantee reliability. UDP Transmission Methods are Unicast,
Broadcast and Multicast according to Data transmit/receive range.
Figure 8 shows UDP Operation Flow.
Figure 8 UDP Operation Flow
4.4.1 UDP Unicast
UDP Unicast is the first Communication Method in which sender is one and receiver is one.
Before Data Transmit, SOCKET performs the ARP Process. In the ARP Process, if there is no
response from Peer against of ARP Request within the Retransmission Time, Sn_IR [TIMEOUT]
is set to ‘1’. (Ref 4.8.1 ARP & PING Retransmission)
If previous Destination and current Destination are the same, the ARP Process is skipped.
Also, the ARP Process is skipped by Sn_CR [SEND_MAD] and Sn_DHAR.
OPEN
SOCKET n is configured as UDP Mode by OPEN Command.
{
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W5100S Datasheet Version1.0.0
START :
/* set UDP Mode */
Sn_MR[3:0] = ‘0010’;
/* set Source PORT Number, 5000(0x1388) */
Sn_PORTR[0:1] = {0x13, 0x88};
/* set SOCKET Option such as Broadcast Block. */
// refer to 3.2.23 Sn_MR2 (SOCKET n Mode register 2)
// Sn_MR2[BRDB] = ‘1’;
/* set OPEN Command */
Sn_CR = OPEN;
while(Sn_CR != 0x00); /* wait until OPEN Command is cleared*/
/* check SOCKET for UDP Mode */
if(Sn_SR != SOCK_UDP) goto START;
}
Received DATA?
Refer to 4.3.1 TCP Server : Received DATA?
Receiving Process
UDP Mode SOCKET can receive Data Packets from more than one Peer. The received Data
Packet is stored in SOCKET n RX Buffer Block with “PACKET INFO” as shown in Figure 9. If the
received Data is bigger than SOCKET n RX Buffer Free Size, it is discarded.
(Ref 4.3.1 TCP Server : Receiving Process)
Figure 9 Received UDP DATA in SOCKETn RX Buffer Block
{
/* receive PACKINFO */
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goto
4.3.1 TCP Server : Receiving Process with get_size = 8;
/* extract Destination IP, Port, Size in PACKET INFO*/
dest_ip[0:3] = destination_address[0:3];
dest_port = (destination_address[4]
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