ESP32-S2-SAOLA-1MI

ESP32-S2 Family Datasheet Including: ESP32-S2 ESP32-S2FH2 ESP32-S2FH4 ESP32-S2FN4R2 ESP32-S2R2 Version 1.3 Espressif Systems Copyright © 2021 www.espressif.com About This Document This document provides the specifications of ESP32-S2 family. Document Updates Please always refer to the latest version on https://www.espressif.com/en/support/download/documents. Revision History For any changes to this document over time, please refer to the last page. Documentation Change Notification Espressif provides email notifications to keep customers updated on changes to technical documentation. Please subscribe at www.espressif.com/en/subscribe. Note that you need to update your subscription to receive notifications of new products you are not currently subscribed to. Certification Download certificates for Espressif products from www.espressif.com/en/certificates. Espressif Systems 2 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Product Overview ESP32-S2 family is a highly-integrated, low-power, 2.4 ESP32-S2 family is designed for ultra-low-power GHz Wi-Fi System-on-Chip (SoC) solution. With its applications with its multiple low-power modes. Its state-of-the-art power and RF performance, this SoC featured fine-grained clock gating, dynamic voltage is an ideal choice for a wide variety of application and frequency scaling, and adjustable power amplifier scenarios relating to Internet of Things (IoT), wearable output power, contribute to an optimal trade-off electronics and smart home. between communication range, data rate and power ESP32-S2 family includes a Wi-Fi subsystem that consumption. integrates a Wi-Fi MAC, Wi-Fi radio and baseband, RF The device provides a rich set of peripheral interfaces switch, RF balun, power amplifier, low noise amplifier including SPI, I2S, UART, I2C, LED_PWM, LCD (LNA), etc. The chip is fully compliant with the IEEE interface, camera interface, ADC, DAC, touch sensor, 802.11b/g/n protocol and offers a complete Wi-Fi temperature sensor, as well as 43 GPIOs. It also solution. includes a full-speed USB On-The-Go (OTG) interface At the core of this chip is an Xtensa® 32-bit LX7 CPU to enable USB communication. that operates at up to 240 MHz. The chip supports ESP32-S2 family has several dedicated hardware application development, without the need for a host security features. Cryptographic accelerators are MCU. integrated for AES, SHA and RSA algorithms. The on-chip memory includes 320 KB SRAM and 128 Additional hardware security features are provided by KB ROM. It also supports multiple external the RNG, HMAC and Digital Signature modules as well SPI/QSPI/OSPI flash and external RAM chips for more as flash encryption and secure boot signature verification features. These features allow the device to memory space. meet stringent security requirements. Block Diagram Espressif’s ESP32-S2 Wi-Fi SoC ROM Xtensa® 32-bit LX7 Microprocessor Wi-Fi Wi-Fi MAC Cache SRAM RF RF receiver Clock generator Wi-Fi baseband Balun JTAG Switch Main CPU RF transmitter Peripherals and Sensors Embedded flash / PSRAM General purpose Timers SPI / LCD interface I2S / Camera interface / LCD interface GPIO I2C LED_PWM UART Pulse counter RMT USB OTG DAC TWAI ADC Touch sensor Temperature sensor RTC ULP co-processor PMU RTC memory Cryptographic Hardware Acceleration SHA RSA AES RNG HMAC Digital signature Figure 1: Block Diagram of ESP32-S2 Espressif Systems 3 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Features Wi-Fi • IEEE 802.11 b/g/n-compliant • Automatic Beacon monitoring (hardware TSF) • Supports 20 MHz, 40 MHz bandwidth in 2.4 • 4 × virtual Wi-Fi interfaces GHz band • Simultaneous support for Infrastructure Station, • Single-band 1T1R mode with data rate up to SoftAP, and Promiscuous modes 150 Mbps Note that when ESP32-S2 family is in Station mode and performs a scan, the SoftAP channel • WMM will change along with the Station channel. • TX/RX A-MPDU, RX A-MSDU • Antenna diversity • Immediate Block ACK • 802.11mc FTM • Fragmentation and defragmentation CPU and Memory • Xtensa® single-core 32-bit LX7 microprocessor, • 16 KB SRAM in RTC up to 240 MHz • Embedded flash and PSRAM (see details in • 128 KB ROM Chapter 1: Family Member Comparison) • 320 KB SRAM • SPI/QSPI/OSPI supports multiple flash and external RAM chips Advanced Peripheral Interfaces • 43 × programmable GPIOs • 1 × full-speed USB OTG • 2 × 13-bit SAR ADCs, up to 20 channels • 1 × temperature sensor • 2 × 8-bit DAC • 1 × DVP 8/16 camera interface, implemented using the hardware resources of I2S • 14 × touch sensing IOs • 1 × LCD interface (8-bit serial RGB/8080/6800), • 4 × SPI implemented using the hardware resources of • 1 × I2S SPI2 • 2 × I2C • 1 × LCD interface (8/16/24-bit parallel), • 2 × UART implemented using the hardware resources of • RMT (TX/RX) I2S • 1 × TWAI® controller compatible with ISO • LED PWM controller, up to 8 channels 11898-1 (CAN Specification 2.0) Security • Secure boot • Cryptographic hardware acceleration: • Flash encryption – AES-128/192/256 (FIPS PUB 197) • 4096-bit OTP, up to 1792 bits for users – Hash (FIPS PUB 180-4) Espressif Systems 4 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 – RSA – HMAC – Random Number Generator (RNG) – Digital signature Applications (A Non-exhaustive List) • Generic Low-power IoT Sensor Hubs • Audio Applications • Generic Low-power IoT Data Loggers – Internet music players • Cameras for Video Streaming – Live streaming devices • Over-the-top (OTT) Devices – Internet radio players • USB Devices – Audio headsets • Speech Recognition • Health Care Applications • Image Recognition – Health monitoring • Mesh Networks – Baby monitors • Home Automation • Wi-Fi-enabled Toys – Light control – Remote control toys – Smart plugs – Proximity sensing toys – Smart door locks – Educational toys • Smart Buildings • Wearable Electronics – Smart lighting – Smart watches – Energy monitoring – Smart bracelets • Industrial Automation • Retail & Catering Applications – Industrial wireless control – POS machines – Industrial robotics – Service robots • Smart Agriculture • Touch Sensing Applications – Smart greenhouses – Waterproof design – Smart irrigation – Distance sensing applications – Agriculture robotics – Linear slider, wheel slider designs Espressif Systems 5 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Contents Product Overview 3 Block Diagram 3 Features 4 Applications 5 1 Family Member Comparison 10 1.1 Family Nomenclature 10 1.2 Comparison 10 2 Pin Definitions 11 2.1 Pin Layout 11 2.2 Pin Description 12 2.3 Power Scheme 15 2.4 Strapping Pins 16 3 Functional Description 18 3.1 18 3.2 3.3 3.4 CPU and Memory 3.1.1 CPU 18 3.1.2 Internal Memory 18 3.1.3 External Flash and RAM 18 3.1.4 Address Mapping Structure 19 3.1.5 Cache 19 System Clocks 20 3.2.1 CPU Clock 20 3.2.2 RTC Clock 20 3.2.3 Audio PLL Clock 20 Analog Peripherals 20 3.3.1 Analog-to-Digital Converter (ADC) 20 3.3.2 Digital-to-Analog Converter (DAC) 21 3.3.3 Temperature Sensor 21 3.3.4 Touch Sensor 21 Digital Peripherals 22 3.4.1 General Purpose Input / Output Interface (GPIO) 22 3.4.2 Serial Peripheral Interface (SPI) 22 3.4.3 LCD Interface 23 3.4.4 Universal Asynchronous Receiver Transmitter (UART) 23 3.4.5 I2C Interface 24 3.4.6 I2S Interface 24 3.4.7 Camera Interface 24 3.4.8 Infrared Remote Controller 24 3.4.9 Pulse Counter 24 3.4.10 LED PWM Controller 24 3.4.11 USB 1.1 OTG 25 Espressif Systems 6 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3.4.12 TWAI® Controller 3.5 3.6 3.7 25 Radio and Wi-Fi 25 3.5.1 2.4 GHz Receiver 25 3.5.2 2.4 GHz Transmitter 26 3.5.3 Clock Generator 26 3.5.4 Wi-Fi Radio and Baseband 26 3.5.5 Wi-Fi MAC 26 3.5.6 Networking Features 27 RTC and Low-Power Management 27 3.6.1 Power Management Unit (PMU) 27 3.6.2 Ultra-Low-Power Co-processor 27 Timers and Watchdogs 28 3.7.1 64-bit Timers 28 3.7.2 Watchdog Timers 28 3.8 Cryptographic Hardware Accelerators 29 3.9 Physical Security Features 29 3.10 Peripheral Pin Configurations 30 4 Electrical Characteristics 34 4.1 Absolute Maximum Ratings 34 4.2 Recommended Operating Conditions 34 4.3 VDD_SPI Output Characteristics 34 4.4 DC Characteristics (3.3 V, 25 °C) 35 4.5 ADC Characteristics 35 4.6 Current Consumption Characteristics 36 4.7 Reliability Qualifications 37 4.8 Wi-Fi Radio 38 4.8.1 Transmitter Characteristics 38 4.8.2 Receiver Characteristics 38 5 Package Information 40 6 Learning Resources 41 6.1 Must-Read Documents 41 6.2 Must-Have Resources 41 Appendix A – ESP32-S2 Pin Lists 42 A.1. IO MUX 42 A.2. GPIO Matrix 43 Revision History 48 Espressif Systems 7 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 List of Tables 1 ESP32-S2 Family Member Comparison 10 2 Pin Description 12 3 Description of ESP32-S2 Family Power-up and Reset Timing Parameters 16 4 Strapping Pins 16 5 Capacitive-Sensing GPIOs Available on ESP32-S2 Family 21 6 Peripheral Pin Configurations 30 7 Absolute Maximum Ratings 34 8 Recommended Operating Conditions 34 9 VDD_SPI Output Characteristics 34 10 DC Characteristics (3.3 V, 25 °C) 35 11 ADC Characteristics 35 12 Current Consumption Depending on RF Modes 36 13 Current Consumption Depending on Work Modes 36 14 Reliability Qualifications 37 15 Transmitter Characteristics 38 16 Receiver Characteristics 38 17 GPIO_Matrix 43 Espressif Systems 8 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 List of Figures 1 Block Diagram of ESP32-S2 2 ESP32-S2 Family Nomenclature 10 3 ESP32-S2 Pin Layout (Top View) 11 4 ESP32-S2 Family Power Scheme 15 5 ESP32-S2 Family Power-up and Reset Timing 16 6 Address Mapping Structure 19 7 QFN56 (7×7 mm) Package 40 Espressif Systems 3 9 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 1. Family Member Comparison 1. Family Member Comparison 1.1 Family Nomenclature ESP32-S2 F H x R x PSRAM size (MB) Embedded PSRAM Flash size (MB) Flash temperature H: High temperature N: Normal temperature Embedded flash Chip family Figure 2: ESP32-S2 Family Nomenclature 1.2 Comparison Table 1: ESP32-S2 Family Member Comparison Embedded Flash Embedded PSRAM — — –40 ∼ 105 ESP32-S2FH2 2 MB — –40 ∼ 105 ESP32-S2FH4 4 MB — –40 ∼ 105 ESP32-S2FN4R2 4 MB 2 MB –40 ∼ 85 — 2 MB –40 ∼ 85 Ordering Code ESP32-S2 ESP32-S2R2 Ambient Temperature (°C) Note: For junction temperature, please refer to Table 8. Espressif Systems 10 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 2. Pin Definitions 2. Pin Definitions 43 MTCK 44 MTD0 45 VDD3P3_CPU 46 MTDI 47 MTMS 48 U0TXD 49 U0RXD 50 GPIO45 51 VDDA 52 XTAL_N 53 XTAL_P 54 VDDA 55 GPIO46 56 CHIP_PU 2.1 Pin Layout VDDA 1 42 GPIO38 LNA_IN 2 41 GPIO37 VDD3P3 3 40 GPIO36 VDD3P3 4 39 GPIO35 GPIO0 5 38 GPIO34 GPIO1 6 37 GPIO33 GPIO2 7 36 SPID GPIO3 8 35 SPIQ GPIO4 9 ESP32-S2 Family 34 SPICLK GPIO5 10 33 SPICS0 GPIO6 11 32 SPIWP GPIO7 12 31 SPIHD GPIO8 13 30 VDD_SPI 57 GND GPIO21 28 VDD3P3_RTC_IO 27 GPIO20 26 GPIO19 25 DAC_2 24 DAC_1 23 XTAL_32K_N 22 XTAL_32K_P 21 VDD3P3_RTC 20 GPIO14 19 GPIO13 18 GPIO12 17 GPIO11 16 29 SPICS1 GPIO10 15 GPIO9 14 Figure 3: ESP32-S2 Pin Layout (Top View) Espressif Systems 11 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 2. Pin Definitions Espressif Systems 2.2 Pin Description Table 2: Pin Description 12 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Name No. Type Power domain VDDA 1 PA — Analog power supply LNA_IN 2 I/O — RF input and output VDD3P3 3 PA — Analog power supply VDD3P3 4 PA — Analog power supply GPIO0 5 I/O/T VDD3P3_RTC_IO RTC_GPIO0, GPIO0 GPIO1 6 I/O/T VDD3P3_RTC_IO RTC_GPIO1, GPIO1, TOUCH1, ADC1_CH0 GPIO2 7 I/O/T VDD3P3_RTC_IO RTC_GPIO2, GPIO2, TOUCH2, ADC1_CH1 GPIO3 8 I/O/T VDD3P3_RTC_IO RTC_GPIO3, GPIO3, TOUCH3, ADC1_CH2 GPIO4 9 I/O/T VDD3P3_RTC_IO RTC_GPIO4, GPIO4, TOUCH4, ADC1_CH3 GPIO5 10 I/O/T VDD3P3_RTC_IO RTC_GPIO5, GPIO5, TOUCH5, ADC1_CH4 GPIO6 11 I/O/T VDD3P3_RTC_IO RTC_GPIO6, GPIO6, TOUCH6, ADC1_CH5 GPIO7 12 I/O/T VDD3P3_RTC_IO RTC_GPIO7, GPIO7, TOUCH7, ADC1_CH6 GPIO8 13 I/O/T VDD3P3_RTC_IO RTC_GPIO8, GPIO8, TOUCH8, ADC1_CH7 GPIO9 14 I/O/T VDD3P3_RTC_IO RTC_GPIO9, GPIO9, TOUCH9, ADC1_CH8, FSPIHD GPIO10 15 I/O/T VDD3P3_RTC_IO RTC_GPIO10, GPIO10, TOUCH10, ADC1_CH9, FSPICS0, FSPIIO4 GPIO11 16 I/O/T VDD3P3_RTC_IO RTC_GPIO11, GPIO11, TOUCH11, ADC2_CH0, FSPID, FSPIIO5 GPIO12 17 I/O/T VDD3P3_RTC_IO RTC_GPIO12, GPIO12, TOUCH12, ADC2_CH1, FSPICLK, FSPIIO6 GPIO13 18 I/O/T VDD3P3_RTC_IO RTC_GPIO13, GPIO13, TOUCH13, ADC2_CH2, FSPIQ, FSPIIO7 GPIO14 19 I/O/T VDD3P3_RTC_IO RTC_GPIO14, GPIO14, TOUCH14, ADC2_CH3, FSPIWP, FSPIDQS VDD3P3_RTC 20 PA — XTAL_32K_P 21 I/O/T VDD3P3_RTC_IO RTC_GPIO15, GPIO15, U0RTS, ADC2_CH4, XTAL_32K_P XTAL_32K_N 22 I/O/T VDD3P3_RTC_IO RTC_GPIO16, GPIO16, U0CTS, ADC2_CH5, XTAL_32K_N DAC_1 23 I/O/T VDD3P3_RTC_IO RTC_GPIO17, GPIO17, U1TXD, ADC2_CH6, DAC_1 DAC_2 24 I/O/T VDD3P3_RTC_IO RTC_GPIO18, GPIO18, U1RXD, ADC2_CH7, DAC_2, Function Analog power supply CLK_OUT3 13 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 No. Type Power domain GPIO19 25 I/O/T VDD3P3_RTC_IO RTC_GPIO19, GPIO19, U1RTS, ADC2_CH8, CLK_OUT2, USB_D- GPIO20 26 I/O/T VDD3P3_RTC_IO RTC_GPIO20, GPIO20, U1CTS, ADC2_CH9, CLK_OUT1, USB_D+ VDD3P3_RTC_IO 27 PD VDD3P3_RTC_IO Input power supply for RTC IO GPIO21 28 I/O/T VDD3P3_RTC_IO RTC_GPIO21, GPIO21 SPICS1 29 I/O/T VDD_SPI SPICS1, GPIO26 VDD_SPI 30 PD — SPIHD 31 I/O/T VDD_SPI SPIHD, GPIO27 SPIWP 32 I/O/T VDD_SPI SPIWP, GPIO28 SPICS0 33 I/O/T VDD_SPI SPICS0, GPIO29 SPICLK 34 I/O/T VDD_SPI SPICLK, GPIO30 SPIQ 35 I/O/T VDD_SPI SPIQ, GPIO31 SPID 36 I/O/T VDD_SPI SPID, GPIO32 GPIO33 37 I/O/T VDD3P3_CPU / VDD_SPI SPIIO4, GPIO33, FSPIHD GPIO34 38 I/O/T VDD3P3_CPU / VDD_SPI SPIIO5, GPIO34, FSPICS0 GPIO35 39 I/O/T VDD3P3_CPU / VDD_SPI SPIIO6, GPIO35, FSPID GPIO36 40 I/O/T VDD3P3_CPU / VDD_SPI SPIIO7, GPIO36, FSPICLK GPIO37 41 I/O/T VDD3P3_CPU / VDD_SPI SPIDQS, GPIO37, FSPIQ GPIO38 42 I/O/T VDD3P3_CPU GPIO38, FSPIWP MTCK 43 I/O/T VDD3P3_CPU MTCK, GPIO39, CLK_OUT3 MTDO 44 I/O/T VDD3P3_CPU MTDO, GPIO40, CLK_OUT2 VDD3P3_CPU 45 PD — MTDI 46 I/O/T VDD3P3_CPU MTDI, GPIO41, MTMS 47 I/O/T VDD3P3_CPU MTMS, GPIO42 U0TXD 48 I/O/T VDD3P3_CPU U0TXD, GPIO43, CLK_OUT1 U0RXD 49 I/O/T VDD3P3_CPU U0RXD, GPIO44, CLK_OUT2 GPIO45 50 I/O/T VDD3P3_CPU GPIO45 VDDA 51 PA — Analog power supply XTAL_N 52 — — External crystal output Function Output power supply: 1.8 V or the same voltage as VDD3P3_RTC_IO Input power supply for CPU IO CLK_OUT1 2. Pin Definitions Espressif Systems Name No. Type Power domain XTAL_P 53 — — External crystal input VDDA 54 PA — Analog power supply GPIO46 55 I VDD3P3_CPU CHIP_PU 56 I VDD3P3_RTC_IO Function GPIO46 High: on, enables the chip. Low: off, the chip powers off. Note: Do not leave the CHIP_PU pin floating. GND 57 G — Ground Note: • P: power pin; I: input; O: output; T: high impedance. – CS# = SPICS0 – DI = SPID – DO = SPIQ 14 Submit Documentation Feedback • Ports of embedded flash correspond to pins of ESP32-S2FH2 and ESP32-S2FH4 as follows: – CLK = SPICLK – WP# = SPIWP – HOLD# = SPIHD Ports of embedded PSRAM correspond to pins of ESP32-S2FN4R2 and ESP32-S2R2 as follows: – CE# = SPICS1 – SI/SIO0 = SPID ESP32-S2 Family Datasheet V1.3 – SO/SIO1 = SPIQ – SCLK = SPICLK – SIO2 = SPIWP – SIO3 = SPIHD These pins are not recommended for other uses. • For the data port connection between ESP32-S2 family and external flash, please refer to Section 3.4.2. • Power supply for GPIO33, GPIO34, GPIO35, GPIO36 and GPIO37 is configurable to be either VDD3P3_CPU (default) or VDD_SPI. • The pin function in this table refers only to some fixed settings and do not cover all cases for signals that can be input and output through the GPIO matrix. For more information on the GPIO matrix, please refer to Table 17. 2. Pin Definitions Espressif Systems Name 2. Pin Definitions 2.3 Power Scheme Digital pins of ESP32-S2 family are divided into four different power domains: • VDD3P3_RTC_IO • VDD3P3_CPU • VDD_SPI • VDD3P3_RTC VDD3P3_RTC_IO is the input power supply for RTC and CPU. VDD3P3_CPU is the input power supply for CPU. VDD_SPI can be an input power supply or an output power supply. VDD_SPI connects to the output of an internal LDO whose input is VDD3P3_RTC_IO. When VDD_SPI is connected to the same PCB net together with VDD3P3_RTC_IO, the internal LDO should be disabled. VDD3P3_RTC is the input power supply for RTC analog. The power scheme diagram is shown in Figure 4. VDD3P3_RTC_IO LDO RSPI LDO 1.8 V 1.1 V VDD3P3_CPU VDD3P3_RTC LDO 1.1 V VDD_SPI 3.3 V or 1.8 V VDD_SPI RTC CPU Domain Domain Domain RTC IO RTC analog Domain Figure 4: ESP32-S2 Family Power Scheme The VDD_SPI voltage can be configured at 1.8 V using an internal LDO, or powered by VDD3P3_RTC_IO via RSP I (nominal 3.3 V). Since ESP32-S2FH2, ESP32-S2FH4, ESP32-S2FN4R2, and ESP32-S2R2 are embedded with both/either 3.3 V SPI flash and/or PSRAM, the VDD_SPI must be powered by VDD3P3_RTC_IO via RSP I . The VDD_SPI can be powered off via software to minimize the current leakage of flash in the Deep-sleep mode. Notes on CHIP_PU: The illustration below shows the power-up and reset timing of ESP32-S2 family. Details about the parameters are listed in Table 3. Espressif Systems 15 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 2. Pin Definitions t0 t1 2.8 V VDDA, VDD3P3, VDD3P3_RTC, VDD3P3_RTC_IO, VDD3P3_CPU VIL_nRST CHIP_PU Figure 5: ESP32-S2 Family Power-up and Reset Timing Table 3: Description of ESP32-S2 Family Power-up and Reset Timing Parameters Parameters Description Time between bringing up the VDDA, VDD3P3, VDD3P3_RTC, t0 VDD3P3_RTC_IO and VDD3P3_CPU rails, and activating CHIP_PU. Duration of CHIP_PU signal level < VIL_nRST (refer to its value in Table 10 DC t1 Characteristics) to reset the chip. Min Unit 50 µs 50 µs 2.4 Strapping Pins ESP32-S2 family has three strapping pins: • GPIO0 • GPIO45 • GPIO46 Software can read the values of corresponding bits from register ”GPIO_STRAPPING”. During the chip’s system reset (power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog reset, and crystal clock glitch detection reset), the latches of the strapping pins sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut down. GPIO0, GPIO45 and GPIO46 are connected to the chip’s internal pull-up/pull-down during the chip reset. Consequently, if they are unconnected or the connected external circuit is high-impedance, the internal weak pull-up/pull-down will determine the default input level of these strapping pins. To change the strapping bit values, users can apply the external pull-down/pull-up resistances, or use the host MCU’s GPIOs to control the voltage level of these pins when powering on ESP32-S2 family. After reset, the strapping pins work as normal-function pins. Refer to Table 4 for a detailed boot-mode configuration of the strapping pins. Table 4: Strapping Pins VDD_SPI Voltage 1 2 Pin Default 3.3 V 1.8 V GPIO45 Pull-down 0 1 Booting Mode 3 Espressif Systems 16 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 2. Pin Definitions Pin Default SPI Boot Download Boot GPIO0 Pull-up 1 0 GPIO46 Pull-down Don’t-care 0 Enabling/Disabling ROM Code Print During Booting 4 5 Pin Default Enabled Disabled GPIO46 Pull-down See note 5 See note 5 Note: 1. The functionality of strapping pin GPIO45 to select VDD_SPI voltage may be disabled by setting VDD_SPI_FORCE eFuse to 1. In such a case the voltage is selected with eFuse bit VDD_SPI_TIEH. 2. Since ESP32-S2FH2, ESP32-S2FH4, ESP32-S2FN4R2, and ESP32-S2R2 are embedded with both/either 3.3 V SPI flash and/or PSRAM, VDD_SPI must be configured to 3.3 V. 3. The strapping combination of GPIO46 = 1 and GPIO0 = 0 is invalid and will trigger unexpected behavior. 4. ROM code can be printed over U0TXD (by default) or DAC_1, depending on the eFuse bit. 5. When eFuse UART_PRINT_CONTROL value is: 0, print is normal during boot and not controlled by GPIO46. 1 and GPIO46 is 0, print is normal during boot; but if GPIO46 is 1, print is disabled. 2 and GPIO46 is 0, print is disabled; but if GPIO46 is 1, print is normal. 3, print is disabled and not controlled by GPIO46. Espressif Systems 17 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description 3. Functional Description This chapter describes the functions of ESP32-S2 family. 3.1 CPU and Memory 3.1.1 CPU ESP32-S2 family contains one low-power Xtensa® 32-bit LX7 microprocessor with the following features: • 7-stage pipeline that supports the clock frequency of up to 240 MHz • 16/24-bit Instruction Set providing high code-density • support for 32-bit multiplier and 32-bit divider • unbuffered GPIO instructions • support for 32 interrupts at six levels • support for windowed ABI with 64 physical general registers • support for trace function with TRAX compressor, up to 16 KB trace memory • JTAG for debugging 3.1.2 Internal Memory ESP32-S2 family’s internal memory includes: • 128 KB of ROM: for booting and core functions • 320 KB of on-chip SRAM: for data and instructions • RTC FAST Memory: 8 KB of SRAM in RTC. It can be accessed by the main CPU. It can retain data in Deep-sleep mode. • RTC SLOW Memory: 8 KB of SRAM in RTC. It can be accessed by the main CPU or the co-processor. It can retain data in Deep-sleep mode. • 4 Kbit of eFuse: 1792 bits are reserved for user data, such as encryption key and device ID. • Embedded flash and PSRAM: see details in Chapter 1: Family Member Comparison 3.1.3 External Flash and RAM ESP32-S2 family supports multiple external QSPI/OSPI flash and RAM chips. It also supports hardware encryption/decryption based on XTS-AES to protect developers’ programs and data in flash and RAM. The external flash and RAM can be mapped into the CPU instruction memory space and read-only data memory space. The RAM can also be mapped into the CPU data memory space. Up to 1 GB of external flash and RAM can be supported. Through high-speed caches, ESP32-S2 family can support the following mappings at the same time. • Up to 7.5 MB of instruction memory space can be mapped at a time into flash and RAM. If more than 3.5 MB are mapped, cache performance may be slightly reduced due to the CPU’s pipeline characteristics. • Up to 4 MB of read-only data memory space can be mapped into flash or RAM as individual 64 KB blocks. 8-bit, 16-bit and 32-bit reads are supported. Espressif Systems 18 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description • Up to 10.5 MB of read-write data memory space can be mapped into RAM as individual 64 KB blocks. 8-bit, 16-bit and 32-bit reads and writes are supported. Blocks from this 10.5 MB space can also be mapped into flash, for read operations only. Note: After ESP32-S2 family is initialized, firmware can customize the mapping of external RAM or flash into the CPU address space. 3.1.4 Address Mapping Structure 0x0000_0000 0x3EFF_FFFF 0x3F00_0000 0x3F3F_FFFF 0x3F40_0000 0x3F4F_FFFF 0x3F50_0000 0x3FF7_FFFF 0x3FF8_0000 0x3FF9_DFFF 0x3FF9_E000 0x3FFF_FFFF Cache 0x4000_0000 0x4007_1FFF 0x4007_2000 0x4007_FFFF 0x4008_0000 0x407F_FFFF External memory Embedded memory DMA 0x4080_0000 0x4FFF_FFFF MMU 0x5000_0000 0x5000_1FFF 0x5000_2000 0x5FFF_FFFF 0x6000_0000 0x600B_FFFF DMA Peripheral 0x600C_0000 0x617F_FFFF 0x6180_0000 0x6180_3FFF 0x6180_4000 0xFFFF_FFFF Figure 6: Address Mapping Structure Note: The memory space with gray background is not available for use. 3.1.5 Cache ESP32-S2 family has independent instruction Cache and data Cache that have the following features: • configurable size of 8 KB or 16 KB • 4-way set associative • block size of 16 bytes or 32 bytes • pre-load function Espressif Systems 19 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description • lock function • support for critical word first and early restart 3.2 System Clocks 3.2.1 CPU Clock The CPU clock has four possible sources: • external 40 MHz crystal clock • internal 8 MHz oscillator • PLL clock • audio PLL clock The application can select the clock source from the external crystal clock source, the PLL clock, the audio PLL clock, or the internal 8 MHz oscillator. The selected clock source drives the CPU clock directly, or after division, depending on the application. 3.2.2 RTC Clock The RTC slow clock has three possible sources: • external low-speed (32 kHz) crystal clock • internal RC oscillator (typically about 90 kHz, and adjustable) • internal 31.25 kHz clock (derived from the internal 8 MHz oscillator divided by 256) The RTC fast clock has two possible sources: • external divide-by-4 crystal clock • internal divide-by-N oscillator of 8 MHz The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller; while the RTC fast clock for RTC peripherals and sensing controllers. 3.2.3 Audio PLL Clock The audio clock is generated by the low-noise fractional-N PLL. 3.3 Analog Peripherals 3.3.1 Analog-to-Digital Converter (ADC) ESP32-S2 family integrates two 13-bit SAR ADCs and supports measurements on 20 channels (analog-enabled pins). The ULP-coprocessor in ESP32-S2 family is also designed to measure voltage. The ULP can operate while the main CPU is in Deep-sleep mode, which lowers the total power consumption. By using threshold settings, and / or via other triggers or events, we can interrupt the CPU from the sleep state. The ADCs can be configured to measure voltage on up to 20 pins. For ADC characteristics, please refer to Table 11. Espressif Systems 20 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description 3.3.2 Digital-to-Analog Converter (DAC) ESP32-S2 family has two 8-bit DAC channels that convert two digital signals into two analog voltage signal outputs. The two DAC channels support independent conversions. The design structure is composed of integrated resistor strings and a buffer. This dual DAC supports VDD3P3_RTC_IO power supply as input voltage reference. 3.3.3 Temperature Sensor The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via an ADC into a digital value. The temperature sensor has a range of –20 °C to 110 °C. It is designed primarily to sense the temperature changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O load. Generally, the chip’s internal temperature is higher than the ambient temperature. 3.3.4 Touch Sensor ESP32-S2 family has 14 capacitive-sensing GPIOs, which detect variations induced by touching or approaching the GPIOs with a finger or other objects. The low-noise nature of the design and the high sensitivity of the circuit allow relatively small pads to be used. Arrays of pads can also be used, so that a larger area or more points can be detected. The touch sensing performance can be further enhanced by the waterproof design and digital filtering feature. The 14 capacitive-sensing GPIOs are listed in Table 5. Table 5: Capacitive-Sensing GPIOs Available on ESP32-S2 Family Capacitive-sensing signal name Espressif Systems Pin name TOUCH1 GPIO1 TOUCH2 GPIO2 TOUCH3 GPIO3 TOUCH4 GPIO4 TOUCH5 GPIO5 TOUCH6 GPIO6 TOUCH7 GPIO7 TOUCH8 GPIO8 TOUCH9 GPIO9 TOUCH10 GPIO10 TOUCH11 GPIO11 TOUCH12 GPIO12 TOUCH13 GPIO13 TOUCH14 GPIO14 21 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description 3.4 Digital Peripherals 3.4.1 General Purpose Input / Output Interface (GPIO) ESP32-S2 family has 43 GPIO pins which can be assigned various functions by programming the appropriate registers. Some GPIOs can be used both for digital signals but also for analog functions, such as ADC, DAC and touch sensing. All GPIOs can be configured as internal pull-up or pull-down, or set to high impedance, except for GPIO46, which is fixed to pull-down. When configured as an input, the input value can be read by software through the register. The input can also be set to edge-trigger or level-trigger to generate CPU interrupts. Except for GPIO46 (input only), all digital IO pins are bi-directional, non-inverting and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to hold their states. 3.4.2 Serial Peripheral Interface (SPI) ESP32-S2 family features four SPI interfaces (SPI0, SPI1, SPI2 and SPI3). SPI0 and SPI1 can only be configured to operate in SPI memory mode; SPI2 can be configured to operate in SPI memory and general-purpose SPI modes; SPI3 can only be configured to operate in general-purpose SPI mode. • SPI Memory mode In SPI memory mode, SPI0, SPI1 and SPI2 interface with external SPI memory. Data transmission is in multiples of bytes. Up to 8-line STR/DDR reads and writes are supported. The clock frequency is configurable to a maximum of 80 MHz in STR mode and a maximum of 40 MHz in DDR mode. • SPI2 General-purpose SPI (GP-SPI) mode When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. The master mode supports 2-line full-duplex communication and 1-/2-/4-/8-line half-duplex communication. The slave mode supports 2-line full-duplex communication and 1-/2-/4-line half-duplex communication. The host’s clock frequency is configurable. Data transmission is in multiples of bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface supports DMA. – In 2-line full-duplex communication mode, the host’s clock frequency is configurable to 80 MHz at most, and the slave’s clock frequency to 40 MHz at most. Four modes of SPI transfer format are supported. – In 1-/2-/4-/8-line half-duplex communication mode, the host’s clock frequency is configurable to 80 MHz at most and the four modes of SPI transfer format are supported. – In 1-/2-/4-line half-duplex communication mode, the slave’s clock frequency is configurable to 40 MHz at most, and the four modes of SPI transfer format are also supported. • SPI3 General-purpose SPI (GP-SPI) mode As a general-purpose SPI interface, SPI3 can operate in master and slave modes, in 2-line full-duplex and 1-line half-duplex communication modes. The host’s clock frequency is configurable. Data transmission is in multiples of bytes. The clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI3 interface supports DMA. – In 2-line full-duplex communication mode, the host’s clock frequency is configurable to a maximum of 80 MHz, and the slave’s clock frequency to 40 MHz at most. Four modes of SPI transfer format are Espressif Systems 22 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description supported. – In 1-line half-duplex communication mode, the host’s clock frequency is configurable to a maximum of 80 MHz, and the slave’s clock frequency to 40 MHz at most. The four modes of SPI transfer format are supported. In most cases, the data port connection between ESP32-S2 family and external flash is as follows: SPI 8-line mode: • SPID (SPID) = IO0 • SPIQ (SPIQ) = IO1 • SPIWP (SPIWP) = IO2 • SPIHD (SPIHD) = IO3 • GPIO33 = IO4 • GPIO34 = IO5 • GPIO35 = IO6 • GPIO36 = IO7 • GPIO37 = DQS SPI 4-line mode: • SPID (SPID) = IO0 • SPIQ (SPIQ) = IO1 • SPIWP (SPIWP) = IO2 • SPIHD (SPIHD) = IO3 SPI 2-line mode: • SPID (SPID) = IO0 • SPIQ (SPIQ) = IO1 SPI 1-line mode: • SPID (SPID) = DI • SPIQ (SPIQ) = DO • SPIWP (SPIWP) = WP# • SPIHD (SPIHD) = HOLD# 3.4.3 LCD Interface The LCD interface supports 8-bit serial RGB, 8080 and 6800 modes. It is implemented using the hardware resources of SPI2. The LCD interface can also support 8/16/24-bit parallel interface (8080), implemented using the hardware resources of I2S. 3.4.4 Universal Asynchronous Receiver Transmitter (UART) ESP32-S2 family has two UART interfaces, i.e., UART0, UART1, which provide asynchronous communication (RS232 and RS485) and IrDA support, communicating at a speed of up to 5 Mbps. UART provides hardware Espressif Systems 23 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description management of the CTS and RTS signals and software flow control (XON and XOFF). All of the interfaces can be accessed by the DMA controller or directly by the CPU. 3.4.5 I2C Interface ESP32-S2 family has two I2C bus interfaces which can serve as I2C master or slave, depending on the user’s configuration. The I2C interfaces support: • standard mode (100 Kbit/s) • fast mode (400 Kbit/s) • up to 5 MHz (constrained by SDA pull-up strength) • 7-bit/10-bit addressing mode • dual addressing mode Users can program command registers to control I2C interfaces, so that they have more flexibility. 3.4.6 I2S Interface ESP32-S2 family includes a standard I2S interface. It can operate in master or slave mode, in full-duplex and half-duplex communication modes, and can be configured to operate with an 8-/16-/24-/32-bit resolution as an input or output channel. BCK clock frequency, from 10 kHz up to 40 MHz, is supported. The I2S interface has a dedicated DMA controller. PCM interface is supported. 3.4.7 Camera Interface ESP32-S2 family supports one 8 or 16-bit DVP image sensor, with clock frequency of up to 40 MHz. The camera interface is implemented by using the hardware resources of I2S. 3.4.8 Infrared Remote Controller The infrared remote controller supports four channels of infrared remote transmission and reception. By programming the pulse waveform, it supports various infrared and other single wire protocols. Four channels share a 256 × 32-bit block of memory to store the transmitting or receiving waveform. 3.4.9 Pulse Counter The pulse counter captures pulse and counts pulse edges through multiple modes. It has four channels, each of which captures four signals at a time. The four input signals include two pulse signals and two control signals. 3.4.10 LED PWM Controller The LED PWM controller can generate eight independent channels. The LED PWM controller: • can generate digital waveforms with configurable periods and duties. The accuracy of duty can be up to 18 bits within a 1 ms period. • has multiple clock sources, including APB clock and external crystal clock. • can operate when the CPU is in Light-sleep mode. Espressif Systems 24 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description • supports gradual increase or decrease of duty cycle, which is useful for the LED RGB color-gradient generator. 3.4.11 USB 1.1 OTG ESP32-S2 family features a full-speed USB OTG interface which is compliant with the USB 1.1 specification. It has the following features: • software-configurable endpoint settings and suspend/resume • support for dynamic FIFO sizing • support for session request protocol (SRP) and host negotiation protocol (HNP) • a full-speed USB PHY integrated in the chip 3.4.12 TWAI® Controller ESP32-S2 family has a TWAI® controller with the following features: • compatible with ISO 11898-1 protocol (CAN Specification 2.0) • standard frame format (11-bit ID) and extended frame format (29-bit ID) • bit rates from 1 Kbit/s to 1 Mbit/s • multiple modes of operation: Normal, Listen Only, and Self-Test • 64-byte receive FIFO • special transmissions: single-shot transmissions and self reception • acceptance filter (single and dual filter modes) • error detection and handling: error counters, configurable error interrupt threshold, error code capture, arbitration lost capture 3.5 Radio and Wi-Fi The ESP32-S2 family radio consists of the following blocks: • 2.4 GHz receiver • 2.4 GHz transmitter • Bias and regulators • Balun and transmit-receive switch • Clock generator 3.5.1 2.4 GHz Receiver The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions, RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits and baseband filters are integrated with ESP32-S2 family. Espressif Systems 25 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description 3.5.2 2.4 GHz Transmitter The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the antenna with a high-powered Complementary Metal Oxide Semiconductor (CMOS) power amplifier. The use of digital calibration further improves the linearity of the power amplifier. Additional calibrations are integrated to cancel any radio imperfections, such as: • carrier leakage • I/Q amplitude/phase matching • baseband nonlinearities • RF nonlinearities • antenna matching These built-in calibration routines reduce the cost, time, and specialized equipment required for product testing, and certification. 3.5.3 Clock Generator The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All components of the clock generator are integrated into the chip, including all inductors, varactors, filters, regulators and dividers. The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are optimized on-chip with patented calibration algorithms which ensure the best performance of the receiver and the transmitter. 3.5.4 Wi-Fi Radio and Baseband The ESP32-S2 family Wi-Fi radio and baseband support the following features: • 802.11b/g/n • 802.11n MCS0-7 that supports 20 MHz and 40 MHz bandwidth • 802.11n MCS32 • 802.11n 0.4 µs guard-interval • single stream, data rate up to 150 Mbps • STBC RX (Single spatial stream) • adjustable transmitting power • antenna diversity; ESP32-S2 family supports antenna diversity with an external RF switch. One or more GPIOs control the RF switch and select the best antenna to minimize the effects of channel imperfections. 3.5.5 Wi-Fi MAC ESP32-S2 family implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS) STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled automatically with minimal host interaction to minimize the active-duty period. Espressif Systems 26 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description The ESP32-S2 family Wi-Fi MAC applies low-level protocol functions automatically. They are as follows: • 4 × virtual Wi-Fi interfaces • simultaneous Infrastructure BSS Station mode/SoftAP mode/Promiscuous mode • RTS protection, CTS protection, Immediate Block ACK • fragmentation and defragmentation • TX/RX A-MPDU, RX A-MSDU • TXOP • WMM • CCMP, TKIP, WAPI, WEP, BIP • automatic beacon monitoring (hardware TSF) • 802.11mc FTM 3.5.6 Networking Features Users are provided with libraries for TCP/IP networking, ESP-MESH networking, and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and 1.2 support is also provided. 3.6 RTC and Low-Power Management 3.6.1 Power Management Unit (PMU) With the use of advanced power-management technologies, ESP32-S2 family can switch between different power modes. • Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen. • Modem-sleep mode: The CPU is operational and the clock speed can be reduced. The Wi-Fi baseband and radio are disabled, but Wi-Fi connection can remain active. • Light-sleep mode: The CPU is paused. The RTC peripherals, as well as the ULP co-processor are running. Any wake-up events (MAC, host, RTC timer, or external interrupts) will wake up the chip. Wi-Fi connection can remain active. • Deep-sleep mode: Only the RTC memory and RTC peripherals are powered on. Wi-Fi connection data are stored in the RTC memory. The ULP co-processor is functional. • Hibernation mode: The internal 8-MHz oscillator and ULP co-processor are disabled. The RTC recovery memory is powered down. Only one RTC timer on the slow clock and certain RTC GPIOs are active. The RTC timer or the RTC GPIOs can wake up the chip from the Hibernation mode. For power consumption in different power modes, please refer to Table 13. 3.6.2 Ultra-Low-Power Co-processor The ULP co-processor is designed as a simplified, low-power replacement of CPU in sleep modes. It can be also used to supplement the functions of the CPU in normal working mode. The ULP co-processor and RTC memory remain powered on during the Deep-sleep mode. Hence, the developer can store a program for the ULP Espressif Systems 27 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description co-processor in the RTC slow memory to access RTC GPIO, RTC peripheral devices, RTC timers and internal sensors during the Deep-sleep mode. ESP32-S2 family has two ULP co-processors, with one based on RISC-V instruction set architecture (ULP-RISC-V) and the other on finite state machine (ULP-FSM). ULP-RISC-V has the following features: • support for RV32IMC instruction set • thirty-two 32-bit general-purpose registers • 32-bit multiplier and divider • support for interrupts • boot by the CPU, its dedicated timer, or RTC GPIO ULP-FSM has the following features: • support for common instructions including arithmetic, jump, and program control instructions • support for on-board sensor measurement instructions • boot by the CPU, its dedicated timer, or RTC GPIO Note that these two co-processors cannot work simultaneously. 3.7 Timers and Watchdogs 3.7.1 64-bit Timers There are four general-purpose timers embedded in ESP32-S2 family. They are all 64-bit generic timers which are based on 16-bit prescalers and 64-bit auto-reload-capable up/down-timers. The timers’ features are summarized as follows: • a 16-bit clock prescaler, from 1 to 65536 • a 64-bit time-base counter programmable to be incrementing or decrementing • able to read real-time value of the time-base counter • halting and resuming the time-base counter • programmable alarm generation • timer value reload (Auto-reload at alarm or software-controlled instant reload) • level and edge interrupt generation 3.7.2 Watchdog Timers The ESP32-S2 family contains three watchdog timers: one in each of the two timer groups (called Main System Watchdog Timers, or MWDT) and one in the RTC Module (called the RTC Watchdog Timer, or RWDT). Each watchdog timer allows for four separately configurable stages and each stage can be programmed to take one of three (or four for RWDT) actions upon expiry, unless the watchdog is fed or disabled. The actions upon expiry are: interrupt, CPU reset, core reset and system reset. Only RWDT can trigger a system reset that will reset the entire digital circuits, which is the main system including the RTC itself. A timeout value can be set for each stage individually. Espressif Systems 28 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description During the flash boot process, RWDT and the first MWDT are enabled automatically in order to detect and recover from booting errors. Watchdog timers have the following features: • four stages, each with a programmable timeout value. Each stage can be configured and enabled/disabled separately • one of three/four (for MWDTs/ RWDT) possible actions (interrupt, CPU reset, core reset and system reset) available upon expiry of each stage • 32-bit expiry counter • write protection, to prevent RWDT and MWDT configuration from being altered inadvertently • flash boot protection If the boot process from an SPI flash does not complete within a predetermined period of time, the watchdog will reboot the entire main system. 3.8 Cryptographic Hardware Accelerators ESP32-S2 family is equipped with hardware accelerators of general algorithms, such as AES (FIPS PUB 197), ECB/CBC/OFB/CFB/CTR (NIST SP 800-38A), GCM (NIST SP 800-38D), SHA (FIPS PUB 180-4), RSA, and ECC, which support independent arithmetic, such as Big Integer Multiplication and Big Integer Modular Multiplication. The maximum operation length for RSA, Big Integer Multiplication and Big Integer Modular Multiplication is 4096 bits. The maximum factor length for Big Integer Multiplication is 2048 bits. 3.9 Physical Security Features • Transparent external flash and RAM encryption (AES-XTS) with software inaccessible key prevents unauthorized readout of user application code or data. • Secure Boot feature uses a hardware root of trust to ensure only signed firmware (with RSA-PSS signature) can be booted. • HMAC module can use a software inaccessible MAC key to generate SHA-HMAC signatures for identity verification, as well as other uses. • Digital Signature module can use a software inaccessible secure key to generate MAC signatures for identity verification. Espressif Systems 29 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description 3.10 Peripheral Pin Configurations Table 6: Peripheral Pin Configurations Interface Signal Pin Function ADC ADC1_CH0 GPIO1 Two 13-bit SAR ADCs ADC1_CH1 GPIO2 ADC1_CH2 GPIO3 ADC1_CH3 GPIO4 ADC1_CH4 GPIO5 ADC1_CH5 GPIO6 ADC1_CH6 GPIO7 ADC1_CH7 GPIO8 ADC1_CH8 GPIO9 ADC1_CH9 GPIO10 ADC2_CH0 GPIO11 ADC2_CH1 GPIO12 ADC2_CH2 GPIO13 ADC2_CH3 GPIO14 ADC2_CH4 XTAL_32K_P ADC2_CH5 XTAL_32K_N ADC2_CH6 DAC_1 ADC2_CH7 DAC_2 ADC2_CH8 GPIO19 ADC2_CH9 GPIO20 DAC_1 DAC_1 DAC_2 DAC_2 TOUCH1 GPIO1 TOUCH2 GPIO2 TOUCH3 GPIO3 TOUCH4 GPIO4 TOUCH5 GPIO5 TOUCH6 GPIO6 TOUCH7 GPIO7 TOUCH8 GPIO8 TOUCH9 GPIO9 TOUCH10 GPIO10 TOUCH11 GPIO11 TOUCH12 GPIO12 TOUCH13 GPIO13 TOUCH14 GPIO14 MTDI MTDI MTCK MTCK MTMS MTMS MTDO MTDO DAC Touch sensor JTAG Espressif Systems Two 8-bit DACs Capacitive touch sensors JTAG for software debugging 30 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description Interface Signal Pin Function UART U0RXD_in Any GPIO pins Two UART channels with hardware flow-control U0CTS_in and DMA U0DSR_in U0TXD_out U0RTS_out U0DTR_out U1RXD_in U1CTS_in U1TXD_out U1RTS_out I2C I2CEXT0_SCL_in Any GPIO pins Two I2C channels in slave or master mode Any GPIO pins 8 independent channels, 80 MHz clock/RTC I2CEXT0_SDA_in I2CEXT1_SCL_in I2CEXT1_SDA_in I2CEXT0_SCL_out I2CEXT0_SDA_out I2CEXT1_SCL_out I2CEXT1_SDA_out LED PWM ledc_ls_sig_out0~7 clock/XTAL clock. Duty accuracy: 18 bits I2S I2S0I_DATA_in0~15 Any GPIO pins Stereo input and output from/to the audiocodec; I2S0O_BCK_in parallel LCD data output; parallel camera data I2S0O_WS_in input I2S0I_BCK_in I2S0I_WS_in I2S0I_H_SYNC I2S0I_V_SYNC I2S0I_H_ENABLE I2S0O_BCK_out I2S0O_WS_out I2S0I_BCK_out I2S0I_WS_out I2S0O_DATA_out0~23 Infrared Remote RMT_SIG_IN0~3 controller RMT_SIG_OUT0~3 SPI0/1 SPICLK_out SPICLK Support Standard SPI, Dual SPI, QSPI, QPI, SPICS0_out SPICS0 OSPI, and OPI. Support STR and DDR modes. SPICS1_out SPICS1 Support interface with external flash and RAM SPID_in/out SPID SPIQ_in/out SPIQ SPIWP_in/out SPIWP SPIHD_in/out SPIHD SPID4_in/out GPIO33 SPID5_in/out GPIO34 SPID6_in/out GPIO35 Espressif Systems Any GPIO pins Four channels for an IR transceiver of various waveforms 31 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description Interface SPI2 Signal Pin Function SPID7_in/out GPIO36 SPIDQS_in/out GPIO37 FSPICLK_in/out Any GPIO pins FSPICS0_in/out Supports SPI that can interface with LCD and other external devices. Supports the following FSPICS1 ~ 5_out features: FSPID_in/out • Both master and slave modes FSPIQ_in/out • Four modes of SPI transfer format FSPIWP_in/out • Configurable SPI frequency FSPIHD_in/out • 72-byte FIFO or DMA buffer FSPIIO4 ~ 7_in/out Supports Standard SPI, Dual SPI, QSPI, QPI, FSPIDQS_out OSPI, and OPI. Supports STR and DDR modes. FSPICD_out Supports interface with external flash and RAM FSPI_VSYNC_out FSPI_HSYNC_out FSPI_DE_out SPI3 SPI3_CLK_in/out Any GPIO pins SPI3_CS0_in/out Supports Standard SPI, with the following features: SPI3_CS1_out • Both master and slave modes SPI3_CS2_out • Four modes of SPI transfer format SPI3_D_in/out • Configurable SPI frequency; SPI3_Q_in/out • 72-byte FIFO or DMA buffer. SPI3_HD_in/out SPI3_DQS_out SPI3_CD_out Pulse counter pcnt_sig_ch0_in0 Any GPIO pins pcnt_sig_ch1_in0 Captures pulse and counts pulse edges in multiple different modes pcnt_ctrl_ch0_in0 pcnt_ctrl_ch1_in0 pcnt_sig_ch0_in1 pcnt_sig_ch1_in1 pcnt_ctrl_ch0_in1 pcnt_ctrl_ch1_in1 pcnt_sig_ch0_in2 pcnt_sig_ch1_in2 pcnt_ctrl_ch0_in2 pcnt_ctrl_ch1_in2 pcnt_sig_ch0_in3 pcnt_sig_ch1_in3 pcnt_ctrl_ch0_in3 pcnt_ctrl_ch1_in3 USB OTG Espressif Systems D- GPIO19 D+ GPIO20 Full-speed USB OTG 32 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 3. Functional Description Interface Signal Pin Function TWAI twai_rx Any GPIO pins Compatible with ISO 11898-1 protocol twai_tx twai_bus_off_on twai_clkout Note: • GPIO46 is input-only and can not be used for output function. Espressif Systems 33 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the device. These are stress ratings only, and do not refer to the functional operation of the device. Table 7: Absolute Maximum Ratings Symbol Parameter VDDA, VDD3P3, VDD3P3_RTC, Voltage applied to power supply VDD3P3_CPU, VDD_SPI, VDD3P3_RTC_IO pins per power domain TST ORE Storage temperature Min Max Unit –0.3 3.6 V –40 150 °C 4.2 Recommended Operating Conditions Table 8: Recommended Operating Conditions Parameter Min Typ Max Unit Voltage applied to power supply pins per power domain 2.8 3.3 3.6 V — 1.8 3.3 3.6 V VDD3P3_RTC_IO2 — 3.0 3.3 3.6 V VDD3P3_CPU Voltage applied to power supply pin 2.8 3.3 3.6 V IV DD 3 Current delivered by external power supply 0.5 — — A TJ Junction temperature –40 — 125 °C Symbol VDDA, VDD3P3, VDD3P3_RTC VDD_SPI (working as input power supply)1 Note: 1. Please refer to Power Scheme, section 2.3, for more information. 2. When VDD_SPI is used to drive peripherals, VDD3P3_RTC_IO should comply with the peripherals’ specifications. For more information, please refer to Table 9. 3. When using a single-power supply, the recommended output current is 500 mA or more. 4.3 VDD_SPI Output Characteristics Table 9: VDD_SPI Output Characteristics Typ Unit Symbol Parameter RSP I On-resistance in 3.3 V mode 5 Ω ISP I Output current in 1.8 V mode 40 mA Espressif Systems 34 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics Note: In real-life applications, when VDD_SPI works in 3.3 V output mode, VDD3P3_RTC_IO may be affected by RSP I . For example, when VDD3P3_RTC_IO is used to drive an external 3.3 V flash, it should comply with the following specifications: VDD3P3_RTC_IO > VDD_flash_min + I_flash_max*RSP I Among which, VDD_flash_min is the minimum operating voltage of the flash, and I_flash_max the maximum current. For more information, please refer to Power Scheme, section 2.3. 4.4 DC Characteristics (3.3 V, 25 °C) Table 10: DC Characteristics (3.3 V, 25 °C) Symbol Parameter CIN Pin capacitance VIH Min Typ — 0.75 × VDD High-level input voltage 1 Max 2 Unit — pF — VDD + 0.3 V 1 V 1 VIL Low-level input voltage –0.3 — 0.25 × VDD IIH High-level input current — — 50 nA IIL Low-level input current — — 50 nA VOH 2 High-level output voltage 0.8 × VDD1 — — V VOL 2 Low-level output voltage — — 0.1 × VDD1 V — 40 — mA — 28 — mA — kΩ — kΩ 1 High-level source current (VDD = 3.3 V, VOH IOH >= 2.64 V, PAD_DRIVER = 3) Low-level sink current (VDD1 = 3.3 V, VOL = IOL 0.495 V, PAD_DRIVER = 3) RP U Pull-up resistor — 45 RP D Pull-down resistor — 45 VIH _nRST VIL_nRST 0.75 × VDD Chip reset release voltage 1 –0.3 Chip reset voltage 1 — VDD + 0.3 V — 1 V 0.25 × VDD Note: 1. VDD is the I/O voltage for a particular power domain of pins. 2. VOH and VOL are measured using high-impedance load. 4.5 ADC Characteristics Table 11: ADC Characteristics Parameter DNL (Differential nonlinearity) INL (Integral nonlinearity) Espressif Systems Description RTC controller; ADC connected to an external 100 nF capacitor; DC signal input; ambient temperature at 25 °C; Wi-Fi off 35 Submit Documentation Feedback Min Max Unit –7 7 LSB –12 12 LSB ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics Note: • When reading voltages greater than 2450 mV, ADC accuracy will be worse than that in the table above. • To get better DNL results, users can sample multiple times and apply a filter, or calculate the average value. 4.6 Current Consumption Characteristics The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF port. All transmitters’ measurements are based on a 100% duty cycle. Table 12: Current Consumption Depending on RF Modes Work mode Description TX Active (RF working) RX Peak (mA) 802.11b, 20 MHz, 1 Mbps, @19.5 dBm 310 802.11g, 20 MHz, 54 Mbps, @15 dBm 220 802.11n, 20 MHz, MCS7, @13 dBm 200 802.11n, 40 MHz, MCS7, @13 dBm 160 802.11b/g/n, 20 MHz 63 802.11n, 40 MHz 68 Note: The current consumption figures for in RX mode are for cases when the peripherals are disabled and the CPU idle. Table 13: Current Consumption Depending on Work Modes Work mode Modem-sleep Light-sleep Deep-sleep Power off Espressif Systems The CPU is powered on Description Current consumption (Typ) 240 MHz 19 mA 160 MHz 16 mA Normal speed: 80 MHz 12 mA — 450 µA The ULP co-processor ULP-FSM is powered on ULP-RISC-V 170 µA ULP sensor-monitored pattern 190 µA 22 µA @1% duty RTC timer + RTC memory 25 µA RTC timer only 20 µA CHIP_PU is set to low level, the chip is powered off 1 µA 36 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics Note: • The current consumption figures in Modem-sleep mode are for cases where the CPU is powered on and the cache idle. • When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, current consumption changes accordingly. • In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU load and the peripherals used. • During Deep-sleep, when the ULP co-processor is powered on, peripherals such as GPIO and I2C are able to operate. • The ”ULP sensor-monitored pattern” refers to the mode where the ULP coprocessor or the sensor works periodically. When touch sensors work with a duty cycle of 1%, the typical current consumption is 22 µA. 4.7 Reliability Qualifications Table 14: Reliability Qualifications Test Item HTOL (High Temperature Operating Life) ESD (Electro-Static Discharge Sensitivity) Latch up Test Conditions Test Standard 125 °C, 1000 hours JESD22-A108 HBM (Human Body Mode) 1 ± 2000 V CDM (Charge Device Mode) 2 JESD22-A114 ± 500 V JESD22-C101F Current trigger ± 200 mA JESD78 Voltage trigger 1.5 × VDDmax Bake 24 hours @125 °C Preconditioning Moisture soak (level 3: 192 hours @30 °C, 60% RH) IR reflow solder: 260 + 0 °C, 20 seconds, three times TCT (Temperature Cycling Test) J-STD-020, JESD47, JESD22-A113 –65 °C / 150 °C, 500 cycles JESD22-A104 130 °C, 85% RH, 96 hours JESD22-A118 150 °C, 1000 hours JESD22-A103 – 40 °C, 1000 hours JESD22-A119 uHAST (Highly Accelerated Stress Test, unbiased) HTSL (High Temperature Storage Life) LTSL (Low Temperature Storage Life) 1. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. 2. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Espressif Systems 37 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics 4.8 Wi-Fi Radio 4.8.1 Transmitter Characteristics Table 15: Transmitter Characteristics Parameter Rate TX Power Typ Unit 11b, 1 Mbps 19.5 dBm 11b, 11 Mbps 19.5 11g, 6 Mbps 18 11g, 54 Mbps 15 11n, HT20, MCS0 18 11n, HT20, MCS7 13 11n, HT40, MCS0 18 11n, HT40, MCS7 13 4.8.2 Receiver Characteristics Table 16: Receiver Characteristics Espressif Systems Parameter Rate Typ Unit RX Sensitivity 1 Mbps –97 dBm 2 Mbps –95 5.5 Mbps –93 11 Mbps –88 6 Mbps –92 9 Mbps –91 12 Mbps –89 18 Mbps –87 24 Mbps –84 36 Mbps –80 48 Mbps –76 54 Mbps –75 11n, HT20, MCS0 –92 11n, HT20, MCS1 –88 11n, HT20, MCS2 –85 11n, HT20, MCS3 –83 11n, HT20, MCS4 –79 11n, HT20, MCS5 –75 11n, HT20, MCS6 –74 11n, HT20, MCS7 –72 11n, HT40, MCS0 –89 11n, HT40, MCS1 –86 11n, HT40, MCS2 –83 11n, HT40, MCS3 –80 11n, HT40, MCS4 –76 38 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 4. Electrical Characteristics Parameter RX Maximum Input Level Adjacent Channel Rejection Espressif Systems Rate Typ 11n, HT40, MCS5 –72 11n, HT40, MCS6 –71 11n, HT40, MCS7 –69 11b, 1 Mbps 5 11b, 11 Mbps 5 11g, 6 Mbps 5 11g, 54 Mbps 0 11n, HT20, MCS0 5 11n, HT20, MCS7 0 11n, HT40, MCS0 5 11n, HT40, MCS7 0 11b, 11 Mbps 35 11g, 6 Mbps 31 11g, 54 Mbps 14 11n, HT20, MCS0 31 11n, HT20, MCS7 13 11n, HT40, MCS0 19 11n, HT40, MCS7 8 39 Submit Documentation Feedback Unit dBm dB ESP32-S2 Family Datasheet V1.3 5. Package Information 5. Package Information Pin 1 Pin 2 Pin 3 Pin 1 Pin 2 Pin 3 Figure 7: QFN56 (7×7 mm) Package Note: • The pins of the chip are numbered in an anti-clockwise direction from Pin 1 in the top view; • For the source file of recommended PCB land pattern (dxf), you can view it with Autodesk Viewer; • For information about tape, reel, and product marking, please refer to Espressif Chip-Packing Information. Espressif Systems 40 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 6. Learning Resources 6. Learning Resources 6.1 Must-Read Documents Click on the following links to access documents related to ESP32-S2. • ESP-IDF Programming Guide It hosts extensive documentation for ESP-IDF, ranging from hardware guides to API reference. • ESP32-S2 Technical Reference Manual The manual provides detailed information on how to use the ESP32-S2 memory and peripherals. • ESP32-S2 Hardware Design Guidelines The guidelines provide recommended design practices when developing standalone or add-on systems based on the ESP32-S2 series of products, including the ESP32-S2 chip, the ESP32-S2 modules and development boards. • Espressif Products Ordering Information 6.2 Must-Have Resources Here are the must-have resources related to ESP32-S2. • ESP32 BBS Engineer-to-Engineer (E2E) Community for Espressif products where you can post questions, share knowledge, explore ideas, and help solve problems with fellow engineers. • GitHub Development projects built around ESP chips are freely distributed under Espressif’s MIT license on GitHub. This channel of communication has been established to help developers get started with ESP chips and encourage them to share their knowledge of Espressif’s hardware and software. • Tools A webpage where you can download Flash Download Tools, Certification and Test Guide, and demonstration, etc. Espressif Systems 41 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists Appendix A – ESP32-S2 Pin Lists A.1. IO MUX IO_MUX Pin No. 1 Analog Function0 Analog Function1 RTC_GPIO Digital Function0 Type Digital Function1 Type Drive Strength (Default) At Reset After Reset VDD3P3_RTC_IO TOUCH1 ADC1_CH0 VDD3P3_RTC_IO TOUCH2 ADC1_CH1 RTC_GPIO0 GPIO0 I/O/T GPIO0 RTC_GPIO1 GPIO1 I/O/T GPIO1 RTC_GPIO2 GPIO2 I/O/T GPIO2 I/O/T 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu, I/O/T 2‘d2 oe=0, ie=1 oe=0, ie=1 I/O/T 2‘d2 oe=0, ie=1 GPIO3 VDD3P3_RTC_IO TOUCH3 ADC1_CH2 RTC_GPIO3 GPIO3 I/O/T oe=0, ie=1 GPIO3 I/O/T 2‘d2 oe=0, ie=1 9 GPIO4 VDD3P3_RTC_IO TOUCH4 ADC1_CH3 RTC_GPIO4 GPIO4 oe=0, ie=0 I/O/T GPIO4 I/O/T 2‘d2 oe=0, ie=1 10 GPIO5 11 GPIO6 VDD3P3_RTC_IO TOUCH5 ADC1_CH4 RTC_GPIO5 VDD3P3_RTC_IO TOUCH6 ADC1_CH5 RTC_GPIO6 oe=0, ie=0 GPIO5 I/O/T GPIO5 I/O/T 2‘d2 oe=0, ie=0 oe=0, ie=0 GPIO6 I/O/T GPIO6 I/O/T 2‘d2 oe=0, ie=0 12 GPIO7 VDD3P3_RTC_IO TOUCH7 ADC1_CH6 oe=0, ie=0 RTC_GPIO7 GPIO7 I/O/T GPIO7 I/O/T 2‘d2 oe=0, ie=0 13 GPIO8 VDD3P3_RTC_IO TOUCH8 oe=0, ie=0 ADC1_CH7 RTC_GPIO8 GPIO8 I/O/T GPIO8 I/O/T 2‘d2 oe=0, ie=0 14 GPIO9 VDD3P3_RTC_IO oe=0, ie=0 TOUCH9 ADC1_CH8 RTC_GPIO9 FSPIHD I1/O/T GPIO9 I/O/T 15 GPIO10 VDD3P3_RTC_IO TOUCH10 ADC1_CH9 RTC_GPIO10 FSPICS0 I1/O/T GPIO10 I/O/T FSPIIO4 16 17 GPIO11 VDD3P3_RTC_IO TOUCH11 ADC2_CH0 RTC_GPIO11 FSPID I1/O/T GPIO11 I/O/T GPIO12 VDD3P3_RTC_IO TOUCH12 ADC2_CH1 RTC_GPIO12 FSPICLK I1/O/T GPIO12 I/O/T 18 GPIO13 VDD3P3_RTC_IO TOUCH13 ADC2_CH2 RTC_GPIO13 FSPIQ I1/O/T GPIO13 19 GPIO14 VDD3P3_RTC_IO TOUCH14 ADC2_CH3 RTC_GPIO14 FSPIWP I1/O/T GPIO14 21 XTAL_32K_P VDD3P3_RTC_IO XTAL_32K_P ADC2_CH4 RTC_GPIO15 GPIO15 I/O/T 22 XTAL_32K_N VDD3P3_RTC_IO XTAL_32K_N ADC2_CH5 RTC_GPIO16 GPIO16 23 DAC_1 VDD3P3_RTC_IO DAC_1 ADC2_CH6 RTC_GPIO17 GPIO17 24 DAC_2 VDD3P3_RTC_IO DAC_2 ADC2_CH7 RTC_GPIO18 25 GPIO19 VDD3P3_RTC_IO USB_D- ADC2_CH8 26 GPIO20 VDD3P3_RTC_IO USB_D+ ADC2_CH9 28 GPIO21 VDD3P3_RTC_IO 29 SPICS1 31 Power Supply Pin Analog Pin Digital Pin Power Domain 5 GPIO0 VDD3P3_RTC_IO 6 GPIO1 7 GPIO2 8 Digital Function2 Type Digital Function3 Type Digital Function4 Type VDDA 2 LNA_IN 3 VDD3P3 4 VDD3P3 FSPIHD I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 I1/O/T FSPICS0 I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 FSPIIO5 I1/O/T FSPID I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 FSPIIO6 I1/O/T FSPICLK I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 I/O/T FSPIIO7 I1/O/T FSPIQ I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 I/O/T FSPIDQS I1/O/T FSPIWP I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 GPIO15 I/O/T U0RTS O 2‘d2 oe=0, ie=0 oe=0, ie=0 I/O/T GPIO16 I/O/T U0CTS I1 2‘d2 oe=0, ie=0 oe=0, ie=0 I/O/T GPIO17 I/O/T U1TXD O 2‘d2 oe=0, ie=0 oe=0, ie=1 GPIO18 I/O/T GPIO18 I/O/T U1RXD I1 CLK_OUT3 O 2‘d2 oe=0, ie=0 oe=0, ie=1 RTC_GPIO19 GPIO19 I/O/T GPIO19 I/O/T U1RTS O CLK_OUT2 O 2‘d2 oe=0, ie=0 oe=0, ie=0 RTC_GPIO20 GPIO20 I/O/T GPIO20 I/O/T U1CTS I1 CLK_OUT1 O 2‘d2 oe=0, ie=0 oe=0, ie=0 RTC_GPIO21 GPIO21 I/O/T GPIO21 I/O/T 2‘d2 oe=0, ie=0 oe=0, ie=0 VDD_SPI SPICS1 I1/O/T GPIO26 I/O/T 2‘d2 oe=0, ie=1, wpu oe=1, ie=1, wpu SPIHD VDD_SPI SPIHD I1/O/T GPIO27 I/O/T 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu 32 SPIWP VDD_SPI SPIWP I1/O/T GPIO28 I/O/T 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu 33 SPICS0 VDD_SPI SPICS0 I1/O/T GPIO29 I/O/T 2‘d2 oe=0, ie=1, wpu oe=1, ie=1, wpu 34 SPICLK VDD_SPI SPICLK I1/O/T GPIO30 I/O/T 2‘d2 oe=0, ie=1, wpu oe=1, ie=1, wpu 35 SPIQ VDD_SPI SPIQ I1/O/T GPIO31 I/O/T 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu 36 SPID VDD_SPI SPID I1/O/T GPIO32 I/O/T 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu 37 GPIO33 VDD3P3_CPU / VDD_SPI GPIO33 I/O/T GPIO33 I/O/T FSPIHD I1/O/T SPIIO4 I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 38 GPIO34 VDD3P3_CPU / VDD_SPI GPIO34 I/O/T GPIO34 I/O/T FSPICS0 I1/O/T SPIIO5 I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 39 GPIO35 VDD3P3_CPU / VDD_SPI GPIO35 I/O/T GPIO35 I/O/T FSPID I1/O/T SPIIO6 I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 40 GPIO36 VDD3P3_CPU / VDD_SPI GPIO36 I/O/T GPIO36 I/O/T FSPICLK I1/O/T SPIIO7 I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 41 GPIO37 VDD3P3_CPU / VDD_SPI GPIO37 I/O/T GPIO37 I/O/T FSPIQ I1/O/T SPIDQS I1/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 42 GPIO38 VDD3P3_CPU GPIO38 I/O/T GPIO38 I/O/T FSPIWP I1/O/T GPIO38 I/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 43 MTCK VDD3P3_CPU MTCK I1 GPIO39 I/O/T CLK_OUT3 O 2‘d2 oe=0, ie=0 oe=0, ie=1 MTDO VDD3P3_CPU MTDO O/T GPIO40 I/O/T CLK_OUT2 O 2‘d2 oe=0, ie=0 oe=0, ie=1 46 MTDI VDD3P3_CPU MTDI I1 GPIO41 I/O/T CLK_OUT1 O 2‘d2 oe=0, ie=0 oe=0, ie=1 47 MTMS VDD3P3_CPU MTMS I0 GPIO42 I/O/T 2‘d2 oe=0, ie=0 oe=0, ie=1 48 U0TXD VDD3P3_CPU U0TXD O GPIO43 I/O/T CLK_OUT1 O 2‘d2 oe=0, ie=1, wpu oe=1, ie=1, wpu 49 U0RXD VDD3P3_CPU U0RXD I1 GPIO44 I/O/T CLK_OUT2 O 2‘d2 oe=0, ie=1, wpu oe=0, ie=1, wpu 50 GPIO45 VDD3P3_CPU GPIO45 I/O/T GPIO45 I/O/T 2‘d2 oe=0, ie=1, wpd oe=0, ie=1, wpd GPIO46 VDD3P3_CPU GPIO46 I GPIO46 I oe=0, wpd, ie=1 oe=0, wpd, ie=1 20 27 30 VDD3P3_RTC VDD3P3_RTC_IO VDD_SPI 44 45 51 VDD3P3_CPU VDDA 52 XTAL_N 53 54 XTAL_P VDDA 55 56 Total VDD3P3_RTC_IO CHIP_PU 10 3 43 Notes: • Power supply for GPIO33, GPIO34, GPIO35, GPIO36 and GPIO37 is configurable to be either VDD3P3_CPU (default) or VDD_SPI. • SPIHD, SPIWP, SPICS0, SPICLK, SPIQ, SPID pins of ESP32-S2FH2 and ESP32-S2FH4 are connected to embedded flash and not recommended for other uses. • wpu: weak pull-up • wpd: weak pull-down • ie: input enable • oe: output enable • Each column about digital “Function" is accompanied by a column about “Type". Please see the following explanations for the meanings of “type" with respect to each “function" they are associated with. For each “Function-N", “type" signifies: - I: input only. If a function other than “Function-N" is assigned, the input signal of “Function-N" is still from this pin. - I1: input only. If a function other than “Function-N" is assigned, the input signal of “Function-N" is always “1". - I0: input only. If a function other than “Function-N" is assigned, the input signal of “Function-N" is always “0". - O: output only. - T: high-impedance. - I/O/T: combinations of input, output, and high-impedance according to the function signal. - I1/O/T: combinations of input, output, and high-impedance, according to the function signal. If a function is not selected, the input signal of the function is “1”. Espressif Systems 42 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists A.2. GPIO Matrix Table 17: GPIO_Matrix Signal No. Input signals Default Same input value if signal from IO unassigned* Output enable of MUX core Output signals output signals 0 SPIQ_in 0 yes SPIQ_out SPIQ_oe 1 SPID_in 0 yes SPID_out SPID_oe 2 SPIHD_in 0 yes SPIHD_out SPIHD_oe 3 SPIWP_in 0 yes SPIWP_out SPIWP_oe 4 - - - SPICLK_out_mux SPICLK_oe 5 - - - SPICS0_out SPICS0_oe 6 - - - SPICS1_out SPICS1_oe 7 SPID4_in 0 yes SPID4_out SPID4_oe 8 SPID5_in 0 yes SPID5_out SPID5_oe 9 SPID6_in 0 yes SPID6_out SPID6_oe 10 SPID7_in 0 yes SPID7_out SPID7_oe 11 SPIDQS_in 0 yes SPIDQS_out SPIDQS_oe 14 U0RXD_in 0 yes U0TXD_out 1’d1 15 U0CTS_in 0 yes U0RTS_out 1’d1 16 U0DSR_in 0 no U0DTR_out 1’d1 17 U1RXD_in 0 yes U1TXD_out 1’d1 18 U1CTS_in 0 yes U1RTS_out 1’d1 21 U1DSR_in 0 no U1DTR_out 1’d1 23 I2S0O_BCK_in 0 no I2S0O_BCK_out 1’d1 25 I2S0O_WS_in 0 no I2S0O_WS_out 1’d1 27 I2S0I_BCK_in 0 no I2S0I_BCK_out 1’d1 28 I2S0I_WS_in 0 no I2S0I_WS_out 1’d1 29 I2CEXT0_SCL_in 1 no I2CEXT0_SCL_out I2CEXT0_SCL_oe 30 I2CEXT0_SDA_in 1 no I2CEXT0_SDA_out I2CEXT0_SDA_oe 39 pcnt_sig_ch0_in0 0 no gpio_wlan_prio 1’d1 40 pcnt_sig_ch1_in0 0 no gpio_wlan_active 1’d1 41 pcnt_ctrl_ch0_in0 0 no - 1’d1 42 pcnt_ctrl_ch1_in0 0 no - 1’d1 43 pcnt_sig_ch0_in1 0 no - 1’d1 44 pcnt_sig_ch1_in1 0 no - 1’d1 45 pcnt_ctrl_ch0_in1 0 no - 1’d1 46 pcnt_ctrl_ch1_in1 0 no - 1’d1 47 pcnt_sig_ch0_in2 0 no - 1’d1 48 pcnt_sig_ch1_in2 0 no - 1’d1 49 pcnt_ctrl_ch0_in2 0 no - 1’d1 50 pcnt_ctrl_ch1_in2 0 no - 1’d1 Espressif Systems 43 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists Signal No. Input signals Default Same input value if signal from IO unassigned* Output enable of MUX core Output signals output signals 51 pcnt_sig_ch0_in3 0 no - 1’d1 52 pcnt_sig_ch1_in3 0 no - 1’d1 53 pcnt_ctrl_ch0_in3 0 no - 1’d1 54 pcnt_ctrl_ch1_in3 0 no - 1’d1 64 usb_otg_iddig_in 0 no - 1’d1 65 usb_otg_avalid_in 0 no - 1’d1 66 usb_srp_bvalid_in 0 no usb_otg_idpullup 1’d1 67 usb_otg_vbusvalid_in 0 no usb_otg_dppulldown 1’d1 68 usb_srp_sessend_in 0 no usb_otg_dmpulldown 1’d1 69 - - - usb_otg_drvvbus 1’d1 70 - - - usb_srp_chrgvbus 1’d1 71 - - - usb_srp_dischrgvbus 1’d1 72 SPI3_CLK_in 0 no SPI3_CLK_out_mux SPI3_CLK_oe 73 SPI3_Q_in 0 no SPI3_Q_out SPI3_Q_oe 74 SPI3_D_in 0 no SPI3_D_out SPI3_D_oe 75 SPI3_HD_in 0 no SPI3_HD_out SPI3_HD_oe 76 SPI3_CS0_in 0 no SPI3_CS0_out SPI3_CS0_oe 77 - - - SPI3_CS1_out SPI3_CS1_oe 78 - - - SPI3_CS2_out SPI3_CS2_oe 79 - - - ledc_ls_sig_out0 1’d1 80 - - - ledc_ls_sig_out1 1’d1 81 - - - ledc_ls_sig_out2 1’d1 82 - - - ledc_ls_sig_out3 1’d1 83 rmt_sig_in0 0 no ledc_ls_sig_out4 1’d1 84 rmt_sig_in1 0 no ledc_ls_sig_out5 1’d1 85 rmt_sig_in2 0 no ledc_ls_sig_out6 1’d1 86 rmt_sig_in3 0 no ledc_ls_sig_out7 1’d1 87 - - - rmt_sig_out0 1’d1 88 - - - rmt_sig_out1 1’d1 89 - - - rmt_sig_out2 1’d1 90 - - - rmt_sig_out3 1’d1 95 I2CEXT1_SCL_in 1 no I2CEXT1_SCL_out I2CEXT1_SCL_oe 96 I2CEXT1_SDA_in 1 no I2CEXT1_SDA_out I2CEXT1_SDA_oe 100 - - - gpio_sd0_out 1’d1 101 - - - gpio_sd1_out 1’d1 102 - - - gpio_sd2_out 1’d1 103 - - - gpio_sd3_out 1’d1 104 - - - gpio_sd4_out 1’d1 105 - - - gpio_sd5_out 1’d1 106 - - - gpio_sd6_out 1’d1 Espressif Systems 44 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists Signal No. Input signals Default Same input value if signal from IO unassigned* Output enable of MUX core Output signals output signals 107 - - - gpio_sd7_out 1’d1 108 FSPICLK_in 0 yes FSPICLK_out_mux FSPICLK_oe 109 FSPIQ_in 0 yes FSPIQ_out FSPIQ_oe 110 FSPID_in 0 yes FSPID_out FSPID_oe 111 FSPIHD_in 0 yes FSPIHD_out FSPIHD_oe 112 FSPIWP_in 0 yes FSPIWP_out FSPIWP_oe 113 FSPIIO4_in 0 yes FSPIIO4_out FSPIIO4_oe 114 FSPIIO5_in 0 yes FSPIIO5_out FSPIIO5_oe 115 FSPIIO6_in 0 yes FSPIIO6_out FSPIIO6_oe 116 FSPIIO7_in 0 yes FSPIIO7_out FSPIIO7_oe 117 FSPICS0_in 0 yes FSPICS0_out FSPICS0_oe 118 - - - FSPICS1_out FSPICS1_oe 119 - - - FSPICS2_out FSPICS2_oe 120 - - - FSPICS3_out FSPICS3_oe 121 - - - FSPICS4_out FSPICS4_oe 122 - - - FSPICS5_out FSPICS5_oe 123 twai_rx 1 no twai_tx 1’d1 124 - - - twai_bus_off_on 1’d1 125 - - - twai_clkout 1’d1 126 - - - SUBSPICLK_out_mux SUBSPICLK_oe 127 SUBSPIQ_in 0 yes SUBSPIQ_out SUBSPIQ_oe 128 SUBSPID_in 0 yes SUBSPID_out SUBSPID_oe 129 SUBSPIHD_in 0 yes SUBSPIHD_out SUBSPIHD_oe 130 SUBSPIWP_in 0 yes SUBSPIWP_out SUBSPIWP_oe 131 - - - SUBSPICS0_out SUBSPICS0_oe 132 - - - SUBSPICS1_out SUBSPICS1_oe 133 - - - FSPIDQS_out FSPIDQS_oe 134 - - - FSPI_HSYNC_out FSPI_HSYNC_oe 135 - - - FSPI_VSYNC_out FSPI_VSYNC_oe 136 - - - FSPI_DE_out FSPI_DE_oe 137 - - - FSPICD_out FSPICD_oe 139 - - - SPI3_CD_out SPI3_CD_oe 140 - - - SPI3_DQS_out SPI3_DQS_oe 143 I2S0I_DATA_in0 0 no I2S0O_DATA_out0 1’d1 144 I2S0I_DATA_in1 0 no I2S0O_DATA_out1 1’d1 145 I2S0I_DATA_in2 0 no I2S0O_DATA_out2 1’d1 146 I2S0I_DATA_in3 0 no I2S0O_DATA_out3 1’d1 147 I2S0I_DATA_in4 0 no I2S0O_DATA_out4 1’d1 148 I2S0I_DATA_in5 0 no I2S0O_DATA_out5 1’d1 149 I2S0I_DATA_in6 0 no I2S0O_DATA_out6 1’d1 Espressif Systems 45 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists Signal No. Input signals Default Same input value if signal from IO unassigned* Output enable of MUX core Output signals output signals 150 I2S0I_DATA_in7 0 no I2S0O_DATA_out7 1’d1 151 I2S0I_DATA_in8 0 no I2S0O_DATA_out8 1’d1 152 I2S0I_DATA_in9 0 no I2S0O_DATA_out9 1’d1 153 I2S0I_DATA_in10 0 no I2S0O_DATA_out10 1’d1 154 I2S0I_DATA_in11 0 no I2S0O_DATA_out11 1’d1 155 I2S0I_DATA_in12 0 no I2S0O_DATA_out12 1’d1 156 I2S0I_DATA_in13 0 no I2S0O_DATA_out13 1’d1 157 I2S0I_DATA_in14 0 no I2S0O_DATA_out14 1’d1 158 I2S0I_DATA_in15 0 no I2S0O_DATA_out15 1’d1 159 - - - I2S0O_DATA_out16 1’d1 160 - - - I2S0O_DATA_out17 1’d1 161 - - - I2S0O_DATA_out18 1’d1 162 - - - I2S0O_DATA_out19 1’d1 163 - - - I2S0O_DATA_out20 1’d1 164 - - - I2S0O_DATA_out21 1’d1 165 - - - I2S0O_DATA_out22 1’d1 166 - - - I2S0O_DATA_out23 1’d1 167 SUBSPID4_in 0 yes SUBSPID4_out SUBSPID4_oe 168 SUBSPID5_in 0 yes SUBSPID5_out SUBSPID5_oe 169 SUBSPID6_in 0 yes SUBSPID6_out SUBSPID6_oe 170 SUBSPID7_in 0 yes SUBSPID7_out SUBSPID7_oe 171 SUBSPIDQS_in 0 yes SUBSPIDQS_out SUBSPIDQS_oe 193 I2S0I_H_SYNC 0 no - 1’d1 194 I2S0I_V_SYNC 0 no - 1’d1 195 I2S0I_H_ENABLE 0 no - 1’d1 215 - - - ant_sel0 1’d1 216 - - - ant_sel1 1’d1 217 - - - ant_sel2 1’d1 218 - - - ant_sel3 1’d1 219 - - - ant_sel4 1’d1 220 - - - ant_sel5 1’d1 221 - - - ant_sel6 1’d1 222 - - - ant_sel7 1’d1 223 sig_in_func_223 0 no sig_in_func223 1’d1 224 sig_in_func_224 0 no sig_in_func224 1’d1 225 sig_in_func_225 0 no sig_in_func225 1’d1 226 sig_in_func_226 0 no sig_in_func226 1’d1 227 sig_in_func_227 0 no sig_in_func227 1’d1 235 pro_alonegpio_in0 0 no pro_alonegpio_out0 1’d1 236 pro_alonegpio_in1 0 no pro_alonegpio_out1 1’d1 Espressif Systems 46 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Appendix A – ESP32-S2 Pin Lists Signal No. Input signals Default Same input value if signal from IO unassigned* Output enable of MUX core Output signals output signals 237 pro_alonegpio_in2 0 no pro_alonegpio_out2 1’d1 238 pro_alonegpio_in3 0 no pro_alonegpio_out3 1’d1 239 pro_alonegpio_in4 0 no pro_alonegpio_out4 1’d1 240 pro_alonegpio_in5 0 no pro_alonegpio_out5 1’d1 241 pro_alonegpio_in6 0 no pro_alonegpio_out6 1’d1 242 pro_alonegpio_in7 0 no pro_alonegpio_out7 1’d1 251 - - - clk_i2s_mux 1’d1 Espressif Systems 47 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Revision History Revision History Date Version Release notes • Added chip variant ESP32-S2R2; • Updated Table 14 Reliability Qualifications; 2021.06 V1.3 • Added the link to recommended PCB land pattern in Chapter 5 Package Information; • Added Chapter 6 Learning Resources; • Other minor updates. • Added chip variant ESP32-S2FN4R2; • Added information about TWAI® Controller; • Updated operating temperature to ambient temperature in Table 1 2021.02 V1.2 ESP32-S2 Family Member Comparison; • Updated Table 12 Current Consumption Characteristics; • Updated current consumption drawn by ULP-FSM and ULP-RISC-V respectively in Table 13 Current Consumption Characteristics. 2020.09 V1.1 • Added chip variant ESP32-S2FH2�ESP32-S2FH4; • Added Chapter 1 Family Member Comparison. • Modified the second note under Table 4 Strapping Pins; • Modified the frequency of internal RC oscillator in Section 3.2.2 RTC Clock from 150 kHz to 90 kHz; • Renamed RISCV to RISC-V and ULP-RISCV to ULP-RISC-V in Section 2020.06 V1.0 3.6.2 Ultra-Low-Power Co-processor; • Modified a few figures in Table 13 Current Consumption Characteristics; • Added a note about VOH and VOL under Table 10 DC Characteristics (3.3 V, 25 °C); • Added Table 14 Reliability Qualifications; • Other small changes. Updated Section 3.6.2 Ultra-Low-Power Co-processor; Updated Section 3.7 Timers and Watchdogs; 2019.11 V0.4 Updated Table 17 GPIO_Matrix; Added documentation feedback hyperlink; Fixed formatting issues; Other small changes. 2019.08 V0.3 Overall update. Updated Figure 4 ESP32-S2 Family Power Scheme; 2019.06 V0.2 Updated Section 2.4 Strapping Pins; Updated Figure 6 Address Mapping Structure; Updated Section 4 Electrical Characteristics. 2019.04 V0.1 Espressif Systems Preliminary release. 48 Submit Documentation Feedback ESP32-S2 Family Datasheet V1.3 Disclaimer and Copyright Notice Information in this document, including URL references, is subject to change without notice. ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES TO ITS AUTHENTICITY AND ACCURACY. NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. All liability, including liability for infringement of any proprietary rights, relating to use of information in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a registered trademark of Bluetooth SIG. www.espressif.com All trade names, trademarks and registered trademarks mentioned in this document are property of their respective owners, and are hereby acknowledged. Copyright © 2021 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.