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Product Folder Sample & Buy Technical Documents Support & Community Tools & Software ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 ADC081S021 Single-Channel, 50-ksps to 200-ksps, 8-Bit A/D Converter 1 Features 3 Description • The ADC081S021 device is a low-power, singlechannel CMOS 8-bit analog-to-digital converter with a high-speed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC081S021 is fully specified over a sample rate range of 50 ksps to 200 ksps. The converter is based upon a successive-approximation register architecture with an internal track-and-hold circuit. 1 • • • • • • • • Characterized and Specified Over Multiple Sample Rates 6-Pin WSON and SOT-23 Packages Variable Power Management Single Power Supply With 2.7-V to 5.25-V Range Compatible With SPI™, QSPI™, MICROWIRE™, and DSP DNL: +0.04/–0.03 LSB (Typical) INL: +0.04/–0.03 LSB (Typical) SNR: 49.6 dB (Typical) Power Consumption: – 3.6-V Supply: 1.3 mW (Typical) – 5.25-V Supply: 7.7 mW (Typical) 2 Applications • • • Portable Systems Remote Data Acquisition Instrumentation and Control Systems The output serial data is straight binary, and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces. The ADC081S021 operates with a single supply that can range from 2.7 V to 5.25 V. Normal power consumption using a 3.6-V or 5.25-V supply is 1.3 mW and 7.7 mW, respectively. The power-down feature reduces the power consumption to as low as 2.6 µW using a 5.25-V supply. The ADC081S021 is packaged in 6-pin WSON and SOT-23 packages. Operation over the industrial temperature range of −40°C to 85°C is ensured. Device Information(1) PART NUMBER ADC081S021 PACKAGE BODY SIZE (NOM) SOT-23 (6) 2.50 mm × 2.20 mm WSON (6) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Block Diagram VIN T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 4 4 4 5 5 7 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 Functional Block Diagram ....................................... 12 8.3 Feature Description................................................. 12 8.4 Device Functional Modes........................................ 13 9 Application and Implementation ........................ 16 9.1 Application Information............................................ 16 9.2 Typical Application .................................................. 17 10 Power Supply Recommendations ..................... 19 10.1 Noise Considerations ............................................ 19 11 Layout................................................................... 19 11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 20 12 Device and Documentation Support ................. 21 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Documentation Support ........................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 21 22 22 22 22 22 13 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (November 2013) to Revision G Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 • Changed table title Pin-Compatible Alternatives by Resolution and Speed to Device Comparison Table ............................ 3 Changes from Revision E (March 2013) to Revision F • Changed sentence in the "Using the ADC081S021" section ............................................................................................... 12 Changes from Revision D (March 2013) to Revision E • 2 Page Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 5 Device Comparison Table SPECIFIED SAMPLE RATE RANGE (1) RESOLUTION (1) 50 TO 200 KSPS 200 TO 500 KSPS 500 KSPS TO 1 MSPS 12 Bits ADC081S021121S021 ADC081S021121S051 ADC081S021121S101 10 Bits ADC081S021101S021 ADC081S021101S051 ADC081S021101S101 8 Bits ADC081S021 ADC081S021081S051 ADC081S021081S101 All devices are fully pin and function compatible. 6 Pin Configuration and Functions DBV Package 6-Pin SOT-23 Top View NGF Package 6-Pin WSON Top View V   A 1 6 CS GND 2 5 SDATA     IN 3 4 SCLK V V   A 1 6 CS GND 2 5 SDATA     3 4 SCLK V IN Pin Functions PIN NO. NAME TYPE (1) DESCRIPTION 1 VA P Positive supply pin. This pin must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with a 1-µF capacitor and a 0.1-µF monolithic capacitor placed within 1 cm of the power pin. 2 GND G The ground return for the supply and signals. 3 VIN I Analog input. This signal can range from 0 V to VA. 4 SCLK I Digital clock input. This clock directly controls the conversion and readout processes. 5 SDATA O Digital data output. The output samples are clocked out of this pin on falling edges of the SCLK pin. 6 CS I Chip select. On the falling edge of CS, a conversion process begins. (1) G = Ground, I = Input, O = Output, P = Power Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 3 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT Analog supply voltage, VA –0.3 6.5 V Voltage on any analog pin to GND –0.3 VA + 0.3 V Voltage on any digital pin to GND –0.3 6.5 V ±10 mA ±20 mA 150 °C 150 °C Input current at any pin (4) Package input current (4) See (5) Power consumption at TA = 25°C Junction temperature, TJ Storage temperature, Tstg (1) (2) (3) (4) (5) –65 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are measured with respect to GND = 0 V, unless otherwise specified. If Military/Aerospace specified devices are required, please contact the TI Office/Distributors for availability and specifications. When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin must be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two. These specifications do not apply to the VA pin. The current into the VA pin is limited by the analog supply voltage specification. The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation listed above is reached only when the device is operated in a severe fault condition (that is, when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions must always be avoided. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge (1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (2) ±3500 Machine model (MM) ±300 UNIT V Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) VA Supply voltage Digital input pins voltage (regardless of supply voltage) Analog input pins voltage Clock frequency MIN MAX UNIT 2.7 5.25 V –0.3 5.25 V 0 VA 25 20000 1 Msps –40 85 °C Sample rate TA (1) 4 Operating temperature V kHz All voltages are measured with respect to GND = 0 V, unless otherwise specified. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 7.4 Thermal Information ADC081S021 THERMAL METRIC (1) DBV (SOT-23) NGF (WSON) 6 PINS 6 PINS UNIT RθJA Junction-to-ambient thermal resistance 184.5 99.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 151.2 118.3 °C/W RθJB Junction-to-board thermal resistance 29.7 68.9 °C/W ψJT Junction-to-top characterization parameter 29.8 6.6 °C/W ψJB Junction-to-board characterization parameter 29.1 69.2 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance — 14.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics Typical values correspond to TA = 25°C, and minimum and maximum limits apply over –40°C to 85°C operating temperature range (unless otherwise noted). VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 15 pF (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN (2) TYP MAX (2) UNIT STATIC CONVERTER CHARACTERISTICS Resolution with no missing codes VA = 2.7 V to 3.6 V INL Integral non-linearity VA = 4.75 V to 5.25 V ±0.03 TA = 25°C TA = –40°C to 85°C VOFF GE Differential non-linearity Offset error Gain error VA = 4.75 V to 5.25 V LSB ±0.3 ±0.3 LSB ±0.2 –0.03 0.04 ±0.2 ±0.2 VA = 2.7 V to 3.6 V LSB LSB –0.01 ±0.2 LSB VA = 4.75 V to 5.25 V 0.03 ±0.2 LSB VA = 2.7 V to 3.6 V 0.04 ±0.4 LSB 0.1 ±0.4 LSB VA = 4.75 V to 5.25 V VA = 2.7 V to 3.6 V TUE TA = –40°C to 85°C ±0.3 0.04 ±0.03 TA = 25°C Bits –0.03 VA = 2.7 V to 3.6 V DNL 8 Total unadjusted error VA = 4.75 V to 5.25 V TA = 25°C TA = –40°C to 85°C TA = 25°C TA = –40°C to 85°C –0.065 0.055 ±0.3 ±0.3 –0.06 0.03 ±0.3 ±0.3 LSB LSB DYNAMIC CONVERTER CHARACTERISTICS SINAD Signal-to-noise plus distortion ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 49 49.5 dBFS SNR Signal-to-noise ratio VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 49 49.6 dBFS THD Total harmonic distortion VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS SFDR Spurious-free dynamic range VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 65 68 dBFS ENOB Effective number of bits VA = 2.7 V to 5.25 V, fIN = 100 kHz, –0.02 dBFS 7.8 7.9 Bits Intermodulation distortion, second order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –83 dBFS Intermodulation distortion, third order terms VA = 5.25 V, fa = 103.5 kHz, fb = 113.5 kHz –82 dBFS IMD (1) (2) –77 –65 dBFS Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level). Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 5 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) Typical values correspond to TA = 25°C, and minimum and maximum limits apply over –40°C to 85°C operating temperature range (unless otherwise noted). VA = 2.7 V to 5.25 V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, and CL = 15 pF (unless otherwise noted).(1) PARAMETER FPBW –3 dB full power bandwidth MIN (2) TEST CONDITIONS TYP MAX (2) UNIT VA = 5 V 11 MHz VA = 3 V 8 MHz ANALOG INPUT CHARACTERISTICS VIN Input range IDCL DC leakage current CINA Input capacitance 0 to VA V ±1 µA Track mode 30 pF Hold mode 4 pF DIGITAL INPUT CHARACTERISTICS VIH Input high voltage VIL Input low voltage IIN Input current CIND Digital input capacitance VA = 5.25 V 2.4 VA = 3.6 V 2.1 V V VA = 5 V 0.8 V VA = 3 V 0.4 V ±0.1 ±1 µA 2 4 pF VIN = 0 V or VA DIGITAL OUTPUT CHARACTERISTICS VOH Output high voltage VOL Output low voltage ISOURCE = 200 µA VA – 0.2 VA – 0.07 ISOURCE = 1 mA ISINK = 200 µA V 0.03 ISINK = 1 mA 0.4 V ±0.1 ±10 µA 2 4 pF 0.1 IOZH, IOZL TRI-STATE leakage current COUT V VA – 0.1 TRI-STATE output capacitance Output coding V Straight (natural) binary POWER SUPPLY CHARACTERISTICS VA Supply voltage 5.25 V Supply current, normal mode (operational, CS low) VA = 5.25 V, fSAMPLE = 200 ksps 1.47 2.2 mA VA = 3.6 V, fSAMPLE = 200 ksps 0.36 0.9 mA Supply current, shutdown (CS high) fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 500 nA VA = 5.25 V, fSCLK = 4 MHz, fSAMPLE = 0 ksps 60 µA Power consumption, normal mode (operational, CS low) VA = 5.25 V 7.7 11.6 mW VA = 3.6 V 1.3 3.24 mW Power consumption, shutdown (CS high) fSCLK = 0 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 2.6 µW fSCLK = 4 MHz, VA = 5.25 V, fSAMPLE = 0 ksps 315 µW IA PD 2.7 AC ELECTRICAL CHARACTERISTICS fSCLK Clock frequency fS Sample rate tHOLD Hold time, falling edge DC SCLK duty cycle tACQ Minimum time required for acquisition See (3) 1 4 (3) 50 200 ksps 13 SCLK See fSCLK = 4 MHz 40% 50% MHz 60% 350 Quiet time tAD Aperture delay 3 ns tAJ Aperture jitter 30 ps (4) 6 50 ns tQUIET (3) See (4) ns This is the frequency range over which the electrical performance is ensured. The device is functional over a wider range which is specified under Operating Ratings. Minimum quiet time required by bus relinquish and the start of the next conversion. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 7.6 Timing Requirements The following specifications apply for VA = 2.7 V to 5.25 V, GND = 0 V, fSCLK = 1.0 MHz to 4.0 MHz, CL = 25 pF, fSAMPLE = 50 ksps to 200 ksps, and TA = –40°C to 85°C (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCS Minimum CS pulse width 10 ns tCSSU CS setup time prior to SCLK falling edge 10 ns tCSH CS hold time after SCLK falling edge tEN Delay from CS until SDATA TRI-STATE disabled (2) 1 ns VA = 2.7 V to 3.6 V 20 ns 40 ns 20 ns tACC Data access time after SCLK falling edge (3) tCL SCLK low pulse width 0.4 × tSCLK ns tCH SCLK high pulse width 0.4 × tSCLK ns tH SCLK to data valid hold time VA = 2.7 V to 3.6 V 7 ns VA = 4.75 V to 5.25 V 5 VA = 2.7 V to 3.6 V 6 VA = 4.75 V to 5.25 V 5 VA = 4.75 V to 5.25 V tDIS SCLK falling edge to SDATA high impedance (4) tPOWER-UP Power-up time from full power down (1) (2) (3) (4) TA = 25°C ns 25 ns 25 ns 1 µs Data sheet minimum and maximum specification limits are specified by design, test, or statistical analysis. Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V. Measured with the timing test circuit and defined as the time taken by the output signal to cross 1 V or 2 V. tDIS is derived from the time taken by the outputs to change by 0.5 V with the timing test circuit. The measured number is then adjusted to remove the effects of charging or discharging the output capacitance. This means that tDIS is the true bus relinquish time, independent of the bus loading. IOL 200 PA To Output Pin 1.6 V CL 25 pF IOH 200 PA Figure 1. Timing Test Circuit Hold Track | CS tCS tSU tACQ tCL 1 2 3 | SCLK 4 5 14 15 16 17 Z1 Z0 DB7 3 leading zero bits 18 19 20 tQUIET tCH | Z2 13 tACC tEN SDATA 12 tH tDIS TRI-STATE Zero Zero 8 data bits Zero Zero 4 trailing zeroes Figure 2. Serial Timing Diagram Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 7 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com SCLK 1 tCSH 2 tCSSU CS Figure 3. SCLK and CS Timing Parameters 8 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 7.7 Typical Characteristics TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz (unless otherwise noted) Figure 4. DNL fSCLK = 1 MHz Figure 5. INL fSCLK = 1 MHz Figure 6. DNL fSCLK = 4 MHz Figure 7. INL fSCLK = 4 MHz Figure 8. DNL vs Clock Frequency Figure 9. INL vs Clock Frequency Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 9 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Typical Characteristics (continued) TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz (unless otherwise noted) 10 Figure 10. Total Unadjusted Error vs Clock Frequency VA = 3 V or 5 V Figure 11. SNR vs Clock Frequency Figure 12. SINAD vs Clock Frequency Figure 13. SFDR vs Clock Frequency Figure 14. THD vs Clock Frequency Figure 15. Spectral Response, VA = 5 V fSCLK = 1 MHz Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 Typical Characteristics (continued) TA = 25°C, fSAMPLE = 50 ksps to 200 ksps, fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz (unless otherwise noted) Figure 16. Spectral Response, VA = 5 V fSCLK = 4 MHz Figure 17. Power Consumption vs Throughput fSCLK = 4 MHz Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 11 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com 8 Detailed Description 8.1 Overview The ADC081S021 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC081S021 in both track and hold modes are shown in Figure 19 and Figure 18, respectively. In Figure 19, the device is in track mode: switch SW1 connects the sampling capacitor to the input, and SW2 balances the comparator inputs. The device is in this state until CS is brought low, at which point the device moves to hold mode. 8.2 Functional Block Diagram VIN T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA Copyright © 2016, Texas Instruments Incorporated 8.3 Feature Description The serial interface timing diagram for the ADC is shown in Timing Requirements. CS is chip select, which initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream. Basic operation of the ADC begins with CS going low, which initiates a conversion process and data transfer. Subsequent rising and falling edges of SCLK are labelled with reference to the falling edge of CS; for example, the third falling edge of SCLK shall refer to the third falling edge of SCLK after CS goes low. At the fall of CS, the SDATA pin comes out of TRI-STATE and the converter moves from track mode to hold mode. The input signal is sampled and held for conversion on the falling edge of CS. The converter moves from hold mode to track mode on the 13th rising edge of SCLK (see Timing Requirements). It is at this point that the interval for the TACQ specification begins. At least 350 ns must pass between the 13th rising edge of SCLK and the next falling edge of CS. The SDATA pin is placed back into TRI-STATE after the 16th falling edge of SCLK, or at the rising edge of CS, whichever occurs first. After a conversion is completed, the quiet time (tQUIET) must be satisfied before bringing CS low again to begin another conversion. Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent rising edges of SCLK. The ADC produces three leading zero bits on SDATA, followed by eight data bits, most significant first. After the data bits, the ADC clocks out four trailing zeros. If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK. 8.3.1 Determining Throughput Throughput depends on the frequency of SCLK and how much time is allowed to elapse between the end of one conversion and the start of another. At the maximum specified SCLK frequency, the maximum ensured throughput is obtained by using a 20 SCLK frame. As shown in Timing Requirements, the minimum allowed time between CS falling edges is determined by: 1. 12.5 SCLKs for Hold mode. 2. The larger of two quantities: either the minimum required time for Track mode (tACQ) or 2.5 SCLKs to finish reading the result. 12 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 Feature Description (continued) 3. 0, 1/2, or 1 SCLK padding to ensure an even number of SCLK cycles so there is a falling SCLK edge when CS next falls. For example, at the fastest rate for this family of parts, SCLK is 20 MHz and 2.5 SCLKs are 125 ns, so the minimum time between CS falling edges is calculated by Equation 1. 12.5 × 50 ns + 350 ns + 0.5 × 50 ns = 1000 ns (1) (12.5 SCLKs + tACQ + 1/2 SCLK) which corresponds to a maximum throughput of 1 MSPS. At the slowest rate for this family, SCLK is 1 MHz. Using a 20 cycle conversion frame as shown in Timing Requirements yields a 20-μs time between CS falling edges for a throughput of 50 KSPS. It is possible, however, to use fewer than 20 clock cycles provided the timing parameters are met. With a 1-MHz SCLK, there are 2500 ns in 2.5 SCLK cycles, which is greater than tACQ. After the last data bit has come out, the clock needs one full cycle to return to a falling edge. Thus the total time between falling edges of CS is 12.5 × 1 μs + 2.5 × 1 μs + 1 × 1 μs = 16 μs which is a throughput of 62.5 KSPS. 8.4 Device Functional Modes Figure 18 shows the device in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the chargeredistribution DAC to add or subtract fixed amounts of charge from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The device moves from hold mode to track mode (Figure 19) on the 13th rising edge of SCLK. CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 18. Hold Mode CHARGE REDISTRIBUTION DAC VIN SAMPLING CAPACITOR SW1 SW2 GND + - CONTROL LOGIC VA 2 Figure 19. Track Mode 8.4.1 Transfer Function The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC is VA/256. The ideal transfer characteristic is shown in Figure 20. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA/512. Other code transitions occur at steps of one LSB. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 13 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Device Functional Modes (continued) 111...111 111...000 | | ADC CODE 111...110 1 LSB = VA/256 011...111 000...010 | 000...001 000...000 0V 1 LSB ANALOG INPUT +VA-1 LSB Figure 20. Ideal Transfer Characteristic 8.4.2 Modes of Operation The ADC has two possible modes of operation: normal mode and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device enters shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or stays in normal mode if CS remains low. Once in shutdown mode, the device stays there until CS is brought low again. By varying the ratio of time spent in the normal and shutdown modes, a system may trade off throughput for power consumption, with a sample rate as low as zero. 8.4.2.1 Normal Mode The fastest possible throughput is obtained by leaving the ADC in normal mode at all times, so there are no power-up delays. To keep the device in normal mode continuously, CS must be kept low until after the 10th falling edge of SCLK after the start of a conversion (remember that a conversion is initiated by bringing CS low). If CS is brought high after the 10th falling edge, but before the 16th falling edge, the device remains in normal mode, but the current conversion is aborted and the SDATA returns to TRI-STATE (truncating the output word). Sixteen SCLK cycles are required to read all of a conversion word from the device. After sixteen SCLK cycles have elapsed, CS may be idled either high or low until the next conversion. If CS is idled low, it must be brought high again before the start of the next conversion, which begins when CS is again brought low. After sixteen SCLK cycles, SDATA returns to TRI-STATE. Another conversion may be started, after tQUIET has elapsed, by bringing CS low again. 8.4.2.2 Shutdown Mode Shutdown mode is appropriate for applications that either do not sample continuously, or it is acceptable to trade throughput for power consumption. When the ADC is in shutdown mode, all of the analog circuitry is turned off. To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 21. Once CS has been brought high in this manner, the device enters shutdown mode, the current conversion is aborted and SDATA enters TRI-STATE. If CS is brought high before the second falling edge of SCLK, the device does not change mode; this is to avoid accidentally changing mode as a result of noise on the CS line. 14 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 Device Functional Modes (continued) Figure 21. Entering Shutdown Mode Figure 22. Entering Normal Mode To exit shutdown mode, bring CS back low. Upon bringing CS low, the ADC begins powering up (power-up time is specified in Timing Requirements). This microsecond of power-up delay results in the first conversion result being unusable. The second conversion performed after power up, however, is valid, as shown in Figure 22. If CS is brought back high before the 10th falling edge of SCLK, the device returns to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC is fully powered up after 16 SCLK cycles. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 15 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information A typical application of the ADC is shown in Typical Application. Power is provided in this example by the Texas Instruments LP2950 low-dropout voltage regulator (see LP295x-N Series of Adjustable Micropower Voltage Regulators, SNVS764), available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network placed close to the ADC. Because the reference for the ADC is the supply voltage, any noise on the supply degrades device noise performance. To keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC supply pin. Because of the ADC's low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. The three-wire interface is shown connected to a microprocessor or DSP. 9.1.1 Analog Inputs An equivalent circuit for the ADC's input is shown in Figure 23. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time must the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes begin to conduct, which could result in erratic operation. For this reason, the ESD diodes must not be used to clamp the input signal. The capacitor C1 in Figure 23 has a typical value of 4 pF, and is mainly the package pin capacitance. Resistor R1 is the ON resistance of the track or hold switch, and is typically 500 Ω. Capacitor C2 is the ADC sampling capacitor and is typically 26 pF. The ADC delivers best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. This is especially important when using the ADC to sample AC signals. Also important when sampling dynamic signals is an anti-aliasing filter. VA D1 R1 C2 26 pF VIN C1 4 pF D2 Conversion Phase - Switch Open Track Phase - Switch Closed Copyright © 2016, Texas Instruments Incorporated Figure 23. Equivalent Input Circuit 9.1.2 Digital Inputs and Outputs The ADC digital inputs (SCLK and CS) are not limited by the same maximum ratings as the analog inputs. The digital input pins are instead limited to 5.25 V with respect to GND, regardless of VA, the supply voltage. This allows the ADC to be interfaced with a wide range of logic levels, independent of the supply voltage. 16 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 9.2 Typical Application The ADC081S021 is a low-power, single-channel CMOS 8-bit analog-to-digital converter that uses the supply voltage as a reference, enabling the devices to operate with a full-scale input range of 0 to VA. An example low power application with the LMT87 which is a wide range ±0.3°C (typical) accurate temperature sensor is shown in Figure 24. LP2950 1 PF 0.1 PF 5V 1 PF 0.1 PF VA SCLK VIN ADC081S021 CS SDATA MICROPROCESSOR DSP GND Copyright © 2016, Texas Instruments Incorporated Figure 24. Typical Application Circuit 9.2.1 Design Requirements A successful ADC081S021 and LMT87 design is contrained by the following factors: • VIN range needs to be 0 V to VA where VA can range from 2.7 V to 5.25 V • Output level of the LMT87 can range from 538 mV to 3277 mV (which satisfies the VIN condition) 9.2.2 Detailed Design Procedure Designing for an accurate measurement requires careful attention to timing requirements for the ADC081S021. Because the ADC081S021 uses the supply voltage as a reference, it is important to make sure that the supply voltage is settled to its final level before exiting the shutdown mode and beginning a conversion. After the supply voltage is settled, the CS is brought to a low level (ideally 0 V) to start a conversion. It is also important to ensure that any noise on the power supply must be less than ½ LSB in amplitude. The supply voltage must be regarded as a precise voltage reference. After the CS is brought low, the user needs to wait for one complete conversion cycle (approximately 1 μs) for meaningful data. The dummy conversion cycle can be considered the start-up time of the ADC081S021. The ADC081S021 digital output can then be correlated to the LMT87 output level to get an accurate temperature reading. At VDD = 2.7 V, 1 LSB of ADC081S021 is 10.54 mV. This information can be used to calculate the output level of LMT87 which can then be correlated to temperature. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 17 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Typical Application (continued) 9.2.3 Application Curves 3500 3000 111...110 1500 1000 111...000 | ADC CODE 2000 | VOUT Level (mV) 111...111 2500 1 LSB = VA/256 011...111 500 000...010 ±65 ±15 35 85 135 Temperature (ƒC) 185 C001 000...001 | 0 000...000 0V Figure 25. LMT87 Output Voltage vs Temperature 18 1 LSB ANALOG INPUT +VA-1 LSB Figure 26. Ideal Transfer Characteristic Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 10 Power Supply Recommendations The ADC takes time to power up, either after first applying VA, or after returning to normal mode from shutdown mode. This corresponds to one dummy conversion for any SCLK frequency within the specifications in this document. After this first dummy conversion, the ADC performs conversions properly. NOTE The tQUIET time must still be included between the first dummy conversion and the second valid conversion. When the VA supply is first applied, the ADC may power up in either of the two modes: normal or shutdown. As such, one dummy conversion must be performed after start-up, as described in the previous paragraph. The part may then be placed into either normal mode or the shutdown mode, as described in Normal Mode and Shutdown Mode. When the ADC is operated continuously in normal mode, the maximum ensured throughput is fSCLK / 20 at the maximum specified fSCLK. Throughput may be traded for power consumption by running fSCLK at its maximum specified rate and performing fewer conversions per unit time, raising the ADC CS line after the 10th and before the 15th fall of SCLK of each conversion. A plot of typical power consumption versus throughput is shown in Typical Characteristics. To calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. The curve of power consumption vs throughput (Figure 17) is essentially linear. This is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 10.1 Noise Considerations The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance causes voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, discharging the output capacitance when the digital output goes from a logic high to a logic low dumps current into the die substrate, which is resistive. Load discharge currents cause ground bounce noise in the substrate that degrades noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. To keep noise out of the power supply, keep the output load capacitance as small as practical. It is good practice to use a 100-Ω series resistor at the ADC output, placed as close to the ADC output pin as practical. This limits the charge and discharge current of the output capacitance and maintain noise performance. 11 Layout 11.1 Layout Guidelines Capacitive coupling between noisy digital circuitry and sensitive analog circuitry can lead to poor performance. TI strongly recommends keeping the analog and digital circuitry separated from each other and the clock line as short as possible. Digital circuits create substantial supply and ground current transients. This digital noise could have significant impact upon system noise performance. To avoid performance degradation due to supply noise, do not use the same supply for the ADC081S021 that is used for digital logic. Generally, analog and digital lines must cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line must also be treated as a transmission line and be properly terminated. The analog input must be isolated from noisy signal lines to avoid coupling of spurious signals into the input. Any external component (that is, a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground must be connected to a very clean point in the ground plane. Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 19 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Layout Guidelines (continued) TI recommends the use of a single, uniform ground plane and the use of split power planes. The power planes must be placed within the same board layer. All analog circuitry (input amplifiers, filters, reference components, and so on) must be placed over the analog power plane. All digital circuitry and I/O lines must be placed over the digital power plane. In addition, all components in the reference circuitry and the input signal chain that are connected to ground must be connected together with short traces and enter the analog ground plane at a single, quiet point. 11.2 Layout Example Figure 27. DBV Package Layout Figure 28. NGF Package Layout 20 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 ADC081S021 www.ti.com SNAS308G – APRIL 2005 – REVISED MAY 2016 12 Device and Documentation Support 12.1 Device Support 12.1.1 Device Nomenclature ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS when the signal is sampled and the part moves from track to hold. The start of the time interval that contains TACQ is the 13th rising edge of SCLK of the previous conversion when the part moves from hold to track. The user must ensure that the time between the 13th rising edge of SCLK and the falling edge of the next CS is not less than TACQ to meet performance specifications. APERTURE DELAY is the time after the falling edge of CS when the input signal is acquired or held for conversion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. Aperture jitter manifests itself as noise in the output. CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC081S021 to convert the input voltage to a digital word. This is from the falling edge of CS when the input signal is sampled to the 16th falling edge of SCLK when the SDATA output goes into TRI-STATE. DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK. EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD − 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC081S021 of this (ENOB) number of bits. FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF − 1 LSB), after adjusting for offset error. INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC081S021 input at the same time. It is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. IMD is usually expressed in dB. MISSING CODES are those output codes that never appear at the ADC081S021 outputs. The ADC081S021 is ensured not to have any missing codes. OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (that is, GND + 1 LSB). SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or DC SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the RMS value of the input signal to the RMS value of all of the other spectral components below half the clock frequency, including harmonics but excluding DC Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 21 ADC081S021 SNAS308G – APRIL 2005 – REVISED MAY 2016 www.ti.com Device Support (continued) SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is any signal present in the output spectrum that is not present at the input and may or may not be a harmonic. TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the RMS total of the first five harmonic components at the output to the RMS level of the input signal frequency as seen at the THD = 20 ‡ log10 A f 22 + + A f 62 A f 12 output. THD is calculated as where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies. THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the acquisition time plus the conversion time. TOTAL UNADJUSTED ERROR is the worst deviation found from the ideal transfer function. As such, it is a comprehensive specification which includes full scale error, linearity error, and offset error. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: LP295x-N Series of Adjustable Micropower Voltage Regulators, SNVS764 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 12.4 Trademarks SPI, QSPI, MICROWIRE, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 12.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2005–2016, Texas Instruments Incorporated Product Folder Links: ADC081S021 PACKAGE OPTION ADDENDUM www.ti.com 30-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) ADC081S021CIMF NRND SOT-23 DBV 6 1000 Non-RoHS & Green Call TI Level-1-260C-UNLIM -40 to 85 X09C ADC081S021CIMF/NOPB ACTIVE SOT-23 DBV 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 X09C ADC081S021CIMFX/NOPB ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 X09C ADC081S021CISD/NOPB ACTIVE WSON NGF 6 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 X9C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of