nRF24LE1-F16Q32-R

nRF24LE1 Ultra-low Power Wireless System On-Chip Solution Product Specification v1.6 Key Features • • • • • • • • • • • • • • nRF24L01+ 2.4 GHz transceiver (250 kbps, 1 Mbps and 2 Mbps air data rates) Fast microcontroller (8051 compatible) 16 kB program memory (on-chip Flash) 1 kB data memory (on-chip RAM) 1 kB NV data memory 512 bytes NV data memory (extended endurance) AES encryption HW accelerator 16-32bit multiplication/division co-processor (MDU) 6-12 bit ADC High flexibility IOs Serves a set of power modes from ultra low power to a power efficient active mode Several versions in various QFN packages: X 4×4mm QFN24 X 5×5mm QFN32 X 7×7mm QFN48 Support for HW debugger HW support for firmware upgrade Applications • • • • • • Computer peripherals X Mouse X Keyboard X Remote control X Gaming Advanced remote controls X Audio/Video X Entertainment centers X Home appliances Goods tracking and monitoring: X Active RFID X Sensor networks Security systems X Payment X Alarm X Access control Health, wellness and sports X Watches X Mini computers X Sensors Remote control toys All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. August 2010 nRF24LE1 Product Specification Liability disclaimer Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications are not implied. Exposure to limiting values for extended periods may affect device reliability. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Data sheet status Objective product specification This product specification contains target specifications for product development. Preliminary product specification This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. Product specification This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Contact details For your nearest dealer, please see www.nordicsemi.com Main office: Otto Nielsens veg 12 7004 Trondheim Norway Phone: +47 72 89 89 00 Fax: +47 72 89 89 89 ww.nordicsemi.no Revision 1.6 2 of 196 nRF24LE1 Product Specification Revision History Date March 2009 September 2009 Version 1.2 1.3 April 2010 1.4 July 2010 1.5 August 2010 1.6 Description Updated Figure 33., Figure 34. and Table 35.. Added Table 93. Updated BOM, Table 28., Table 29.,Table 34.,Table 46., Table 53., Table 61.,Table 87., Table 101., Table 113., Table 115., sections 6.3.4.1, 9.1, 9.3 13.3.3, 29.1.2, 29.2.2, 29.3.2 and 30.1. Simplified way of writing binary numbers and denoting register bits. Updated Figure 9., Figure 10., Figure 30., Note: on page 87, Figure 46., Figure 51. and Figure 52. Updated section 2.1, section 12.3 , section 13.3.1, Table 14. , Table 15., Table 27.,Table 58., Table 111. ,Table 114. and Table 115. Updated BOM information in chapter 29. Updated 6.3.5.1 on page 77, Table 57. on page 109, Table 58. on page 111, Table 88. on page 150, and Human Body Model Class in chapter 24 on page 176. Added RoHS statement and updated Table 88. on page 150. RoHS statement Nordic Semiconductor’s products meet the requirements of Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of Hazardous Substances (RoHS). Complete hazardous substance reports as well as material composition reports for all active Nordic products can be found on our web site www.nordicsemi.com. Revision 1.6 3 of 196 nRF24LE1 Product Specification Contents 1 Introduction .............................................................................................. 10 1.1 Prerequisites ....................................................................................... 10 1.2 Writing conventions ............................................................................. 10 2 Product overview ..................................................................................... 11 2.1 Features .............................................................................................. 11 2.2 Block diagram ..................................................................................... 13 2.3 Pin assignments .................................................................................. 14 2.3.1 24-pin 4x4 QFN-package variant .................................................... 14 2.3.2 32-pin 5x5 QFN-package variant .................................................... 14 2.3.3 48-pin 7x7 QFN-package variant .................................................... 15 2.4 Pin functions ........................................................................................ 15 3 RF transceiver .......................................................................................... 16 3.1 Features .............................................................................................. 16 3.2 Block diagram ..................................................................................... 17 3.3 Functional description ......................................................................... 17 3.3.1 Operational Modes ......................................................................... 17 3.3.2 Air data rate .................................................................................... 21 3.3.3 RF channel frequency .................................................................... 21 3.3.4 Received Power Detector measurements ...................................... 21 3.3.5 PA control ....................................................................................... 21 3.3.6 RX/TX control ................................................................................. 22 3.4 Enhanced ShockBurst™ ..................................................................... 22 3.4.1 Features ......................................................................................... 22 3.4.2 Enhanced ShockBurst™ overview ................................................. 22 3.4.3 Enhanced Shockburst™ packet format .......................................... 23 3.4.4 Automatic packet assembly ............................................................ 26 3.4.5 Automatic packet disassembly ....................................................... 27 3.4.6 Automatic packet transaction handling ........................................... 28 3.4.7 Enhanced ShockBurst flowcharts ................................................... 30 3.4.8 MultiCeiver™ .................................................................................. 33 3.4.9 Enhanced ShockBurst™ timing ...................................................... 35 3.4.10 Enhanced ShockBurst™ transaction diagram ................................ 38 3.4.11 Compatibility with ShockBurst™ ..................................................... 42 3.5 Data and control interface ................................................................... 43 3.5.1 SFR registers .................................................................................. 43 3.5.2 SPI operation .................................................................................. 44 3.5.3 Data FIFO ....................................................................................... 46 3.5.4 Interrupt .......................................................................................... 47 3.6 Register map ....................................................................................... 48 3.6.1 Register map table ......................................................................... 48 4 MCU ........................................................................................................... 54 4.1 Block diagram ..................................................................................... 55 4.2 Features .............................................................................................. 55 4.3 Functional description ......................................................................... 56 Revision 1.6 4 of 196 nRF24LE1 Product Specification 4.3.1 Arithmetic Logic Unit (ALU) ............................................................ 56 4.3.2 Instruction set summary ................................................................. 56 4.3.3 Opcode map ................................................................................... 60 5 Memory and I/O organization .................................................................. 62 5.1 PDATA memory addressing ................................................................ 63 5.2 MCU Special Function Registers ........................................................ 63 5.2.1 Accumulator - ACC ......................................................................... 63 5.2.2 B Register – B ................................................................................ 63 5.2.3 Program Status Word Register - PSW ........................................... 64 5.2.4 Stack Pointer – SP ......................................................................... 64 5.2.5 Data Pointer – DPH, DPL ............................................................... 64 5.2.6 Data Pointer 1 – DPH1, DPL1 ........................................................ 65 5.2.7 Data Pointer Select Register – DPS ............................................... 65 5.2.8 PCON register ................................................................................ 65 5.2.9 Special Function Register Map ....................................................... 66 5.2.10 Special Function Registers reset values ........................................ 67 6 Flash memory ........................................................................................... 70 6.1 Features .............................................................................................. 70 6.2 Block diagram ..................................................................................... 70 6.3 Functional description ......................................................................... 71 6.3.1 Using the NV data memory ............................................................ 71 6.3.2 Flash memory configuration ........................................................... 71 6.3.3 Brown-out ....................................................................................... 76 6.3.4 Flash programming from the MCU ................................................. 77 6.3.5 Flash programming through SPI ..................................................... 77 6.3.6 Hardware support for firmware upgrade ......................................... 81 7 Random Access memory (RAM) ............................................................. 84 7.1 SRAM configuration ............................................................................ 84 8 Timers/counters ....................................................................................... 86 8.1 Features .............................................................................................. 86 8.2 Block diagram ..................................................................................... 86 8.3 Functional description ......................................................................... 87 8.3.1 Timer 0 and Timer 1 ....................................................................... 87 8.3.2 Timer 2 ........................................................................................... 89 8.4 SFR registers ...................................................................................... 91 8.4.1 Timer/Counter control register – TCON .......................................... 91 8.4.2 Timer mode register - TMOD .......................................................... 92 8.4.3 Timer 0 – TH0, TL0 ........................................................................ 92 8.4.4 Timer 1 – TH1, TL1 ........................................................................ 92 8.4.5 Timer 2 control register – T2CON .................................................. 93 8.4.6 Timer 2 – TH2, TL2 ........................................................................ 93 8.4.7 Compare/Capture enable register – CCEN .................................... 94 8.4.8 Capture registers – CC1, CC2, CC3 .............................................. 94 8.4.9 Compare/Reload/Capture register – CRCH, CRCL ....................... 95 8.5 Real Time Clock - RTC ....................................................................... 95 8.5.1 Features ......................................................................................... 95 Revision 1.6 5 of 196 nRF24LE1 Product Specification 8.5.2 Functional description of SFR registers .......................................... 95 9 Interrupts .................................................................................................. 99 9.1 Features .............................................................................................. 99 9.2 Block diagram ..................................................................................... 99 9.3 Functional description .......................................................................... 100 9.4 SFR registers ....................................................................................... 100 9.4.1 Interrupt Enable 0 Register – IEN0.................................................. 101 9.4.2 Interrupt Enable 1 Register – IEN1 ................................................. 101 9.4.3 Interrupt Priority Registers – IP0, IP1 .............................................. 101 9.4.4 Interrupt Request Control Registers – IRCON ................................ 102 10 Watchdog................................................................................................... 103 10.1 Features ............................................................................................... 103 10.2 Block diagram ...................................................................................... 103 10.3 Functional description .......................................................................... 103 11 Power and clock management................................................................. 105 11.1 Block diagram ...................................................................................... 105 11.2 Modes of operation .............................................................................. 105 11.3 Functional description .......................................................................... 110 11.3.1 Clock control.................................................................................... 110 11.3.2 Power down control – PWRDWN .................................................... 113 11.3.3 Operational mode control - OPMCON ............................................. 114 11.3.4 Reset result – RSTREAS ................................................................ 114 11.3.5 Wakeup configuration register – WUCON ....................................... 115 11.3.6 Pin wakeup configuration ................................................................ 115 12 Power supply supervisor ......................................................................... 117 12.1 Features ............................................................................................... 117 12.2 Block diagram ...................................................................................... 117 12.3 Functional description .......................................................................... 117 12.3.1 Power-on reset ................................................................................ 117 12.3.2 Brown-out reset ............................................................................... 118 12.3.3 Power-fail comparator ..................................................................... 118 12.4 SFR registers ....................................................................................... 119 13 On-chip oscillators.................................................................................... 120 13.1 Features ............................................................................................... 120 13.2 Block diagrams..................................................................................... 120 13.3 Functional description .......................................................................... 121 13.3.1 16 MHz crystal oscillator.................................................................. 121 13.3.2 16 MHz RC oscillator ....................................................................... 122 13.3.3 External 16 MHz clock ..................................................................... 122 13.3.4 32.768 kHz crystal oscillator ............................................................ 122 13.3.5 32.768 kHz RC oscillator ................................................................. 123 13.3.6 Synthesized 32.768 kHz clock......................................................... 123 13.3.7 External 32.768 kHz clock ............................................................... 123 14 MDU – Multiply Divide Unit....................................................................... 124 14.1 Features ............................................................................................... 124 14.2 Block diagram ...................................................................................... 124 Revision 1.6 6 of 196 nRF24LE1 Product Specification 14.3 Functional description .......................................................................... 14.4 SFR registers ....................................................................................... 14.4.1 Loading the MDx registers............................................................... 14.4.2 Executing calculation ....................................................................... 14.4.3 Reading the result from the MDx registers ...................................... 14.4.4 Normalizing...................................................................................... 14.4.5 Shifting............................................................................................. 14.4.6 The mdef flag................................................................................... 14.4.7 The mdov flag .................................................................................. 15 Encryption/decryption accelerator .......................................................... 15.1 Features ............................................................................................... 15.2 Block diagram ...................................................................................... 15.3 Functional description .......................................................................... 16 Random number generator ...................................................................... 16.1 Features ............................................................................................... 16.2 Block diagram ...................................................................................... 16.3 Functional description .......................................................................... 16.4 SFR registers ....................................................................................... 17 General purpose IO port and pin assignments ...................................... 17.1 Block diagram ...................................................................................... 17.2 Functional description .......................................................................... 17.2.1 General purpose IO pin functionality ............................................... 17.2.2 PortCrossbar functionality ............................................................... 17.3 IO pin maps.......................................................................................... 17.3.1 Pin assignments in package 24 pin 4x4 mm ................................... 17.3.2 Pin assignments in package 32 pin 5x5 mm ................................... 17.3.3 Pin assignments in package 48 pin 7x7 mm ................................... 17.3.4 Programmable registers .................................................................. 18 SPI .............................................................................................................. 18.1 Features ............................................................................................... 18.2 Block diagram ...................................................................................... 18.3 Functional description .......................................................................... 18.3.1 SPI master ....................................................................................... 18.3.2 SPI slave ......................................................................................... 18.3.3 Slave SPI timing .............................................................................. 19 Serial port (UART) ..................................................................................... 19.1 Features ............................................................................................... 19.2 Block diagram ...................................................................................... 19.3 Functional description .......................................................................... 19.3.1 Serial port 0 control register – S0CON ............................................ 19.3.2 Serial port 0 data buffer – S0BUF ................................................... 19.3.3 Serial port 0 reload register – S0RELH, S0RELL ............................ 19.3.4 Serial port 0 baud rate select register - ADCON ............................. 20 2-Wire ......................................................................................................... 20.1 Features ............................................................................................... 20.2 Functional description .......................................................................... Revision 1.6 7 of 196 124 124 125 126 126 126 126 126 127 128 128 128 128 130 130 130 130 131 132 132 133 133 134 135 136 137 138 140 147 147 147 148 148 150 151 155 155 155 155 156 157 157 158 159 159 159 nRF24LE1 Product Specification 20.2.1 Recommended use ......................................................................... 20.2.2 Master transmitter/receiver .............................................................. 20.2.3 Slave transmitter/receiver ................................................................ 20.3 SFR registers ....................................................................................... 21 ADC ............................................................................................................ 21.1 Features ............................................................................................... 21.2 Block diagram ...................................................................................... 21.3 Functional description .......................................................................... 21.3.1 Activation ......................................................................................... 21.3.2 Input selection ................................................................................. 21.3.3 Reference selection ......................................................................... 21.3.4 Resolution........................................................................................ 21.3.5 Conversion modes........................................................................... 21.3.6 Output data coding .......................................................................... 21.3.7 Driving the analog input ................................................................... 21.3.8 SFR registers................................................................................... 22 Analog comparator ................................................................................... 22.1 Features ............................................................................................... 22.2 Block diagram ...................................................................................... 22.3 Functional description .......................................................................... 22.3.1 Activation ......................................................................................... 22.3.2 Input selection ................................................................................. 22.3.3 Reference selection ......................................................................... 22.3.4 Output polarity ................................................................................. 22.3.5 Input voltage range.......................................................................... 22.3.6 Configuration examples................................................................... 22.3.7 Driving the analog input ................................................................... 22.3.8 SFR registers................................................................................... 23 PWM ........................................................................................................... 23.1 Features ............................................................................................... 23.2 Block diagram ...................................................................................... 23.3 Functional description .......................................................................... 24 Absolute maximum ratings ...................................................................... 25 Operating condition .................................................................................. 26 Electrical specifications ........................................................................... 26.1 Power consumption.............................................................................. 27 HW debugger support .............................................................................. 27.1 Features ............................................................................................... 27.2 Functional description .......................................................................... 28 Mechanical specifications........................................................................ 29 Reference circuits ..................................................................................... 29.1 Q48 application example...................................................................... 29.1.1 Schematic ........................................................................................ 29.1.2 Layout .............................................................................................. 29.1.3 Bill Of Materials (BOM) .................................................................... 29.2 Q32 application example...................................................................... Revision 1.6 8 of 196 159 159 160 162 165 165 165 165 165 166 166 166 166 167 168 169 171 171 171 171 171 171 172 172 172 172 172 173 174 174 174 174 176 177 178 183 185 185 185 186 188 188 188 189 189 190 nRF24LE1 Product Specification 29.2.1 Schematic ........................................................................................ 29.2.2 Layout .............................................................................................. 29.2.3 Bill Of Materials (BOM) .................................................................... 29.3 Q24 application example...................................................................... 29.3.1 Schematic ........................................................................................ 29.3.2 Layout .............................................................................................. 29.3.3 Bill Of Materials (BOM) .................................................................... 30 Ordering information ................................................................................ 30.1 Package marking ................................................................................. 30.1.1 Abbreviations ................................................................................... 30.2 Product options .................................................................................... 30.2.1 RF silicon ......................................................................................... 30.2.2 Development tools ........................................................................... 31 Glossary..................................................................................................... Revision 1.6 9 of 196 190 191 191 192 192 193 193 194 194 194 195 195 195 196 nRF24LE1 Product Specification 1 Introduction The nRF24LE1 is a member of the low-cost, high-performance family of intelligent 2.4 GHz RF transceivers with embedded microcontrollers. The nRF24LE1 is optimized to provide a single chip solution for ULP wireless applications. The combination of processing power, memory, low power oscillators, real-time counter, AES encryption accelerator, random generator and a range of power saving modes provides an ideal platform for implementation of RF protocols. Benefits of using nRF24LE1 include tighter protocol timing, security, lower power consumption and improved co-existence performance. For the application layer the nRF24LE1 offers a rich set of peripherals including: SPI, 2-wire, UART, 6 to 12 bit ADC, PWM and an ultra low power analog comparator for voltage level system wake-up. The nRF24LE1 comes in three different package variants: • • • An ultra compact 4×4mm 24 pin QFN (7 generic I/O pins) A compact 5×5mm 32 pin QFN (15 generic I/O pins) A 7×7mm 48 pin QFN (31 generic I/O pins) The 4×4mm 24 pin QFN is ideal for low I/O count applications where small size is key. Examples include wearable sports sensors and watches. The 5×5mm 32 pin QFN is ideal for medium I/O count applications such as wireless mouse, remote controls and toys. The 7×7mm 48 pin QFN is designed for high I/O count products like wireless keyboards. 1.1 Prerequisites In order to fully understand the product specification, a good knowledge of electronics and software engineering is necessary. 1.2 Writing conventions This product specification follows a set of typographic rules that makes the document consistent and easy to read. The following writing conventions are used: • Commands, bit state conditions, and register names are written in Courier. • Pin names and pin signal conditions are written in Courier bold. • Cross references are underlined and highlighted in blue. Revision 1.6 10 of 196 nRF24LE1 Product Specification 2 Product overview 2.1 Features Features of the nRF24LE1 include: • • • • • Fast 8-bit microcontroller: X Intel MCS 51 compliant instruction set X Reduced instruction cycle time, up to 12 times compared to legacy 8051 X 32 bit multiplication – division unit Memory: X Program memory: 16 kB of Flash memory with security features (up to 1k erase/ write cycles) X Data memory: 1 kB of on-chip RAM memory X Non-volatile data memory: 1 kB X Non-volatile data memory extended endurance: 512 bytes (up to 20k erase/ write cycles) A number of on-chip hardware resources are available through programmable multi-purpose input/ output pins (7-31 pins dependent on package variant): X GPIO X SPI master X SPI slave X 2-Wire master/ slave X Full duplex serial port X PWM X ADC X Analog comparator X External interrupts X Timer inputs X 32.768 kHz crystal oscillator X Debug interface High performance 2.4 GHz RF-transceiver X True single chip GFSK transceiver X Enhanced ShockBurst™ link layer support in HW: X Packet assembly/disassembly X Address and CRC computation X Auto ACK and retransmit X On the air data rate 250 kbps, 1 Mbps or 2 Mbps X Digital interface (SPI) speed 0-8 Mbps X 125 RF channel option, with 79 (2.402 GHz-2.480 GHz) channels within 2.400 - 2.4835 GHz X Short switching time enable frequency hopping X Fully RF compatible with nRF24LXX X RF compatible with nRF2401A, nRF2402, nRF24E1, nRF24E2 in 250 kbps and 1 Mbps mode A/D converter: X 6, 8, 10 or 12 bit resolution X 14 input channels X Single ended or differential input X Full-scale range set by internal reference, external reference or VDD X Single step mode with conversion time down to 3 µs X Continuous mode with 2, 4, 8 or 16 kbps sampling rate X Low current consumption; only 0.1mA at 2 ksps X Mode for measuring supply voltage Revision 1.6 11 of 196 nRF24LE1 Product Specification • • • • • • • • • Analog comparator: X Used as wakeup source X Low current consumption (0.75µA typical) X Differential or single-ended input X Single-ended threshold programmable to 25%, 50%, 75% or 100% of VDD or an arbitrary reference voltage from pin X 14-channel input multiplexer X Rail-to-rail input voltage range X Programmable output polarity Encryption/decryption accelerator X Utilize time and power effective AES firmware Random number generator: X Non-deterministic architecture based on thermal noise X No seed value required X Non-repeating sequence X Corrector algorithm ensures uniform statistical distribution X Data rate up to 10 kB per second X Operational while the processor is in standby System reset and power supply monitoring: X On-chip power-on and brown-out reset X Watchdog timer reset X Reset from pin X Power-fail comparator with programmable threshold and interrupt to MCU On-chip timers: X Three16-bit timers/counters operating at the system clock (sources from the 16 MHz on-chip oscillators) X One 16-bit timer/counter operating at the low frequency clock (32.768 kHz) On-chip oscillators: X 16 MHz crystal oscillator XOSC16M X 16 MHz RC-oscillator RCOSC16M X 32.768 kHz crystal oscillator XOSC32K X 32.768 kHz RC-oscillator RCOSC32K Power management function: X Low power design supporting fully static stop/ standby X Programmable MCU clock frequency from 125 kHz to 16 MHz X On chip voltage regulators supporting low power mode X Watchdog and wakeup functionality running in low power mode On chip support for FS2 or nRFprobe™ HW debug Complete firmware platform available: X Hardware abstraction layer (HAL) Functions X Library functions X Gazell Wireless protocol X Application examples Revision 1.6 12 of 196 nRF24LE1 Product Specification 2.2 Block diagram Program (FLASH) VREG1V7 VDD_1V7 VREG1V2 VDD_1V2 Data (SRAM) NVMEM (FLASH) Memory bus decoder 1.9 V 3.6V MEM-bus IRAM 256 byte Interrupt Control System Config MCU Crypt CoProc Watch dog RTC RNG SFR-bus Serial ports Timers R80515 GPIO SPI Master SPI Slave 2-Wire M/S L01 i/f (SPI) Wakeup Config OCI Digital Crossbar PWM ADC i/f POR Brown out detector XOSC 16 MHz Retention Latches Comparator Debounce mux RCOSC 16 MHz Debounce XOSC 32 kHz Debounce RCOSC 32 kHz Debounce mux CK16M Power Management WakeUP OnPin Pin Crossbar CLKLF Multi purpose pins - bidir dig/ analog Figure 1. nRF24LE1 block diagram To find more information on the blocks, see Table 1. below: Name Memory (Program, Data, NVMEM) Power management RF Transceiver 2-Wire SPI (Master and Slave) GPIO PWM Watchdog Reference Chapter 5 on page 62 Chapter 11 on page 105 Chapter 3 on page 16 Chapter 20 on page 159 Chapter 18 on page 147 Chapter 17 on page 132 Chapter 23 on page 174 Chapter 10 on page 103 Table 1. Block diagram cross references Revision 1.6 13 of 196 RF Transceiver ADC nRF24LE1 Product Specification Pin assignments 2.3.1 24-pin 4x4 QFN-package variant P0.0 XC1 XC2 VDD VSS IREF 2.3 24 23 22 21 20 19 P0.1 VDD DEC1 DEC2 PROG VSS 1 nRF24LE1D 2 3 QFN24 4x4 4 5 6 Exposed die pad 8 17 16 15 14 13 VDD VSS ANT2 ANT1 VDD_PA RESET 99 10 11 12 VDD P0.2 P0.3 P0.4 P0.5 P0.6 7 18 Figure 2. nRF24LE1D pin assignment (top view) for a QFN24 4×4 mm package 32-pin 5x5 QFN-package variant P0.0 XC1 XC2 P1.6 P1.5 VDD VSS IREF 2.3.2 32 31 30 29 28 27 26 P0.1 VDD DEC1 DEC2 P0.2 PROG P0.3 VSS 25 1 2 3 4 5 6 24 nRF24LE1E QFN32 5x5 7 8 23 22 21 20 19 18 Exposed die pad 17 VDD VSS ANT2 ANT1 VDD_PA RESET P1.4 P1.3 VDD P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 9 10 11 12 13 14 15 16 Figure 3. nRF24LE1E pin assignment (top view) for a QFN32 5×5 mm package Revision 1.6 14 of 196 nRF24LE1 Product Specification 48-pin 7x7 QFN-package variant P0.0 P3.6 XC1 XC2 P3.5 P3.4 P3.3 P3.2 P3.1 VDD VSS IREF 2.3.3 48 47 46 45 44 43 42 41 40 39 38 37 P0.1 P0.2 VDD DEC1 DEC2 P0.3 P0.4 P0.5 P0.6 PROG P0.7 VSS 1 36 2 35 3 34 4 33 nRF24LE1F 5 32 31 6 QFN48 7x7 7 8 30 29 9 28 10 27 26 11 Exposed die pad 12 25 VDD VSS ANT2 ANT1 VDD_PA P3.0 RESET P2.7 P2.6 P2.5 P2.4 P2.3 VDD P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 13 14 15 16 17 18 19 20 21 22 23 24 Figure 4. nRF24LE1F pin assignment (top view) for a QFN48 7×7 mm package 2.4 Pin functions Name VDD VSS DEC1 DEC2 P0.0 – P3.6 Type Power Power Power Digital or analog I/O PROG RESET IREF Digital Input Digital Input Analog Input VDD_PA Power Output ANT1, ANT2 RF XC1, XC2 Analog Input Exposed die Power/heat relief pad Description Power supply (+1.9V to +3.6V DC) Ground (0V) Power supply outputs for de-coupling purposes (100nF for DEC1, 33nF for DEC2) General purpose I/O pins. Number of I/O available depends on package type. Input to enable flash programming Reset for microcontroller, active low Device reference current output. To be connected to reference resistor on PCB. Power supply output (+1.8V) for on-chip RF Power amplifier Differential antenna connection (TX and RX) Crystal connection for 16M crystal For the nRF24LE1 QFN48 7×7mm and QFN32 5×5mm connect the die pad to GND. For nRF24LE1 QFN24 4×4mm do not connect the die pad to GND. Table 2. nRF24LE1 pin functions Revision 1.6 15 of 196 nRF24LE1 Product Specification 3 RF transceiver The nRF24LE1 uses the same 2.4 GHz GFSK RF transceiver with embedded protocol engine (Enhanced ShockBurst™) that is found in the nRF24L01+ single chip RF transceiver. The RF transceiver is designed for operation in the world wide ISM frequency band at 2.400 - 2.4835 GHz and is very well suited for ultra low power wireless applications. The RF transceiver module is configured and operated through the RF transceiver map. This register map is accessed by the MCU through a dedicated on-chip Serial Peripheral interface (SPI) and is available in all power modes of the RF transceiver module. The embedded protocol engine (Enhanced ShockBurst™) enables data packet communication and supports various modes from manual operation to advanced autonomous protocol operation. Data FIFOs in the RF transceiver module ensure a smooth data flow between the RF transceiver module and the nRF24LE1 MCU. The rest of this chapter is written in the context of the RF transceiver module as the core and the rest of the nRF24LE1 as external circuitry to this module. 3.1 Features Features of the RF transceiver include: • • • • • • General X Worldwide 2.4 GHz ISM band operation X Common antenna interface in transmit and receive X GFSK modulation X 250kbps, 1 and 2Mbps on air data rate Transmitter X Programmable output power: 0, -6, -12 or -18dBm X 11.1mA at 0dBm output power Receiver X Integrated channel filters X 13.3mA at 2Mbps X -82dBm sensitivity at 2 Mbps X -85dBm sensitivity at 1 Mbps X -94dBm sensitivity at 250 kbps RF Synthesizer X Fully integrated synthesizer X 1 MHz frequency programming resolution X Accepts low cost ±60 ppm 16 MHz crystal X 1 MHz non-overlapping channel spacing at 1 Mbps X 2 MHz non-overlapping channel spacing at 2 Mbps Enhanced ShockBurst™ X 1 to 32 bytes dynamic payload length X Automatic packet handling (assembly/disassembly) X Automatic packet transaction handling (auto ACK, auto retransmit) 6 data pipe MultiCeiver™ for 6:1 star networks Revision 1.6 16 of 196 nRF24LE1 Product Specification 3.2 Block diagram RF Transmitter TX Filter PA RFCON.rfce Baseband RFCON.rfcsn TX FIFOs GFSK Modulator SPI SPI (Slave) (Master) Enhanced ShockBurst Baseband Engine RF Receiver RX Filter LNA ANT2 GFSK Demodulator RX FIFOs RF Synthesiser Power Management Register map RFIRQ ANT1 Radio Control RFCON.rfcken XOSC16M Figure 5. RF transceiver block diagram 3.3 Functional description This section describes the different operating modes of the RF transceiver and the parameters used to control it. The RF transceiver module has a built-in state machine that controls the transitions between the different operating modes. The state machine is controlled by SFR register RFCON and RF transceiver register CONFIG, see section 3.5 for details. 3.3.1 Operational Modes You can configure the RF transceiver to power down, standby, RX and TX mode. This section describes these modes in detail. 3.3.1.1 State diagram The state diagram (Figure 6.) shows the operating modes of the RF transceiver and how they function. At the end of the reset sequence the RF transceiver enters Power Down mode. When the RF transceiver enters Power Down mode the MCU can still control the module through the SPI and the rfcsn bit in the RFCON register. There are three types of distinct states highlighted in the state diagram: • • • Recommended operating mode: is a recommended state used during normal operation. Possible operating mode: is a possible operating state, but is not used during normal operation. Transition state: is a time limited state used during start up of the oscillator and settling of the PLL. Revision 1.6 17 of 196 nRF24LE1 Product Specification . Legend: Undefined Undefined Undefined Recommended operating mode Power on reset 50ms Possible operating mode Transition state Recommended path between operating modes Power Down Possible path between operating modes CE = 1 Pin signal condition PWR_DN = 1 Bit state condition TX FIFO empty PWR_UP=0 PWR_UP = 1 Start up time is 150µs System information PWR_UP=0 PWR_UP = 0 PRIM_RX = 0 TX FIFO empty rfce = 1 Standby-I PWR_UP = 0 rfce = 0 RX Settling 130 us PRIM_RX = 1 rfce = 1 Standby-II TX FIFO not empty PRIM_RX = 0 rfce = 1 for more than 10µs TX finished with one packet rfce = 0 rfce = 0 TX FIFO not empty rfce = 1 TX Settling 130 us RX Mode TX FIFO empty rfce = 1 PWR_UP=0 TX Mode PWR_UP = 0 rfce = 1 TX FIFO not empty Figure 6. Radio control state diagram 3.3.1.2 Power down mode In power down mode the RF transceiver is disabled with minimal current consumption. All the register values available from the SPI are maintained and the SPI can be activated. For start up times see Table 4. on page 20. Power down mode is entered by setting the PWR_UP bit in the CONFIG register low. 3.3.1.3 Standby modes Standby-I mode By setting the PWR_UP bit in the CONFIG register to 1, the RF transceiver enters standby-I mode. StandbyI mode is used to minimize average current consumption while maintaining short start up times. Change to the active mode only happens if the rfce bit is enabled and when it is not enabled, the RF transceiver returns to standby-I mode from both the TX and RX modes. Revision 1.6 18 of 196 nRF24LE1 Product Specification Standby-II mode In standby-II mode extra clock buffers are active and more current is used compared to standby-I mode. The RF transceiver enters standby-II mode if the rfce bit is held high on a PTX operation with an empty TX FIFO. If a new packet is downloaded to the TX FIFO, the PLL immediately starts and the packet is transmitted after the normal PLL settling delay (130µs). The register values are maintained and the SPI can be activated during both standby modes. For start up times see Table 4. on page 20. 3.3.1.4 RX mode The RX mode is an active mode where the RF transceiver is used as a receiver. To enter this mode, the RF transceiver must have the PWR_UP bit, PRIM_RX bit and the rfce bit is set high. In RX mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the baseband protocol engine. The baseband protocol engine constantly searches for a valid packet. If a valid packet is found (by a matching address and a valid CRC) the payload of the packet is presented in a vacant slot in the RX FIFOs. If the RX FIFOs are full, the received packet is discarded. The RF transceiver remains in RX mode until the MCU configures it to standby-I mode or power down mode. However, if the automatic protocol features (Enhanced ShockBurst™) in the baseband protocol engine are enabled, the RF transceiver can enter other modes in order to execute the protocol. In RX mode a Received Power Detector (RPD) signal is available. The RPD is a signal that is set high when a RF signal higher than -64 dBm is detected inside the receiving frequency channel. The internal RPD signal is filtered before presented to the RPD register. The RF signal must be present for at least 40µs before the RPD is set high. How to use the RPD is described in Section 3.3.4 on page 21. 3.3.1.5 TX mode The TX mode is an active mode for transmitting packets. To enter this mode, the RF transceiver must have the PWR_UP bit set high, PRIM_RX bit set low, a payload in the TX FIFO and a high pulse on the rfce bit for more than 10 µs. The RF transceiver stays in TX mode until it finishes transmitting a packet. If rfce = 0, RF transceiver returns to standby-I mode. If rfce = 1, the status of the TX FIFO determines the next action. If the TX FIFO is not empty the RF transceiver remains in TX mode and transmits the next packet. If the TX FIFO is empty the RF transceiver goes into standby-II mode. The RF transceiver transmitter PLL operates in open loop when in TX mode. It is important never to keep the RF transceiver in TX mode for more than 4ms at a time. If the Enhanced ShockBurst™ features are enabled, RF transceiver is never in TX mode longer than 4 ms. Revision 1.6 19 of 196 nRF24LE1 Product Specification 3.3.1.6 Operational modes configuration The following table (Table 3.) describes how to configure the operational modes. RX mode TX mode PWR_UP register 1 1 PRIM_RX register 1 0 TX mode 1 0 Standby-II Standby-I Power Down 1 1 0 0 - Mode FIFO state rfce 1 1 Data in TX FIFO. Will empty all levels in TX FIFOa. Minimum 10µs Data in TX FIFO.Will empty one high pulse level in TX FIFOb. 1 TX FIFO empty 0 No ongoing packet transmission - a. If the rfce bit is held high the TX FIFO is emptied and all necessary ACK and possible retransmits are carried out. The transmission continues as long as the TX FIFO is refilled. If the TX FIFO is empty when the rfce bit is still high, the RF transceiver enters standby-II mode. In this mode the transmission of a packet is started as soon as the rfcsn is set high after an upload (UL) of a packet to TX FIFO. b. This operating mode pulses the rfce bit high for at least 10µs. This allows one packet to transmit. This is the normal operating mode. After the packet is transmitted, the RF transceiver enters standbyI mode. Table 3. RF transceiver main modes 3.3.1.7 Timing information The timing information in this section relates to the transitions between modes and the timing for the rfce bit. The transition from TX mode to RX mode or vice versa is the same as the transition from the standby modes to TX mode or RX mode (130µs), as described in Table 4. Name Tpd2stby Tstby2a Thce Tpece2csn RF Transceiver Power Down Î Standby mode Standby modes Î TX/RX mode Minimum rfce high Delay from rfce pos. edge to rfcsn low Max. Min. Comments 1µsa 130µs 10µs 4µs a. This presupposes that the XO is running. Please refer to CLKLFCTRL for bit 3 in Table 59. on page 112. Table 4. Operational timing of RF transceiver Note: If VDD is turned off, or if the nRF24LE1 enters Deep Sleep or Memory Retention mode, the register values are lost and you must configure the RF transceiver before entering the TX or RX modes. Revision 1.6 20 of 196 nRF24LE1 Product Specification 3.3.2 Air data rate The air data rate is the modulated signaling rate the RF transceiver uses when transmitting and receiving data. It can be 250 kbps, 1 Mbps or 2 Mbps. Using lower air data rate gives better receiver sensitivity than higher air data rate. But, high air data rate gives lower average current consumption and reduced probability of on-air collisions. The air data rate is set by the RF_DR bit in the RF_SETUP register. A transmitter and a receiver must be programmed with the same air data rate to communicate with each other. The RF transceiver is fully compatible with nRF24L01. For compatibility with nRF2401A, nRF2402, nRF24E1, and nRF24E2 the air data rate must be set to 250 kbps or 1 Mbps. 3.3.3 RF channel frequency The RF channel frequency determines the center of the channel used by the RF transceiver. The channel occupies a bandwidth of less than 1 MHz at 250kbps and 1Mbps and a bandwidth of less than 2 MHz at 2Mbps. The RF transceiver can operate on frequencies from 2.400 GHz to 2.525 GHz. The programming resolution of the RF channel frequency setting is 1 MHz. At 2Mbps the channel occupies a bandwidth wider than the resolution of the RF channel frequency setting. To ensure non-overlapping channels in 2Mbps mode, the channel spacing must be 2 MHz or more. At 1Mbps and 250kbps the channel bandwidth is the same or lower than the resolution of the RF frequency. The RF channel frequency is set by the RF_CH register according to the following formula: F0= 2400 + RF_CH MHz You must program a transmitter and a receiver with the same RF channel frequency to communicate with each other. 3.3.4 Received Power Detector measurements Received Power Detector (RPD), located in register 09, bit 0, triggers at received power levels above -64 dBm that are present in the RF channel you receive on. If the received power is less than -64 dBm, RDP = 0. The RPD can be read out at any time while the RF transceiver is in receive mode. This offers a snapshot of the current received power level in the channel. The RPD is latched whenever a packet is received or when the MCU sets rfce low. The status of RPD is correct when RX mode is enabled and after a wait time of Tstby2a +Tdelay_AGC= 130us + 40µs. The RX gain varies over temperature which means that the RPD threshold also varies over temperature. The RPD threshold value is reduced by - 5dB at T = -40°C and increased by + 5dB at 85°C. 3.3.5 PA control The PA (Power Amplifier) control is used to set the output power from the RF transceiver power amplifier. In TX mode PA control has four programmable steps, see Table 5. on page 22. Revision 1.6 21 of 196 nRF24LE1 Product Specification The PA control is set by the RF_PWR bits in the RF_SETUP register. SPI RF-SETUP RF output power (RF_PWR) 11 0dBm 10 -6dBm 01 -12dBm 00 -18dBm DC current consumption 11.1mA 8.8mA 7.3mA 6.8mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 15Ω+j88Ω. Table 5. RF output power setting for the RF transceiver 3.3.6 RX/TX control The RX/TX control is set by PRIM_RX bit in the CONFIG register and sets the RF transceiver in transmit/ receive. 3.4 Enhanced ShockBurst™ Enhanced ShockBurst™ is a packet based data link layer that features automatic packet assembly and timing, automatic acknowledgement and retransmissions of packets. Enhanced ShockBurst™ enables the implementation of ultra low power and high performance communication. The Enhanced ShockBurst™ features enable significant improvements of power efficiency for bi-directional and uni-directional systems, without adding complexity on the host controller side. 3.4.1 Features The main features of Enhanced ShockBurst™ are: • • • • 3.4.2 1 to 32 bytes dynamic payload length Automatic packet handling Auto packet transaction handling X Auto Acknowledgement X Auto retransmit 6 data pipe MultiCeiver™ for 1:6 star networks Enhanced ShockBurst™ overview Enhanced ShockBurst™ uses ShockBurst™ for automatic packet handling and timing. During transmit, ShockBurst™ assembles the packet and clocks the bits in the data packet for transmission. During receive, ShockBurst™ constantly searches for a valid address in the demodulated signal. When ShockBurst™ finds a valid address, it processes the rest of the packet and validates it by CRC. If the packet is valid the payload is moved into a vacant slot in the RX FIFOs. All high speed bit handling and timing is controlled by ShockBurst™. Enhanced ShockBurst™ features automatic packet transaction handling for the easy implementation of a reliable bi-directional data link. An Enhanced ShockBurst™ packet transaction is a packet exchange between two transceivers, with one transceiver acting as the Primary Receiver (PRX) and the other transceiver acting as the Primary Transmitter (PTX). An Enhanced ShockBurst™ packet transaction is always initiated by a packet transmission from the PTX, the transaction is complete when the PTX has received an Revision 1.6 22 of 196 nRF24LE1 Product Specification acknowledgment packet (ACK packet) from the PRX. The PRX can attach user data to the ACK packet enabling a bi-directional data link. The automatic packet transaction handling works as follows: 1. You begin the transaction by transmitting a data packet from the PTX to the PRX. Enhanced ShockBurst™ automatically sets the PTX in receive mode to wait for the ACK packet. If the packet is received by the PRX, Enhanced ShockBurst™ automatically assembles and transmits an acknowledgment packet (ACK packet) to the PTX before returning to receive mode. If the PTX does not receive the ACK packet immediately, Enhanced ShockBurst™ automatically retransmits the original data packet after a programmable delay and sets the PTX in receive mode to wait for the ACK packet. 2. 3. In Enhanced ShockBurst™ it is possible to configure parameters such as the maximum number of retransmits and the delay from one transmission to the next retransmission. All automatic handling is done without the involvement of the MCU. 3.4.3 Enhanced Shockburst™ packet format The format of the Enhanced ShockBurst™ packet is described in this section. The Enhanced ShockBurst™ packet contains a preamble field, address field, packet control field, payload field and a CRC field. Figure 7. shows the packet format with MSB to the left. P re a m b le 1 b y te A d d re s s 3 -5 b y te P a c k e t C o n tro l F ie ld 9 b it P a y lo a d 0 - 3 2 b y te C R C 1 -2 b y te Figure 7. An Enhanced ShockBurst™ packet with payload (0-32 bytes) 3.4.3.1 Preamble The preamble is a bit sequence used to synchronize the receivers demodulator to the incoming bit stream. The preamble is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilize the receiver. 3.4.3.2 Address This is the address for the receiver. An address ensures that the correct packet is detected by the receiver. The address field can be configured to be 3, 4 or, 5 bytes long with the AW register. Note: Addresses where the level shifts only one time (that is, 000FFFFFFF) can often be detected in noise and can give a false detection, which may give a raised Packet-Error-Rate. Addresses as a continuation of the preamble (hi-low toggling) raises the Packet-Error-Rate. Revision 1.6 23 of 196 nRF24LE1 Product Specification 3.4.3.3 Packet Control Field Figure 8. shows the format of the 9 bit packet control field, MSB to the left. Payload length 6bit PID 2bit NO_ACK 1bit Figure 8. Packet control field The packet control field contains a 6 bit payload length field, a 2 bit PID (Packet Identity) field and a 1 bit NO_ACK flag. Payload length This 6 bit field specifies the length of the payload in bytes. The length of the payload can be from 0 to 32 bytes. Coding: 000000 = 0 byte (only used in empty ACK packets.) 100000 = 32 byte, 100001 = Don’t care. This field is only used if the Dynamic Payload Length function is enabled. PID (Packet identification) The 2 bit PID field is used to detect if the received packet is new or retransmitted. PID prevents the PRX operation from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI. The PID and CRC fields (see section 3.4.3.5 on page 25) are used by the PRX operation to determine if a packet is retransmitted or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, the RF transceiver compares the CRC sums from both packets. If the CRC sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. No Acknowledgment flag (NO_ACK) The Selective Auto Acknowledgement feature controls the NO_ACK flag. This flag is only used when the auto acknowledgement feature is used. Setting the flag high, tells the receiver that the packet is not to be auto acknowledged. 3.4.3.4 Payload The payload is the user defined content of the packet. It can be 0 to 32 bytes wide and is transmitted on-air when it is uploaded (unmodified) to the device. Enhanced ShockBurst™ provides two alternatives for handling payload lengths; static and dynamic. The default is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. Static payload length is set by the RX_PW_Px registers on the receiver side. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal the value in the RX_PW_Px register on the receiver side. Revision 1.6 24 of 196 nRF24LE1 Product Specification Dynamic Payload Length (DPL) is an alternative to static payload length. DPL enables the transmitter to send packets with variable payload length to the receiver. This means that for a system with different payload lengths it is not necessary to scale the packet length to the longest payload. With the DPL feature the nRF24L01+ can decode the payload length of the received packet automatically instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using the R_RX_PL_WID command. Note: Always check if the packet width reported is 32 bytes or shorter when using the R_RX_PL_WID command. If its width is longer than 32 bytes then the packet contains errors and must be discarded. Discard the packet by using the Flush_RX command. In order to enable DPL the EN_DPL bit in the FEATURE register must be enabled. In RX mode the DYNPD register must be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD set. 3.4.3.5 CRC (Cyclic Redundancy Check) The CRC is the error detection mechanism in the packet. It may either be 1 or 2 bytes and is calculated over the address, Packet Control Field and Payload. The polynomial for 1 byte CRC is X8 + X2 + X + 1. Initial value 0xFF. The polynomial for 2 byte CRC is X16+ X12 + X5 + 1. Initial value 0xFFFF. No packet is accepted by Enhanced ShockBurst™ if the CRC fails. Revision 1.6 25 of 196 nRF24LE1 Product Specification 3.4.4 Automatic packet assembly The automatic packet assembly assembles the preamble, address, packet control field, payload and CRC to make a complete packet before it is transmitted. Start: Collect Address from TX_ADDR register TX_ADDR MSB =1 No Yes Add preamble 0x55 Add preamble 0xAA EN_DPL=1 Yes PCF[8:3]= #bytes in upper level of TX_FIFO New data in TX_FIFO No No REUSE_TX_PL active Yes Yes PCF[2:1]++ No SPI TX command W_TX_PAYLOAD_NOACK W_TX_PAYLOAD PCF[0]=0 PCF[0]=1 Collect Payload from TX_FIFO EN_CRC = 1 Yes No CRCO = 1 Yes No Calculate and add 2 Byte CRC based on Address, PCF and Payload Calculate and add 1 Byte CRC based on Address, PCF and Payload STOP Figure 9. Automatic packet assembly Revision 1.6 26 of 196 nRF24LE1 Product Specification 3.4.5 Automatic packet disassembly After the packet is validated, Enhanced ShockBurst™ disassembles the packet and loads the payload into the RX FIFO, and asserts the RX_DR IRQ. Start Read Address width from SETUP_AW No Monitor SETUP_AW wide window of received bit stream Received window = RX_ADDR_Px Yes PCF = 9 first bits received after valid address EN_DPL=1 No No Yes Payload = PCF[8:3] bytes from received bit stream Payload = RX_PW_Px bytes from received bit stream No CRCO = 1 Yes TX_CRC = 2 Bytes from received bit stream TX_CRC = 1 Byte from received bit stream RX_CRC = 2 Byte CRC calculated from received Address, PCF and Payload RX_CRC = 1 Byte CRC calculated from received Address, PCF and Payload TX_CRC = RX_CRC Yes PCF[2:1] Changed from last packet No CRC Changed from last packet No Yes New packet received Reject the duplicate received packet STOP Figure 10. Automatic packet disassembly Revision 1.6 27 of 196 nRF24LE1 Product Specification 3.4.6 Automatic packet transaction handling Enhanced ShockBurst™ features two functions for automatic packet transaction handling; auto acknowledgement and auto re-transmit. 3.4.6.1 Auto Acknowledgement Auto acknowledgment is a function that automatically transmits an ACK packet to the PTX after it has received and validated a packet. The auto acknowledgement function reduces the load of the system MCU and reduces average current consumption. The Auto Acknowledgement feature is enabled by setting the EN_AA register. Note: If the received packet has the NO_ACK flag set, auto acknowledgement is not executed. An ACK packet can contain an optional payload from PRX to PTX. In order to use this feature, the Dynamic Payload Length (DPL) feature must be enabled. The MCU on the PRX side has to upload the payload by clocking it into the TX FIFO by using the W_ACK_PAYLOAD command. The payload is pending in the TX FIFO (PRX) until a new packet is received from the PTX. The RF transceiver can have three ACK packet payloads pending in the TX FIFO (PRX) at the same time. RX Pipe address ACK generator Address decoder and buffer controller TX FIFO Payload 3 Payload 2 Payload 1 TX Pipe address SPI Module From MCU Figure 11. TX FIFO (PRX) with pending payloads Figure 11. shows how the TX FIFO (PRX) is operated when handling pending ACK packet payloads. From the MCU the payload is clocked in with the W_ACK_PAYLOAD command. The address decoder and buffer controller ensure that the payload is stored in a vacant slot in the TX FIFO (PRX). When a packet is received, the address decoder and buffer controller are notified with the PTX address. This ensures that the right payload is presented to the ACK generator. If the TX FIFO (PRX) contains more than one payload to a PTX, payloads are handled using the first in – first out principle. The TX FIFO (PRX) is blocked if all pending payloads are addressed to a PTX where the link is lost. In this case, the MCU can flush the TX FIFO (PRX) by using the FLUSH_TX command. In order to enable Auto Acknowledgement with payload the EN_ACK_PAY bit in the FEATURE register must be set. 3.4.6.2 Auto Retransmission (ART) The auto retransmission is a function that retransmits a packet if an ACK packet is not received. It is used in an auto acknowledgement system on the PTX. When a packet is not acknowledged, you can set the number of times it is allowed to retransmit by setting the ARC bits in the SETUP_RETR register. PTX enters RX mode and waits a time period for an ACK packet each time a packet is transmitted. The amount of time the PTX is in RX mode is based on the following conditions: Revision 1.6 28 of 196 nRF24LE1 Product Specification • • • Auto Retransmit Delay (ARD) elapsed. No address match within 250µs. After received packet (CRC correct or not) if address match within 250µs. The RF transceiver asserts the TX_DS IRQ when the ACK packet is received. The RF transceiver enters standby-I mode if there is no more untransmitted data in the TX FIFO and the rfce bit in the RFCON register is low. If the ACK packet is not received, the RF transceiver goes back to TX mode after a delay defined by ARD and retransmits the data. This continues until acknowledgment is received, or the maximum number of retransmits is reached. Two packet loss counters are incremented each time a packet is lost, ARC_CNT and PLOS_CNT in the OBSERVE_TX register. The ARC_CNT counts the number of retransmissions for the current transaction. You reset ARC_CNT by initiating a new transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. You reset PLOS_CNT by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make an overall assessment of the channel quality. The ARD defines the time from the end of a transmitted packet to when a retransmit starts on the PTX. ARD is set in SETUP_RETR register in steps of 250µs. A retransmit is made if no ACK packet is received by the PTX. There is a restriction on the length of ARD when using ACK packets with payload. The ARD time must never be shorter than the sum of the startup time and the time on-air for the ACK packet. • • For 2Mbps data rate and 5-byte address; 15 byte is maximum ACK packet payload length for ARD=250µs (reset value). For 1Mbps data rate and 5-byte address; 5 byte is maximum ACK packet payload length for ARD=250µs (reset value). ARD=500µs is long enough for any ACK payload length in 1 or 2Mbps mode. • For 250kbps data rate and 5-byte address the following values apply: ARD 1500 µs 1250 µs 1000 µs 750 µs 500 µs ACK packet size (in bytes) All ACK payload sizes < 24 < 16 10 µs TIRQ TUL PTX SPI Tstdby2a TOA IRQ: TX DS1 UL PTX CE PTX IRQ PTX MODE Standby-I PLL Lock TX Standby-I 1 IRQ if No Ack is on. TIRQ = 8.2 µs @ 1 Mbps, TIRQ = 6.0 µs @ 2 Mbps, Tstdby2a = 130 µs Figure 17. Transmitting one packet with NO_ACK on The following equations calculate various timing measurements: Symbol TOA Description Time on-air Equation ⎤ ⋅ ⎛⎜1[byte]+ 3,4 or 5 [bytes ]+ N [bytes ]+ 1 or 2 [bytes ]⎞⎟ + 8⎡bit ⎢⎣ byte ⎥⎦ ⎝ preamble packet length address payload CRC ⎠ = = air data rate air data rate bit s packet control field T ACK = ⎤ ⋅ ⎛⎜1[byte]+ 3,4 or 5 [bytes]+ N [bytes ]+ 1 or 2 [bytes ]⎞⎟ + 8⎡bit ⎣⎢ byte⎥⎦ ⎝ preamble packet length address payload CRC ⎠ = air data rate air data rate bit s packet control field TU L = ⎤ ⋅ N [bytes ] 8 ⎡ bit payload length ⎣⎢ byte ⎥⎦ payload = SPI data rate SPI data rate bit s TOA Time on-air Ack TACK [ ] Time Upload TUL TESB [ ] 9 [bit ] [ ] Time Enhanced Shock- TESB = TUL + 2 . Tstby2a + TOA + TACK + TIRQ Burst™ cycle Table 7. Timing equations Revision 1.6 36 of 196 9 [bit ] nRF24LE1 Product Specification TESB Cycle >10us TUL PTX SPI 130us TIRQ TOA IRQ: TX DS UL PTX rfce PTX IRQ PTX MODE PRX MODE Standby 1 Standby 1 PLL Lock PLL Lock TX RX PLL Lock RX Standby 1 PLL Lock TX PLL Lock TACK 130us RX PRX IRQ PRX rfce PRX SPI IRQ:RX DR/DL 130us 130us TIRQ Figure 18. Timing of Enhanced ShockBurst™ for one packet upload (2 Mbps) In Figure 18. the transmission and acknowledgement of a packet is shown. The PRX operation activates RX mode (rfce=1), and the PTX operation is activated in TX mode (rfce=1 for minimum 10µs). After 130µs the transmission starts and finishes after the elapse of TOA. When the transmission ends the PTX operation automatically switches to RX mode to wait for the ACK packet from the PRX operation. When the PRX operation receives the packet it sets the interrupt for the host MCU and switches to TX mode to send an ACK. After the PTX operation receives the ACK packet it sets the interrupt to the MCU and clears the packet from the TX FIFO. Revision 1.6 37 of 196 nRF24LE1 Product Specification In Figure 19. the PTX timing of a packet transmission is shown when the first ACK packet is lost. To see the complete transmission when the ACK packet fails see Figure 22. on page 40. >10us TUL PTX SPI ARD 130us TOA 130us PLL Lock TX PLL Lock 250us max 130us UL PTX CE PTX IRQ PTX MODE Standby I RX Standby II PLL Lock TX Figure 19. Timing of Enhanced ShockBurst™ when the first ACK packet is lost (2Mbps) 3.4.10 Enhanced ShockBurst™ transaction diagram This section describes several scenarios for the Enhanced ShockBurst™ automatic transaction handling. The call outs in this section’s figures indicate the IRQs and other events. For MCU activity the event may be placed at a different timeframe. Note: The figures in this section indicate the earliest possible download (DL) of the packet to the MCU and the latest possible upload (UL) of payload to the transmitter. Revision 1.6 38 of 196 nRF24LE1 Product Specification 3.4.10.1 Single transaction with ACK packet and interrupts In Figure 20. the basic auto acknowledgement is shown. After the packet is transmitted by the PTX and received by the PRX the ACK packet is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas the TX_DS IRQ is asserted when the packet is acknowledged and the ACK packet is received by the PTX. MCU PTX UL IRQ Ack received IRQ:TX DS (PID=1) 130us1 PTX TX:PID=1 RX PRX RX ACK:PID=1 Packet received IRQ: RX DR (PID=1) MCU PRX DL 1 Radio Turn Around Delay Figure 20. TX/RX cycles with ACK and the according interrupts 3.4.10.2 Single transaction with a lost packet Figure 21. is a scenario where a retransmission is needed due to loss of the first packet transmit. After the packet is transmitted, the PTX enters RX mode to receive the ACK packet. After the first transmission, the PTX waits a specified time for the ACK packet, if it is not in the specific time slot the PTX retransmits the packet as shown in Figure 21. MCU PTX UL Packet PID=1 lost during transmission IRQ No address detected. RX off to save current Auto retransmit delay elapsed 130us1 PTX TX:PID=1 Retransmit of packet PID=1 130us1 RX ACK received IRQ: TX DS (PID=1) 130us1 TX:PID=1 RX ARD PRX RX ACK:PID=1 Packet received. IRQ: RX DR (PID=1) MCU PRX DL 1 Radio Turn Around Delay Figure 21. TX/RX cycles with ACK and the according interrupts when the first packet transmit fails Revision 1.6 39 of 196 nRF24LE1 Product Specification When an address is detected the PTX stays in RX mode until the packet is received. When the retransmitted packet is received by the PRX (see Figure 21. on page 39), the RX_DR IRQ is asserted and an ACK is transmitted back to the PTX. When the ACK is received by the PTX, the TX_DS IRQ is asserted. 3.4.10.3 Single transaction with a lost ACK packet Figure 22. is a scenario where a retransmission is needed after a loss of the ACK packet. The corresponding interrupts are also indicated. MCU PTX UL IRQ No address detected. RX off to save current 130us PTX TX:PID=1 Auto retransmit delay elapsed 1 130us Retransmit of packet PID=1 1 ACK received IRQ: TX DS (PID=1) 130us1 RX TX:PID=1 RX ARD PRX RX ACK:PID=1 Packet received. IRQ: RX DR (PID=1) RX ACK PID=1 lost during transmission MCU PRX ACK:PID=1 Packet detected as copy of previous, discarded DL 1 Radio Turn Around Delay Figure 22. TX/RX cycles with ACK and the according interrupts when the ACK packet fails 3.4.10.4 Single transaction with ACK payload packet Figure 23. is a scenario of the basic auto acknowledgement with payload. After the packet is transmitted by the PTX and received by the PRX the ACK packet with payload is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas on the PTX side the TX_DS IRQ is asserted when the ACK packet is received by the PTX. On the PRX side, the TX_DS IRQ for the ACK packet payload is asserted after a new packet from PTX is received. The position of the IRQ in Figure 23. shows where the MCU can respond to the interrupt. MCU PTX UL1 DL IRQ UL2 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) Transmit of packet PID=2 ≥130us3 130us1 PTX TX:PID=1 PRX RX RX TX:PID=2 ACK1 PAY RX Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=1) MCU PRX UL2 DL DL IRQ 1 Radio Turn Around Delay 2 Uploading Payload for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 23. TX/RX cycles with ACK Payload and the according interrupts Revision 1.6 40 of 196 nRF24LE1 Product Specification 3.4.10.5 Single transaction with ACK payload packet and lost packet Figure 24. is a scenario where the first packet is lost and a retransmission is needed before the RX_DR IRQ on the PRX side is asserted. For the PTX both the TX_DS and RX_DR IRQ are asserted after the ACK packet is received. After the second packet (PID=2) is received on the PRX side both the RX_DR (PID=2) and TX_DS (ACK packet payload) IRQ are asserted. MCU PTX UL1 DL IRQ UL2 Packet PID=1 lost during transmission No address detected. RX off to save current Auto retransmit delay elapsed 130us1 PTX TX:PID=1 Retransmit of packet PID=1 130us1 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) ≥130us3 130us1 RX TX:PID=1 RX TX:PID=2 ACK1 PAY RX ARD PRX RX Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=1) MCU PRX UL 2 DL DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 24. TX/RX cycles and the according interrupts when the packet transmission fails 3.4.10.6 MCU PTX Two transactions with ACK payload packet and the first ACK packet lost UL1 UL2 No address detected. RX off to save current 130us PTX TX:PID=1 DL IRQ UL3 Auto retransmit delay elapsed 1 130us ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) Retransmit of packet PID=1 1 RX 130us TX:PID=1 ACK received IRQ: TX DS (PID=2) RX DR (ACK2PAY) ≥ 130us 1 ≥130us3 130us 1 3 RX TX:PID=2 RX TX:PID=3 ACK1 PAY RX ACK2 PAY RX ARD PRX RX ACK1 PAY Packet received. IRQ: RX DR (PID=1) MCU PRX UL12 RX ACK PID=1 lost during transmission DL Packet detected as copy of previous, discarded Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=3) TX DS (ACK2PAY) DL IRQ UL2 2 1 Radio Turn Around Delay 2 Uploading Payload for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 25. TX/RX cycles with ACK Payload and the according interrupts when the ACK packet fails In Figure 25. the ACK packet is lost and a retransmission is needed before the TX_DS IRQ is asserted, but the RX_DR IRQ is asserted immediately. The retransmission of the packet (PID=1) results in a discarded packet. For the PTX both the TX_DS and RX_DR IRQ are asserted after the second transmission of ACK, which is received. After the second packet (PID=2) is received on the PRX both the RX_DR (PID=2) and TX_DS (ACK1PAY) IRQ is asserted. The callouts explains the different events and interrupts. Revision 1.6 41 of 196 nRF24LE1 Product Specification 3.4.10.7 Two transactions where max retransmissions is reached MCU PTX UL IRQ No address detected. RX off to save current 130 µs PTX IRQ TX:PID=1 Auto retransmit delay elapsed 1 130 µs RX Retransmit of packet PID=1 1 TX:PID=1 ARD 130 µs ≥130 µs 1 RX No address detected. RX off to save current No address detected. RX off to save current 3 130 µs TX:PID=1 ARD IRQ:MAX_RT 1 RX ARD 130 µs1 PRX RX ACK1 PAY Packet received. IRQ: RX DR (PID=1) MCU PRX UL2 RX ACK PID=1 lost during transmission ACK PID=1 lost during transmission ACK1 PAY Packet detected as copy of previous, discarded RX ACK PID=1 lost during transmission DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130 µs Figure 26. TX/RX cycles with ACK Payload and the according interrupts when the transmission fails. ARC is set to 2. MAX_RT IRQ is asserted if the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC). In Figure 26. the packet transmission ends with a MAX_RT IRQ. The payload in TX FIFO is NOT removed and the MCU decides the next step in the protocol. A toggle of the rfce bit in the RFCON register starts a new transmitting sequence of the same packet. The payload can be removed from the TX FIFO using the FLUSH_TX command. 3.4.11 Compatibility with ShockBurst™ You must disable Enhanced ShockBurst™ for backward compatibility with the nRF2401A, nRF2402, nRF24E1 and, nRF24E2. Set the register EN_AA = 0x00 and ARC = 0 to disable Enhanced ShockBurst™. In addition, the RF transceiver air data rate must be set to 1Mbps or 250kbps. 3.4.11.1 ShockBurst™ packet format The ShockBurst™ packet format is described in this chapter. Figure 27. shows the packet format with MSB to the left. Preamble 1 byte Address 3-5 byte Payload 1 - 32 byte CRC 1-2 byte Figure 27. A ShockBurst™ packet compatible with nRF2401/nRF2402/nRF24E1/nRF24E2 devices. The ShockBurst™ packet format has a preamble, address, payload and CRC field that are the same as the Enhanced ShockBurst™ packet format described in section 3.4.3 on page 23. The differences between the ShockBurst™ packet and the Enhanced ShockBurst™ packet are: • The 9 bit Packet Control Field is not present in the ShockBurst™ packet format. Revision 1.6 42 of 196 nRF24LE1 Product Specification • The CRC is optional in the ShockBurst™ packet format and is controlled by the EN_CRC bit in the CONFIG register. 3.5 Data and control interface The data and control interface gives you access to all the features in the RF transceiver. Compared to the standalone component SFR registers are used instead of port pins. Otherwise the interface is identical to the standalone nRF24L01+ chip. 3.5.1 SFR registers Address Name/Mnemonic (Hex) 0xE4 SPIRCON0 0xE5 Reset value 6:0 0x01 Bit SPIRCON1 maskIrqRxFifoFull 3:0 3 0x0F 1 maskIrqRxDataReady 2 1 maskIrqTxFifoEmpty maskIrqTxFifoReady 1 1 0 1 spiMasterStatus SPIRSTAT rxFifoFull 3:0 0x03 3 0 rxDataReady 2 0 txFifoEmpty 1 1 txFifoReady 0 1 SPIRDAT 7:0 0x00 0xE6 0xE7 Type Description R/W SPI Master configuration register 0. Reserved. Do not alter. R/W SPI Master configuration register 1. R/W 1: Disable interrupt when RX FIFO is full. 0: Enable interrupt when RX FIFO is full. R/W 1: Disable interrupt when data is available in RX FIFO. 0: Enable interrupt when data is available in RX FIFO. R/W 1: Disable interrupt when TX FIFO is empty. 0: Enable interrupt when TX FIFO is empty. R/W 1: Disable interrupt when a location is available in TX FIFO. 0: Enable interrupt when a location is available in TX FIFO. R SPI Master status register. R Interrupt source. 1: RX FIFO full. 0: RX FIFO can accept more data from SPI. Cleared when the cause is removed. R Interrupt source. 1: Data available in RX FIFO. 0: No data in RX FIFO. Cleared when the cause is removed. R Interrupt source. 1: TX FIFO empty. 0: Data in TX FIFO. Cleared when the cause is removed. R Interrupt source. 1: Location available in TX FIFO. 0: TX FIFO full. Cleared when the cause is removed. R/W SPI Master data register. Accesses TX (write) and RX (read) FIFO buffers, both two bytes deep. Table 8. RF transceiver SPI master registers Revision 1.6 43 of 196 nRF24LE1 Product Specification The RF transceiver SPI Master is configured through SPIRCON1. Four different sources can generate interrupt, unless they are masked by their respective bits in SPIRCON1. SPIRSTAT reveals which sources that are active. SPIRDAT accesses both the TX (write) and the RX (read) FIFOs, which are two bytes deep. The FIFOs are dynamic and can be refilled according to the state of the status flags: “FIFO ready” means that the FIFO can accept data. “Data ready” means that the FIFO can provide data, minimum one byte. Addr 0xE8 Bit 7:3 2 1 0 Name rfcken rfcsn rfce R/W RW RW RW Function Reserved RF Clock Enable (16 MHz) Enable RF command. 0: enabled Enable RF Transceiver. 1: enabled Table 9. RFCON register RFCON controls the RF transceiver SPI Slave chip select signal (CSN), the RF transceiver chip enable signal (CE) and the RF transceiver clock enable signal (CKEN). 3.5.2 SPI operation This section describes the SPI commands and timing. 3.5.2.1 SPI commands The SPI commands are shown in Table 10. on page 45 Every new command must be started by writing 0 to rfcsn in the RFCON register. The SPI command is transferred to RF transceiver by writing the command to the SPIRDAT register. After the first transfer the RF transceiver's STATUS register can be read from SPIRDAT when the transfer is completed. The serial shifting SPI commands is in the following format: . Revision 1.6 44 of 196 nRF24LE1 Product Specification Command name R_REGISTER W_REGISTER Command # Data bytes word (binary) 000A AAAA 1 to 5 LSByte first 001A AAAA 1 to 5 LSByte first R_RX_PAYLOAD 0110 0001 1 to 32 LSByte first W_TX_PAYLOAD 1010 0000 FLUSH_TX FLUSH_RX 1110 0001 1110 0010 1 to 32 LSByte first 0 0 REUSE_TX_PL 1110 0011 0 R_RX_PL_WIDa 0110 0000 1 W_ACK_PAYLOADa 1010 1PPP 1 to 32 LSByte first W_TX_PAYLOAD_NO ACKa NOP 1011 0000 1 to 32 LSByte first 0 1111 1111 Operation Read command and status registers. AAAAA = 5 bit Register Map Address Write command and status registers. AAAAA = 5 bit Register Map Address Executable in power down or standby modes only. Read RX-payload: 1 – 32 bytes. A read operation always starts at byte 0. Payload is deleted from FIFO after it is read. Used in RX mode. Write TX-payload: 1 – 32 bytes. A write operation always starts at byte 0 used in TX payload. Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. Used for a PTX operation Reuse last transmitted payload. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission. Read RX payload width for the top R_RX_PAYLOAD in the RX FIFO. Note: Flush RX FIFO if the read value is larger than 32 bytes. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled using first in - first out principle. Write payload: 1– 32 bytes. A write operation always starts at byte 0. Used in TX mode. Disables AUTOACK on this specific packet. No Operation. Might be used to read the STATUS register a. The bits in the FEATURE register shown in Table 11. on page 53 have to be set. Table 10. Command set for the RF transceiver SPI The W_REGISTER and R_REGISTER commands operate on single or multi-byte registers. When accessing multi-byte registers read or write to the MSBit of LSByte first. You can terminate the writing before all bytes in a multi-byte register are written, leaving the unwritten MSByte(s) unchanged. For example, the LSByte of RX_ADDR_P0 can be modified by writing only one byte to the RX_ADDR_P0 register. The content of the status register is always read to MISO after a high to low transition on CSN. Revision 1.6 45 of 196 nRF24LE1 Product Specification Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low transition. The pipe information is unreliable if the STATUS register is read during an RFIRQ high to low transition. 3.5.3 Data FIFO The data FIFOs store transmitted payloads (TX FIFO) or received payloads that are ready to be clocked out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode. The following FIFOs are present in the RF transceiver: • • TX three level, 32 byte FIFO RX three level, 32 byte FIFO Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payloads for ACK packets to three different PTX operations. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO using the FLUSH_TX command. The RX FIFO in PRX can contain payloads from up to three different PTX operations and a TX FIFO in PTX can have up to three payloads stored. You can write to the TX FIFO using these three commands; W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands provide access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in PTX and PRX mode. This command provides access to the RX_PLD register. The payload in TX FIFO in a PTX is not removed if the MAX_RT IRQ is asserted. RX FIFO 32 byte 32 byte Data 32 byte RX FIFO Controller TX FIFO Controller Control SPI command decoder SPI Data Control TX FIFO Data 32 byte Data 32 byte 32 byte Figure 28. FIFO (RX and TX) block diagram You can read if the TX and RX FIFO are full or empty in the FIFO_STATUS register. TX_REUSE (also available in the FIFO_STATUS register) is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX. Revision 1.6 46 of 196 nRF24LE1 Product Specification 3.5.4 Interrupt The RF transceiver can send interrupts to the MCU. The interrupt (RFIRQ) is activated when TX_DS, RX_DR or MAX_RT are set high by the state machine in the STATUS register. RFIRQ is deactivated when the MCU writes '1' to the interrupt source bit in the STATUS register. The interrupt mask in the CONFIG register is used to select the IRQ sources that are allowed to activate RFIRQ. By setting one of the mask bits high, the corresponding interrupt source is disabled. By default all interrupt sources are enabled. Note: The 3 bit pipe information in the STATUS register is updated during the RFIRQ high to low transition. The pipe information is unreliable if the STATUS register is read during a RFIRQ high to low transition. Revision 1.6 47 of 196 nRF24LE1 Product Specification 3.6 Register map You can configure and control the radio (using read and write commands) by accessing the register map through the SPI. 3.6.1 Register map table All undefined bits in the table below are redundant. They are read out as '0'. Note: Addresses 18 to 1B are reserved for test purposes, altering them makes the chip malfunction. Address (Hex) 00 01 Mnemonic Bit Reset Value CONFIG Reserved MASK_RX_DR 7 6 0 0 MASK_TX_DS 5 0 MASK_MAX_RT 4 0 EN_CRC 3 1 CRCO 2 0 PWR_UP PRIM_RX 1 0 0 0 Type Description Configuration Register R/W Only '0' allowed R/W Mask interrupt caused by RX_DR 1: Interrupt not reflected on the RFIRQ 0: Reflect RX_DR as active low on RFIRQ R/W Mask interrupt caused by TX_DS 1: Interrupt not reflected on the RFIRQ 0: Reflect TX_DS as active low interrupt on RFIRQ R/W Mask interrupt caused by MAX_RT 1: Interrupt not reflected on RFIRQ 0: Reflect MAX_RT as active low on RFIRQ R/W Enable CRC. Forced high if one of the bits in the EN_AA is high R/W CRC encoding scheme '0' - 1 byte '1' – 2 bytes R/W 1: POWER UP, 0:POWER DOWN R/W RX/TX control 1: PRX, 0: PTX Enable ‘Auto Acknowledgment’ Function Disable this functionality to be compatible with nRF2401. EN_AA Enhanced ShockBurst™ Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 7:6 5 4 3 2 1 0 00 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W Only '00' allowed Enable auto acknowledgement data pipe 5 Enable auto acknowledgement data pipe 4 Enable auto acknowledgement data pipe 3 Enable auto acknowledgement data pipe 2 Enable auto acknowledgement data pipe 1 Enable auto acknowledgement data pipe 0 EN_RXADDR Reserved ERX_P5 ERX_P4 ERX_P3 ERX_P2 ERX_P1 ERX_P0 7:6 5 4 3 2 1 0 00 0 0 0 0 1 1 R/W R/W R/W R/W R/W R/W R/W Enabled RX Addresses Only '00' allowed Enable data pipe 5. Enable data pipe 4. Enable data pipe 3. Enable data pipe 2. Enable data pipe 1. Enable data pipe 0. 02 Revision 1.6 48 of 196 nRF24LE1 Product Specification Address (Hex) Mnemonic 03 SETUP_AW 04 Bit Reset Value Reserved AW 7:2 1:0 000000 11 SETUP_RETR ARDa 7:4 0000 ARC 3:0 0011 RF_CH Reserved RF_CH 7 6:0 0 0000010 RF_SETUP CONT_WAVE Reserved RF_DR_LOW 7 6 5 0 0 0 PLL_LOCK RF_DR_HIGH 4 3 0 1 RF_PWR 2:1 11 05 06 Revision 1.6 Type Description Setup of Address Widths (common for all data pipes) R/W Only '000000' allowed R/W RX/TX Address field width '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' – 5 bytes LSByte is used if address width is below 5 bytes Setup of Automatic Retransmission R/W Auto Retransmit Delay ‘0000’ – Wait 250µs ‘0001’ – Wait 500µs ‘0010’ – Wait 750µs …….. ‘1111’ – Wait 4000µs (Delay defined from end of transmission to start of next transmission)b R/W Auto Retransmit Count ‘0000’ –Re-Transmit disabled ‘0001’ – Up to 1 Re-Transmit on fail of AA …… ‘1111’ – Up to 15 Re-Transmit on fail of AA RF Channel R/W Only '0' allowed R/W Sets the frequency channel the RF Transceiver operates on RF Setup Register R/W Enables continuous carrier transmit when high. R/W Only '0' allowed R/W Set RF Data Rate to 250kbps. See RF_DR_HIGH for encoding. R/W Force PLL lock signal. Only used in test R/W Select between the high speed data rates. This bit is don’t care if RF_DR_LOW is set. Encoding: RF_DR_LOW, RF_DR_HIGH: ‘00’ – 1Mbps ‘01’ – 2Mbps ‘10’ – 250kbps ‘11’ – Reserved R/W Set RF output power in TX mode '00' – -18dBm '01' – -12dBm '10' – -6dBm '11' – 0dBm 49 of 196 nRF24LE1 Product Specification Address (Hex) 07 Mnemonic Bit Obsolete 0 Reset Value Type Don’t care STATUS Reserved RX_DR 7 6 0 0 R/W R/W TX_DS 5 0 R/W MAX_RT 4 0 R/W RX_P_NO 3:1 111 R TX_FULL 0 0 R OBSERVE_TX PLOS_CNT 7:4 0 R ARC_CNT 3:0 0 R RPD Reserved RPD 7:1 0 000000 0 R R 0A RX_ADDR_P0 39:0 0xE7E7E 7E7E7 0B RX_ADDR_P1 39:0 0C RX_ADDR_P2 7:0 0D RX_ADDR_P3 7:0 08 09 Revision 1.6 Description Status Register (In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) Only '0' allowed Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFOc. Write 1 to clear bit. Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. Maximum number of TX retransmits interrupt Write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable further communication. Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. Transmit observe register Count lost packets. The counter is overflow protected to 15, and discontinues at max until reset. The counter is reset by writing to RF_CH. Count retransmitted packets. The counter is reset when transmission of a new packet starts. Received Power Detector. This register is called CD (Carrier Detect) in the nRF24L01. The name is different in the RF transceiver due to the different input power level threshold for this bit. See section 3.3.4 on page 21. R/W Receive address data pipe 0. 5 Bytes maximum length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) 0xC2C2C R/W Receive address data pipe 1. 5 Bytes maximum 2C2C2 length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) 0xC3 R/W Receive address data pipe 2. Only LSB. MSBytes are equal to RX_ADDR_P1 39:8 0xC4 R/W Receive address data pipe 3. Only LSB. MSBytes are equal to RX_ADDR_P139:8 50 of 196 nRF24LE1 Product Specification Address (Hex) 0E Mnemonic Bit RX_ADDR_P4 7:0 Reset Value 0xC5 0F RX_ADDR_P5 7:0 0xC6 10 TX_ADDR 39:0 0xE7E7E 7E7E7 R/W Transmit address. Used for a PTX operation only. (LSByte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX operation with Enhanced ShockBurst™ enabled. 11 RX_PW_P0 Reserved RX_PW_P0 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P1 Reserved RX_PW_P1 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P2 Reserved RX_PW_P2 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P3 Reserved RX_PW_P3 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P4 Reserved 7:6 00 R/W Only '00' allowed 12 13 14 15 Revision 1.6 Type Description R/W Receive address data pipe 4. Only LSB. MSBytes are equal to RX_ADDR_P[139:8] R/W Receive address data pipe 5. Only LSB. MSBytes are equal to RX_ADDR_P[139:8] 51 of 196 nRF24LE1 Product Specification Address (Hex) Mnemonic Bit RX_PW_P4 5:0 Reset Value 0 RX_PW_P5 Reserved RX_PW_P5 7:6 5:0 00 0 FIFO_STATUS Reserved TX_REUSE 7 6 0 0 TX_FULL 5 0 TX_EMPTY 4 1 Reserved RX_FULL 3:2 1 00 0 RX_EMPTY 0 1 N/A ACK_PLD 255:0 X N/A TX_PLD 255:0 X 16 17 Revision 1.6 Type Description R/W Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes FIFO Status Register R/W Only '0' allowed R Used for a PTX operation Pulse the rfce high for at least 10µs to Reuse last transmitted payload. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX R TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. R TX FIFO empty flag. 1: TX FIFO empty. 0: Data in TX FIFO. R/W Only '00' allowed R RX FIFO full flag. 1: RX FIFO full. 0: Available locations in RX FIFO. R RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. W Written by separate SPI command ACK packet payload to data pipe number PPP given in SPI command. Used in RX mode only. Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled first in first out. W Written by separate SPI command TX data payload register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only. 52 of 196 nRF24LE1 Product Specification Address (Hex) N/A Mnemonic Bit RX_PLD 255:0 Reset Value X DYNPD Reserved DPL_P5 7:6 5 0 0 DPL_P4 4 0 DPL_P3 3 0 DPL_P2 2 0 DPL_P1 1 0 DPL_P0 0 0 FEATURE Reserved EN_DPL EN_ACK_PAYd EN_DYN_ACK 7:3 2 1 0 0 0 0 0 1C 1D Type Description R Read by separate SPI command. RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX channels share the same FIFO. Enable dynamic payload length R/W Only ‘00’ allowed R/W Enable dynamic payload length data pipe 5. (Requires EN_DPL and ENAA_P5) R/W Enable dynamic payload length data pipe 4. (Requires EN_DPL and ENAA_P4) R/W Enable dynamic payload length data pipe 3. (Requires EN_DPL and ENAA_P3) R/W Enable dynamic payload length data pipe 2. (Requires EN_DPL and ENAA_P2) R/W Enable dynamic payload length data pipe 1. (Requires EN_DPL and ENAA_P1) R/W Enable dynamic payload length data pipe 0. (Requires EN_DPL and ENAA_P0) R/W R/W R/W R/W R/W Feature Register Only ‘00000’ allowed Enables Dynamic Payload Length Enables Payload with ACK Enables the W_TX_PAYLOAD_NOACK command a. Please take care when setting this parameter. If the ACK payload is more than 15 byte in 2 Mbps mode the ARD must be 500 µs or more, if the ACK payload is more than 5 byte in 1Mbps mode the ARD must be 500 µs or more. In 250 kbps mode (even when the payload is not in ACK) the ARD must be 500µs or more. b. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode for a minimum of 250 µs, but it stays in RX mode to the end of the packet if that is longer than 250 µs. Then it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and then retransmits the packet. c. The RX_DR IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt should be: 1) read payload through SPI, 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from step 1). d. If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Payload Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive the ACK packets with payloads. If the ACK payload is more than 15 byte in 2 Mbps mode the ARD must be 500 µs or more, and if the ACK payload is more than 5 byte in 1 Mbps mode the ARD must be 500 µs or more. In 250 kbps mode (even when the payload is not in ACK) the ARD must be 500 µs or more. Table 11. Register map of the RF transceiver Revision 1.6 53 of 196 nRF24LE1 Product Specification 4 MCU The nRF24LE1 contains a fast 8-bit MCU, which executes the normal 8051 instruction set. The architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Most of the one-byte instructions are performed in a single cycle. The MCU uses one clock per cycle. This leads to a performance improvement rate of 8.0 (in terms of MIPS) with respect to legacy 8051 devices. The original 8051 had a 12-clock architecture. A machine cycle needed 12 clocks and most instructions were either one or two machine cycles. Except for MUL and DIV instructions, the 8051 used either 12 or 24 clocks for each instruction. Each cycle in the 8051 also used two memory fetches. In many cases, the second fetch was a dummy, and extra clocks were wasted. Table 12. shows the speed advantage compared to a legacy 8051. A speed advantage of 12 implies that the instruction is executed twelve times faster. The average speed advantage is 8.0. However, the real speed improvement seen in any system depends on the instruction mix. Speed advantage 24 12 9.6 8 6 4.8 4 3 Average: 8.0 Number of instructions 1 27 2 16 44 1 18 2 Sum: 111 Number of opcodes 1 83 2 38 89 2 31 9 Sum: 255 Table 12. Speed advantage summary Revision 1.6 54 of 196 nRF24LE1 Product Specification 4.1 Block diagram Timer 0 and 1 Memory control Internal Flash and RAM PC DPTR DPTR1 TL0 TL1 TH0 TH1 TCON TMOD Timer inputs DPS Timer 2 Memory/SFR Interface TL2 RAM/SFR control T2CON TH2 CRCL CRCH CCL1 CCH1 SP CCL2 CCH2 CCL3 CCH3 ALU ACC B PSW ISR IP0 IP1 IEN0 IEN1 Interrupt inputs MDU MD0 MD2 MD4 ARCON SERIAL 0 S0CON S0BUF MD1 MD3 MD5 GPIO P0, P1, P2, P3 Figure 29. MCU block diagram 4.2 • • • • • • Features Control Unit X 8-bit instruction decoder X Reduced instruction cycle time (up to 12 times in respect to standard 80C51) Arithmetic-Logic Unit X 8-bit arithmetic and logical operations X Boolean manipulations X 8 x 8 bit multiplication and 8 / 8 bit division Multiplication-Division Unit X 16 x 16 bit multiplication X 32 / 16 bit and 16 / 16 bit division X 32-bit normalization X 32-bit L/R shifting Three 16-bit Timers/Counters X 80C51-like Timer 0 & 1 X 80515-like Timer 2 Compare/Capture Unit, dedicated to Timer 2 X Software control capture Full Duplex Serial Interfaces X Serial 0 (80C51-like) X Synchronous mode, fixed baud rate Revision 1.6 55 of 196 Serial 0 Interface Port Port Port Port 0 1 2 3 nRF24LE1 Product Specification 8-bit UART mode, variable baud rate 9-bit UART mode, fixed baud rate X 9-bit UART mode, variable baud rate X Baud Rate Generator Interrupt Controller X Four Priority Levels with 13 interrupt sources Memory interface X 16-bit address bus X Dual Data Pointer for fast data block transfer Hardware support for software debug X X • • • 4.3 Functional description 4.3.1 Arithmetic Logic Unit (ALU) The Arithmetic Logic Unit (ALU) provides 8-bit division, 8-bit multiplication, and 8-bit addition with or without carry. The ALU also provides 8-bit subtraction with borrow and some bitwise logic operations, that is, logical AND, OR, Exclusive OR or NOT. All operations are unsigned integer operations. Additionally, the ALU can increment or decrement 8-bit registers. For accumulator only, it can rotate left or right through carry or not, swap nibbles, clear or complement bits and perform a decimal adjustment. The ALU is handled by three registers, which are memory mapped as special function registers. Operands for operations may come from accumulator ACC, register B or from outside of the unit. The result may be stored in accumulator ACC or may be driven outside of the unit. The control register, that contains flags such as carry, overflow or parity, is the PSW (Program Status Word) register. The nRF24LE1 also contains an on-chip co-processor MDU (Multiplication Division Unit). This unit enables 32-bit division, 16-bit multiplication, shift and normalize operations, see chapter 14 on page 124 for details. 4.3.2 Instruction set summary All instructions are binary code compatible and perform the same functions as they do within the legacy 8051 processor. The following tables give a summary of the instruction set with the required corresponding clock cycles. Mnemonic ADD A,Rn ADD A,direct ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A, direct ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A, direct Description Add register to accumulator Add directly addressed data to accumulator Add indirectly addressed data to accumulator Add immediate data to accumulator Add register to accumulator with carry Add directly addressed data to accumulator with carry Add indirectly addressed data to accumulator with carry Add immediate data to accumulator with carry Subtract register from accumulator with borrow Subtract directly addressed data from accumulator with borrow SUBB A, @Ri Subtract indirectly addressed data from accumulator with borrow SUBB A, #data Subtract immediate data from accumulator with borrow INC A Increment accumulator Revision 1.6 56 of 196 Code 0x28-0x2F 0x25 0x26-0x27 0x24 0x38-0x3F 0x35 0x36-0x37 0x34 0x98-0x9F 0x95 Bytes Cycles 1 1 2 2 1 2 2 2 1 1 2 2 1 2 2 2 1 1 2 2 0x96-0x97 1 2 0x94 0x04 2 1 2 1 nRF24LE1 Product Specification Mnemonic INC Rn INC direct INC @Ri INC DPTR DEC A DEC Rn DEC direct DEC @Ri MUL AB DIV DA A Description Increment register Increment directly addressed location Increment indirectly addressed location Increment data pointer Decrement accumulator Decrement register Decrement directly addressed location Decrement indirectly addressed location Multiply A and B Divide A by B Decimal adjust accumulator Code 0x08-0x0F 0x05 0x06-0x07 0xA3 0x14 0x18-0x1F 0x15 0x16-0x17 0xA4 0x84 0xD4 Bytes Cycles 1 2 2 3 1 3 1 1 1 1 1 2 2 3 1 3 1 5 1 5 1 1 Table 13. Arithmetic operations Mnemonic ANL A, Rn ANL A,direct ANL A,@Ri ANL A,#data ANL direct,A ANL direct,#data ORL A,Rn ORL A,direct ORL A,@Ri ORL A,#data ORL direct,A ORL direct,#data XRL A,Rn XRL A, direct XRL A,@Ri XRL A,#data XRL direct,A XRL direct,#data CLR A CPL A RL A RLC A RR A RRC A SWAP A Description AND register to accumulator AND directly addressed data to accumulator AND indirectly addressed data to accumulator AND immediate data to accumulator AND accumulator to directly addressed location AND immediate data to directly addressed location OR register to accumulator OR directly addressed data to accumulator OR indirectly addressed data to accumulator OR immediate data to accumulator OR accumulator to directly addressed location OR immediate data to directly addressed location Exclusive OR register to accumulator Exclusive OR indirectly addressed data to accumulator Exclusive OR indirectly addressed data to accumulator Exclusive OR immediate data to accumulator Exclusive OR accumulator to directly addressed location Exclusive OR immediate data to directly addressed location Clear accumulator Complement accumulator Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within the accumulator Code 0x58-0x5F 0x55 0x56-0x57 0x54 0x52 0x53 1 2 1 2 2 3 Cycles 1 2 2 2 3 4 0x48-0x4F 0x45 0x46-0x47 0x44 0x42 0x43 1 2 1 2 2 3 1 2 2 2 3 4 0x68-0x6F 0x66-0x67 1 2 1 2 0x66-0x67 1 2 0x64 0x62 2 2 2 3 0x63 3 4 0xE4 0xF4 0x23 0x33 0x03 0x13 0xC4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 14. Logic operations Revision 1.6 57 of 196 Bytes nRF24LE1 Product Specification Mnemonic MOV A,Rn MOV A,direct MOV A,@Ri Description Move register to accumulator Move directly addressed data to accumulator Move indirectly addressed data to accumulator MOV A,#data Move immediate data to accumulator MOV Rn,A Move accumulator to register MOV Rn,direct Move directly addressed data to register MOV Rn,#data Move immediate data to register MOV direct,A Move accumulator to direct MOV direct,Rn Move register to direct MOV Move directly addressed data to directly directl,direct2 addressed location MOV Move indirectly addressed data to directly direct,@Ri addressed location MOV Move immediate data to directly addressed direct,#data location MOV @Ri,A Move accumulator to indirectly addressed location MOV Move directly addressed data to indirectly @Ri,direct addressed location MOV Move immediate data to indirectly addressed @Ri,#data location MOV Load data pointer with a 16-bit immediate DPTR,#datal6 MOVC Load accumulator with a code byte relative A,@A+DPTR to DPTR MOVC Load accumulator with a code byte relative A,@A+PC to PC MOVX A,@Ri Movea external RAM (8-bit addr) to accumulator MOVX Movea external RAM (16-bit addr) to A,@DPTR accumulator MOVX @Ri,A Movea accumulator to external RAM (8-bit addr) MOVX Movea accumulator to external RAM (16-bit @DPTR,A addr) PUSH direct Push directly addressed data onto stack POP direct Pop directly addressed location from stack XCH A,Rn Exchange register with accumulator XCH A,direct Exchange directly addressed location with accumulator XCH A,@Ri Exchange indirect RAM with accumulator XCHD A,@Ri Exchange low-order nibbles of indirect and accumulator Code 0xE8-0xEF 0xE5 0xE6-0xE7 Bytes 1 2 1 Cycles 1 2 2 0x74 0xF8-0xFF 0xA8-0xAF 0x78-0x7F 0xF5 0x88-0x8F 0x85 2 1 2 2 2 2 3 2 2 4 2 3 3 4 0x86-0x87 2 4 0x75 3 3 0xF6-0xF7 1 3 0xA6-0xA7 2 5 0x76-0x77 2 3 0x90 3 3 0x93 1 3 0x83 1 3 0xE2-0xE3 1 4 0xE0 1 4 0xF2-0xF3 1 5 0xF0 1 5 0xC0 0xD0 0xC8-0xCF 0xC5 2 2 1 2 4 3 2 3 0xC6-0xC7 0xD6-0xD7 1 1 3 3 a. The MOVX instructions perform one of two actions depending on the state of pmw bit (pcon.4). Table 15. Data transfer operations Revision 1.6 58 of 196 nRF24LE1 Product Specification Mnemonic ACALL addr11 LCALL addr16 RET RETI AJMP addr11 LJMP addrl6 SJMP rel JMP @A+DPTR JZ rel JNZ rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel CJNE A, direct, rel CJNE A,#data,rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel NOP Description Absolute subroutine call Long subroutine call Code xxx10001b 0x12 Bytes 2 3 Cycles 6 6 Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative address) Jump indirect relative to the DPTR 0x22 0x32 xxx00001b 0x02 0x80 0x73 1 1 2 3 2 1 4 4 3 4 3 2 Jump if accumulator is zero Jump if accumulator is not zero Jump if carry flag is set Jump if carry flag is not set Jump if directly addressed bit is set Jump if directly addressed bit is not set Jump if directly addressed bit is set and clear bit Compare directly addressed data to accumulator and jump if not equal Compare immediate data to accumulator and jump if not equal Compare immediate data to register and jump if not equal Compare immediate data to indirect addressed value and jump if not equal Decrement register and jump if not zero Decrement directly addressed location and jump if not zero No operation 0x60 0x70 0x40 0x50 0x20 0x30 0x10 0xB5 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 4 0xB4 3 4 0xB8-0xBF 3 4 0xB6-B7 3 4 0xD8-DF 0xD5 2 3 3 4 0x00 1 1 Table 16. Program branches Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,C Description Clear carry flag Clear directly addressed bit Set carry flag Set directly addressed bit Complement carry flag Complement directly addressed bit AND directly addressed bit to carry flag AND complement of directly addressed bit to carry OR directly addressed bit to carry flag OR complement of directly addressed bit to carry Move directly addressed bit to carry flag Move carry flag to directly addressed bit Table 17. Boolean manipulation Revision 1.6 59 of 196 Code 0xC3 0xC2 0xD3 0xD2 0xB3 0xB2 0x82 0xB0 0x72 0xA0 0xA2 0x92 Bytes 1 2 1 2 1 2 2 2 2 2 2 2 Cycles 1 3 1 3 1 3 2 2 2 2 2 3 nRF24LE1 Product Specification 4.3.3 Opcode map Opcode 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H Revision 1.6 Mnemonic NOP AJMP addr11 JUMP addrl6 RRA INCA INC direct INC @R0 INC @R1 INC R0 INC R1 INC R2 INC R3 INC R4 INC R5 INC R6 INC R7 JBC bit, rel ACALL addr11 LCALL add r16 RRC A DEC A DEC direct DEC @R0 DEC @R1 DEC R0 DEC R1 DEC R2 DECR3 DECR4 DECR5 DECR6 DECR7 JB bit, rel AJMP addr11 RET RL A ADD A, #data ADD A, direct ADD A,@R0 ADD A,@R1 ADD A,R0 ADD A,R1 ADD A,R2 ADD A,R3 ADD A,R4 ADD A,R5 ADD A,R6 ADD A,R7 JNB bit, rel ACALL addr11 Opcode 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H Mnemonic ANL A,@R0 ANL A,@R1 ANL A,R0 ANL A,R1 ANL A,R2 ANL A,R3 ANL A,R4 ANL A,R5 ANL A,R6 ANL A,R7 JZ rel AJMP addr11 XRL direct, A XRL direct, #data XRL A, #data XRL A,direct XRLA,@R0 XRL A,@R1 XRL A,R0 XRL A,R1 XRL A,R2 XRL A,R3 XRL A,R4 XRL A,R5 XRL A,R6 XRL A,R7 JNZ rel ACALL addr11 ORL C, bit JMP @A+DPTR MOV A, #data MOV direct, #data MOV @R0,#data MOV @R1, #data MOV R0, #data MOV R1, #data MOV R2, #data MOV R3, #data MOV R4, #data MOV R5, #data MOV R6, #data MOV R7, #data SJMP rel AJMP addr11 ANL C, bit MOVC A,@A+PC DIV AB MOV direct, direct MOV direct,@R0 MOV direct,@R1 60 of 196 Opcode ACH ADH AE AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH Mnemonic MOV R4,direct MOV R5,direct MOV R6,direct MOV R7,direct ANL C,/bit ACALL addr11 CPL bit CPLC CJNE A,#data,rel CJNE A, direct, rel CJNE @R0,#data,rel CJNE @R1, #data,rel CJNE R0, #data,rel CJNE R1,#data,rel CJNE R2,#data,rel CJNE R3,#data,rel CJNE R4,#data,rel CJNE R5,#data,rel CJNE R6,#data,rel CJNE R7,#data,rel PUSH direct AJMP addr11 CLR bit CLR C SWAP A XCH A, direct XCH A,@R0 XCH A,@R1 XCH A,R0 XCH A,R1 XCH A,R2 XCHA,R3 XCH A,R4 XCH A,R5 XCH A,R6 XCHA,R7 POP direct ACALL addr11 SETB bit SETB C DAA DJNZ direct, rel XCHDA,@R0 XCHD A,@R1 DJNZ R0,rel DJNZ R1,rel DJNZ R2,rel DJNZ R3,rel DJNZ R4,rel DJNZ R5,rel nRF24LE1 Product Specification Opcode 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H Mnemonic RETI RLC A ADDC A,#data ADDC A, direct ADDC A,@R0 ADDC A,@R1 ADDC A,R0 ADDC A,R1 ADDC A,R2 ADDC A,R3 ADDC A,R4 ADDC A,R5 ADDC A,R6 ADDC A,R7 JC rel AJMP addr11 ORL direct, A ORL direct, #data ORL A, #data ORL A, direct ORL A,@R0 ORL A,@R1 ORL A,R0 ORL A,R1 ORL A,R2 ORLA,R3 ORL A,R4 ORL A,R5 ORL A,R6 ORLA,R7 JNC rel ACALL addr11 ANL direct, A ANL direct, #data ANL A, #data ANL A, direct Opcode 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH Mnemonic MOV direct,R0 MOV direct,R1 MOV direct,R2 MOV direct,R3 MOV direct,R4 MOV direct, R5 MOV direct,R6 MOV direct,R7 MOV DPTR, #datal6 ACALL addr11 MOV bit, C MOVCA,@A+DPTR SUBB A, #data SUBB A, direct SUBB A,@R0 SUBB A,@R1 SUBB A, R0 SUBB A,R1 SUBB A,R2 SUBB A,R3 SUBB A,R4 SUBB A,R5 SUBB A,R6 SUBB A,R7 ORL C,/bit AJMP addr11 MOV C, bit INC DPTR MUL AB MOV @R0,direct MOV @R1,direct MOV R0,direct MOV R1,direct MOV R2,direct MOV R3,direct Table 18. Opcode map Revision 1.6 61 of 196 Opcode DE DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH Mnemonic DJNZ R6,rel DJNZ R7,rel MOVX A,@DPTR AJMP addr11 MOVX A,@R0 MOVX A,@R1 CLR A MOVA, direct MOVA,@R0 MOV A,@R1 MOV A,R0 MOV A,R1 MOV A,R2 MOV A,R3 MOV A,R4 MOV A,R5 MOV A,R6 MOV A,R7 MOVX @DPTR,A ACALL addr11 MOVX @R0,A MOVX @R1,A CPL A MOV direct, A MOV @R0,A MOV @R1,A MOV R0,A MOV R1,A MOV R2,A MOV R3,A MOV R4,A MOV R5,A MOV R6,A MOV R7,A nRF24LE1 Product Specification 5 Memory and I/O organization The MCU has 64 kB of separate address space for code and data, an area of 256 byte for internal data (IRAM) and an area of 128 byte for Special Function Registers (SFR). The nRF24LE1 memory blocks has a default setting of 16 kB program memory (flash), 1 kB of data memory (SRAM) and 2 blocks (1 kB standard endurance/512 bytes extended endurance) of non-volatile data memory (flash), see default memory map in Figure 30. Read- or write access to the grey areas in this figure may behave unpredictably. Data Space (XDATA, accessible by MOVX) Code Space (accessible by MOVC) 0xFFFF 0xFFFF NV Data Memory 512 byte 0xFE00 NV Data Memory 512 byte 0xFC00 NV Data Memory 256 byte Extended endurance NV Data Memory 256 byte Extended endurance IRAM SFR Accessible by indirect addressing only Accessible by direct addressing only 0xFF 0x3FFF 0x0200 0x0000 0x80 0x7F Program memory (Flash) 16 kbyte 0x0400 0x80 Accessible by direct and indirect addressing DataNonRetentive (SRAM) 512 byte DataRetentive (SRAM) 512 byte 0xFF 0x0000 Special Function Registers 0x00 Figure 30. Memory map The lower 128 bytes of the IRAM contains work registers (0x00 - 0x1F) and bit addressable memory (0x20 - 0x2F). The upper half can only be accessed by indirect addressing. The lowest 32 bytes of the IRAM form four banks, each consisting of eight registers (R0 - R7). Two bits of the program memory status word (PSW) select which bank is used. The next 16 bytes of memory form a block of bit-addressable memory, accessible through bit addresses 0x00 - 0x7F. Revision 1.6 62 of 196 nRF24LE1 Product Specification 5.1 PDATA memory addressing The nRF24LE1 supports PDATA (Paged Data memory) addressing into data space. One page (256 bytes) can be accessed by an indirect addressing scheme through registers R0 and R1 (@R0, @R1). The MPAGE register controls the start address of the PDATA page: Addr 0xC9 Bit 7:0 R/W R/W Function Start address of the PDATA page Reset value: 0x00 Table 19. MPAGE register MPAGE sets the upper half of the 16 bit address space. For example, setting MPAGE to 0x80 starts PDATA from address 0x8000. 5.2 MCU Special Function Registers 5.2.1 Accumulator - ACC Accumulator is used by most of the MCU instructions to hold the operand and to store the result of an operation. The mnemonics for accumulator specific instructions refer to accumulator as A, not ACC. Address 0xE0 bit7 acc.7 bit6 acc.6 bit5 acc.5 bit4 acc.4 bit3 acc.3 bit2 acc.2 bit1 acc.1 bit0 acc.0 Table 20. ACC register 5.2.2 B Register – B The B register is used during multiplying and division instructions. It can also be used as a scratch-pad register to hold temporary data. Address 0xF0 bit7 b.7 bit6 b.6 bit5 b.5 bit4 b.4 bit3 b.3 Table 21. B register Revision 1.6 63 of 196 bit2 b.2 bit1 b.1 bit0 b.0 nRF24LE1 Product Specification 5.2.3 Program Status Word Register - PSW The PSW register contains status bits that reflect the current state of the MCU. Note: The Parity bit can only be modified by hardware upon the state of ACC register. Address Bit Name Description 0xD0 7 cy Carry flag: Carry bit in arithmetic operations and accumulator for Boolean operations. 6 ac Auxiliary Carry flag: Set if there is a carry-out from 3rd bit of Accumulator in BCD operations 5 f0 General purpose flag 0 4-3 rs Register bank select, bank 0..3 (0x00-0x07, 0x08-0x0f, 0x10-0x17, 0x180x1f) 2 ov Overflow flag: Set if overflow in Accumulator during arithmetic operations 1 f1 General purpose flag 1 0 p Parity flag: Set if odd number of ‘1’ in ACC. Table 22. PSW register 5.2.4 Stack Pointer – SP This register points to the top of stack in internal data memory space. It is used to store the return address of a program before executing interrupt routine or subprograms. The SP is incremented before executing PUSH or CALL instruction and it is decremented after executing POP or RET(I) instruction (it always points to the top of stack). Address 0x81 Register name SP Table 23. SP register 5.2.5 Data Pointer – DPH, DPL Address 0x82 0x83 Register name DPL DPH Table 24. Data Pointer register (DPH:DPL) The Data Pointer Registers can be accessed through DPL and DPH. The actual data pointer is selected by DPS register. These registers are intended to hold 16-bit address in the indirect addressing mode used by MOVX (move external memory), MOVC (move program memory) or JMP (computed branch) instructions. They may be manipulated as 16-bit register or as two separate 8-bit registers. DPH holds higher byte and DPL holds lower byte of indirect address. It is generally used to access external code or data space (for example, MOVC A, @A+DPTR or MOV A, @DPTR respectively). Revision 1.6 64 of 196 nRF24LE1 Product Specification 5.2.6 Data Pointer 1 – DPH1, DPL1 Address 0x84 0x85 Register name DPL1 DPH1 Table 25. Data Pointer 1 register (DPH1:DPL1) The Data Pointer Register 1 can be accessed through DPL1 and DPH1. The actual data pointer is selected by DPS register. These registers are intended to hold 16-bit address in the indirect addressing mode used by MOVX (move external memory), MOVC (move program memory) or JMP (computed branch) instructions. They may be manipulated as 16-bit register or as two separate 8-bit registers. DPH1 holds higher byte and DPL1 holds lower byte of indirect address. It is generally used to access external code or data space (for example, MOVC A,@A+DPTR or MOV A,@DPTR respectively). The Data Pointer 1 is an extension to the standard 8051 architecture to speed up block data transfers. 5.2.7 Data Pointer Select Register – DPS The MCU contains two Data Pointer registers. Both of them can be used as 16-bits address source for indirect addressing. The DPS register serves for selecting active data pointer register. Address Bit Name 0x92 7:1 0 dps Description Not used Data Pointer Select. 0: select DPH:DPL, 1: select DPH1:DPL1 Table 26. DPS register 5.2.8 PCON register The PCON register is used to control the Program Memory Write Mode and Serial Port 0 baud rate doubler. Address Bit Name Description 0x87 7 smod Serial port 0 baud rate select, see Table 91. on page 151 and Table 93. on page 156. 6 gf3 General purpose flag 3 5 gf2 General purpose flag 2 4 pmw Program memory write mode: 1: MOVX instructions will access memory code space 0: MOVX instructions will access memory data space 3 gf1 General purpose flag 1 2 gfo General purpose flag 0 1 Not used. This bit must always be cleared. Always read as 0. 0 Not used. This bit must always be cleared. Always read as 0. Table 27. PCON register Revision 1.6 65 of 196 nRF24LE1 Product Specification 5.2.9 Special Function Register Map The map of Special Function Registers is shown in Table 28. Undefined locations must not be read or written. Address 0xF8-0xFF X000 FSR X001 FPCR X010 FCR X011 Reserved 0xF0-0xF7 B 0xE8-0xEF RFCON MD0 MD1 MD2 0xE0-0xE7 ACC W2CON1 W2CON0 Reserved 0xD8-0xDF ADCON W2SADR W2DAT COMPCON 0xD0-0xD7 PSW ADCCON ADCCON ADCCON1 3 2 0xC8-0xCF T2CON MPAGE CRCL CRCH 0xC0-0xC7 IRCON CCEN CCL1 CCH1 0xB8-0xBF IEN1 IP1 S0RELH Reserved 0xB0-0Xb7 P3 RSTREA PWM- RTC2CON S CON 0xA8-0xAF IEN0 IP0 S0RELL RTC2CPT0 1 0xA0-0xA7 P2 PWMDC PWMDC CLKCTRL 0 1 0x98-0x9F S0CON S0BUF Reserved Reserved 0x90-0x97 P1 free DPS P0DIR 0x88-0x8F TCON TMOD TL0 TL1 0x80-0x87 P0 SP DPL DPH X100 X101 SPIMCON0 SPIMCON1 X110 SPIMSTAT X111 SPIMDAT MD3 MD4 MD5 ARCON SPIRCON0 SPIRCON1 SPIRSTAT SPIRDAT POFCON CCPDATIA CCPCCPDATO DATIB ADCDATH ADCDATL RNGCTL RNGDAT TL2 TH2 WUOPC1 WUOPC0 CCL2 CCH2 CCL3 CCH3 SPISCON0 SPISSTAT SPISDAT RTC2CMP0 RTC2CMP1 RTC2CPT 00 RTC2CPT10 CLKLFC- OPMCON WDSV TRL PWRDWN WUCON INTEXP MEMCON Reserved P1DIR TH0 DPL1 Reserved P2DIR TH1 DPH1 P0CON P3DIR Reserved Reserved P1CON P2CON P3CON Table 28. Special Function Registers locations The registers in the X000 column in B register are both byte and bit addressable. The other registers are only byte addressable. Revision 1.6 66 of 196 nRF24LE1 Product Specification 5.2.10 Special Function Registers reset values Register name Address ACC ADCCON1 ADCCON2 ADCCON3 ADCDATH ADCDATL ARCON B CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CCPDATIA CCPDATIB CCPDATO CLKLFCTRL CLKCTRL COMPCON CRCH CRCL DPH DPL DPH1 DPL1 DPS FCR FPCR FSR IEN0 IEN1 INTEXP IP0 IP1 IRCON MD0 MD1 MD2 MD3 MD4 MD5 MEMCON MPAGE OPMCON P0 P0CON P0DIR Revision 1.6 0xE0 0xD3 0xD2 0xD1 0xD4 0xD5 0xEF 0xF0 0xC1 0xC3 0xC5 0xC7 0xC2 0xC4 0xC6 0xDD 0xDE 0xDF 0xAD 0xA3 0xDB 0xCB 0xCA 0x83 0x82 0x85 0x84 0x92 0xFA 0xF9 0xF8 0xA8 0xB8 0xA6 0xA9 0xB9 0xC0 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xA7 0xC9 0xAE 0x80 0x9E 0x93 Reset value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x10 0xFF Description Accumulator ADC Configuration Register 1 ADC Configuration Register 2 ADC Configuration Register 3 ADC Data high byte ADC Data low byte Arithmetic Control Register B Register Compare/Capture Enable Register Compare/Capture Register 1, high byte Compare/Capture Register 2, high byte Compare/Capture Register 3, high byte Compare/Capture Register 1, low byte Compare/Capture Register 2, low byte Compare/Capture Register 3, low byte Encryption/Decryption accelerator Data In Register A Encryption/Decryption accelerator Data In Register B Encryption/Decryption accelerator Data Out Register 32 kHz (CLKLF) control Clock control Comparator Control Register Compare/Reload/Capture Register, high byte Compare/Reload/Capture Register, low byte Data Pointer High 0 Data Pointer Low 0 Data Pointer High 1 Data Pointer Low 1 Data Pointer Select Register Flash Command Register Flash Protect Configuration Register Flash Status Register Interrupt Enable Register 0 Interrupt Priority Register / Enable Register 1 Interrupt Expander Register Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Memory Configuration Register Start address of the PDATA page Operational Mode Control Port 0 value Port 0 Configuration Register Port 0 pin direction control 67 of 196 nRF24LE1 Product Specification Register name Address P1 P1CON P1DIR P2 P2CON P2DIR P3 P3CON P3DIR POFCON PSW PWMCON PWMDC0 PWMDC1 PWRDWN RFCON RNGCTL RNGDAT RSTREAS RTC2CMP0 RTC2CMP1 RTC2CON RTC2CPT00 RTC2CPT01 RTC2CPT10 S0BUF S0CON S0RELH S0RELL SP SPIMCON0 SPIMCON1 SPIMDAT SPIMSTAT SPIRCON0 SPIRCON1 SPIRDAT SPIRSTAT SPISCON0 SPISDAT SPISSTAT T2CON TCON TH0 TH1 TH2 TL0 TL1 TL2 TMOD W2CON0 Revision 1.6 0x90 0x9F 0x94 0xA0 0x97 0x95 0xB0 0x8F 0x96 0xDC 0xD0 0xB2 0xA1 0xA2 0xA4 0xE8 0xD6 0xD7 0xB1 0xB4 0xB5 0xB3 0xB6 0xAB 0xAC 0x99 0x98 0xBA 0xAA 0x81 0xFC 0xFD 0xFF 0xFE 0xE4 0xE5 0xE7 0xE6 0xBC 0xBF 0xBE 0xC8 0x88 0x8C 0x8D 0xCD 0x8A 0x8B 0xCC 0x89 0xE2 Reset value 0xFF 0x10 0xFF 0xFF 0x10 0xFF 0xFF 0x10 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x40 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x03 0xD9 0x07 0x02 0x0F 0x00 0x03 0x01 0x0F 0x00 0x03 0xF0 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 Description Port 1 value Port 1 Configuration Register Port 1 pin direction control Port 2 value Port 2 Configuration Register Port 2 pin direction control Port 3 value Port 3 Configuration Register Port 3 pin direction control Power-fail Comparator Configuration Register Program Status Word PWM Configuration Register PWM Duty Cycle for channel 0 PWM Duty Cycle for channel 1 Power-down control RF Transceiver Control Register Random Number Generator Control Register Random Number Generator Data Register Reset Reason Register RTC2 Compare Value Register 0 RTC2 Compare Value Register 1 RTC2 Configuration Register RTC2 Capture Value Register 00 RTC2 Capture Value Register 01 RTC2 Capture Value Register 10 Serial Port 0, Data Buffer Serial Port 0, Control Register Serial Port 0, Reload Register, high byte Serial Port 0, Reload Register, low byte Stack Pointer SPI Master Configuration Register 0 SPI Master Configuration Register 1 SPI Master Data Register SPI Master Status Register RF Transceiver SPI Master Configuration Register 0 RF Transceiver SPI Master Configuration Register 1 RF Transceiver SPI Master Data Register RF Transceiver SPI Master Status Register SPI Slave Configuration Register 0 SPI Slave Data Register SPI Slave Status Register Timer 2 Control Register Timer/Counter Control Register Timer 0, high byte Timer 1, high byte Timer 2, high byte Timer 0, low byte Timer 1, low byte Timer 2, low byte Timer Mode Register 2-Wire Configuration Register 0 68 of 196 nRF24LE1 Product Specification Register name Address W2CON1 W2DAT W2SADR ADCON WDSW WUCON WUOPC0 WUOPC1 0xE1 0xDA 0xD9 0xD8 0xAF 0xA5 0xCF 0xCE Reset value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Description 2-Wire Configuration Register 1/Status Register 2-Wire Data Register 2-Wire Slave Address Register Serial Port 0 Baud Rate Select register (only adcon.7 bit used) Watchdog Start Value Register Wakeup configuration register Wakeup On Pin Configuration Register 0 Wakeup On Pin Configuration Register 1 Table 29. Special Function Registers reset values Revision 1.6 69 of 196 nRF24LE1 Product Specification 6 Flash memory This section describes the operation of the embedded flash memory. MCU can read and write the memory and under special circumstances the MCU can also perform erase and write operations, for instance, when performing a firmware upgrade. The Flash memory is configured and programmed through an external SPI slave interface. After programming, read and write operations from the external interfaces can be disabled for code protection. 6.1 • • • • • • • • • • • 6.2 Features 16 kB code memory 1k NV data memory Page size 512 bytes for NV data memory and program memory Two pages of 256 bytes each for extended endurance memory 32 pages of main block + 1 InfoPage Endurance minimum 1000 write/erase cycles Extended endurance memory, minimum 20000 write/erase cycles Direct SPI programmable Configurable MCU write protection Readback protection HW support for FW upgrades Block diagram The Flash block in nRF24LE1 is split in 16 kB of generic code space memory and 1.5 kB of Non Volatile data memory. to/from MCU FCSN FSCK MUX NVM Control PROG Cclk SPI Slave Flash FMOSI FMISO Figure 31. nRF24LE1 Flash block diagram Revision 1.6 70 of 196 nRF24LE1 Product Specification 6.3 Functional description The Flash block gives the MCU its code space for program storage and NVM space for storing of application data. Two pages of 256 bytes each of the NVM memory have extended endurance and can be erased/ written a minimum of 20000 times as opposed to 1000 for the ‘normal’ flash based NVM. The different parts of the memory can be accessed by the MCU through normal code and data space operations. Configuration and setup of the memory behavior during normal mode (that is, when MCU is running application code) is defined by data stored in a separate InfoPage. During the chip reset/start-up sequence the configuration data in the InfoPage is read and stored in the memory configuration SFR’s. 6.3.1 Using the NV data memory The 1.5 kB NV memory is divided into two 256-byte extended endurance pages and two 512 byte normal endurance pages. Table 30. shows the mapping of those four pages for MCU access, SPI access and the page number used for erase (both MCU and SPI). Data memory area Extended endurance data Normal endurance data MCU address SPI address 0xFA00 - 0xFAFF NA 0xFB00 - 0xFBFF NA 0xFC00 - 0xFDFF 0x4400 0x45FF 0xFE00 - 0xFFFF 0x4600 0x47FF Page no. 32 33 34 35 Table 30. Mapping for MCU access, SPI access and page number for erase The NV data memory is read/written as normal flash as described in section 6.3.3 on page 76, except that when writing the NV memory the PMW bit in the PCON register must be cleared. When writing/reading the XDATA memory addresses must be used. In order to erase a NV data memory page, the corresponding flash page address (32 - 35) must be used. Note that a NV data memory byte can only be written once for every page erase. The memory mapping for the NV data memory is illustrated in Figure 30. on page 62. 6.3.2 Flash memory configuration The on-chip flash memory is divided into 2 blocks, the 16 kB + 1.5 kB NVM main block (MB) and a 512 byte Information Page (IP). The memory configuration is stored in the InfoPage (IP) and the following configuration can be done: 1. 2. 3. Split the code space of the main block into 2 areas, protected and unprotected (against MCU erase/write operations). Disable Read and Write access to the flash from external interfaces SPI and HW debug. Enable HW debug features. All configuration of the flash memory must be done through the external SPI interface. The configuration information is stored in the InfoPage during programming of the device and is read out to the flash configuration SFR’s during each reset/startup sequence of the circuit. Revision 1.6 71 of 196 nRF24LE1 Product Specification 6.3.2.1 InfoPage content The InfoPage is a separate page (512 bytes) of flash memory that contains Nordic system tuning parameters and the configurable options of the flash memory. Any changes to the flash memory configuration must be done by updating this page. The InfoPage content is as follows: InfoPage data Device system Number of unprotected pages: NUPP (page address of start of protected area) Reserved Flash main block read back protect Name DSYS a NUPP Size 32 bytes 1 byte Address Comment 0x00 Reserved for device use. Do not erase or modify. 0x20 Read out to register FPCR during start up NUPP=0xFF: all pages are unprotected RDISMB 2 bytes 1 byte 0x21 0x23 Reserved, must be 0xFF Disable flash main block access from external interfaces (SPI, HW debug). Byte value: • 0xFF: Flash main block accessible from external interfaces • Other value: No read/erase/write of flash main block from external interfaces. Only read of info page Enable HW debug ENDEBUG 1 byte 0x24 Can only be changed once by SPI command RDISMB. Can only be reset by SPI command ERASE ALL Enable on chip HW debug features and JTAG interface. Byte value: • 0xFF: HW debug features disabled • other value: HW debug features and JTAG interface enabled Reserved For user data - 219 bytes 256 bytes 0x25 0x100 Reserved, must be 0xFF Free to use a. NOTE: This InfoPage area is used to store nRF24LE1 system and tuning parameters. Erasing the content of this area WILL cause changes to device behavior and performance. Table 31. InfoPage content DSYS - Device System parameters This InfoPage area is used by the nRF24LE1 to store core data like tuning parameters. Erasing and/or changing this area will cause severe changes to device behavior. The operations that can affect this area are SPI commands ERASE ALL, ERASE PAGE and PROGRAM operations to any of these flash addresses with the bit INFEN in register FSR set to logic 1. If you are going to utilise the ERASE ALL SPI command the content of this InfoPage area must be read out, stored and written back into nRF24LE1 after the ERASE ALL command finishes. Revision 1.6 72 of 196 nRF24LE1 Product Specification Protected pages and data pages The flash area can be split into a unprotected and a protected area. Protecting an area of the flash means that the area is read only for the MCU, but it can still be read, erased and written by the SPI interface. The feature protects a part of the code space against illegal erase/write operations from the MCU. The protected area can typically be used for firmware upgrade functions (see section 6.3.6 on page 81). The code space area of the flash main block is divided into 32 pages with 512 bytes page size. Leaving this byte unchanged (NUPP=0xFF) will leave all the 32 pages of the code space unprotected, i.e. the MCU can erase and write to any section of it. If a number