NRF24L01-REEL

nRF24L01 Single Chip 2.4GHz Transceiver Product Specification Key Features • • • • • • • • • • • • • • • • • • Worldwide 2.4GHz ISM band operation Up to 2Mbps on air data rate Ultra low power operation 11.3mA TX at 0dBm output power 12.3mA RX at 2Mbps air data rate 900nA in power down 22µA in standby-I On chip voltage regulator 1.9 to 3.6V supply range Enhanced ShockBurst™ Automatic packet handling Auto packet transaction handling 6 data pipe MultiCeiver™ Air compatible with nRF2401A, 02, E1 and E2 Low cost BOM ±60ppm 16MHz crystal 5V tolerant inputs Compact 20-pin 4x4mm QFN package Applications • • • • • • • • • • • • • Wireless PC Peripherals Mouse, keyboards and remotes 3-in-one desktop bundles Advanced Media center remote controls VoIP headsets Game controllers Sports watches and sensors RF remote controls for consumer electronics Home and commercial automation Ultra low power sensor networks Active RFID Asset tracing systems Toys All rights reserved. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. July 2007 nRF24L01 Product Specification Liability disclaimer Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor ASA does not assume any liability arising out of the application or use of any product or circuits described herein. All application information is advisory and does not form part of the specification. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the specifications are not implied. Exposure to limiting values for extended periods may affect device reliability. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Data sheet status Objective product specification This product specification contains target specifications for product development. Preliminary product specification This product specification contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. Product specification This product specification contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Contact details Visit www.nordicsemi.no for Nordic Semiconductor sales offices and distributors worldwide Main office: Otto Nielsens vei 12 7004 Trondheim Phone: +47 72 89 89 00 Fax: +47 72 89 89 89 www.nordicsemi.no Revision 2.0 Page 2 of 74 nRF24L01 Product Specification Writing Conventions This product specification follows a set of typographic rules that makes the document consistent and easy to read. The following writing conventions are used: • Commands, bit state conditions, and register names are written in Courier. • Pin names and pin signal conditions are written in Courier bold. • Cross references are underlined and highlighted in blue. Revision History Date July 2007 Revision 2.0 Version 2.0 Description • • Restructured layout in a new template Added details of the following features: X Dynamic Payload Length (DPL) X Acknowledgement Payload (ACK_PLD) X Feature register X ACTIVATE SPI command X Selective Auto Acknowledgement (NO_ACK) Page 3 of 74 nRF24L01 Product Specification Contents 1 1.1 1.2 2 2.1 2.2 3 4 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.2 6.3 6.4 6.5 6.6 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 Introduction ............................................................................................... Features ............................................................................................... Block diagram ...................................................................................... Pin Information.......................................................................................... Pin assignment..................................................................................... Pin functions......................................................................................... Absolute maximum ratings ...................................................................... Operating conditions ................................................................................ Electrical specifications ........................................................................... Power consumption.............................................................................. General RF conditions ......................................................................... Transmitter operation ........................................................................... Receiver operation ............................................................................... Crystal specifications ........................................................................... DC characteristics ................................................................................ Power on reset ..................................................................................... Radio Control ............................................................................................ Operational Modes............................................................................... State diagram .................................................................................. Power Down Mode .......................................................................... Standby Modes................................................................................ RX mode.......................................................................................... TX mode .......................................................................................... Operational modes configuration..................................................... Timing Information ........................................................................... Air data rate.......................................................................................... RF channel frequency .......................................................................... PA control............................................................................................. LNA gain .............................................................................................. RX/TX control ....................................................................................... Enhanced ShockBurst™ .......................................................................... Features ............................................................................................... Enhanced ShockBurst™ overview ....................................................... Enhanced Shockburst™ packet format................................................ Preamble ......................................................................................... Address ........................................................................................... Packet Control Field ........................................................................ Payload............................................................................................ CRC (Cyclic Redundancy Check) ................................................... Automatic packet handling ................................................................... Static and Dynamic Payload Length................................................ Automatic packet assembly ............................................................. Automatic packet validation ............................................................. Automatic packet disassembly ........................................................ Automatic packet transaction handling ................................................ Revision 2.0 Page 4 of 74 7 8 9 10 10 11 12 13 14 14 15 15 16 17 18 18 19 19 19 20 20 21 21 21 22 22 23 23 23 23 24 24 24 25 25 25 25 26 26 26 26 27 27 28 28 nRF24L01 Product Specification 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.7 7.8 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 Auto Acknowledgement ................................................................... Auto Retransmission (ART) ............................................................. Enhanced ShockBurst flowcharts ........................................................ PTX operation.................................................................................. PRX operation ................................................................................. Multiceiver ............................................................................................ Enhanced ShockBurstTM timing .......................................................... Enhanced ShockBurstTM transaction diagram .................................... Single transaction with ACK packet and interrupts.......................... Single transaction with a lost packet ............................................... Single transaction with a lost ACK packet ....................................... Single transaction with ACK payload packet ................................... Single transaction with ACK payload packet and lost packet .......... Two transactions with ACK payload packet and the first ACK packet lost ............................................................................... 7.9.7 Two transactions where max retransmissions is reached ............... 7.10 Compatibility with ShockBurst™ .......................................................... 7.10.1 ShockBurst™ packet format ............................................................ 8 Data and Control Interface ....................................................................... 8.1 Features ............................................................................................... 8.2 Functional description .......................................................................... 8.3 SPI operation ....................................................................................... 8.3.1 SPI Commands ............................................................................... 8.3.2 SPI timing ........................................................................................ 8.4 Data FIFO ............................................................................................ 8.5 Interrupt ................................................................................................ 9 Register Map.............................................................................................. 9.1 Register map table ............................................................................... 10 Peripheral RF Information ........................................................................ 10.1 Antenna output ..................................................................................... 10.2 Crystal oscillator ................................................................................... 10.3 nRF24L01 sharing crystal with an MCU............................................... 10.3.1 Crystal parameters .......................................................................... 10.3.2 Input crystal amplitude and current consumption ............................ 10.4 PCB layout and decoupling guidelines................................................. 11 Mechanical specifications........................................................................ 12 Ordering information ................................................................................ 12.1 Package marking ................................................................................. 12.2 Abbreviations ....................................................................................... 13 Glossary of Terms..................................................................................... Appendix A - Enhanced ShockBurst™ - Configuration and Communication Example .................................................................. Enhanced ShockBurst™ Transmitting Payload ................................... Enhanced ShockBurst™ Receive Payload .......................................... Appendix B - Configuration for compatibility with nRF24XX................ Appendix C - Carrier wave output power................................................ Revision 2.0 Page 5 of 74 29 29 31 31 33 35 38 40 40 41 41 42 42 43 43 44 44 45 45 45 45 45 47 51 52 53 53 59 59 59 59 59 59 60 61 63 63 63 64 65 65 65 67 68 nRF24L01 Product Specification Configuration ........................................................................................ Appendix D - Application example .......................................................... PCB layout examples ........................................................................... Appendix E - Stationary disturbance detection ..................................... Revision 2.0 Page 6 of 74 68 69 70 74 nRF24L01 Product Specification 1 Introduction The nRF24L01 is a single chip 2.4GHz transceiver with an embedded baseband protocol engine (Enhanced ShockBurst™), designed for ultra low power wireless applications. The nRF24L01 is designed for operation in the world wide ISM frequency band at 2.400 - 2.4835GHz. An MCU (microcontroller) and very few external passive components are needed to design a radio system with the nRF24L01. The nRF24L01 is configured and operated through a Serial Peripheral Interface (SPI.) Through this interface the register map is available. The register map contains all configuration registers in the nRF24L01 and is accessible in all operation modes of the chip. The embedded baseband protocol engine (Enhanced ShockBurst™) is based on packet communication and supports various modes from manual operation to advanced autonomous protocol operation. Internal FIFOs ensure a smooth data flow between the radio front end and the system’s MCU. Enhanced ShockBurst™ reduces system cost by handling all the high-speed link layer operations. The radio front end uses GFSK modulation. It has user configurable parameters like frequency channel, output power and air data rate. The air data rate supported by the nRF24L01 is configurable to 2Mbps. The high air data rate combined with two power saving modes makes the nRF24L01 very suitable for ultra low power designs. Internal voltage regulators ensure a high Power Supply Rejection Ratio (PSRR) and a wide power supply range. Revision 2.0 Page 7 of 74 nRF24L01 Product Specification 1.1 Features Features of the nRF24L01 include: • • • • • • • • Radio X Worldwide 2.4GHz ISM band operation X 126 RF channels X Common RX and TX pins X GFSK modulation X 1 and 2Mbps air data rate X 1MHz non-overlapping channel spacing at 1Mbps X 2MHz non-overlapping channel spacing at 2Mbps Transmitter X Programmable output power: 0, -6, -12 or -18dBm X 11.3mA at 0dBm output power Receiver X Integrated channel filters X 12.3mA at 2Mbps X -82dBm sensitivity at 2Mbps X -85dBm sensitivity at 1Mbps X Programmable LNA gain RF Synthesizer X Fully integrated synthesizer X No external loop filer, VCO varactor diode or resonator X Accepts low cost ±60ppm 16MHz crystal Enhanced ShockBurst™ X 1 to 32 bytes dynamic payload length X Automatic packet handling X Auto packet transaction handling X 6 data pipe MultiCeiver™ for 1:6 star networks Power Management X Integrated voltage regulator X 1.9 to 3.6V supply range X Idle modes with fast start-up times for advanced power management X 22uA Standby-I mode, 900nA power down mode X Max 1.5ms start-up from power down mode X Max 130us start-up from standby-I mode Host Interface X 4-pin hardware SPI X Max 8Mbps X 3 separate 32 bytes TX and RX FIFOs X 5V tolerant inputs Compact 20-pin 4x4mm QFN package Revision 2.0 Page 8 of 74 nRF24L01 Product Specification 1.2 Block diagram RF Transmitter PA Baseband TX Filter CSN TX FIFOs GFSK Modulator SPI LNA ANT2 Radio Control VDD_PA DVDD Power Management IREF RF Synthesiser VSS XC2 RX FIFOs VDD XC1 GFSK Demodulator Figure 1. nRF24L01 block diagram Revision 2.0 Page 9 of 74 Register map ANT1 RX Filter MISO MOSI Enhanced ShockBurst Baseband Engine RF Receiver SCK IRQ CE nRF24L01 Product Specification VDD VSS IREF Pin assignment DVDD 2.1 Pin Information VSS 2 20 19 18 17 16 CE 1 15 VDD CSN 2 14 VSS 13 ANT2 nRF24L01 SCK 3 QFN20 4X4 5 11 VDD_PA 6 7 8 9 10 XC1 MISO XC2 ANT1 VSS 12 VDD 4 IRQ MOSI Figure 2. nRF24L01 pin assignment (top view) for the QFN20 4x4 package Revision 2.0 Page 10 of 74 nRF24L01 Product Specification 2.2 Pin functions Pin 1 2 3 4 5 6 7 8 9 10 11 Name CE CSN SCK MOSI MISO IRQ VDD VSS XC2 XC1 VDD_PA Pin function Digital Input Digital Input Digital Input Digital Input Digital Output Digital Output Power Power Analog Output Analog Input Power Output 12 13 14 15 16 ANT1 ANT2 VSS VDD IREF RF RF Power Power Analog Input 17 18 19 VSS VDD DVDD Power Power Power Output 20 VSS Power Description Chip Enable Activates RX or TX mode SPI Chip Select SPI Clock SPI Slave Data Input SPI Slave Data Output, with tri-state option Maskable interrupt pin. Active low Power Supply (+1.9V - +3.6V DC) Ground (0V) Crystal Pin 2 Crystal Pin 1 Power Supply Output(+1.8V) for the internal nRF24L01 Power Amplifier. Must be connected to ANT1 and ANT2 as shown in Figure 30. Antenna interface 1 Antenna interface 2 Ground (0V) Power Supply (+1.9V - +3.6V DC) Reference current. Connect a 22kΩ resistor to ground. See: Figure 30. Ground (0V) Power Supply (+1.9V - +3.6V DC) Internal digital supply output for de-coupling purposes. See: Figure 30. Ground (0V) Table 1. nRF24L01 pin function Revision 2.0 Page 11 of 74 nRF24L01 Product Specification 3 Absolute maximum ratings Note: Exceeding one or more of the limiting values may cause permanent damage to nRF24L01. Operating conditions Supply voltages VDD VSS Input voltage VI Output voltage VO Total Power Dissipation PD (TA=85°C) Temperatures Operating Temperature Storage Temperature Minimum Maximum Units -0.3 3.6 0 V V -0.3 5.25 V VSS to VDD VSS to VDD -40 -40 Table 2. Absolute maximum ratings Revision 2.0 Page 12 of 74 60 mW +85 +125 °C °C nRF24L01 Product Specification 4 Operating conditions Symbol Parameter (condition) VDD Supply voltage Supply voltage if input signals >3.6V VDD TEMP Operating Temperature Notes Table 3. Operating conditions Revision 2.0 Page 13 of 74 Min. 1.9 2.7 -40 Typ. 3.0 3.0 +27 Max. Units 3.6 V 3.3 V +85 ºC nRF24L01 Product Specification 5 Electrical specifications Conditions: VDD = +3V, VSS = 0V, TA = - 40ºC to + 85ºC 5.1 Power consumption Symbol IVDD_PD IVDD_ST1 IVDD_ST2 IVDD_SU IVDD_TX0 IVDD_TX6 IVDD_TX12 IVDD_TX18 IVDD_AVG IVDD_TXS IVDD_2M IVDD_LC IVDD_1M IVDD_LC IVDD_RXS a. b. c. d. e. Parameter (condition) Notes Idle modes Supply current in power down a Supply current in standby-I mode Supply current in standby-II mode Average current during 1.5ms crystal oscillator startup Transmit b Supply current @ 0dBm output power b Supply current @ -6dBm output power b Supply current @ -12dBm output power b Supply current @ -18dBm output power c Average Supply current @ -6dBm output power, Enhanced ShockBurst™ d Average current during TX settling Receive Supply current 2Mbps Supply current 2Mbps LNA low current Supply current 1Mbps Supply current 1Mbps LNA low current e Average current during RX settling Min. Typ. Max. Units 900 22 320 285 nA μA μA μA 11.3 9.0 mA mA 7.5 mA 7.0 mA 0.12 mA 8.0 mA 12.3 11.5 mA mA 11.8 11.1 mA mA 8.4 mA Current is given for a 12pF crystal. Current when using external clock is dependent on signal swing. Antenna load impedance = 15Ω+j88Ω. Antenna load impedance = 15Ω+j88Ω. Average data rate 10kbps and full packets Average current consumption for TX startup (130µs) and when changing mode from RX to TX (130µs). Average current consumption for RX startup (130µs) and when changing mode from TX to RX (130µs). Table 4.Power consumption Revision 2.0 Page 14 of 74 nRF24L01 Product Specification 5.2 General RF conditions Symbol fOP PLLres fXTAL Δf1M Δf2M RGFSK FCHAN- Parameter (condition) Operating frequency PLL Programming resolution Crystal frequency Frequency deviation @ 1Mbps Frequency deviation @ 2Mbps Air Data rate Non-overlapping channel spacNEL 1M ing @ 1Mbps FCHAN- Non-overlapping channel spacNEL 2M ing @ 2Mbps Notes Min. 2400 c 1 Units MHz MHz MHz kHz kHz kbps MHz c 2 MHz a Typ. Max. 2525 1 16 ±160 ±320 1000 b 2000 a. Usable band is determined by local regulations b. Data rate in each burst on-air c. The minimum channel spacing is 1Mhz Table 5. General RF conditions 5.3 Transmitter operation Symbol PRF PRFC PRFCR PBW2 PBW1 PRF1 PRF2 Parameter (condition) Maximum Output Power RF Power Control Range RF Power Accuracy 20dB Bandwidth for Modulated Carrier (2Mbps) 20dB Bandwidth for Modulated Carrier (1Mbps) 1st Adjacent Channel Transmit Power 2MHz 2nd Adjacent Channel Transmit Power 4MHz Notes Min. a a. Antenna load impedance = 15Ω+j88Ω Table 6.Transmitter operation Revision 2.0 Page 15 of 74 16 Typ. 0 18 1800 Max. +4 20 ±4 2000 Units dBm dB dB kHz 900 1000 kHz -20 dBm -50 dBm nRF24L01 Product Specification 5.4 Receiver operation Symbol RXmax RXSENS RXSENS Parameter (condition) Maximum received signal at 3.6V, the VDD of the nRF24L01 must be between 2.7V and 3.3V (3.0V±10%) Table 9. Digital input pin Symbol VOH VOL Parameter (condition) HIGH level output voltage (IOH=-0.25mA) LOW level output voltage (IOL=0.25mA) Notes Min. VDD -0.3 Typ. Max. VDD 0.3 Units V V Max. 100 10.3 Units ms ms Table 10. Digital output pin 5.7 Power on reset Symbol TPUP TPOR Parameter (condition) Power ramp up time Power on reset Notes b a. From 0V to 1.9V b. Measured when the VDD reaches 1.9V to when the reset finishes Table 11. Power on reset Revision 2.0 Page 18 of 74 Min. Typ. 1.6 5.3 a nRF24L01 Product Specification 6 Radio Control This chapter describes the different modes the nRF24L01 radio transceiver can operate in and the parameters used to control the radio. The nRF24L01 has a built-in state machine that controls the transitions between the different operating modes of the chip. The state machine takes input from user defined register values and internal signals. 6.1 Operational Modes The nRF24L01 can be configured in four main modes of operation. This section describes these modes. 6.1.1 State diagram The state diagram (Figure 3.) shows the modes the nRF24L01 can operate in and how they are accessed. The nRF24L01 is undefined until the VDD becomes 1.9V or higher. When this happens nRF24L01 enters the Power on reset state where it remains in reset until it enters the Power Down mode. Even when the nRF24L01 enters Power Down mode the MCU can control the chip through the SPI and the Chip Enable (CE) pin Three types of states are used in the state diagram. “Recommended operating mode” is a state that is used during normal operation. “Possible operating mode” is a state that is allowed to use, but it is not used during normal operation. “Transition state” is a time limited state used during start up of the oscillator and settling of the PLL. Revision 2.0 Page 19 of 74 nRF24L01 Product Specification . Legend: Undefined Undefined Undefined VDD >= 1.9V Recommended operating mode Power on reset 10.3ms Possible operating mode Transition state Recommended path between operating modes Start up 1.5ms Power Down Possible path between operating modes CE = 1 Pin signal condition PWR_DN = 1 Bit state condition TX FIFO empty PWR_UP=0 PWR_UP = 1 System information PWR_UP=0 PWR_UP = 0 PRIM_RX = 0 TX FIFO empty CE = 1 Standby-I PWR_UP = 0 CE = 0 RX Settling 130 us PRIM_RX = 1 CE = 1 Standby-II TX FIFO not empty PRIM_RX = 0 CE = 1 for more than 10µs TX finished with one packet CE = 0 CE = 0 TX FIFO not empty CE = 1 TX Settling 130 us RX Mode TX FIFO empty CE = 1 PWR_UP=0 TX Mode PWR_UP = 0 CE = 1 TX FIFO not empty Figure 3. Radio control state diagram 6.1.2 Power Down Mode In power down mode nRF24L01 is disabled with minimal current consumption. In power down mode all the register values available from the SPI are maintained and the SPI can be activated. For start up time see Table 13. on page 22. Power down mode is entered by setting the PWR_UP bit in the CONFIG register low. 6.1.3 Standby Modes By settting the PWR_UP bit in the CONFIG register to 1, the device enters standby-I mode. Standby-I mode is used to minimize average current consumption while maintaining short start up times. In this mode part of the crystal oscillator is active. This is the mode the nRF24L01 returns to from TX or RX mode when CE is set low. In standby-II mode extra clock buffers are active compared to standby-I mode and much more current is used compared to standby-I mode. Standby-II occurs when CE is held high on a PTX device with empty TX FIFO. If a new packet is uploaded to the TX FIFO, the PLL starts and the packet is transmitted. Revision 2.0 Page 20 of 74 nRF24L01 Product Specification The register values are maintained during standby modes and the SPI may be activated. For start up time see Table 13. on page 22. 6.1.4 RX mode The RX mode is an active mode where the nRF24L01 radio is a receiver. To enter this mode, the nRF24L01 must have the PWR_UP bit set high, PRIM_RX bit set high and the CE pin set high. In this mode the receiver demodulates the signals from the RF channel, constantly presenting the demodulated data to the baseband protocol engine. The baseband protocol engine constantly searches for a valid packet. If a valid packet is found (by a matching address and a valid CRC) the payload of the packet is presented in a vacant slot in the RX FIFO. If the RX FIFO is full, the received packet is discarded. The nRF24L01 remains in RX mode until the MCU configures it to standby-I mode or power down mode. If the automatic protocol features (Enhanced ShockBurst™) in the baseband protocol engine are enabled, the nRF24L01 can enter other modes in order to execute the protocol. In RX mode a carrier detect signal is avaliable. The carrier detect is a signal that is set high when a RF signal is detected inside the receiving frequency channel. The signal must be FSK modulated for a secure detection. Other signals can also be detected. The Carrier Detect (CD) is set high when an RF signal is detected in RX mode, otherwise CD is low. The internal CD signal is filtered before presented to CD register. The RF signal must be present for at least 128µs before the CD is set high. How to use the CD is described in Appendix E on page 74. 6.1.5 TX mode The TX mode is an active mode where the nRF24L01 transmits a packet. To enter this mode, the nRF24L01 must have the PWR_UP bit set high, PRIM_RX bit set low, a payload in the TX FIFO and, a high pulse on the CE for more than 10µs. The nRF24L01 stays in TX mode until it finishes transmitting a current packet. If CE = 0 nRF24L01 returns to standby-I mode. If CE = 1, the next action is determined by the status of the TX FIFO. If the TX FIFO is not empty the nRF24L01 remains in TX mode, transmitting the next packet. If the TX FIFO is empty the nRF24L01 goes into standby-II mode.The nRF24L01 transmitter PLL operates in open loop when in TX mode. It is important to never keep the nRF24L01 in TX mode for more than 4ms at a time. If the auto retransmit is enabled, the nRF24L01 is never in TX mode long enough to disobey this rule. 6.1.6 Operational modes configuration The following table (Table 12.) describes how to configure the operational modes. RX mode TX mode PWR_UP register 1 1 PRIM_RX register 1 0 TX mode 1 0 Standby-II Standby-I Power Down 1 1 0 0 - Mode Revision 2.0 CE 1 1 FIFO state Data in TX FIFO. Will empty all levels in TX FIFOa. minimum 10μs Data in TX FIFO.Will empty one high pulse level in TX FIFOb. 1 TX FIFO empty 0 No ongoing packet transmission - Page 21 of 74 nRF24L01 Product Specification a. In this operating mode if the CE is held high the TX FIFO is emptied and all necessary ACK and possible retransmits are carried out. The transmission continues as long as the TX FIFO is refilled. If the TX FIFO is empty when the CE is still high, nRF24L01 enters standby-II mode. In this mode the transmission of a packet is started as soon as the CSN is set high after a upload (UL) of a packet to TX FIFO. b. This operating mode pulses the CE high for at least 10µs. This allows one packet to be transmitted. This is the normal operating mode. After the packet is transmittet, the nRF24L01 enters standby-I mode. Table 12. nRF24L01 main modes 6.1.7 Timing Information The timing information in this section is related to the transitions between modes and the timing for the CE pin. The transition from TX mode to RX mode or vice versa is the same as the transition from standby-I to TX mode or RX mode,Tstby2a. Name Tpd2stby nRF24L01 Power Down Î Standby mode Max. 1.5ms Tpd2stby Power Down Î Standby mode 150µs Standby modes Î TX/RX mode Minimum CE high Delay from CE pos. edge to CSN low 130µs Tstby2a Thce Tpece2csn Min. Comments Internal crystal oscillator With external clock 10µs 4µs Table 13. Operational timing of nRF24L01 When nRF24L01 is in power down mode it must settle for 1.5ms before it can enter the TX or RX modes. If an external clock is used this delay is reduced to 150µs, see Table 13. on page 22. The settling time must be controlled by the MCU. Note: The register value is lost if VDD is turned off. In this case, nRF24L01 must be configured before entering the TX or RX modes. 6.2 Air data rate The air data rate is the modulated signaling rate the nRF24L01 uses when transmitting and receiving data. The air data rate can be 1Mbps or 2Mbps. The 1Mbps data rate gives 3dB better receiver sensitivity compared to 2Mbps. High air data rate means lower average current consumption and reduced probability of on-air collisions. The air data rate is set by the RF_DR bit in the RF_SETUP register. A transmitter and a receiver must be programmed with the same air data rate to be able to communicate with each other. For compatibility with nRF2401A, nRF24E1, nRF2402 and nRF24E2 the air data rate must be set to 1Mbps. Revision 2.0 Page 22 of 74 nRF24L01 Product Specification 6.3 RF channel frequency The RF channel frequency determines the center of the channel used by the nRF24L01. The channel occupies a bandwidth of 1MHz at 1Mbps and 2MHz at 2Mbps. nRF24L01 can operate on frequencies from 2.400GHz to 2.525GHz. The resolution of the RF channel frequency setting is 1MHz. At 2Mbps the channel occupies a bandwidth wider than the resolution of the RF channel frequency setting. To ensure non-overlapping channels in 2Mbps mode, the channel spacing must be 2MHz or more. At 1Mbps the channel bandwidth is the same as the resolution of the RF frequency setting. The RF channel frequency is set by the RF_CH register according to the following formula: F0= 2400 + RF_CH [MHz] A transmitter and a receiver must be programmed with the same RF channel frequency to be able to communicate with each other. 6.4 PA control The PA control is used to set the output power from the nRF24L01 power amplifier (PA). In TX mode PA control has four programmable steps, see Table 14. The PA control is set by the RF_PWR bits in the RF_SETUP register. SPI RF-SETUP RF output power (RF_PWR) 11 0dBm 10 -6dBm 01 -12dBm 00 -18dBm DC current consumption 11.3mA 9.0mA 7.5mA 7.0mA Conditions: VDD = 3.0V, VSS = 0V, TA = 27ºC, Load impedance = 15Ω+j88Ω. Table 14. RF output power setting for the nRF24L01 6.5 LNA gain The gain in the Low Noise Amplifier (LNA) in the nRF24L01 receiver is controlled by the LNA gain setting. The LNA gain makes it possible to reduce the current consumption in RX mode with 0.8mA at the cost of 1.5dB reduction in receiver sensitivity. The LNA gain has two steps and is set by the LNA_HCURR bit in the RF_SETUP register. 6.6 RX/TX control The RX/TX control is set by PRIM_RX bit in the CONFIG register and sets the nRF24L01 in transmit/ receive. Revision 2.0 Page 23 of 74 nRF24L01 Product Specification 7 Enhanced ShockBurst™ Enhanced ShockBurst™ is a packet based data link layer. It features automatic packet assembly and timing, automatic acknowledgement and re-transmissions of packets. Enhanced ShockBurst™ enables the implementation of ultra low power, high performance communication with low cost host microcontrollers. The features enable significant improvements of power efficiency for bi-directional and uni-directional systems, without adding complexity on the host controller side. 7.1 Features The main features of Enhanced ShockBurst™ are: • • • • 7.2 1 to 32 bytes dynamic payload length Automatic packet handling Auto packet transaction handling X Auto Acknowledgement X Auto retransmit 6 data pipe MultiCeiver™ for 1:6 star networks Enhanced ShockBurst™ overview Enhanced ShockBurst™ uses ShockBurst™ for automatic packet handling and timing. During transmit, ShockBurst™ assembles the packet and clocks the bits in the data packet into the transmitter for transmission. During receive, ShockBurst™ constantly searches for a valid address in the demodulated signal. When ShockBurst™ finds a valid address, it processes the rest of the packet and validates it by CRC. If the packet is valid the payload is moved into the RX FIFO. The high speed bit handling and timing is controlled by ShockBurst™. Enhanced ShockBurst™ features automatic packet transaction handling that enables the implementation of a reliable bi-directional data link. An Enhanced ShockBurst™ packet transaction is a packet exchange between to transceivers, where one transceiver is the Primary Receiver (PRX) and the other is the Primary Transmitter (PTX). An Enhanced ShockBurst™ packet transaction is always initiated by a packet transmission from the PTX, the transaction is complete when the PTX has received an acknowledgment packet (ACK packet) from the PRX. The automatic packet transaction handling works as follows: • • • The user initiates the transaction by transmitting a data packet from the PTX to the PRX. Enhanced ShockBurst™ automatically sets the PTX in receive mode to wait for the ack packet. If the packet is received by the PRX, Enhanced ShockBurst™ automatically assembles and transmits an acknowledgment packet (ACK packet) to the PTX before returning to receive mode If the PTX does not receive the ACK packet within a set time, Enhanced ShockBurst™ will automatically retransmit the original data packet and set the PTX in receive mode to wait for the ACK packet The PRX can attach user data to the ACK packet enabling a bi-directional data link. The Enhanced ShockBurst™ is highly configurable; it is possible to configure parameters such as maximum number of retransmits and the delay from one transmission to the next retransmission. All automatic handling is done without involvement of the MCU. Section 7.3 on page 25 gives a description of the Enhanced ShockBurst packet format, section 7.4 on page 26 describes autmatic packet handling, section 7.5 on page 28 describes automatic packet transaction handling, section 7.6 on page 31 provides flowcharts for PTX and PRX operation. Revision 2.0 Page 24 of 74 nRF24L01 Product Specification 7.3 Enhanced Shockburst™ packet format The format of the Enhanced ShockBurst™ packet is described in this chapter. The Enhanched ShockBurst™ packet contains a preamble field, address field, packet control field, payload field and a CRC field. Figure 4. on page 25 shows the packet format with MSB to the left. P re a m b le 1 b y te A d d re s s 3 -5 b y te P a c k e t C o n tro l F ie ld 9 b it P a y lo a d 0 - 3 2 b y te C R C 1 -2 b y te Figure 4. An Enhanced ShockBurst™ packet with payload (0-32 bytes) 7.3.1 Preamble The preamble is a bit sequence used to detect 0 and 1 levels in the receiver. The preamble is one byte long and is either 01010101 or 10101010. If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are enough transitions in the preamble to stabilize the receiver. 7.3.2 Address This is the address for the receiver. An address ensures that the correct packet are detected by the receiver. The address field can be configured to be 3, 4 or, 5 bytes long with the AW register. Note: Addresses where the level shifts only one time (that is, 000FFFFFFF) can often be detected in noise and can give a false detection, which may give a raised Packet-Error-Rate. Addresses as a continuation of the preamble (hi-low toggling) raises the Packet-Error-Rate. 7.3.3 Packet Control Field Figure 5 shows the format of the 9 bit packet control field, MSB to the left. Payload length 6bit PID 2bit NO_ACK 1bit Figure 5. Packet control field The packet control field contains a 6 bit payload length field, a 2 bit PID (Packet Identity) field and, a 1 bit NO_ACK flag. 7.3.3.1 Payload length This 6 bit field specifies the length of the payload in bytes. The length of the payload can be from 0 to 32 bytes. Revision 2.0 Page 25 of 74 nRF24L01 Product Specification Coding: 000000 = 0 byte (only used in empty ACK packets.) 100000 = 32 byte, 100001 = Don’t care. This field is only used if the Dynamic Payload Length function is enabled. 7.3.3.2 PID (Packet identification) The 2 bit PID field is used to detect if the received packet is new or retransmitted. PID prevents the PRX device from presenting the same payload more than once to the MCU. The PID field is incremented at the TX side for each new packet received through the SPI. The PID and CRC fields (see section 7.3.5 on page 26) are used by the PRX device to determine if a packet is retransmitted or new. When several data packets are lost on the link, the PID fields may become equal to the last received PID. If a packet has the same PID as the previous packet, nRF24L01 compares the CRC sums from both packets. If the CRC sums are also equal, the last received packet is considered a copy of the previously received packet and discarded. 7.3.3.3 No Acknowledgment flag(NO_ACK) The Selective Auto Acknowledgement feature controls the NO_ACK flag. This flag is only used when the auto acknowledgement feature is used. Setting the flag high, tells the receiver that the packet is not to be auto acknowledged. 7.3.4 Payload The payload is the user defined content of the packet. It can be 0 to 32 bytes wide and is transmitted on-air as it is uploaded (unmodified) to the device. 7.3.5 CRC (Cyclic Redundancy Check) The CRC is the error detection mechanism in the packet. It may either be 1 or 2 bytes and is calculated over the address, Packet Control Field, and Payload. The polynomial for 1 byte CRC is X8 + X2 + X + 1. Initial value 0xFF The polynomial for 2 byte CRC is X16+ X12 + X5 + 1. Initial value 0xFFFF No packet is accepted by Enhanced ShockBurst™ if the CRC fails. 7.4 Automatic packet handling Enhanced ShockBurst™ uses ShockBurst™ for automatic packet handling. The functions are static and dynamic payload length, automatic packet assembly, automatic packet validation and automatic packet disassembly. 7.4.1 Static and Dynamic Payload Length The Enhanced ShockBurst™ provides two alternatives for handling payload lengths, static and dynamic. The default alternative is static payload length. With static payload length all packets between a transmitter and a receiver have the same length. Static payload length is set by the RX_PW_Px registers on the receiver side. The payload length on the transmitter side is set by the number of bytes clocked into the TX_FIFO and must equal the value in the RX_PW_Px register on the receiver side Dynamic Payload Length(DPL) is an alternative to static payload length.DPL enables the transmitter to send packets with variabel payload length to the receiver. This means for a system with different payload lenghts it is not necessary to scale the packet length to the longest payload. Revision 2.0 Page 26 of 74 nRF24L01 Product Specification With DPL feature the nRF24L01 can decode the payload length of the received packet automatically instead of using the RX_PW_Px registers. The MCU can read the length of the received payload by using the R_RX_PL_WID command. In order to enable DPL the EN_DPL bit in the FEATURE register must be set. In RX mode the DYNPD register has to be set. A PTX that transmits to a PRX with DPL enabled must have the DPL_P0 bit in DYNPD set. 7.4.2 Automatic packet assembly The automatic packet assembly assembles the preamble, address, packet control field, payload and CRC to make a complete packet before it is transmitted. 7.4.2.1 Preamble The preamble is automaticly generated based on the address field. 7.4.2.2 Address The address is fetched from the TX_ADDR register. The address field can be configured to be 3, 4 or 5 bytes long with the AW register. 7.4.2.3 Packet control field For the static packet lenght option the payload length field is not used. With DPL enabled, the value in the payload length field is automaticly set to the number of bytes in the payload clocked into the TX FIFO. The transmitter increments the PID field each time it generates a new packet and uses the same PID on packets that are retransmitted. Refer to the left flow chart in Figure 6. on page 28 The PTX can set the NO_ACK flag bit in the Packet Control Field with this command: W_TX_PAYLOAD_NOACK However, the function must first be enabled in the FEATURE register by setting the EN_DYN_ACK bit. When you use this option the PTX goes directly to standby-I mode after transmitting the packet and the PRX does not transmit an ACK packet when it receives the packet. 7.4.2.4 Payload The payload is fetched from the TX FIFO. 7.4.2.5 CRC The CRC is automaticly calculated based on the packet content with the polynomials in 7.3.5 on page 26. The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. 7.4.3 Automatic packet validation Enhanced ShockBurst™ features automatic packet validation. In receive mode the nRF24L01 is constanly searching for a valid address (given in the RX_ADDR registers.) If a valid address is detected the Enhanched ShockBurst™ will start to validate the packet. Revision 2.0 Page 27 of 74 nRF24L01 Product Specification With static packet length the Enhanced ShockBurst™ will capture the packet according to the length given by the RX_PW register. With DPL Enhanced ShockBurst™ captures the packet according to the payload lenght field in the packet control field. After capturing the packet Enhanced ShockBurst™ will perform CRC. If the CRC is valid, Enhanced ShockBurst™ will check PID. The received PID is compared with the previous received PID. If the PID fields are different, the packet is considered new. If the PID fields are equal the receiver must check if the received CRC is equal to the previous CRC. If the CRCs are equal, the packet is defined as equal to the previous packet and is discarded. Refer to the right flow chart in Figure 6. on page 28 PTX side functionality PRX side functionality Start New packet from MCU? Start PID equal last PID? Yes increment PID Yes No CRC equal last CRC? Yes No No New packet is valid for MCU Discard packet as a copy End End Figure 6. PID generation/detection 7.4.4 Automatic packet disassembly After the packet is validated,Enhanched ShockBurst™ disassembles the packet and loads the payload into the RX FIFO, and assert the RX_DR IRQ 7.5 Automatic packet transaction handling Enhanced ShockBurst™ features two functions for automatic packet transaction handling; auto acknowledgement and auto re-transmit. Revision 2.0 Page 28 of 74 nRF24L01 Product Specification 7.5.1 Auto Acknowledgement Auto acknowledgment is a function that automatically transmits an ACK packet to the PTX after it has received and validated a packet. The auto acknowledgement function reduces the load of the system MCU and can remove the need for dedicated SPI hardware. This also reduces cost and average current consumption. The Auto Acknowledgement feature is enabled by setting the EN_AA register. Note: If the received packet has the NO_ACK flag set, the auto acknowledgement is not executed. An ACK packet can contain an optional payload from PRX to PTX. In order to use this feature, the dynamic payload length feature mus be enabled. The MCU on the PRX side has to upload the payload by clocking it into the TX FIFO by using the W_ACK_PAYLOAD command. The payload is pending in the TX FIFO (PRX) until a new packet is received from the PTX. nRF24L01 can have three ACK packet payloads pending in the TX FIFO (PRX) at the same time. RX Pipe address ACK generator Address decoder and buffer controller TX FIFO Payload 3 Payload 2 Payload 1 TX Pipe address SPI Module From MCU Figure 7. TX FIFO (PRX) with pending payloads Figure 7. shows how the TX FIFO (PRX) is operated when handling pending ACK packet payloads. From the MCU the payload is clocked in with the W_ACK_PAYLOAD command. The address decoder and buffer controller ensure that the payload is stored in a vacant slot in the TX FIFO (PRX). When a packet is received, the address decoder and buffer controller are notified with the PTX address. This ensures that the right payload is presented to the ACK generator. If the TX FIFO (PRX) contains more than one payload to a PTX, payloads are handled using the first in – first out principle. The TX FIFO (PRX) is blocked if all pending payloads are addressed to a PTX where the link is lost. In this case, the MCU can flush the TX FIFO (PRX) by using the FLUSH_TX command. In order to enable Auto Acknowledgement with payload the EN_ACK_PAY bit in the FEATURE register must be set. 7.5.2 Auto Retransmission (ART) The auto retransmission is a function that retransmits a packet if an ACK packet is not received. It is used at the PTX side in an auto acknowledgement system. You can set up the number of times a packet is allowed to be retransmitted if a packet is not acknowledged with the ARC bits in the SETUP_RETR register. PTX enters RX mode and waits a time period for an ACK packet each time a packet is transmitted. The time period the PTX is in RX mode is based on the following conditions: • • • Auto Retransmit Delay (ARD) elapsed or No address match within 250µs or After received packet (CRC correct or not) if address match within 250µs nRF24L01 asserts the TX_DS IRQ when the ACK packet is received Revision 2.0 Page 29 of 74 nRF24L01 Product Specification nRF24L01 enters standby-I mode if there is no more untransmitted data in the TX FIFO and the CE pin is low. If the ACK packet is not received, nRF24L01 goes back to TX mode after a delay defined by ARD and retransmits the data. This continues until acknowledgment is received, or the maximum number of retransmits is reached. Set PWR_UP =0 to abort auto retransmission. Two packet loss counters are incremented each time a packet is lost, ARC_CNT and PLOS_CNT in the OBSERVE_TX register. The ARC_CNT counts the number of retransmissions for the current transaction. The PLOS_CNT counts the total number of retransmissions since the last channel change. You reset ARC_CNT by initiating a new transaction. You reset PLOS_CNT by writing to the RF_CH register. It is possible to use the information in the OBSERVE_TX register to make a overall assessment of the channel quality. The ARD defines the time from the end of a transmitted packet to a retransmit starts on the PTX side. ARD is set in SETUP_RETR register in steps of 250µs. A retransmit is made if no ACK packet is received by the PTX. There is a restriction for the length of ARD when using ACK packets with payload. The ARD time must never be shorter than the sum of the startup time and the time on-air for the ACK packet. For 1Mbps data rate and 5 byte address; 5 byte is maximum ACK packet payload length for ARD=250µs (reset value). For 2Mbps data rate and 5 byte address; 15 byte is maximum ACK packet payload length for ARD=250µs (reset value). ARD=500µs will be long enough for any payload length. As an alternative to Auto Retransmit it is possible to manually set the nRF24L01 to retransmit a packet a number of times. This is done by the REUSE_TX_PL command. The MCU must initiate each transmission of the packet with the CE pin after this command has been used. Revision 2.0 Page 30 of 74 nRF24L01 Product Specification 7.6 Enhanced ShockBurst flowcharts This section shows flowcharts for PTX and PRX operation in Enhanced ShockBurst™. ShockBurst™ operation is marked with a dashed square in the flow charts. 7.6.1 PTX operation The flowchart in Figure 8. shows how a nRF24L01 configured as a PTX behaves after entering standby-I mode. Start Primary TX ShockBurst operation Standby-I mode No Is CE=1? Yes No Is CE =1? Yes Standby-II mode No Packet in TX FIFO? Packet in TX FIFO? Yes TX Settling Yes No No Packet in TX FIFO? TX mode Transmit Packet Yes Yes Set TX_DS IRQ Is Auto ReTransmit enabled? No Is CE =1? Yes No_ACK? Yes No RX Settling RX mode No Set MAX_RT IRQ Timeout? Is an ACK received? No Yes Yes Yes Standby-I mode Has the ACK payload? No No Has ARD elapsed? TX mode Retransmit last packet Yes TX Settling No Put payload in RX FIFO. Set TX_DS IRQ and RX_DR IRQ Set TX_DS IRQ Number of retries = ARC? Yes Figure 8. PTX operations in Enhanced ShockBurst™ You activate PTX mode by setting the CE pin high. If there is a packet present in the TX FIFO the nRF24L01 enters TX mode and transmits the packet. If Auto Retransmit is enabled, the state machine Revision 2.0 Page 31 of 74 nRF24L01 Product Specification checks if the NO_ACK flag is set. If it is not set, the nRF24L01 enters RX mode to receive an ACK packet. If the received ACK packet is empty, only the TX_DS IRQ is asserted. If the ACK packet contains a payload, both TX_DS IRQ and RX_DR IRQ are asserted simultaneously before nRF24L01 returns to standby-I mode. If the ACK packet is not received before timeout occurs, the nRF24L01 returns to standby-I mode. It stays in standby-I mode until the ARD has elapsed. If the number of retransmits has not reached the ARC, the nRF24L01 enters TX mode and transmits the last packet once more. While executing the Auto Retransmit feature, the number of retransmits can reach the maximum number defined in ARC. If this happens, the nRF24L01 asserts the MAX_RT IRQ and returns to standby-I mode. If the CE is high and the TX FIFO is empty, the nRF24L01 enters Standby-II mode. Revision 2.0 Page 32 of 74 nRF24L01 Product Specification 7.6.2 PRX operation The flowchart in Figure 9. shows how a nRF24L01 configured as a PRX behaves after entering standby-I mode. Start Primary RX ShockBurst operation Standby-I mode No Is CE =1? No Yes RX Settling RX mode Is CE =1? Yes RX FIFO Full? Yes No Packet received? No Put payload in RX FIFO and set RX_DR IRQ Yes Is Auto Acknowledgement enabled? No Yes Is the received packet a new packet? No Yes Yes Put payload in RX FIFO and set RX_DR IRQ Discard packet Was there payload attached with the last ACK? No Yes Set TX_DS IRQ No_ACK set in received packet? No No Pending payload in TX FIFO? Yes TX Settling TX Settling TX mode Transmit ACK TX mode Transmit ACK with payload Figure 9. PRX operations in Enhanced ShockBurst™ You activate PRX mode by setting the CE pin high. The nRF24L01 enters RX mode and starts searching for packets. If a packet is received and Auto Acknowledgement is enabled the nRF24L01 decides if this is a new packet or a copy of a previously received packet. If the packet is new the payload is made available in the RX FIFO and the RX_DR IRQ is asserted. If the last received packet from the transmitter is acknowledged with an ACK packet with payload, the TX_DS IRQ indicates that the PTX received the ACK packet Revision 2.0 Page 33 of 74 nRF24L01 Product Specification with payload. If the No_ACK flag is not set in the received packet, the PRX enters TX mode. If there is a pending payload in the TX FIFO it is attached to the ACK packet. After the ACK packet is transmitted, the nRF24L01 returns to RX mode. A copy of a previously received packet might be received if the ACK packet is lost. In this case, the PRX discards the received packet and transmits an ACK packet before it returns to RX mode. Revision 2.0 Page 34 of 74 nRF24L01 Product Specification 7.7 Multiceiver Multiceiver is a feature used in RX mode that contains a set of 6 parallel data pipes with unique addresses. A data pipe is a logical channel in the physical RF channel. Each data pipe has its own physical address decoding in the nRF24L01. PTX3 PTX4 PTX2 2 Da ta P 5 Pi pe PTX6 Da ta Pipe 3 pe Pi Data Data ta Da PTX1 Pipe 4 PTX5 ipe 1 Da ip ta P e0 PRX Frequency Channel N Figure 10. PRX using multiceiver nRF24L01 configured as PRX (primary receiver) can receive data addressed to six different data pipes in one frequency channel as shown in Figure 10. Each data pipe has its own unique address and can be configured for individual behavior. Up to six nRF24L01s configured as PTX can communicate with one nRF24L01 configured as PRX. All data pipe addresses are searched for simultaneously. Only one data pipe can receive a packet at a time. All data pipes can perform Enhanced ShockBurst™ functionality. The following settings are common to all data pipes: • • • • • • CRC enabled/disabled (CRC always enabled when Enhanced ShockBurst™ is enabled) CRC encoding scheme RX address width Frequency channel Air data rate LNA gain The data pipes are enabled with the bits in the EN_RXADDR register. By default only data pipe 0 and 1 are enabled. Each data pipe address is configured in the RX_ADDR_PX registers. Revision 2.0 Page 35 of 74 nRF24L01 Product Specification Note: Always ensure that none of the data pipes have the same address. Each pipe can have up to 5 byte configurable address. Data pipe 0 has a unique 5 byte address. Data pipes 1-5 share the 4 most significant address bytes. The LSByte must be unique for all 6 pipes. Figure 11. is an example of how data pipes 0-5 are addressed. Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Data pipe 0 (RX_ADDR_P0) 0xE7 0xD3 0xF0 0x35 0x77 Data pipe 1 (RX_ADDR_P1) 0xC2 0xC2 0xC2 0xC2 0xC2 Data pipe 2 (RX_ADDR_P2) 0xC2 0xC2 0xC2 0xC2 0xC3 Data pipe 3 (RX_ADDR_P3) 0xC2 0xC2 0xC2 0xC2 0xC4 Data pipe 4 (RX_ADDR_P4) 0xC2 0xC2 0xC2 0xC2 0xC5 Data pipe 5 (RX_ADDR_P5) 0xC2 0xC2 0xC2 0xC2 0xC6 Figure 11. Addressing data pipes 0-5 Revision 2.0 Page 36 of 74 nRF24L01 Product Specification A3 B6 3 B5 B4 5B6A B3 0x 3B4B B 0x R: DD _P0: _A TX ADDR _ RX PTX3 TX RX _AD _A DR DD : R_ P0 0x :0 B3 xB B4 3B B5 4B B6 5B 0F 60 F The PRX, using multiceiver and Enhanced ShockBurst™, receives packets from more than one PTX. To ensure that the ACK packet from the PRX is transmitted to the correct PTX, the PRX takes the data pipe address where it received the packet and uses it as the TX address when transmitting the ACK packet. Figure 12. is an example of how address configuration could be for the PRX and PTX. On the PRX the RX_ADDR_Pn, defined as the pipe address, must be unique. On the PTX the TX_ADDR must be the same as the RX_ADDR_P0 and as the pipe address for the designated pipe. PTX4 PTX2 Da ta Pip e Pi p PTX6 Da ta 2 TX _ A R X _ D D R: A DD 0x R_ P 0 : 0 B 3 B 4B 5 x B3 B4 B B 6 F 1 5B 6 F1 5 60 5B 05 4B 5B6 B B3 4B 0 x B3B 0x R: P0: D _ D _A DR TX _AD RX 5 Pipe Data pe Pi Pipe 3 ta Da PTX1 4 PTX5 Data TX _ RX ADDR _A DD : R_ P0 0xB3 :0 xB B4B5 3B 4B B 6CD 5B 6C D e1 D at aP ip e0 PRX Addr Addr Addr Addr Addr Addr Data Data Data Data Data Data Pipe Pipe Pipe Pipe Pipe Pipe 0 1 2 3 4 5 (RX_ADDR_P0): (RX_ADDR_P1): (RX_ADDR_P2): (RX_ADDR_P3): (RX_ADDR_P4): (RX_ADDR_P5): 878 787 87 8 7 878 0x7 87878 R: 0:0x7 P ADD TX_ AD DR_ RX _ 0x7878787878 0xB3B4B5B6F1 0xB3B4B5B6CD 0xB3B4B5B6A3 0xB3B4B5B60F 0xB3B4B5B605 Frequency Channel N Figure 12. Example of data pipe addressing in multiceiver No other data pipe can receive data until a complete packet is received by a data pipe that has detected its address. When multiple PTXs are transmitting to a PRX, the ARD can be used to skew the auto retransmission so that they only block each other once. Revision 2.0 Page 37 of 74 nRF24L01 Product Specification 7.8 Enhanced ShockBurstTM timing This section describes the timing sequence of Enhanced ShockBurst™ and how all modes are initiated and operated. The Enhanced ShockBurst™ timing is controlled through the Data and Control interface. The nRF24L01 can be set to static modes or autonomous modes where the internal state machine controls the events. Each autonomous mode/sequence is ended with an interrupt at the IRQ pin. All the interrupts are indicated as IRQ events in the timing diagrams. >10us TIRQ TUL PTX SPI 130us TOA IRQ: TX DS1 UL PTX CE PTX IRQ PTX MODE Standby 1 PLL Lock TX Standby-I 1 IRQ if No Ack is on. TIRQ = 8.2ηs @ 1Mbps, TIRQ = 6.0ηs @ 2Mbps Figure 13. Transmitting one packet with NO_ACK on The following equations calculate various timing measurements: Symbol TOA Description Time on-air Equation ⎤ ⋅ ⎛⎜1[byte]+ 3,4 or 5 [bytes ]+ N [bytes ]+ 1 or 2 [bytes ]⎞⎟ + 8⎡bit ⎢⎣ byte ⎥⎦ ⎝ preamble packet length address payload CRC ⎠ = = air data rate air data rate bit s packet control field T ACK = ⎤ ⋅ ⎛⎜1[byte]+ 3,4 or 5 [bytes]+ N [bytes ]+ 1 or 2 [bytes ]⎞⎟ + 8⎡bit ⎣⎢ byte⎥⎦ ⎝ preamble packet length address payload CRC ⎠ = air data rate air data rate bit s packet control field TU L = ⎤ ⋅ N [bytes ] 8 ⎡ bit payload length ⎣⎢ byte ⎥⎦ payload = SPI data rate SPI data rate bit s TOA Time on-air Ack TACK [ ] Time Upload TUL TESB [ ] 9 [bit ] [ ] Time Enhanced ShockBurst™ cycle TESB = TUL + 2 ⋅ Tstby 2 a + T ACK + TIRQ Table 15. Timing equations Revision 2.0 Page 38 of 74 9 [bit ] nRF24L01 Product Specification TESB Cycle >10us TUL 130us TIRQ TOA IRQ: TX DS UL PTX SPI PTX CE PTX IRQ PTX MODE PRX MODE Standby 1 Standby 1 PLL Lock PLL Lock TX RX PLL Lock RX Standby 1 PLL Lock TX PLL Lock TACK 130us RX PRX IRQ PRX CE PRX SPI IRQ:RX DR/DL 130us 130us TIRQ Figure 14. Timing of Enhanced ShockBurst™ for one packet upload (2Mbps) In Figure 14. the transmission and acknowledgement of a packet are shown. The PRX device is turned into RX mode (CE=1), and the PTX device is set to TX mode (CE=1 for minimum 10μs). After 130μs the transmission starts and finishes after the elapse of TOA. When the transmission ends the PTX device automatically switches to RX mode to wait for the ACK packet from the PRX device. After the PTX device receives the ACK packet it responds with an interrupt to the MCU. When the PRX device receives the packet it responds with an interrupt to the MCU. Revision 2.0 Page 39 of 74 nRF24L01 Product Specification 7.9 Enhanced ShockBurstTM transaction diagram This section describes how several scenarios for the Enhanced ShockBurst™ automatic transaction handling. The call outs in this section’s figures indicate the IRQs and other events. For MCU activity the event may be placed at a different timeframe. Note: The figures in this section indicate the earliest possible download (DL) of the packet to the MCU and the latest possible upload (UL) of payload to the transmitter. 7.9.1 Single transaction with ACK packet and interrupts In Figure 15. the basic auto acknowledgement is shown. After the packet is transmitted by the PTX and received by the PRX the ACK packet is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas the TX_DS IRQ is asserted when the packet is acknowledged and the ACK packet is received by the PTX. MCU PTX UL IRQ Ack received IRQ:TX DS (PID=1) 130us1 PTX TX:PID=1 RX PRX RX ACK:PID=1 Packet received IRQ: RX DR (PID=1) MCU PRX DL 1 Radio Turn Around Delay Figure 15. TX/RX cycles with ACK and the according interrupts Revision 2.0 Page 40 of 74 nRF24L01 Product Specification 7.9.2 Single transaction with a lost packet Figure 16. is a scenario where a retransmission is needed due to loss of the first packet transmit. After the packet is transmitted, the PTX enters RX mode to receive the ACK packet. After the first transmission, the PTX waits a specified time for the ACK packet, if it is not in the specific time slot the PTX retransmits the packet as shown in Figure 16. MCU PTX UL IRQ Packet PID=1 lost during transmission No address detected. RX off to save current Auto retransmit delay elapsed 130us1 PTX TX:PID=1 Retransmit of packet PID=1 130us1 ACK received IRQ: TX DS (PID=1) 130us1 RX TX:PID=1 RX ARD PRX RX ACK:PID=1 Packet received. IRQ: RX DR (PID=1) MCU PRX DL 1 Radio Turn Around Delay Figure 16. TX/RX cycles with ACK and the according interrupts when the first packet transmit fails When an address is detected the PTX stays in RX mode until the packet is received. When the retransmitted packet is received by the PRX (see Figure 16.), the RX_DR IRQ is asserted and an ACK is transmitted back to the PTX. When the ACK is received by the PTX, the TX_DS IRQ is asserted. 7.9.3 Single transaction with a lost ACK packet Figure 17. is a scenario where a retransmission is needed after a loss of the ACK packet. The corresponding interrupts are also indicated. MCU PTX UL IRQ No address detected. RX off to save current 130us PTX TX:PID=1 Auto retransmit delay elapsed 1 130us Retransmit of packet PID=1 1 RX ACK received IRQ: TX DS (PID=1) 130us1 TX:PID=1 RX RX ACK:PID=1 ARD PRX RX ACK:PID=1 Packet received. IRQ: RX DR (PID=1) MCU PRX ACK PID=1 lost during transmission Packet detected as copy of previous, discarded DL 1 Radio Turn Around Delay Figure 17. TX/RX cycles with ACK and the according interrupts when the ACK packet fails Revision 2.0 Page 41 of 74 nRF24L01 Product Specification 7.9.4 Single transaction with ACK payload packet Figure 18. is a scenario of the basic auto acknowledgement with payload. After the packet is transmitted by the PTX and received by the PRX the ACK packet with payload is transmitted from the PRX to the PTX. The RX_DR IRQ is asserted after the packet is received by the PRX, whereas on the PTX side the TX_DS IRQ is asserted when the ACK packet is received by the PTX. On the PRX side, the TX_DS IRQ for the ACK packet payload is asserted after a new packet from PTX is received. The position of the IRQ in Figure 18. shows where the MCU can respond to the interrupt. MCU PTX UL1 DL IRQ UL2 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) Transmit of packet PID=2 ≥130us3 130us1 PTX TX:PID=1 PRX RX RX TX:PID=2 ACK1 PAY RX Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=1) MCU PRX UL2 DL IRQ DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 18. TX/RX cycles with ACK Payload and the according interrupts 7.9.5 Single transaction with ACK payload packet and lost packet Figure 19. is a scenario where the first packet is lost and a retransmission is needed before the RX_DR IRQ on the PRX side is asserted. For the PTX both the TX_DS and RX_DR IRQ are asserted after the ACK packet is received. After the second packet (PID=2) is received on the PRX side both the RX_DR (PID=2) and TX_DS (ACK packet payload) IRQ are asserted. MCU PTX UL1 DL IRQ UL2 Packet PID=1 lost during transmission No address detected. RX off to save current Auto retransmit delay elapsed 130us1 PTX TX:PID=1 Retransmit of packet PID=1 130us1 RX ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) ≥130us3 130us1 TX:PID=1 RX TX:PID=2 ACK1 PAY RX ARD PRX RX Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=1) MCU PRX UL 2 DL DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 19. TX/RX cycles and the according interrupts when the packet transmission fails Revision 2.0 Page 42 of 74 nRF24L01 Product Specification 7.9.6 Two transactions with ACK payload packet and the first ACK packet lost. MCU PTX UL1 UL2 No address detected. RX off to save current Auto retransmit delay elapsed 130us1 PTX TX:PID=1 DL IRQ UL3 ACK received IRQ: TX DS (PID=1) RX DR (ACK1PAY) Retransmit of packet PID=1 130us1 RX ACK received IRQ: TX DS (PID=2) RX DR (ACK2PAY) ≥130us3 130us 1 ≥130us3 130us 1 TX:PID=1 RX TX:PID=2 RX TX:PID=3 RX ACK1 PAY RX ACK2 PAY RX ARD PRX RX ACK1 PAY Packet received. IRQ: RX DR (PID=1) MCU PRX UL12 Packet detected as copy of previous, discarded ACK PID=1 lost during transmission Packet received. IRQ: RX DR (PID=2) TX DS (ACK1PAY) Packet received. IRQ: RX DR (PID=3) TX DS (ACK2PAY) DL IRQ UL2 2 DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 20. TX/RX cycles with ACK Payload and the according interrupts when the ACK packet fails In Figure 20. the ACK packet is lost and a retransmission is needed before the TX_DS IRQ is asserted, but the RX_DR IRQ is asserted immediately. The retransmission of the packet (PID=1) results in a discarded packet. For the PTX both the TX_DS and RX_DR IRQ are asserted after the second transmission of ACK, which is received. After the second packet (PID=2) is received on the PRX both the RX_DR (PID=2) and TX_DS (ACK1PAY) IRQ is asserted. The callouts explains the different events and interrupts. 7.9.7 Two transactions where max retransmissions is reached MCU PTX UL IRQ No address detected. RX off to save current 130us PTX TX:PID=1 Auto retransmit delay elapsed 1 130us RX Retransmit of packet PID=1 1 130us TX:PID=1 No address detected. RX off to save current ≥130us3 1 RX ARD No address detected. RX off to save current. IRQ:MAX_RT reached 130us1 TX:PID=1 RX ARD 130us1 PRX RX ACK1 PAY Packet received. IRQ: RX DR (PID=1) MCU PRX UL2 RX ACK PID=1 lost during transmission ACK PID=1 lost during transmission ACK1 PAY Packet detected as copy of previous, discarded RX ACK PID=1 lost during transmission DL 1 Radio Turn Around Delay 2 Uploading Paylod for Ack Packet 3 Delay defined by MCU on PTX side, ≥ 130us Figure 21. TX/RX cycles with ACK Payload and the according interrupts when the transmission fails. ARC is set to 2. If the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC), the MAX_RT IRQ is asserted. In Figure 21. the packet transmission ends with a MAX_RT IRQ. The payload in TX FIFO is NOT removed and the MCU decides the next step in the protocol. A toggle of the CE starts a new sequence of transmitting the same packet. The payload can be removed from the TX FIFO using the FLUSH_TX command. Revision 2.0 Page 43 of 74 nRF24L01 Product Specification 7.10 Compatibility with ShockBurst™ The nRF24L01 can have the Enhanced ShockBurst™ feature disabled in order to be backward compatible with the nRF2401A, nRF24E1, nRF2402 and nRF24E2. Disabling the Enhanced ShockBurst™ features is done by setting register EN_AA=0x00 and the ARC = 0. In addition, the nRF24L01 air data rate must be set to 1Mbps. 7.10.1 ShockBurst™ packet format The ShockBurst™ packet format is described in this chapter. MSB to the left. Preamble 1 byte Address 3-5 byte Payload 1 - 32 byte CRC 1-2 byte Figure 22. A ShockBurst™ packet compatible with nRF2401/nRF2402/nRF24E1/nRF24E2 devices. The ShockBurst™ packet format has a preamble, address, payload and CRC field that is the same as in the Enhanced ShockBurst™ packet format described in section 7.3 on page 25. The differences between the ShockBurst™ packet and the Enhanced ShockBurst™ packet are: • • The 9 bit Packet Control Field is not present in the ShockBurst™ packet format. The CRC is optional in the ShockBurst™ packet format and is controled by the EN_CRC bit in the CONFIG register. Revision 2.0 Page 44 of 74 nRF24L01 Product Specification 8 Data and Control Interface The data and control interface gives you access to all the features in the nRF24L01. The data and control interface consists of the following six 5Volt tolerant digital signals: • • • • • • IRQ (this signal is active low and is controlled by three maskable interrupt sources) CE (this signal is active high and is used to activate the chip in RX or TX mode) CSN (SPI signal) SCK (SPI signal) MOSI (SPI signal) MISO (SPI signal) You can use the SPI to activate the nRF24L01 data FIFOs or the register map by 1 byte SPI commands during all modes of operation. 8.1 • • • • • 8.2 Features Special SPI commands for quick access to the most frequently used features 0-8Mbps 4-wire SPI serial interface 8 bit command set Easily configurable register map Full three level FIFO for both TX and RX direction Functional description The SPI is a standard SPI with a maximum data rate of 8Mbps. 8.3 SPI operation This chapter describes the SPI commands and SPI timing. 8.3.1 SPI Commands The SPI commands are shown in Table 16.. Every new command must be started by a high to low transition on CSN. In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin. The serial shifting SPI commands is in the following format: See Figure 23. on page 47 and Figure 24. on page 48 for timing information. Revision 2.0 Page 45 of 74 nRF24L01 Product Specification Command name R_REGISTER W_REGISTER Command # Data bytes word (binary) 000A AAAA 1 to 5 LSByte first 001A AAAA 1 to 5 LSByte first R_RX_PAYLOAD 0110 0001 1 to 32 LSByte first W_TX_PAYLOAD 1010 0000 FLUSH_TX FLUSH_RX 1110 0001 1110 0010 1 to 32 LSByte first 0 0 REUSE_TX_PL 1110 0011 0 ACTIVATE 0101 0000 1 R_RX_PL_WIDa 0110 0000 W_ACK_PAYLOADa 1010 1PPP Revision 2.0 1 to 32 LSByte first Operation Read command and status registers. AAAAA = 5 bit Register Map Address Write command and status registers. AAAAA = 5 bit Register Map Address Executable in power down or standby modes only. Read RX-payload: 1 – 32 bytes. A read operation always starts at byte 0. Payload is deleted from FIFO after it is read. Used in RX mode. Write TX-payload: 1 – 32 bytes. A write operation always starts at byte 0 used in TX payload. Flush TX FIFO, used in TX mode Flush RX FIFO, used in RX mode Should not be executed during transmission of acknowledge, that is, acknowledge package will not be completed. Used for a PTX device Reuse last transmitted payload. Packets are repeatedly retransmitted as long as CE is high. TX payload reuse is active until W_TX_PAYLOAD or FLUSH TX is executed. TX payload reuse must not be activated or deactivated during package transmission This write command followed by data 0x73 activates the following features: • R_RX_PL_WID • W_ACK_PAYLOAD • W_TX_PAYLOAD_NOACK A new ACTIVATE command with the same data deactivates them again. This is executable in power down or stand by modes only. The R_RX_PL_WID, W_ACK_PAYLOAD, and W_TX_PAYLOAD_NOACK features registers are initially in a deactivated state; a write has no effect, a read only results in zeros on MISO. To activate these registers, use the ACTIVATE command followed by data 0x73. Then they can be accessed as any other register in nRF24L01. Use the same command and data to deactivate the registers again. Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101). Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled using first in - first out principle. Write payload: 1– 32 bytes. A write operation always starts at byte 0. Page 46 of 74 nRF24L01 Product Specification Command # Data bytes Operation word (binary) 1011 000 1 to 32 Used in TX mode. Disables AUTOACK on this W_TX_PAYLOAD_NO a specific packet. LSByte first ACK NOP 1111 1111 0 No Operation. Might be used to read the STATUS register Command name a. To activate this feature use the ACTIVATE SPI command followed by data 0x73. The corresponding bits in the FEATURE register shown in Table 24. on page 58 have to be set. Table 16. Command set for the nRF24L01 SPI The W_REGISTER and R_REGISTER commands can operate on single or multi-byte registers. When accessing multi-byte registers you read or write to the MSBit of LSByte first. You can terminate the writing before all bytes in a multi-byte register are written, leaving the unwritten MSByte(s) unchanged. For example, the LSByte of RX_ADDR_P0 can be modified by writing only one byte to the RX_ADDR_P0 register. The content of the status register is always read to MISO after a high to low transition on CSN. Note: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. If the STATUS register is read during an IRQ pin high to low transition, the pipe information is unreliable. 8.3.2 SPI timing SPI operation and timing is shown in Figure 23. on page 47 to Figure 25. on page 48 and in Table 18. on page 49 to Table 23. on page 50. nRF24L01 must be in one of the standby modes or in power down mode before writing to the configuration registers. In Figure 23. on page 47 to Figure 25. on page 48 the following abbreviations are used: Abbreviation Description Cn SPI command bit Sn STATUS register bit Dn Data Bit (Note: LSByte to MSByte, MSBit in each byte first) Table 17. Abbreviations used in Figure 23. to Figure 25. CSN SCK MOSI C7 C6 C5 C4 C3 C2 C1 C0 MISO S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 23. SPI read operation Revision 2.0 Page 47 of 74 D1 5 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 nRF24L01 Product Specification CSN SCK MOSI C7 C6 C5 C4 C3 C2 C1 C0 MISO S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0 D1 5 D1 4 D1 3 Figure 24. SPI write operation Tcwh CSN Tcc Tch Tcl Tcch SCK Tdh Tdc MOSI C7 C6 Tcsd MISO C0 Tcd Tcdz S7 S0 Figure 25. SPI NOP timing diagram Figure 26. shows the Rpull and Cload that are referenced in Table 18. to Table 23. Vdd Rpull Pin of nRF24L01 External Cload Figure 26. Rpull and Cload Revision 2.0 Page 48 of 74 D1 2 D1 1 D1 0 D9 D8 nRF24L01 Product Specification Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 38 55 40 40 0 8 100 2 2 50 38 Units ns ns ns ns ns ns MHz ns ns ns ns ns Table 18. SPI timing parameters (Cload = 5pF) Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 42 58 40 40 0 8 100 2 2 50 42 Units ns ns ns ns ns ns MHz ns ns ns ns ns Table 19. SPI timing parameters (Cload = 10pF) Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 75 86 40 40 0 5 100 2 2 50 75 Table 20. SPI timing parameters (Rpull = 10kΩ, Cload = 50pF) Revision 2.0 Page 49 of 74 Units ns ns ns ns ns ns MHz ns ns ns ns ns nRF24L01 Product Specification Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 116 123 40 40 0 4 100 2 2 50 116 Units ns ns ns ns ns ns MHz ns ns ns ns ns Table 21. SPI timing parameters (Rpull = 10kΩ, Cload = 100pF) Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 75 85 40 40 0 5 100 2 2 50 75 Units ns ns ns ns ns ns MHz ns ns ns ns ns Table 22. SPI timing parameters (Rpull = 50kΩ, Cload = 50pF) Symbol Tdc Tdh Tcsd Tcd Tcl Tch Fsck Tr,Tf Tcc Tcch Tcwh Tcdz Parameters Data to SCK Setup SCK to Data Hold CSN to Data Valid SCK to Data Valid SCK Low Time SCK High Time SCK Frequency SCK Rise and Fall CSN to SCK Setup SCK to CSN Hold CSN Inactive time CSN to Output High Z Min 2 2 Max 116 121 40 40 0 4 100 2 2 50 116 Table 23. SPI timing parameters (Rpull = 50kΩ, Cload = 100pF) Revision 2.0 Page 50 of 74 Units ns ns ns ns ns ns MHz ns ns ns ns ns nRF24L01 Product Specification 8.4 Data FIFO The data FIFOs are used to store payload that is transmitted (TX FIFO) or payload that is received and ready to be clocked out (RX FIFO). The FIFOs are accessible in both PTX mode and PRX mode. The following FIFOs are present in nRF24L01: • • TX three level, 32 byte FIFO RX three level, 32 byte FIFO Both FIFOs have a controller and are accessible through the SPI by using dedicated SPI commands. A TX FIFO in PRX can store payload for ACK packets to three different PTX devices. If the TX FIFO contains more than one payload to a pipe, payloads are handled using the first in - first out principle. The TX FIFO in a PRX is blocked if all pending payloads are addressed to pipes where the link to the PTX is lost. In this case, the MCU can flush the TX FIFO by using the FLUSH_TX command. The RX FIFO in PRX may contain payload from up to three different PTX devices. A TX FIFO in PTX can have up to three payloads stored. The TX FIFO can be written to by three commands, W_TX_PAYLOAD and W_TX_PAYLOAD_NO_ACK in PTX mode and W_ACK_PAYLOAD in PRX mode. All three commands give access to the TX_PLD register. The RX FIFO can be read by the command R_RX_PAYLOAD in both PTX and PRX mode. This command gives access to the RX_PLD register. The payload in TX FIFO in a PTX is NOT removed if the MAX_RT IRQ is asserted. Figure 27. is a block diagram of the TX FIFO and the RX FIFO. RX FIFO 32 byte 32 byte 32 byte RX FIFO Controller TX FIFO Controller Data Control SPI command decoder SPI Data Control TX FIFO Data 32 byte 32 byte Data 32 byte Figure 27. FIFO block diagram In the FIFO_STATUS register it is possible to read if the TX and RX FIFO is full or empty. The TX_REUSE bit is also available in the FIFO_STATUS register. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX. Revision 2.0 Page 51 of 74 nRF24L01 Product Specification 8.5 Interrupt The nRF24L01 has an active low interrupt (IRQ) pin. The IRQ pin is activated when TX_DS IRQ, RX_DR IRQ or MAX_RT IRQ are set high by the state machine in the STATUS register. The IRQ pin resets when MCU writes '1' to the IRQ source bit in the STATUS register. The IRQ mask in the CONFIG register is used to select the IRQ sources that are allowed to assert the IRQ pin. By setting one of the MASK bits high, the corresponding IRQ source is disabled. By default all IRQ sources are enabled. Note: The 3 bit pipe information in the STATUS register is updated during the IRQ pin high to low transition. If the STATUS register is read during an IRQ pin high to low transition, the pipe information is unreliable. Revision 2.0 Page 52 of 74 nRF24L01 Product Specification 9 Register Map You can configure and control the radio chip by accessing the register map through the SPI by using read and write commands. 9.1 Register map table All undefined bits in the table below are redundant. They are read out as '0'. Note: Addresses 18 to 1B are reserved for test purposes, altering them will make the chip malfunction. Address (Hex) 00 01 02 Revision 2.0 Mnemonic Bit Reset Value CONFIG Reserved MASK_RX_DR 7 6 0 0 MASK_TX_DS 5 0 MASK_MAX_RT 4 0 EN_CRC 3 1 CRCO 2 0 PWR_UP PRIM_RX 1 0 0 0 Type Description Configuration Register R/W Only '0' allowed R/W Mask interrupt caused by RX_DR 1: Interrupt not reflected on the IRQ pin 0: Reflect RX_DR as active low interrupt on the IRQ pin R/W Mask interrupt caused by TX_DS 1: Interrupt not reflected on the IRQ pin 0: Reflect TX_DS as active low interrupt on the IRQ pin R/W Mask interrupt caused by MAX_RT 1: Interrupt not reflected on the IRQ pin 0: Reflect MAX_RT as active low interrupt on the IRQ pin R/W Enable CRC. Forced high if one of the bits in the EN_AA is high R/W CRC encoding scheme '0' - 1 byte '1' – 2 bytes R/W 1: POWER UP, 0:POWER DOWN R/W RX/TX control 1: PRX, 0: PTX Enable ‘Auto Acknowledgment’ Function Disable this functionality to be compatible with nRF2401, see page 65 Only '00' allowed Enable auto acknowledgement data pipe 5 Enable auto acknowledgement data pipe 4 Enable auto acknowledgement data pipe 3 Enable auto acknowledgement data pipe 2 Enable auto acknowledgement data pipe 1 Enable auto acknowledgement data pipe 0 EN_AA Enhanced ShockBurst™ Reserved ENAA_P5 ENAA_P4 ENAA_P3 ENAA_P2 ENAA_P1 ENAA_P0 7:6 5 4 3 2 1 0 00 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W EN_RXADDR Reserved ERX_P5 ERX_P4 7:6 5 4 00 0 0 Enabled RX Addresses R/W Only '00' allowed R/W Enable data pipe 5. R/W Enable data pipe 4. Page 53 of 74 nRF24L01 Product Specification Address (Hex) 03 04 05 06 Revision 2.0 Mnemonic Bit ERX_P3 ERX_P2 ERX_P1 ERX_P0 3 2 1 0 Reset Value 0 0 1 1 SETUP_AW Reserved AW 7:2 1:0 000000 11 SETUP_RETR ARD 7:4 0000 ARC 3:0 0011 RF_CH Reserved RF_CH 7 6:0 0 0000010 RF_SETUP Reserved PLL_LOCK RF_DR 7:5 4 3 000 0 1 RF_PWR 2:1 11 LNA_HCURR 0 1 Type R/W R/W R/W R/W Description Enable data pipe 3. Enable data pipe 2. Enable data pipe 1. Enable data pipe 0. Setup of Address Widths (common for all data pipes) R/W Only '000000' allowed R/W RX/TX Address field width '00' - Illegal '01' - 3 bytes '10' - 4 bytes '11' – 5 bytes LSByte is used if address width is below 5 bytes Setup of Automatic Retransmission R/W Auto Retransmit Delay ‘0000’ – Wait 250µS ‘0001’ – Wait 500µS ‘0010’ – Wait 750µS …….. ‘1111’ – Wait 4000µS (Delay defined from end of transmission to start of next transmission)a R/W Auto Retransmit Count ‘0000’ –Re-Transmit disabled ‘0001’ – Up to 1 Re-Transmit on fail of AA …… ‘1111’ – Up to 15 Re-Transmit on fail of AA RF Channel R/W Only '0' allowed R/W Sets the frequency channel nRF24L01 operates on RF Setup Register R/W Only '000' allowed R/W Force PLL lock signal. Only used in test R/W Air Data Rate ‘0’ – 1Mbps ‘1’ – 2Mbps R/W Set RF output power in TX mode '00' – -18dBm '01' – -12dBm '10' – -6dBm '11' – 0dBm R/W Setup LNA gain Page 54 of 74 nRF24L01 Product Specification Address (Hex) 07 Mnemonic Bit Reset Value Type STATUS Reserved RX_DR 7 6 0 0 R/W R/W TX_DS 5 0 R/W MAX_RT 4 0 R/W RX_P_NO 3:1 111 R TX_FULL 0 0 R OBSERVE_TX PLOS_CNT 7:4 0 R ARC_CNT 3:0 0 R CD Reserved CD 7:1 0 000000 0 R R 0A RX_ADDR_P0 39:0 0xE7E7E 7E7E7 0B RX_ADDR_P1 39:0 0xC2C2C 2C2C2 0C RX_ADDR_P2 7:0 0xC3 0D RX_ADDR_P3 7:0 0xC4 0E RX_ADDR_P4 7:0 0xC5 0F RX_ADDR_P5 7:0 0xC6 08 09 Revision 2.0 Description Status Register (In parallel to the SPI command word applied on the MOSI pin, the STATUS register is shifted serially out on the MISO pin) Only '0' allowed Data Ready RX FIFO interrupt. Asserted when new data arrives RX FIFOb. Write 1 to clear bit. Data Sent TX FIFO interrupt. Asserted when packet transmitted on TX. If AUTO_ACK is activated, this bit is set high only when ACK is received. Write 1 to clear bit. Maximum number of TX retransmits interrupt Write 1 to clear bit. If MAX_RT is asserted it must be cleared to enable further communication. Data pipe number for the payload available for reading from RX_FIFO 000-101: Data Pipe Number 110: Not Used 111: RX FIFO Empty TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. Transmit observe register Count lost packets. The counter is overflow protected to 15, and discontinues at max until reset. The counter is reset by writing to RF_CH. See page 65 and page 74. Count retransmitted packets. The counter is reset when transmission of a new packet starts. See page 65. Carrier Detect. See page page 74. R/W Receive address data pipe 0. 5 Bytes maximum length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) R/W Receive address data pipe 1. 5 Bytes maximum length. (LSByte is written first. Write the number of bytes defined by SETUP_AW) R/W Receive address data pipe 2. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8] R/W Receive address data pipe 3. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8] R/W Receive address data pipe 4. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8] R/W Receive address data pipe 5. Only LSB. MSBytes is equal to RX_ADDR_P1[39:8] Page 55 of 74 nRF24L01 Product Specification Address (Hex) Mnemonic Bit 10 TX_ADDR 39:0 0xE7E7E 7E7E7 R/W Transmit address. Used for a PTX device only. (LSByte is written first) Set RX_ADDR_P0 equal to this address to handle automatic acknowledge if this is a PTX device with Enhanced ShockBurst™ enabled. See page 65. 11 RX_PW_P0 Reserved RX_PW_P0 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 0 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P1 Reserved RX_PW_P1 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 1 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P2 Reserved RX_PW_P2 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 2 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P3 Reserved RX_PW_P3 7:6 5:0 00 0 R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 3 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes RX_PW_P4 Reserved 7:6 00 R/W Only '00' allowed 12 13 14 15 Revision 2.0 Reset Value Type Page 56 of 74 Description nRF24L01 Product Specification Address (Hex) Mnemonic Bit RX_PW_P4 5:0 Reset Value 0 RX_PW_P5 Reserved RX_PW_P5 7:6 5:0 00 0 FIFO_STATUS Reserved TX_REUSE 7 6 0 0 TX_FULL 5 0 TX_EMPTY 4 1 Reserved RX_FULL 3:2 1 00 0 RX_EMPTY 0 1 N/A ACK_PLDc 255:0 X N/A TX_PLD 255:0 X 16 17 Revision 2.0 Type Description R/W Number of bytes in RX payload in data pipe 4 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes R/W Only '00' allowed R/W Number of bytes in RX payload in data pipe 5 (1 to 32 bytes). 0 Pipe not used 1 = 1 byte … 32 = 32 bytes FIFO Status Register R/W Only '0' allowed R Reuse last transmitted data packet if set high. The packet is repeatedly retransmitted as long as CE is high. TX_REUSE is set by the SPI command REUSE_TX_PL, and is reset by the SPI commands W_TX_PAYLOAD or FLUSH TX R TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO. R TX FIFO empty flag. 1: TX FIFO empty. 0: Data in TX FIFO. R/W Only '00' allowed R RX FIFO full flag. 1: RX FIFO full. 0: Available locations in RX FIFO. R RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. W Written by separate SPI command ACK packet payload to data pipe number PPP given in SPI command Used in RX mode only Maximum three ACK packet payloads can be pending. Payloads with same PPP are handled first in first out. W Written by separate SPI command TX data payload register 1 - 32 bytes. This register is implemented as a FIFO with three levels. Used in TX mode only Page 57 of 74 nRF24L01 Product Specification Address (Hex) N/A 1C 1D Mnemonic Bit RX_PLD 255:0 Reset Value X Type R DYNPDc Reserved DPL_P5 7:6 5 0 0 R/W R/W DPL_P4 4 0 R/W DPL_P3 3 0 R/W DPL_P2 2 0 R/W DPL_P1 1 0 R/W DPL_P0 0 0 R/W 0 0 0 0 R/W R/W R/W R/W R/W FEATUREc Reserved EN_DPL EN_ACK_PAYd EN_DYN_ACK 7:3 2 1 0 Description Read by separate SPI command RX data payload register. 1 - 32 bytes. This register is implemented as a FIFO with three levels. All RX channels share the same FIFO Enable dynamic payload length Only ‘00’ allowed Enable dyn. payload length data pipe 5. (Requires EN_DPL and ENAA_P5) Enable dyn. payload length data pipe 4. (Requires EN_DPL and ENAA_P4) Enable dyn. payload length data pipe 3. (Requires EN_DPL and ENAA_P3) Enable dyn. payload length data pipe 2. (Requires EN_DPL and ENAA_P2) Enable dyn. payload length data pipe 1. (Requires EN_DPL and ENAA_P1) Enable dyn. payload length data pipe 0. (Requires EN_DPL and ENAA_P0) Feature Register Only ‘00000’ allowed Enables Dynamic Payload Length Enables Payload with ACK Enables the W_TX_PAYLOAD_NOACK command a. This is the time the PTX is waiting for an ACK packet before a retransmit is made. The PTX is in RX mode for a minimum of 250µS, but it stays in RX mode to the end of the packet if that is longer than 250µS. Then it goes to standby-I mode for the rest of the specified ARD. After the ARD it goes to TX mode and then retransmits the packet. b. The RX_DR IRQ is asserted by a new packet arrival event. The procedure for handling this interrupt should be: 1) read payload through SPI, 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more payloads available in RX FIFO, 4) if there are more data in RX FIFO, repeat from 1) c. To activate this feature use the ACTIVATE SPI command followed by data 0x73. The corresponding bits in the FEATURE register must be set. d. If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Payload Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive the ACK packets with payloads. If the payload in ACK is more than 15 byte in 2Mbps mode the ARD must be 500µS or more, and if the payload is more than 5byte in 1Mbps mode the ARD must be 500µS or more. Table 24. Register map of nRF24L01 Revision 2.0 Page 58 of 74 nRF24L01 Product Specification 10 Peripheral RF Information This chapter describes peripheral circuitry and PCB layout requirements that are important for achieving optimum RF performance from the nRF24L01. 10.1 Antenna output The ANT1 and ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD_PA, either through a RF choke or through the center point in a balanced dipole antenna. A load of 15Ω+j88Ω is recommended for maximum output power (0dBm). Lower load impedance (for instance 50Ω) can be obtained by fitting a simple matching network between the load and ANT1 and ANT2. A recommended matching network for 50Ω load impedance is described in Appendix D on page 69. 10.2 Crystal oscillator A crystal being used with the nRF24L01 must fulfil the specifications given in Table 8. on page 17. To achieve a crystal oscillator solution with low power consumption and fast start-up time a crystal with a low load capacitance specification must be used. A lower C0 also gives lower current consumption and faster start-up time, but may increase the cost of the crystal. Typically C0=1.5pF at a crystal specified for C0max=7.0pF. The crystal load capacitance, CL, is given by: CL = C1 '⋅C 2 ' C1 ' + C 2 ' , where C1’ = C1 + CPCB1 +CI1 and C2’ = C2 + CPCB2 + CI2 C1 and C2 are SMD capacitors as shown in the application schematics, see Figure 30. on page 69. CPCB1 and CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pins respectively; the value is typically 1pF for each of these pins. 10.3 nRF24L01 sharing crystal with an MCU When using an MCU to drive the crystal reference input XC1 of the nRF24L01 transceiver the rules described in the following sections (10.3.1 and 10.3.2) must be followed. 10.3.1 Crystal parameters The requirement of load capacitance CL is only set by the MCU when the MCU drives the nRF24L01 clock input. The frequency accuracy of ±60ppm is still required to get a functional radio link. The nRF24L01 loads the crystal by 1pF in addition to the PCB routing. 10.3.2 Input crystal amplitude and current consumption The input signal should not have amplitudes exceeding any rail voltage. Exceeding rail voltage excites the ESD structure and the radio performance is degraded below specification. You must use an external DC block if you are testing the nRF24L01 with a reference source that has no DC offset (which is often the case with a RF source). Revision 2.0 Page 59 of 74 nRF24L01 Product Specification XO_OUT Buffer: Sine to full swing Amplitude controlled current source Current starved inverter: XOSC core Vdd Vdd Vss Vss ESD ESD XC1 XC2 Figure 28. Principle of crystal oscillator The nRF24L01 crystal oscillator is amplitude regulated. It is recommended to use an input signal larger than 0.4V-peak to achieve low current consumption and good signal-to-noise ratio when using an external clock. XC2 is not used and can be left as an open pin when clocked externally. 10.4 PCB layout and decoupling guidelines A well designed PCB is necessary to achieve good RF performance. A poor layout can lead to loss of performance or functionality. A fully qualified RF-layout for the nRF24L01 and its surrounding components, including matching networks, can be downloaded from www.nordicsemi.no. A PCB with a minimum of two layers including a ground plane is recommended for optimum performance. The nRF24L01 DC supply voltage should be decoupled as close as possible to the VDD pins with high performance RF capacitors, see Table 26. on page 69. It is preferable to mount a large surface mount capacitor (for example, 4.7μF ceramic) in parallel with the smaller value capacitors. The nRF24L01 supply voltage should be filtered and routed separately from the supply voltages of any digital circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the nRF24L01 IC. For a PCB with a topside RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a bottom ground plane, the best technique is to have via holes as close as possible to the VSS pads. A minimum of one via hole should be used for each VSS pin. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. The exposed die attach pad is a ground pad connected to the IC substrate die ground and is intentionally not used in our layouts. It is recommended to keep it unconnected. Revision 2.0 Page 60 of 74 nRF24L01 Product Specification 11 Mechanical specifications nRF24L01 uses the QFN20 4x4 package, with matt tin plating. Revision 2.0 Page 61 of 74 nRF24L01 Product Specification Package Type Saw QFN20 (4x4 mm) Min Typ. Max A 0.80 0.85 0.95 A1 A3 K D/E e 0.00 0.02 0.20 0.20 min 4.0 0.5 BSC 0.05 REF. BSCa D2/E2 2.50 2.60 2.70 a. BSC: Basic Spacing between Centers, ref. JEDEC standard 95, page 4.17-11/A Figure 29. nRF24L01 Package Outline Revision 2.0 Page 62 of 74 L 0.35 0.40 0.45 L1 0.15 max b 0.18 0.25 0.30 nRF24L01 Product Specification 12 Ordering information Ordering code nRF24L01-REEL nRF24L01-REEL7 nRF24L01 nRF24L01-EVKIT Description Package Container 2/1Mbps Transceiver 20 pin QFN 4x4 Tape and reelb 2/1Mbps Transceiver 20 pin QFN 4x4 Tape and reel 2/1Mbps Transceiver 20 pin QFN 4x4 Tray 2 node evaluation N/A N/A MOQa 4000 1500 490 1 a. MOQ = Minimum order quantity b. Moisture Sensitivity Level: MSL2@260ºC, three times reflow 12.1 n 2 Y Package marking R F B 4 L 0 1 Y W W L 12.2 X L Abbreviations Abbreviation nRF B X YY WW LL Definition Fixed text Variable Build Code, that is, unique code for production sites, package type and test platform “X" grade, i.e. Engineering Samples (optional) 2 digit Year number 2 digit Week number 2 letter wafer lot number code Attention! Observe precaution for handling Electrostatic Sensitive Device. Revision 2.0 Page 63 of 74 nRF24L01 Product Specification 13 Glossary of Terms Term ACK ART CE CLK CRC CSN ESB GFSK IRQ ISM LNA LSB LSByte Mbps MCU MISO MOSI MSB MSByte PCB PID PLD PRX PTX PWR_DWN PWR_UP RoHS RX RX_DR SPI TX TX_DS Description Acknowledgement Auto Re-Transmit Chip Enable Clock Cyclic Redundancy Check Chip Select NOT Enhanced ShockBurst™ Gaussian Frequency Shift Keying Interrupt Request Industrial-Scientific-Medical Low Noise Amplifier Least Significant Bit Least Significant Byte Megabit per second Microcontroller Unit Master In Slave Out Master Out Slave In Most Significant Bit Most Significant Byte Printed Circuit Board Packet Identity Bits Payload Primary RX Primary TX Power Down Power Up Restriction of use of Certain Hazardous Substances Receive Receive Data Ready Serial Peripheral Interface Transmit Transmit Data Sent Table 25. Glossary Revision 2.0 Page 64 of 74 nRF24L01 Product Specification Appendix A - Enhanced ShockBurst™ - Configuration and Communication Example Enhanced ShockBurst™ Transmitting Payload 1. 2. 3. 4. 5. 6. 7. The configuration bit PRIM_RX has to be low. When the application MCU has data to transmit, the address for the receiving node (TX_ADDR) and payload data (TX_PLD) has to be clocked into nRF24L01 through the SPI. The width of TXpayload is counted from number of bytes written into the TX FIFO from the MCU. TX_PLD must be written continuously while holding CSN low. TX_ADDR does not have to be rewritten if it is unchanged from last transmit. If the PTX device shall receive acknowledge, data pipe 0 has to be configured to receive the ACK packet. The RX address for data pipe 0 (RX_ADDR_P0) has to be equal to the TX address (TX_ADDR) in the PTX device. For the example in Figure 12. on page 37 the following address settings have to be performed for the TX5 device and the RX device: TX5 device: TX_ADDR = 0xB3B4B5B605 TX5 device: RX_ADDR_P0 = 0xB3B4B5B605 RX device: RX_ADDR_P5 = 0xB3B4B5B605 A high pulse on CE starts the transmission. The minimum pulse width on CE is 10µs. nRF24L01 ShockBurst™: X Radio is powered up. X 16MHz internal clock is started. X RF packet is completed (see the packet description). X Data is transmitted at high speed (1Mbps or 2Mbps configured by MCU). If auto acknowledgement is activated (ENAA_P0=1) the radio goes into RX mode immediately, unless the NO_ACK bit is set in the received packet. If a valid packet has been received in the valid acknowledgement time window, the transmission is considered a success. The TX_DS bit in the STATUS register is set high and the payload is removed from TX FIFO. If a valid ACK packet is not received in the specified time window, the payload is retransmitted (if auto retransmit is enabled). If the auto retransmit counter (ARC_CNT) exceeds the programmed maximum limit (ARC), the MAX_RT bit in the STATUS register is set high. The payload in TX FIFO is NOT removed. The IRQ pin is active when MAX_RT or TX_DS is high. To turn off the IRQ pin, the interrupt source must be reset by writing to the STATUS register (see Interrupt chapter). If no ACK packet is received for a packet after the maximum number of retransmits, no further packets can be transmitted before the MAX_RT interrupt is cleared. The packet loss counter (PLOS_CNT) is incremented at each MAX_RT interrupt. That is, ARC_CNT counts the number of retransmits that was required to get a single packet through. PLOS_CNT counts the number of packets that did not get through after maximum number of retransmits. nRF24L01 goes into standby-I mode if CE is low. Otherwise next payload in TX FIFO is transmitted. If TX FIFO is empty and CE is still high, nRF24L01 enters standby-II mode. If nRF24L01 is in standby-II mode, it goes to standby-I mode immediately if CE is set low. Enhanced ShockBurst™ Receive Payload 1. 2. 3. 4. RX is selected by setting the PRIM_RX bit in the CONFIG register to high. All data pipes that receive data must be enabled (EN_RXADDR register), auto acknowledgement for all pipes running Enhanced ShockBurst™ has to be enabled (EN_AA register), and the correct payload widths must be set (RX_PW_Px registers). Addresses have to be set up as described in item 2 in the Enhanced ShockBurst™ transmit payload chapter above. Active RX mode is started by setting CE high. After 130µs nRF24L01 is monitoring the air for incoming communication. When a valid packet has been received (matching address and correct CRC), the payload is stored in the RX-FIFO, and the RX_DR bit in STATUS register is set high. The IRQ pin is active Revision 2.0 Page 65 of 74 nRF24L01 Product Specification 5. 6. 7. 8. when RX_DR is high. RX_P_NO in STATUS register indicates what data pipe the payload has been received in. If auto acknowledgement is enabled, an ACK packet is transmitted back, unless the NO_ACK bit is set in the received packet. If there is a payload in the TX_PLD FIFO, this payload is added to the ACK packet. MCU sets the CE pin low to enter standby-I mode (low current mode). MCU can clock out the payload data at a suitable rate through the SPI. nRF24L01 is now ready for entering TX or RX mode or power down mode. Revision 2.0 Page 66 of 74 nRF24L01 Product Specification Appendix B - Configuration for compatibility with nRF24XX How to setup nRF24L01 to receive from an nRF2401/nRF2402/nRF24E1/nRF24E2: 1. 2. 3. 4. 5. 6. 7. 8. Use the same CRC configuration as the nRF2401/nRF2402/nRF24E1/nRF24E2 Set the PWR_UP and PRIM_RX bit to 1 Disable auto acknowledgement on the data pipe that is addressed Use the same address width as the PTX device Use the same frequency channel as the PTX device Select data rate 1Mbps on both nRF24L01 and nRF2401/nRF2402/nRF24E1/nRF24E2 Set correct payload width on the data pipe that is addressed Set CE high How to setup nRF24L01 to transmit to an nRF2401/nRF24E1: 1. 2. 3. 4. 5. 6. 7. 8. 9. Use the same CRC configuration as the nRF2401/nRF2402/nRF24E1/nRF24E2 Set the PRIM_RX bit to 0 Set the Auto Retransmit Count to 0 to disable the auto retransmit functionality Use the same address width as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses Use the same frequency channel as the nRF2401/nRF2402/nRF24E1/nRF24E2 uses Select data rate 1Mbps on both nRF24L01 and nRF2401/nRF2402/nRF24E1/nRF24E2 Set PWR_UP high Clock in a payload that has the same length as the nRF2401/nRF2402/nRF24E1/nRF24E2 is configured to receive Pulse CE to transmit the packet Revision 2.0 Page 67 of 74 nRF24L01 Product Specification Appendix C - Carrier wave output power The output power of a radio is a critical factor for achieving wanted range. Output power is also the first test criteria needed to qualify for all telecommunication regulations. Configuration 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Set PWR_UP = 1 in the CONFIG register Wait 1.5ms PWR_UP->standby Clear the PRIM_RX in the CONFIG register Set all auto acknowledgement functionality in the EN_AA register and the SETUP_RETR register to 0 Set output power Set PLL_LOCK to 1 Configure TX address as 5 bytes with all 0xFF Fill the TX payload with 32 bytes of 0xFF Turn off CRC Set the wanted RF channel Transmit the packet by pulsing CE (minimum 10µs) Wait until the transmission ends (indicated by IRQ going active, a fixed delay of 1ms can also be used) Set CE high Use the SPI command for re-use of last sent packet (REUSE_TX_PL) Keep CE high as long as the carrier is needed The nRF24L01 should now output a carrier. Note: This is not a clean carrier but is slightly modulated by the preamble. Revision 2.0 Page 68 of 74 nRF24L01 Product Specification Appendix D - Application example nRF24L01 with single ended matching network crystal, bias resistor, and decoupling capacitors. C7 33nF 0402 C8 1nF 0402 1 2 3 4 5 CE CSN SCK MOSI MISO nRF24L01 15 14 13 12 11 VDD VSS ANT2 ANT1 VDD_PA C5 L3 L1 8.2nH 0402 IRQ VDD VSS XC2 XC1 CE CSN SCK MOSI MISO U1 VSS DVDD VDD VSS IREF C9 10nF 0402 R2 22K 0402 20 19 18 17 16 VDD 50ohm, RF I/O 3.9nH 0402 1.5pF 0402 C6 1.0pF 0402 L2 2.7nH 0402 6 7 8 9 10 NRF24L01 IRQ C3 2.2nF 0402 X1 C4 4.7pF 0402 16 MHz R1 1M C1 22pF 0402 C2 22pF 0402 Figure 30. nRF24L01 schematic for RF layouts with single ended 50Ω RF output Part 22pFa 22pFa 2.2nF 4.7pF 1.5pF 1,0pF 33nF 1nF 10nF 8,2nH 2.7nH 3,9nH 1MΩ 22kΩ nRF24L01 16MHz Designator C1 C2 C3 C4 C5 C6 C7 C8 C9 L1 L2 L3 R1 R2 U1 X1 Footprint 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 QFN20 4x4 Description NPO, +/- 2% NPO, +/- 2% X7R, +/- 10% NPO, +/- 0.25pF NPO, +/- 0.1pF NPO, +/- 0.1pF X7R, +/- 10% X7R, +/- 10% X7R, +/- 10% chip inductor +/- 5% chip inductor +/- 5% chip inductor +/- 5% +/-10% +/-1% +/-60ppm, CL=12pF a. C1 and C2 must have values that match the crystals load capacitance, CL. Table 26. Recommended components (BOM) in nRF24L01 with antenna matching network Revision 2.0 Page 69 of 74 nRF24L01 Product Specification PCB layout examples Figure 31. on page 70, Figure 32. on page 71 and Figure 33. on page 71 show a PCB layout example for the application schematic in Figure 30. on page 69. A double-sided FR-4 board of 1.6mm thickness is used. This PCB has a ground plane on the bottom layer. Additionally, there are ground areas on the component side of the board to ensure sufficient grounding of critical components. A large number of via holes connect the top layer ground areas to the bottom layer ground plane. Figure 31. Top overlay (nRF24L01 RF layout with single ended connection to PCB antenna and 0402 size passive components) Revision 2.0 Page 70 of 74 nRF24L01 Product Specification Figure 32. Top layer (nRF24L01 RF layout with single ended connection to PCB antenna and 0402 size passive components) Figure 33. Bottom layer (nRF24L01 RF layout with single ended connection to PCB antenna and 0402 size passive components The nest figure (Figure 34. on page 72, Figure 35. on page 72 and Figure 36. on page 73) is for the SMA output to have a board for direct measurements at a 50Ω SMA connector. Revision 2.0 Page 71 of 74 nRF24L01 Product Specification Figure 34. Top Overlay (Module with OFM crystal and SMA connector) Figure 35. Top Layer (Module with OFM crystal and SMA connector) Revision 2.0 Page 72 of 74 nRF24L01 Product Specification Figure 36. Bottom Layer (Module with OFM crystal and SMA connector) Revision 2.0 Page 73 of 74 nRF24L01 Product Specification Appendix E - Stationary disturbance detection In Enhanced ShockBurst™ it is recommended to use the Carrier Detect functionality only when the PTX device does not succeed to get packets through, as indicated by the MAX_RT IRQ for single packets and by the packet loss counter (PLOS_CNT) if several packets are lost. If the PLOS_CNT in the PTX device indicates a high rate of packet losses, the device can be configured to a PRX device for a short time (Tstbt2a + CD-filter delay = 130µs+128µs = 258µs) to check CD. If CD was high (jam situation), the frequency channel should be changed. If CD was low (out of range or jammed by broadband signals like WLAN), it may continue on the same frequency channel, but you must perform other adjustments (a dummy write to the RF_CH clears the PLOS_CNT). Revision 2.0 Page 74 of 74