L138-DX-225-RI

Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 FEATURES  TI OMAP-L138 Dual Core Application Processor - -      456 MHz (Max) C674x VLIW DSP  Floating Point DSP  32 KB L1 Program Cache  32 KB L1 Data Cache  256 KB L2 cache  1024 KB boot ROM  JTAG Emulation/Debug 456 MHz (Max) ARM926EJ-S MPU  16 KB L1 Program Cache  16 KB L1 Data Cache  8 KB Internal RAM  64 KB boot ROM  JTAG Emulation/Debug Up To 256 MB mDDR2 CPU RAM Up To 512 MB Parallel NAND FLASH Up To 16 MB SPI based NOR FLASH Integrated Power Management Standard SO-DIMM-200 Interface - 10/100 EMAC MII / MDIO - 2 UARTS - 2 McBSPs - 2 USB Ports - Video Output - Camera/Video Input - MMC/SD - SATA - Single 3.3V Power Supply (actual size) APPLICATIONS  Embedded Instrumentation  Industrial Automation  Industrial Instrumentation  Medical Instrumentation  Embedded Control Processing  Network Enabled Data Acquisition  Test and Measurement  Software Defined Radio  Bar Code Scanners  Power Protection Systems  Portable Data Terminals BENEFITS  Rapid Development / Deployment  Multiple Connectivity and Interface Options  Rich User Interfaces  High System Integration  Fixed & Floating Point Operations in Single CPU  High Level OS Support - Linux - QNX 6.4 - Windows Embedded CE Ready - ThreadX Real Time OS  Embedded Digital Signal Processing DESCRIPTION The MityDSP-L138 is a highly configurable, very small form-factor processor card that features a Texas Instruments OMAP-L138 456 MHz (max) Applications Processor (OMAP). The module includes FLASH (NAND, and NOR) and mDDR2 RAM memory subsystems. The MityDSP-L138 provides a complete and flexible digital processing infrastructure necessary for the most demanding embedded applications development. The onboard OMAP-L138 processor provides a dual CPU core topology. The OMAPL138 includes an ARM926EJ-S micro-processor unit (MPU) capable of running the rich 1 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 software applications programmer interfaces (APIs) expected by modern system designers. The ARM architecture supports several operating systems, including linux and windows XP embedded. In addition to the ARM core, the OMAP-L138 also includes a TMS320C674x floating point digital signal processing (DSP) core. The DSP core supports the freely provided TI DSP/BIOS real-time kernel. Users can leverage the DSP to execute real-time compute algorithms (codecs, image/data processing, compression techniques, filtering, etc.) 1.2V Up To 16MB NOR Flash (SPI interface) For uBoot bootloader Up To 256MB mDDR Memory 16-bit wide 1.8V Power Management 3.3V System Clocks JTAG Header JTAG/Emulator Texas Instruments OMAP-L138 456-MHz ARM926EJ-S ™ RISC MPU 456-MHz C674x VLIW DSP GND Up To 512MB NAND Flash 8-bit wide For root FFS 3.3 V EMIFA (16-bit) Boot Config Boot Config VPIF I/O MMCSD 1 EMAC RMII uPP UHPI LCD Resets & RTC SATA USB 0,1 Timers eCAP eHRPWM I2C 0,1 McASP SPI 0,1 McBSP 0,1 MMCSD 0 UART 0,1,2 EMAC MII/MDIO (Many pins are multiplexed between peripherals) SO-DIMM-200 (DDR2 Connector) Figure 1 MityDSP-L138 Block Diagram Figure 1 provides a top level block diagram of the MityDSP-L138 processor card. As shown in the figure, the primary interface to the MityDSP-L138 is through a standard SO-DIMM-200 card edge interface. The interface provides power, synchronous serial connectivity, and many other interfaces provided by the OMAP processor. Details of the SO-DIMM-200 connector interface are included in the SO-DIMM-200 Interface Description, below. 2 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 OMAP-L138 mDDR2 Memory Interface The OMAP-L138 includes a dedicated DDR2 SDRAM memory interface shared between the onboard ARM and DSP cores. The MityDSP-L138 includes up to 256 MB of mDDR2 RAM integrated with the OMAP-L138 processor. The bus interface is capable of burst transfer rates of 600 MB / second. Note that the OSCIN frequency to the OMAPL138 processor on the module is 24MHz. OMAP-L138 SPI NOR FLASH Interface The MityDSP-L138 includes up to 16 MB of SPI NOR FLASH. This FLASH memory is intended to store a factory provided bootloader, and typically a compressed image of a Linux kernel for the ARM core processor. EMIFA - NAND FLASH / External Interface Up to 512 MB of on-board NAND FLASH memory is connected to the OMAP-L138 using the EMIFA bus. The FLASH memory is 8 bits wide and is connected to third chip select line of the EMIFA (CE1). The FLASH memory is typically used to store the following types of data: - ARM Linux / windows XP / QNX embedded root file-system - runtime DSP or ARM software - runtime application data (non-volatile storage) The EMIFA bus is also accessible on the SO-DIMM connector. It can be used to access external memories such as SDRAM, SRAM, NOR flash, NAND flash, or memorymapped ASICs and FPGAs. The inteface is a maximum of 16-bits wide, but can also be used for 8-bit access. The interface has 14 dedicated address lines (plus 2 word/byte select lines), but up to 10 more are available if the MMCSD0 interface is not used, or only partially used. OMAP-L138 Camera and Video Interfaces The OMAP-L138 includes an optional video port I/O interface commonly used to drive LCD screens as well as a camera input interface. These interfaces have been routed to the SO-DIMM-200 connector. OMAP-L138 RTC The OMAP-L138 features an integrated real-time clock, RTC. MityDSP-L138F modules have a 32.768KHz tuning fork crystal connected to RTC XI & RTC XO of the OMAPL138 to support the RTC functionality. Additionally there is a battery input, module Pin 35, which will power the RTC when the module is off, if utilized. Please visit our Redmine Wiki pages at support.criticallink.com for additional details about the RTC feature. 3 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 Debug Interface JTAG and emulator signals for the OMAP-L138 processor have been brought out to a Hirose header that is intended for use with an available Critical Link breakout adapter, Critical Link part number 80-000286. This header can be removed for production units; please contact Critical Link at info@criticallink.com for details. This adapter is not included with individual modules but is included with each Critical Link Development Kit that is ordered. Additional adapters are available through Critical Link distribution partners. Software and Application Development Support Users of the MityDSP-L138 are encouraged to develop applications using the hardware and software development kit provided by Critical Link. The development kit includes a board support package providing a Linux based distribution and compatible gcc compiler tool-chain with debugger. In addition, the development kit includes support libraries necessary to program the DSP core using the TI Code Composer Studio DSP compiler tool-chain. The libraries provide the necessary functions needed to configure the MityDSP-L138, program standalone embedded applications, and interface with the various hardware components both on the processor board as well as a custom application carrier card. The libraries include several interface “cores” – DSP software modules designed to interface with various high performance data converter modules (ADCs, DACs, LCD and touchscreen interfaces, etc) – as well as bootloading and FLASH programming utilities. Growth Options The MityDSP-L138 has been designed to support several upgrade options. These options include various speed grades, memory configurations, and operating temperature specifications including commercial and industrial temperature ranges. The available options are listed in the section below containing ordering information. For additional ordering information and details regarding these options, or to inquire about a particular configuration not listed below, please contact Critical Link at info@criticallink.com. 4 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Maximum Supply Voltage, Vcc Ambient Temperature Range Commercial Ambient Temperature Range Industrial Humidity Storage Temperature Range Shock, Z-Axis Shock, X/Y-Axis 3.5 V -65 to 80C ±10 g ±10 g MIL-STD-810F 0oC to 70oC -40oC to 85oC 0 to 95% Non-condensing Contact Critical Link for Details SO-DIMM-200 Interface Description The primary interface connector for the MityDSP-L138 is the SO-DIMM card edge interface which contains 4 classes of signals:     Power (PWR) Dedicated signals mapped to the OMAP-L138 device (D) Dedicated signals when NAND memory is populated on the module (D*) Multi-function signals mapped to the OMAP-L138 device (M) Table 1 contains a summary of the MityDSP-L138 pin mapping. Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Ball K14 J1 J2 L1 L2 P16 P18 P19 N19 M18 M19 K18 H17 Type PWR PWR PWR PWR PWR D D D D D D D D D D D D D PWR PWR PWR D I/O I O O I I I I/O I/O O I/O I/O O I/O Table 1 SO-DIMM Pin-Out Signal Pin Ball +3.3 V in 2 +3.3 V in 4 +3.3 V in 6 GND 8 GND 10 RESET_IN# 12 SATA_TX_P 14 A4 SATA_TX_N 16 A3 SATA_RX_P 18 A2 SATA_RX_N 20 A1 USB0_ID 22 B4 USB1_D_N 24 B1 USB1_D_P 26 B2 USB0_VBUS 28 B3 USB0_D_N 30 C2 USB0_D_P 32 C3 USB0_DRVVBUS 34 C4 3V RTC Battery 36 C5 +3.3 V in 38 +3.3 V in 40 GND 42 SPI1_MISO 44 D4 5 Type PWR PWR PWR PWR PWR D M M M M M M M M M M M M PWR PWR PWR M I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal +3.3 V in +3.3 V in +3.3 V in GND GND EXT_BOOT# GP0_7 GP0_10 GP0_11 GP0_15 GP0_6 GP0_14 GP0_12 GP0_5 GP0_13 GP0_1 GP0_4 GP0_3 +3.3 V in +3.3 V in GND GP0_2 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com Pin 45 47 491 51 53 552 572 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 Ball G17 H16 G19 F18 G16 G18 F16 F17 F19 E18 E16 D17 D19 C17 D16 E17 D18 C19 C18 C16 A18 B15 C15 A15 C14 D15 B14 D14 A14 C13 E13 B13 A13 D12 C12 B12 D13 D11 E6 C7 B6 A6 D6 A7 D9 E10 D7 Type D D D M D D D M M PWR M M M M M M M M M M PWR M M M D* M M M D* D* M PWR M M M M M M M M M M PWR D* D* D* D* D* D* D* D* D* I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O I/O I I I I I I I I O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O Signal SPI1_MOSI SPI1_ENA SPI1_CLK SPI1_SCS[1] Reserved I2C0_SCL I2C0_SDA UART2_TXD / I2C1_SDA UART2_RXD / I2C1_SCL GND UART1_TXD UART1_RXD MDIO_CLK MDIO_D MII_RXCLK MII_RXDV MII_RXD[0] MII_RXD[1] MII_RXD[2] MII_RXD[3] GND MII_CRS MII_RXER EMA_CS[0] EMA_OE EMA_BA[0] EMA_BA[1] EMA_A[0] EMA_A[1] EMA_A[2] EMA_A[3] GND EMA_A[4] EMA_A[5] EMA_A[6] EMA_A[7] EMA_A[8] EMA_A[9] EMA_A[10] EMA_A[11] EMA_A[12] EMA_A[13] GND EMA_D[15] EMA_D[14] EMA_D[13] EMA_D[12] EMA_D[11] EMA_D[10] EMA_D[9] EMA_D[8] EMA_D[7] MityDSP-L138 System on Module 15-MAR-2022 Pin 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 6 Ball E4 F4 D5 A12 C11 E12 B11 E11 C10 A11 B10 A10 E9 D3 E3 E2 E1 F3 C1 D1 W15 V15 U18 V16 R14 W16 V17 W17 W18 W19 V18 V19 U16 U19 T16 R18 R19 T15 R15 P17 U17 J4 K3 H3 G3 G2 G1 Type M M M M M M M M M PWR M M M M M M M M M M PWR M D M M M M M M M M PWR M M M M M M M M M M PWR M M M M M M M M M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O O O O O I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I/O I/O I/O Signal GP0_0 GP0_8 GP0_9 MMCSD0_DAT[7] MMCSD0_DAT[6] MMCSD0_DAT[5] MMCSD0_DAT[4] MMCSD0_DAT[3] MMCSD0_DAT[2] GND MMCSD0_DAT[1] MMCSD0_DAT[0] MMCSD0_CMD MMCSD0_CLK MII_TXCLK MII_TXD[3] MII_TXD[2] MII_TXD[1] MII_TXD[0] MII_TXEN GND MII_COL NC UPP_CHA_START VP_CLKIN1 UPP_D[15] / RMII_TXD[1] UPP_D[14] / RMII_TXD[0] UPP_D[13] / RMII_TXEN UPP_D[12] / RMII_RXD[1] UPP_D[11] / RMII_RXD[0] UPP_D[10] / RMII_RXER GND UPP_D[9] / RMII_REF_CLK UPP_D[8] / RMII_CRS_DV UPP_D[7] UPP_D[6] UPP_CHA_ENABLE UPP_D[5] UPP_D[4] UPP_D[3] UPP_D[2] UPP_CHA_WAIT GND UPP_D[1] UPP_D[0] UPP_CHA_CLK UPP_CHB_ENABLE VP_CLKOUT2 VP_CLKIN2 UPP_CHB_WAIT UPP_CHB_START UPP_CHB_CLK Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com Pin 149 151 153 155 157 159 161 163 165 167 169 1713 173 175 177 179 181 183 185 187 189 191 193 195 1974 1994 Ball C6 E7 B5 E8 B8 A8 C9 C8 A5 D8 B7 B9 A9 A16 B17 F9 B16 T17 J3 K4 F2 D10 A17 Type D* PWR D* D* D* D* D* D* M M M M PWR D* M M M M M D M M M PWR M D* I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O I O O O O MityDSP-L138 System on Module 15-MAR-2022 Signal EMA_D[6] GND EMA_D[5] EMA_D[4] EMA_D[3] EMA_D[2] EMA_D[1] EMA_D[0] EMA_WEN_DQM[0] EMA_WEN_DQM[1] EMA_SDCKE EMA_CLK GND EMA_WE EMA_CAS EMA_RAS EMA_CS[2] EMA_CS[4] EMA_CS[5] RESET_OUT VP_CLKIN3 VP_CLKOUT3 LCD_MCLK GND EMA_A_RW EMA_CS[3] Pin 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Ball W14 P4 R3 R2 R1 T3 T2 T1 U3 U2 U1 G4 H4 V3 F1 V2 V1 W3 W2 W1 R5 B184 B194 Type M PWR M M M M M M M M M M PWR M M M M M M M M M M PWR D* M I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O O I/O I/O I/O I/O I/O O I I Signal VP_CLKIN0 GND LCD_D[15] LCD_D[14] LCD_D[13] LCD_D[12] LCD_D[11] LCD_D[10] LCD_D[9] LCD_D[8] LCD_D[7] LCD_D[6] GND LCD_VSYNC LCD_HSYNC LCD_D[5] LCD_PCLK LCD_D[4] LCD_D[3] LCD_D[2] LCD_D[1] LCD_D[0] LCD_AC_ENB_CS GND EMA_WAIT[0] EMA_WAIT[1] Note 1: Pin 49, SPI1_CLK, has a 100K Ohm pull-down resistor on the module Note 2: Pins 55 and 57 have 4.70K pull-up resistors on the module Note 3: Pin 171, EMA_CLK, has a 49.9 Ohm resistor in series with the signal on the module Note 4: Pins 197, 198, 199 and 200 have 1.00K Ohm resistors in series with the signals on the module The signal group description for the above pins is included in Table 2 Table 2 Signal Group Description Signal / Group 3.3 V in EXT_BOOT# RESET_IN# Type N/A I I Description 3.3 volt input power referenced to GND. Bootstrap configuration pin. Pull low to configure booting from external UART1. Manual Reset. When pulled to GND for a minimum of 1 usec, resets the processor. 7 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com Signal / Group SPI1_* MityDSP-L138 System on Module 15-MAR-2022 Type I/O MII_* I/O MDIO_DAT MDIO_CLK I/O GP0_* I/O SATA_TX_P SATA_TX_N O SATA_RX_P SATA_RX_N I GND EMA_* N/A I/O Description Serial Peripheral Interface 1 pins. These pins are direct connects to the corresponding SPI1_* pins on the OMAP-L138 processor. The SPI1_* function pins are multiplexed with other functions. These include PWM, Timers, UARTs, I2C0, and GPIO. For details please refer to the OMAP-L138 processor specifications. Media Independent Interface (Ethernet) pins. These pins are direct connects to the corresponding MII_* pins on the OMAP-L138 processor. The MII_* function pins are multiplexed with other functions. These include SPI0, PWM, Timers, UART0, MCBSP, MCASP, and GPIO. For details please refer to the OMAP-L138 processor specifications. MII/RMII Management Interface pins. The MDIO_CLK and MDIO_DAT signals are direct connects to the corresponding MDIO_* signals on the OMAP-L138 processor. The MDIO_* function pins are multiplexed with other functions. These include SPI0 and Timer functions. For details please refer to the OMAP-L138 processor specifications. General Purpose / multiplexed pins. These pins are direct connects to the corresponding GP0[*] pins on the OMAPL138 processor. The include support for the McASP, general purpose I/O, UART flow control, and McBSP 1. For details please refer to the OMAP-L138 processor specifications. Serial ATA Controller Transmit pins. These pins are direct connects to the corresponding SATA_TX_* pins on the OMAP-L138 processor. For details please refer to the OMAP-L138 processor specifications. Serial ATA Controller Receive pins. These pins are direct connects to the corresponding SATA_RX_* pins on the OMAP-L138 processor. For details please refer to the OMAP-L138 processor specifications. System Digital Ground. EMIF-A pins. These pins are direct connects to the corresponding EMA_* pins on the OMAP-L138 processor. Alternatively, these pins can be configured as GPIOs for modules that do not have NAND memory present. For details please refer to the OMAP-L138 processor specifications. Note that pins 197, 198, 199 and 200 have 1.00K Ohm resistors in series with the signals on the module. 8 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com Signal / Group UPP_* Type I/O RMII_* I/O LCD_* I/O VP_* I/O RESET_OUT I/O USB0_*, USB1_* I/O MityDSP-L138 System on Module 15-MAR-2022 Description Universal Parallel Port pins. These pins are direct connects to the corresponding UPP_* pins on the OMAP-L138 processor. The UPP_* function pins are multiplexed with other functions. These include RMII, VP_DIN, MMCSD1, and GPIO. For details please refer to the OMAP-L138 processor specifications. Reduced Media Independent Interface pins. These pins are direct connects to the corresponding RMII_* pins on the OMAP-L138 processor. The RMII_* function pins are multiplexed with other functions. These include UPP and VP_DIN. For details please refer to the OMAP-L138 processor specifications. Liquid Crystal Display pins. These pins are direct connects to the corresponding LCD_* pins on the OMAP-L138 processor. The LCD_* function pins are multiplexed with other functions. These include VP_DOUT, UPP, MMCSD1, and GPIO. For details please refer to the OMAP-L138 processor specifications. Video Port In/Out. These pins are direct connects to the corresponding VP_* pins on the OMAP-L138 processor. The VP_* function pins are multiplexed with other functions. These include UPP, MMCSD1, and GPIO. For details please refer to the OMAPL138 processor specifications. Reset Output pin. This pin is a direct connect to the RESET_OUT pin on the OMAP-L138 processor. This pin can also be configured as a GPIO. For details please refer to the OMAP-L138 processor specifications. Universal Serial Bus 0 / 1 pins. These pins are direct connects to the corresponding USB_* pins on the OMAP-L138 processor. For details please refer to the OMAP-L138 processor specifications. 9 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 DEBUG INTERFACE Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with an available adapter board, Critical Link part number 80-000286, to debug the OMAPL138. Debug Interface Connector Description (J2) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 I/O - GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table 3 OMAP-L138 Hirose Connector Signal Pin I/O Signal 2 O OMAP EMU1 4 O OMAP EMU0 6 I OMAP TCK 8 O OMAP RTCK 10 O OMAP TDO 12 OMAP VCC / 3.3V 14 I OMAP TDI 16 I OMAP TRST 18 I OMAP TMS 20 GND 22 NC FPGA VREF / VCCAUX 24 NC FPGA TMS 26 NC FPGA TCK 28 NC FPGA TDO 30 NC FPGA TDI 10 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 ELECTRICAL CHARACTERISTICS Table 4: Electrical Characteristics Parameter Conditions Symbol V33 I331,2 I33-max1,2 FCPU FEMIF Voltage supply, 3.3 volt input. Quiescent Current draw, 3.3 volt input Max current draw, positive 3.3 volt input. CPU internal clock Frequency (PLL output) EMIF bus frequency 1. 2. Must be ≤ ½ CPU Min Typ Max Units 3.2 170 3.3 230 300 300 100 3.4 250 TBS 456 - Volts mA mA MHz MHz 96 - Power utilization of the MityDSP-L138 is heavily dependent on end-user application. Major factors include: ARM CPU PLL configuration, DSP Utilization and external DDR2 RAM utilization. For power utilization information please visit our Redmine Wiki pages on support.criticallink.com ORDERING INFORMATION The following table lists the standard module configurations. For shipping status, availability, and lead time of these or other configurations please contact Critical Link at info@criticallink.com. Module P/N L138-DX-325-RI L138-FX-325-RC CPU 375 MHz 456 MHz Table 5: Standard Model Numbers FPGA NOR NAND N/A 16MB 256MB N/A 16MB 256MB RAM 128MB 128MB Temperature -40oC to 85o C 0oC to 70o C MECHANICAL INTERFACE A mechanical outline of the MityDSP-L138 is illustrated in Figure 2, below. 11 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C Critical Link, LLC www.CriticalLink.com MityDSP-L138 System on Module 15-MAR-2022 Figure 2 MityDSP-L138 Mechanical Outline REVISION HISTORY Rev n/a Date 31-DEC-2010 n/a 11-FEB-2011 n/a 12-JUL-2011 n/a 17-FEB-2012 n/a 11-DEC-2012 n/a 27-MAR-2013 -1A 18-JUN-2019 -1B -1C 21-OCT-2020 15-MAR-2022 Change Description Initial revision. Update picture. Update Table 1. Change to 456 MHz max speed. Change DDR bandwidth to support 150 MHz clocking. Update model number table. Update NAND to indicate 8 bit data width. Update block diagram accordingly. Updated ordering information. Update Debug Header information, added MILSTD-810F and Up To notation for RAM and NAND Added OMAP-L138 processor pins with notes about on module resistors for specific pins as well as the OSCIN frequency. Added 16MB NOR option, model number and RTC info. Update list of orderable part numbers. Update L138-DX-225-RI to L138-DX-325-RI. 12 Copyright © 2013, Critical Link LLC Specifications Subject to Change 60-000038-1C