ISM14585-L35 Specification
ISM14585-L35
BLE 5.0 SiP
Preliminary Data Sheet
5.0 BLE + Cortex M0 + PMU + PA + RTC + Flash
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ISM14585-L35 Specification
Table of Contents
1
PART NUMBER DETAIL DESCRIPTION .......................................................................................................4
1.1
Ordering Information ..................................................................................................................................4
1.2
For additional configuration options please contact Inventek Systems: .....................................................4
2
OVERVIEW ........................................................................................................................................................5
3
FEATURES .........................................................................................................................................................6
3.1
Feature Highlights: .....................................................................................................................................6
3.2
Application Examples.................................................................................................................................8
3.3
Key Benefits ...............................................................................................................................................9
3.4
Limitations ..................................................................................................................................................9
3.5
Regulatory Compliance .............................................................................................................................. 9
4
COMPLEMENTARY DOCUMENTATION .................................................................................................... 10
4.1
EVB .......................................................................................................................................................... 10
5
ISM14585-L35 SoC & SiP BLOCK DIAGRAMS ............................................................................................ 10
6
Electrical Specification ...................................................................................................................................... 12
6.1
Absolute Maximum Rating ...................................................................................................................... 12
6.2
Recommendable Operation Condition ..................................................................................................... 12
6.2.1
Temperature, Humidity ........................................................................................................................ 12
6.2.2
Voltage................................................................................................................................................. 12
6.3
Current Consumption ............................................................................................................................... 13
6.3.1
BLUETOOTH LOW ENERGY .......................................................................................................... 13
7
RF Specification ................................................................................................................................................. 13
7.1
RF Transmitter Specification .................................................................................................................... 13
7.1.1
BLE RF SPECIFICATION ................................................................................................................. 13
8
Pin Definition ..................................................................................................................................................... 14
8.1
Detail pin definition information .............................................................................................................. 14
8.2
Development Mode Peripheral Pin Mapping ........................................................................................... 16
9
Addition Information ......................................................................................................................................... 16
9.1
Microcontroller Unit ................................................................................................................................. 16
9.2
External Reset ........................................................................................................................................... 17
9.2.1
POR, HW AND SW RESET ............................................................................................................... 17
9.2.2
POWER-ON RESET FUNCTIONALITY .......................................................................................... 19
9.3
DMA Controller ....................................................................................................................................... 21
Figure 7 DMA Controller Block Diagram ................................................................................................................... 22
9.3.1
DMA PERIPHERALS ......................................................................................................................... 22
The list of peripherals that can request for a DMA service is presented in below table .............................................. 22
9.3.2
INPUT/OUTPUT MULTIPLEXER .................................................................................................... 23
9.3.3
DMA CHANNEL OPERATION ........................................................................................................ 23
9.3.4
DMA ARBITRATION ........................................................................................................................ 24
9.3.5
FREEZING DMA CHANNELS .......................................................................................................... 25
9.4
I2C Interface ............................................................................................................................................. 25
9.5
I2C BUS TERMS ..................................................................................................................................... 27
9.5.2
I2C BEHAVIOR .................................................................................................................................. 29
9.5.3
I2C PROTOCOLS ............................................................................................................................... 31
9.5.4
MULTIPLE MASTER ARBITRATION............................................................................................. 36
9.5.5
CLOCK SYNCHRONIZATION ......................................................................................................... 37
9.5.6
OPERATION MODES ........................................................................................................................ 38
9.5.7
DISABLING THE I2C CONTROLLER ............................................................................................. 44
9.6
UART ....................................................................................................................................................... 45
9.6.1
UART (RS232) SERIAL PROTOCOL ............................................................................................... 46
9.6.2
IRDA 1.0 SIR PROTOCOL ................................................................................................................ 47
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9.6.3
CLOCK SUPPORT ............................................................................................................................. 49
9.6.4
CLOCK SUPPORT ............................................................................................................................. 49
9.6.5
PROGRAMMABLE THRE INTERRUPT ......................................................................................... 50
9.6.6
SHADOW REGISTERS ...................................................................................................................... 52
9.6.7
DIRECT TEST MODE ........................................................................................................................ 53
9.7
SPI+ Interface ........................................................................................................................................... 53
9.7.1
OPERATION WITHOUT FIFOS ....................................................................................................... 54
9.8
Wake-Up Timer ........................................................................................................................................ 58
9.9
General Purpose Timers ........................................................................................................................... 60
9.9.1
TIMER 0 .............................................................................................................................................. 60
9.9.2
TIMER 2 .............................................................................................................................................. 63
9.10
Watchdog Timer ....................................................................................................................................... 66
9.11
Input/Output Ports .................................................................................................................................... 68
9.11.1
PROGRAMMABLE PIN ASSIGNMENT ..................................................................................... 69
9.11.2
GENERAL PURPOSE PORT REGISTERS .................................................................................. 69
9.12
General Purpose ADC .............................................................................................................................. 71
9.12.1
INPUT CHANNELS AND INPUT SCALE ................................................................................... 72
9.12.2
STARTING THE ADC AND SAMPLING RATE ........................................................................ 72
9.12.3
NON-IDEAL EFFECTS ................................................................................................................. 73
9.12.4
CHOPPING..................................................................................................................................... 73
9.12.5
OFFSET CALIBRATION .............................................................................................................. 74
9.12.6
ZERO-SCALE ADJUSTMENT ..................................................................................................... 75
9.12.7
COMMON MODE ADJUSTMENT .............................................................................................. 75
9.12.8
INPUT IMPEDANCE, INDUCTANCE, AND INPUT SETTLING .............................................. 75
9.12.9
COMMON MODE ADJUSTMENT .............................................................................................. 76
9.12.10
Sample Rate Converter (SRC) ........................................................................................................ 77
9.12.11
SRC ARCHITECTURE .................................................................................................................. 78
9.13
PDM Interface .......................................................................................................................................... 80
9.14
PCM Controller ........................................................................................................................................ 82
9.14.1
PCM ARCHITECTURE ................................................................................................................. 83
10 MECHANICAL SPECIFICATION ................................................................................................................... 90
10.1
Size of the Module .................................................................................................................................... 90
10.2
Mechanical Dimension ............................................................................................................................. 90
11 Recommend Footprint (Board Design) .............................................................................................................. 91
11.1
Module Dimension Measurement ............................................................................................................. 91
11.2
The X-Y Central Location Coordinates .................................................................................................... 92
12 Recommend Stencil ........................................................................................................................................... 94
13 Recommended Reflow Profile ........................................................................................................................... 95
14 Package and Storage Condition ......................................................................................................................... 95
14.1
Package Dimension .................................................................................................................................. 95
15 REVISION CONTROL ..................................................................................................................................... 96
16 CONTACT INFORMATION ............................................................................................................................ 96
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1 PART NUMBER DETAIL DESCRIPTION
1.1 Ordering Information
Device
ISM14585
ISM14585-EVB
Description
BLE 5.0 + Cortex M0
Module with integrated
PMU, RTC, PA, 8Mb of
Flash and internal
antenna
BLE 5.0 + Cortex M0
Module with integrated
PMU, RTC, PA, 8Mb of
Flash and internal
antenna EVB (Evaluation
Board)
Standard Ordering Number
ISM14585-L35-P8
ISM14585-L35-P8-EVB
1.2 For additional configuration options please contact Inventek
Systems:
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2 OVERVIEW
The Inventek Systems ISM14585-L35 SiP (System in Package), is the smallest, lowest
power and most integrated Bluetooth® 5.0 solution available. The ISM14585-L35
platform is the first BLE module from Inventek's FLEXiBLE product family. The
ISM14585-L35 SiP is an embedded wireless Bluetooth Low Energy (BLE) IoT radio,
based on the Dialog Semiconductor DA14585 radio SoC (System on Chip). The
ISM14585-L35 offers designers all the benefits of the industry-leading DA14580
technology but with even greater flexibility to create more advanced applications from the
smallest footprints and power budgets.
The ISM14585-L35 is ideal for applications such as remote controls, beacons, connected
sensors and innovative medical devices. Among the new features, the ISM14585-L35
supports Data Packet Length Extension, Link Layer Privacy v1.2, Secure Connections,
Bluetooth low energy Mesh and Efficient connectable Advertising.
The ISM14585-L35 integrated Audio Unit (AU) is equipped with a Pulse-Density
Modulation (PDM) interface that can be connected to up to 2 input devices (e.g. MEMS
microphones) or output devices, a PulseCode modulation (PCM) controller which
provides an up to 192 kHz synchronous interface to external audio devices, ISDN circuits
and serial data interfaces (I2S) and a 24-bit Sample Rate Converting unit (SRC) used to
convert the sampling rate of audio samples between the various interfaces. PDM and
PCM functionality can be mapped to any GPIO through the user programmable pin logic.
An integrated DMA controller handles all data transfers between the AU and the RAM
providing the CPU with the freedom to cope with other tasks.
The ISM14585-L35 SiP provide smarter, more flexible, and even lower power BLE
connectivity with an integrated 32bit CortexTM-M0 (16MHz), processor, an integrated
PMU (Power Management Unit), an integrated PA (Power Amplifier), an integrated RTC,
128kB of ROM, 64KB OTP, 1MB SPI Flash as well as a foot print compatible options for
an additional integrated 4Mb, 8Mb, or 16Mb of Flash.
The ISM14585-L35 SiP provides a number of features and standard peripheral interfaces
(see “Features” below), enabling a seamless connection to an embedded design. The
ISM14585-L35 is a very versatile SoC and is ideal for adding Bluetooth low energy to
products like remote controls, proximity tags, beacons, connected medical devices and
smart home nodes. The ISM14585-L35 supports all Bluetooth developments up to and
including Bluetooth 5.0.
The ISM14585-L35 also includes 96KB of RAM, the ISM14585-L35 has double the
memory for User applications of its predecessor to take full advantage of the standard’s
features. The ISM14585-L35 also includes an integrated microphone interface for voice
support at no additional cost. The wide supply voltage range (0.9 –3.6 V) covering a larger
choice of energy sources also enables full design flexibility.
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The ISM14585-L35 is easy to design-in and supports standalone as well as hosted
applications. The ISM14585-L35 is supported by a complete development environment
with Dialog’s SmartSnippets™ software that helps customers optimize software for power
consumption.
The ISM14585-L35 supports several fully qualified profiles embedded in ROM (see
“Typical Applications” below), and the option of loading additional profiles into RAM. The
low cost, small foot print (6.0mm x 8.6mm x 1.2mm), LGA 35 pin package and ease of
design-in make the ISM14585-L35 ideal for a wide range of embedded applications.
The ISM14585-L35 enables wireless connectivity to the simplest existing sensor products
with minimal engineering effort. ISM14585-L35 reduces development time, lowers
manufacturing costs, saves board space, simplifies certification compliance, and
minimizes customer RF expertise required during development of target applications.
The ISM14585-L35 provides the highest level of integration for a wireless system, with
market leading and integrated BLE 5.0 technology based on Dialog’s DA14585 SoC.
The ISM14585-L35 is also fully supported by Dialog’s Smartbond product family
Development Kit-Pro evaluation board and Dialog SmartSnippets Studio SDK.
3 FEATURES
The ISM14585-L35 provides a reduced boot time and supports up to 8 connections.
It has a fully integrated radio transceiver and baseband processor for Bluetooth® Low
Energy. It can be used as a standalone application processor or as a data pump in
hosted systems.
The ISM14585-L35 is optimized for remote control units (RCU) requiring support for
voice commands and motion/gesture recognition. Its integrated Audio Unit (AU) offers
easy interface for MEMS microphones over PDM, external codecs over PCM/I2S and a
Sample Rate Converter unit.
The ISM14585-L35 Bluetooth Low Energy firmware includes the L2CAP service layer
protocols, Security Manager (SM), Attribute Protocol (ATT), the Generic Attribute Profile
(GATT) and the Generic Access Profile (GAP). All profiles published by the Bluetooth
SIG as well as custom profiles are supported.
The transceiver interfaces directly to the antenna and is fully compliant with the
Bluetooth 5.0 standard. The ISM14585-L35 has dedicated hardware for the Link Layer
implementation of Bluetooth Low Energy and interface controllers for enhanced
connectivity capabilities.
3.1 Feature Highlights:
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Frequency Band: 2.4GHz
Complies to the Bluetooth 5 core specification
Suitable for Bluetooth Mesh
Supports up to 8 Bluetooth LE connections
Network Standard: Bluetooth Low Energy
Longest battery life
Low operating voltage (1.8 V to 3.6 V)
•
•
•
Operating Temperature: -40℃ to 85℃
MSL level 3
Low system Bill of Materials
•
•
FCC, CE, IE and Japan certification in-process
Certifications will comply with Bluetooth V5.0, ETSI EN 300, 328 and EN 300 440 Class
2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan)
•
Processing power
o 16 MHz 32 bit ARM Cortex-M0 with SWD
o interface
o Dedicated Link Layer Processor
o AES-128 bit encryption Processor
•
Memory Resources
o Large memory to build complex applications
o Integrated One-Time-Programmable memory 64 kB (OTP)
o 96 kB Data/Retention SRAM
o 128 kB ROM
o Option for 4Mb or 8Mb integrated Flash
•
Power Management
o Integrated Buck/Boost DCDC converter
o P0, P1 and P2 ports with 3.3 V tolerance
o Easy decoupling of only 4 supply pins
o Supports Coin (typ. 3.0 V) and Alkaline (typ. 1.5 V) battery cells
o 1.8 V cold boot support
o 10-bit ADC for battery voltage measurement
o Integrated Power Amplifier for maximum radio performance
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Digital controlled oscillators
o 16 MHz crystal (±20 ppm max) and RC oscillator
o 32 kHz crystal (±50 ppm, ±500 ppm max) and RCX oscillator
•
Flexible Reset Circuitry
o System & Power-On Reset in a single pin
•
Fast cold boot in less than 50ms
•
General-purpose, Capture and Sleep timers
•
Digital interfaces
o Gen. Purpose I/Os: 14
o 2 x UARTs with hardware flow control up to 1 MBd
o SPI+™ interface
o I2C bus at 100 kHz, 400 kHz
o 3-axes capable Quadrature Decoder
o I2S and PDM audio interface
•
Analog interfaces
o 4-channel 10-bit ADC
•
Radio transceiver
o Fully integrated 2.4 GHz CMOS transceiver
o Single wire antenna: no RF matching, or RX/TX switching required
o Supply current at VBAT3V:
▪ TX: 3.4 mA
▪ RX: 3.7 mA (with ideal DCDC)
o 0 dBm transmit output power to 10dBm with integrated PA
o -20 dBm output power in “Near Field Mode”
o -93 dBm receiver sensitivity
•
Package:
o LGA 35, 6.0mm x 8.6mm x 1.2mm
3.2 Application Examples
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Voice-controlled remote controls
Beacons
(Multi-sensor) Wearable devices
o Fitness trackers
o Consumer health
Smartwatches
Human interface devices
o Keyboard
o Mouse
Toys
Consumer appliances
3.3 Key Benefits
•
•
•
Lowest power consumption
Smallest system size
Lowest system cost
3.4 Limitations
Inventek Systems products are not authorized for use in safety-critical applications
(such as life support) where a failure of the Inventek Systems product would
reasonably be expected to cause severe personal injury or death.
3.5 Regulatory Compliance
CE
Regulator
Status
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FCC
IC
RoHS
Pending
Pending
Compliant
Inventek Systems FCC, IC, and CE modular transmitter certifications for the ISM14585-L35
SiP is pending completion. These certifications can be used to the advantage of any
manufacturer developing a product using these devices. In order to take full advantage of the
certifications and remain in compliance, Developers may not interfere, modify, replace and/or
enhance the SiP antenna design, layout and power settings. For FCC compliance, End
Customer finished products will still need to meet the Declaration of Conformity (SDoC)
requirements according to 47 CFR Chapter 1, part 15, subpart B.
The testing required for the Declaration of Conformity (SDoC) requirements is specified in
sections 15.107 and 15.109. The official documents can be oained from the U.S Government
Printing Office online. U.S. Government Printing Office CFR 47.
If it is desired to add a connector or U.FL connector in the RF path or change the antenna to
one of the same type (chip) with equal or less gain, customers can do so without refiling.
Other changes such as a different antenna or adding an antenna diversity switch will require
filing for a Class 2 permissive change. Any Class 2 permissive changes must be performed
under Inventek’s grant, and therefore must be done in cooperation with Inventek. In addition to
this document, Inventek recommends verifying the schematic board design with Inventek
Engineering once the schematic is complete for further review and validation.
Inventek also provides customers additional certifications for specific countries upon request
and an agreed upon service fee.
4 COMPLEMENTARY DOCUMENTATION
4.1 EVB
➢ The Inventek ISM14585-L35 Evaluation Board is the ISM14585-L35-EVB
➢ Please reference the ISM14585-L35-EVB User’s Manual
o Evaluation Board Specification
o EVB User’s Guide
o Design Guidelines
5 ISM14585-L35 SoC & SiP BLOCK DIAGRAMS
DIALOG DA14585 Radio w/Audio I/F SoC:
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Figure 1 Dialog DA14585 SoC Block Diagram
INVENTEK ISM14585-L35 SiP:
Figure 2 Inventek ISM14585-L35 SiP Block Diagram
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•
UART
SPI
I2C
GPIO
SWD
Universal synchronous/asynchronous receiver transmitters
Serial Peripheral Interface
Inter-Integrated Circuit
General-purpose input/output
Serial Wire Debug
6 Electrical Specification
6.1 Absolute Maximum Rating
Supply Power
Storage Temperature
Voltage ripple
Max +4 Volt
- 40° to 125° Celsius
+/- 2%
Max. Values not exceeding Operating
voltage
min
Max
3.6
Power
BT_VBAT
Power Supply Absolute
Maximum Ratings
VDD_PA
-
3.6
VDD_FLASH
-
3.6
VSS-0.3
VBAT+0.3
Voltage on input or
output pin
6.2 Recommendable Operation Condition
6.2.1 Temperature, Humidity
The ISM14585-L35 will withstand the operational requirements as listed in the table
below.
Operating Temperature
Humidity range
-30° to 85° Celsius
Max 95%
Non condensing, relative humidity
6.2.2 Voltage
The Power supply for the ISM14585-L35 will be provided by the host via the power pins
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Symbol
BT_VBAT
VDD_PA
VDD_Flash
Parameter
Min
3
3
3
Typ
3.3
3.3
3.3
Max
3.6
3.6
3.6
Unit
V
V
V
6.3 Current Consumption
6.3.1 BLUETOOTH LOW ENERGY
Condition: Condition: 25deg.C
Item
Condition
Tx Mode
Transmitter and baseband are
both operating, 100%
Receiver and baseband are
both operating, 100%
RX Mode
Min
Nom
TBD
Max
Unit
mA
mA
TBD
7 RF Specification
7.1 RF Transmitter Specification
7.1.1 BLE RF SPECIFICATION
Parameter
Frequency Range
RX sensea
TX Power
Mod char: delta f1 average
Mod char: delta f2 maxc
Mod char: ratio
•
•
•
Mode and Condition
LE GFSK, 0.1% BER,
1 Mbps
N/A
Min. Typ. Max.
2402
2480
Unit
MHz
TBD
-80
dBm
TBD
225
TBD
275
dBm
kHz
%
%
225
99.9
0.8 0.95
Dirty TX is Off.
Up to 1dB of variation may potentially be seen from typical sensitivity specs due
to the chip, board, and associated variations.
At least 99.9% of all delta F2 max frequency values recorded over 10 packets
must be greater than 185 kHz.
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•
Additional specifications to reference is SIG
8 Pin Definition
Figure 3. TOP VIEW
8.1 Detail pin definition information
Pin Name
Pin
Number
I/O Type
Description
Radio
BT_RF
34
I/O
RF I/O antenna port
ANT
35
I/O
Embedded Antenna Port.
Enable: tie to BT_RF pin
Disable: tie to GND when not use.
NC
27
NA
let it not connected.
BT_VBAT
25
AI
VBAT input pin
VDD_PA
32
AI
Digital I/O supply voltage
VDD_FLASH
19
AI
Flash VDD input pin
VDCDC
12
AO
Output of the DC-DC converter
SWITCH
9
AIO
VBAT1V
7
AI
Antenna
Voltage Regulators
INPUT/OUTPUT. Connection for the external DC-DC
converter inductor.
INPUT. Battery connection. Used for an alkaline or a NiMh
battery (1.5 V). If a single coin battery (3 V) is attached to
pin VBAT3V,this pin must be connected to GND.
Straps
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Pin Name
Pin
Number
I/O Type
Description
Digital I/O
P0_0
18
DIO
P0_1
29
DIO
P0_2
30
DIO
P0_3
17
DIO
23
DIO
INPUT/OUTPUT with selectable pull up/down resistor.
Pulldown enabled during and after reset. General purpose
I/O port bit or alternate function nodes. Contains state
retention mechanism during power down.
Drive current is 3.5mA
P0_4
Note1: P0_1 & P0_2 is connected to control pin of internal
PA.
22
DIO
P0_6
20
DIO
P0_7
16
DIO
P1_0 (Note1)
5
DIO
P1_1 (Note 1)
4
DIO
P1_2 (Note 2)
13
DIO
P1_3 (Note 2)
14
DIO
SWCLK
2
DIO
This signal is the JTAG clock by default
SWDIO
3
DIO
This signal is the JTAG data I/O by default
29,30
NA
1,6,8,10,12,24,
28,31,33
NA
P0_5
Note 2: An increased Packet Error rate might occur if GPIO
P1-2 and P1-3 is toggling. The root cause of this
problem is the close location of a few GPIO pins to
the on-chip 16 MHz XTAL oscillator circuitry.
Toggling of these GPIOs might corrupt the clock,
which will be visible in the Packet Error Rate.
Debug Interface
Supplies
NC
GND
RST_N
15
DI
Ground
INPUT. Reset signal (active high). Must be connected to
GND if not used.
Note 1 An increased Packet Error rate might occur if GPIO P1-2 and P1-3 is toggling.
The root cause of this problem is the close location of a few GPIO pins to the on-chip 16
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MHz XTAL oscillator circuitry. Toggling of these GPIOs might corrupt the clock, which
will be visible in the Packet Error Rate.
8.2 Development Mode Peripheral Pin Mapping
Interface
SPI Master
UART
SPI Slave
I2C
9
Signal
SCK
Step A
P0_0
Step B
P0_0
CS
P0_3
P0_1
MISO
P0_6
P0_2
MOSI
TX
RX
Baud Rate
SCK
P0_5
P0_3
P0_0
P0_1
57600 / 8-N-1
P0_0
P0_2
P0_3
115200 / 8-N-1
P0_4
P0_5
57600 / 8-N-1
P0_6
P0_7
9600 / 8-N-1
CS
P0_3
MISO
P0_6
MOSI
SCL
SDA
P0_5
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P0_0
P0_1
Step C
Step D
Addition Information
9.1 Microcontroller Unit
The ISM14585-L35 includes a Cortex-M0 32-bit Reduced Instruction Set Computing
(RISC) processor with a von Neumann architecture (single bus interface). It uses an
instruction set called Thumb, which was first supported in the ARM7TDMI processor.
However, several newer instructions from the ARMv6 architecture and a few
instructions from the Thumb-2 technology are also included. Thumb-2 technology
extends the previous Thumb instruction set to allow all operations to be carried out in
one CPU state. The instruction set in Thumb-2 includes both 16-bit and 32-bit
instructions. Most instructions generated by the C compiler use the 16-bit instructions,
and the 32-bit instructions are used when the 16-bit version cannot carry out the
required operations. This results in high code density and avoids the overhead of
switching between two instruction sets.
In total, the Cortex-M0 processor supports 56 base instructions, although some
instructions can have more than one form. Although the instruction set is small, the
Cortex-M0 processor is highly capable because the Thumb instruction set is highly
optimized.
Academically, the Cortex-M0 processor is classified as load-store architecture, as it has
separate instructions for reading and writing to memory, and instructions for arithmetic
or logical operations that use registers.
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9.2 External Reset
The ISM14585-L35 comprises an RST pad which is active high. It contains an RC filter
for spikes suppression with 400kΩ and 2.8pF for the resistor and the capacitor
respectively. It also contains a 25kΩ pull-down resistor. This pad should be connected
to ground if not needed by the application.
The response is illustrated in the Figure 4 which displays the voltage (V) on the vertical
axis and the time (μs) on the horizontal axis:.
Figure 4. RST Pad Latency
The typical latency of the RST pad is in the range of 2us.
9.2.1 POR, HW AND SW RESET
The Power-On Reset (POR) signal is generated:
● Internally and will release the system’s flip flops as soon as the VDD voltage crosses
the minimum threshold value.
● Externally by a Power-On Reset source (RST pad or GPIO).
There are three main reset signals in the ISM14585-L35:
1. The PWR-On reset which is triggered by a GPIO set as POR source with
selectable polarity and/or the RST pad after a programmable time delay.
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2. The HW reset which is basically triggered by the RST pad when it becomes
active for a short period of time (less than the programmable delay for POR).
3. The SW reset which is triggered by writing the SYS_CTRL_REG[SW_RESET]
bit.
•
The HW reset can also be automatically activated upon waking up of the system
from the Extended or Deep Sleep mode by programming bit PMU_CTRL_REG
[RESET_ON_WAKEUP].
•
The PWR-On reset as well as the HW reset will basically run the cold start-up
sequence and the BootROM code will be executed.
The SW reset is the logical OR of a signal from the ARM CPU (triggered by writing
SCB->AIRCR = 0x05FA0004) and the SYS_CTRL_REG[SW_RESET] bit.
This is mainly used to reboot the system after the base address has been remapped.
The block diagram of the reset block is depicted in Figure 5.
Figure 5. Reset Block Diagram
Certain registers are reset by POR only or by POR and the HW reset signal, but not by
the SW reset. These registers are listed in below table.
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Reset by POR Only
Reset by POR or HW Reset
BANDGAP_REG
POR_PIN_REG
POR_TIMER_REG
RF registers containing the
trimming values for the
VCO, the LNA and the I/O
capacitance
OTPC_NWORDS_REG
CLK_FREQ_TRIM_REG
CLK_RADIO_REG
All RF calibration registers
BLE_CNTL2_REG
CLK_CTRL_REG
PMU_CTRL_REG
SYS_CTRL_REG
CLK_32K_REG_I
CLK_16M_REG_I
CLK_RCX32K_REG
TRIM_CTRL_REG
DEBUG_REG[DEBUGS_FREEZE_EN]
GP_CONTROL_REG[EM_MAP]
Reset by POR, HW or SW
Reset
The rest of the Register File
9.2.2 POWER-ON RESET FUNCTIONALITY
Power-On Reset functionality is available by two sources:
● Reset Pad: Reset pad is always capable of producing a Power-On Reset.
● GPIO Pin: A GPIO can be selected by the user application to act as POR source.
The time needed for the POReset pin to be active is stored in the POR_TIMER_REG.
The register field POR_TIME is a 7-bits field which holds time factor that the total time
for POR is calculated. The maximum value of the field is 0x7F. The total time for POR is
calculated by the following formula:
Total time = POR_TIME x 4096 x RC32k clock period
where RC32k clock period = 31.25μs at 25oC .
The maximum time that a POR can be performed is ~16.2 seconds at 25oC.
The RC32k clock is temperature dependent so based on the temperature span of -10oC
to 50oC, clock frequency range is calculated to be 25kHz to 39kHz. Then,
TPORcold = 13s
TPORhot = 20.8s
9.2.2.1 POR TIMER CLOCK
The Power-On Reset timer is clocked by the RC32k clock. If the application disables the
RC32k, then the hardware takes care of enabling the RC32k clock when the POR
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source (Reset pad or GPIO) is asserted. It should be noted that if POR is generated
from the Reset pad the RC32 will operate with the reset trimming value. If a GPIO is
used as POR source, the RC32 clock will be trimmed. The deviation between both
cases in terms of timing is expected to be minor.
9.2.2.2 RESET PAD
The Reset pad will produce a HW Reset if the pin active time is less than the
programmed value in the POR_TIMER_REG register and a Power-On Reset if it is
greater or equal the value. Reset pad is always Active High.
9.2.2.3 POR FROM GPIO
When a GPIO is used as a Power-on Reset source, the selected pin retains its
capability to act as GPIO. The POR_PIN_REG[PIN_SELECT] field holds the required
GPIO pin number. If the value of the PIN_SELECT field equals to 0 the POR over GPIO
functionality is disabled. The polarity of the pin can be configured by the
POR_PIN_REG [POR_POLARITY] bit where 0 means Active Low and 1 Active High.
9.2.2.4 POWER-ON RESET TIMING DIAGRAM
The operation of the Power-On Reset for both Reset pad and GPIO is depicted in
Figure 6.
Figure 6 Power-On Reset Timing Diagram
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9.2.2.5 POWER-ON RESET CONSIDERATIONS
If any of the POR sources is asserted then the POR timer starts to count. When a POR
source is released before the timer has expired, POR timer will reset to 0. If a second
source is asserted while the first is already asserted and the first is released after that
point, POR will occur; assuming that the total time of both sources kept asserted is
larger or equal than the POR_TIME.
The POR_PIN_REG[PIN_SELECT] field cannot survive any Reset (POR, HW, SW) and
as such the user must take special care on setting up the GPIO POR source right after
a reset. This also applies for the POR_TIMER_REG[POR_TIME] field after a Power-On
Reset.
The user must also take into account that if a GPIO is used as POR source, the
dynamic current of the system increases due to the dynamic current consumed by the
RC32k oscillator. This increase is calculated to be 100nA to 120nA and it is also present
during sleep time period. POR from Reset pin does not add this dynamic current
consumption.
9.3 DMA Controller
The DMA controller has 4 Direct Memory Access (DMA) channels for fast data transfers
from/to SPI, UART, I2C, PDM and PCM to/from any on-chip RAM. The DMA controller
off-loads the ARM interrupt rate if an interrupts is given after a number of transfers.
More peripherals DMA requests are multiplexed on the 4 available channels, to
increase utilization of the DMA. The block diagram of the DMA controller is depicted in
Figure 7.
Features:
•
•
•
•
•
•
•
4 channels with optional peripheral trigger
Full 32 bit source and destination pointers.
Flexible interrupt generation.
Programmable length.
Flexible peripheral request per channel.
Option to initialize memory.
Programmable Edge-Sensitive request support(suggested for UART and I2C
service)
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Figure 7 DMA Controller Block Diagram
9.3.1 DMA PERIPHERALS
The list of peripherals that can request for a DMA service is presented in below table
Name
SPI
SPI
UART
UART
UART2
UART2
I2C
I2C
PCM
PCM
SRC
SRC
Direction
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
RX
TX
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9.3.2 INPUT/OUTPUT MULTIPLEXER
The multiplexing of peripheral requests is controlled by DMA_REQ_MUX_REG. Thus, if
DMA_REQ_MUX_REG [DMAxy_SEL] is set to a certain (non-reserved) value, the
TX/RX request from the corresponding peripheral will be routed to DMA channels y (TX
request) and x (RX request) respectively.
Similarly, an acknowledging de-multiplexing mechanism is applied.
However, when two or more bit-fields (peripheral selectors) of DMA_REQ_MUX_REG
have the same value, the lesser significant selector will be given priority (see also the
register's description).
9.3.3 DMA CHANNEL OPERATION
A DMA channel is switched on with bit DMA_ON. This bit is automatically reset if the
dma transfer is finished. The DMA channels can either be triggered by software or by a
peripheral DMA request. If DREQ_MODE is 0, then a DMA channel is immediately
triggered. If DREQ_MODE is 1 the DMA channel can be triggered by a Hardware
interrupt.
If DMA starts, data is transferred from address DMAx_A_START_REG to address
DMAx_B_START_REG for a length of DMAx_LEN_REG, which can be 8, 16 or 32 bits
wide. The address increment is realized with an internal 13 bits counter
DMAx_IDX_REG, which is set to 0 if the DMA transfer starts and is compared with the
DMA_LEN_REG after each transfer. The register value is multiplied according to the
AINC and BINC and BW values before it is added to
DMA_B_START_REG and DMA_B_START_REG. AINC or BINC must be 0 for register
access.
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Figure 8 DMA Channel Diagram
If at the end of a DMA cycle, the DMA start condition is still true, the DMA continues.
The DMA stops if DREQ_MODE is low or if DMAx_LEN_REG is equal to the internal
index register. This condition also clears the DMA_ON bit.
If bit CIRCULAR is set to 1, the DMA controller automatically resets the internal index
registers and continues from its starting address without intervention of the ARM
CortexTM M0. If the DMA controller is started with DREQ_MODE =0, the DMA will
always stop, regardless of the state of CIRCULAR.
Each DMA channel can generate an interrupt if DMAx_INT_REG if equal to
DMAx_IDX_REG. After the transfer and before DMAx_IDX_REG is incremented, the
interrupt is generated. Example: if DMA_x_INT_REG=0 and DMA_x_LEN_REG=0,
there will be one transfer and an interrupt.
9.3.4 DMA ARBITRATION
The priority level of a DMA channel can be set with bits DMA_PRIO[2-0]. These bits
determine which DMA channel will be activated in case more than one DMA channel
requests DMA. If two or more channels have the same priority, an inherent priority
applies, (see register description).
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With DREQ_MODE = 0, a DMA can be interrupted by a channel with a higher priority if
the DMA_IDLE bit is set. When DMA_INIT is set, however, the DMA channel currently
performing the transfer locks the bus and cannot be interrupted by any other channel,
until the transfer is completed, regardless if DMA_IDLE is set. The purpose of
DMA_INIT is to initialize a specific memory block with a certain value, fetched also from
memory, without any interruption from other active DMA channels that may request the
bus at the same time. Consequently, it should be used only for memory initialization,
while when the DMA transfers data to/ from peripherals, it should be set to '0'. Note that
AINC must be set to '0' and BINC to '1', when DMA_INIT is enabled.
It should be noted that memory initialization could also be performed without having the
DMA_INIT enabled and by simply setting AINC to '0' and BINC to '1', provided that the
source address memory value will not change during the transfer. However, it is not
guaranteed that the DMA transfer will not be interrupted by other channels of higher
priority, when these request access to the bus at the same time.
9.3.5 FREEZING DMA CHANNELS
Each channel of the DMA controller can be temporarily disabled by writing a 1 to freeze
all channels at SET_FREEZE_REG.
To enable the channels again, a 1 to bits at the RESET_FREEZE_REG must be written.
There is no hardware protection from erroneous programming of the DMA registers.
It is noted that the on-going Memory-to-Memory transfers (DREQ_MODE='0') cannot be
interrupted. Thus, in that case, the corresponding DMA channels will be frozen after any
on-going Memory-to memory transfer is completed.
9.4 I2C Interface
The I2C Interface is a programmable control bus that provides support for the
communications link between Integrated Circuits in a system. It is a simple two-wire bus
with a software-defined protocol for system control, which is used in temperature
sensors and voltage level translators to EEPROMs, general-purpose I/O, A/D and D/A
converters.
Features
• Two-wire I2C serial interface consists of a serial data line (SDA) and a serial
clock (SCL)
• Two speeds are supported:
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•
•
•
•
•
•
•
•
•
•
•
o Standard mode (0 to 100kbit/s)
o Fast mode (= MAX_T_POLL_COUNT, exit with the
relevant error code.
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7. If I2C_ENABLE_STATUS[0] is 1, then sleep for ti2c_poll and proceed to the previous
step.
Otherwise, exit with a relevant success code.
9.6 UART
The ISM14585-L35 contains two identical instances of this block, i.e. UART and
UART2. The UART is compliant to the industry-standard 16550 and is used for serial
communication with a peripheral. Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and transmitted to the destination device.
Serial data is also received by the UART and stored for the master (CPU) to read back.
There is also DMA support on the UART block thus the internal FIFOs can be used.
Both UARTs support hardware flow control signals (RTS, CTS).
Features:
• 16 bytes Transmit and receive FIFOs
• Hardware flow control support (CTS/RTS)
• Shadow registers to reduce software overhead and also include a software
programmable reset
• Transmitter Holding Register Empty (THRE) interrupt mode
• IrDA 1.0 SIR mode supporting low power mode.
• Functionality based on the 16550 industry standard:
• Programmable character properties, such as number of data bits per character
(5-8), optional parity bit (with odd or even select) and number of stop bits (1, 1.5
or 2)
• Line break generation and detection
• Prioritized interrupt identification
• Programmable serial data baud rate as calculated by the following: baud rate =
(serial clock frequency)/(divisor).
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Figure 20 UART Block Diagram
9.6.1 UART (RS232) SERIAL PROTOCOL
Because the serial communication between the UART and the selected device is
asynchronous, additional bits (start and stop) are added to the serial data to
indicate the beginning and end. Utilizing these bits allows two devices to be
synchronized. This structure of serial data accompanied by start and stop bits is
referred to as a character, as shown in Figure 21.
Figure 21 Serial Data Format
An additional parity bit may be added to the serial character. This bit appears after the
last data bit and before the stop bit(s) in the character structure to provide the UART
with the ability to perform simple error checking on the received data.
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The UART Line Control Register (UART_LCR_REG) is used to control the serial
character characteristics. The individual bits of the data word are sent after the start bit,
starting with the least significant bit (LSB). These are followed by the optional parity bit,
followed by the stop bit(s), which can be 1, 1.5 or 2.
All the bits in the transmission (with exception to the half stop bit when 1.5 stop bits are
used) are transmitted for exactly the same time duration. This is referred to as a Bit
Period or Bit Time. One BitTime equals 16 baud clocks. To ensure stability on the line
the receiver samples the serial input data at approximately the mid-point of the Bit Time
once the start bit has been detected. As the exact number of baud clocks that each bit
was transmitted for is known, calculating the mid-point for sampling is not difficult, that is
every 16 baud clocks after the mid-point sample of the start bit. Figure 22 shows the
sampling points of the first couple of bits in a serial character.
Figure 22 Receiver Serial Data Sampling Points
As part of the 16550 standard an optional baud clock reference output signal
(baudout_n) is supplied to provide timing information to receiving devices that require it.
The baud rate of the UART is controlled by the serial clock (sclk or pclk in a single clock
implementation) and the Divisor Latch Register (DLH and DLL).
9.6.2 IRDA 1.0 SIR PROTOCOL
The Infrared Data Association (IrDA) 1.0 Serial Infrared (SIR) mode supports
bidirectional data communications with remote devices using infrared radiation as the
transmission medium. IrDA 1.0 SIR mode specifies a maximum baud rate of 115.2kBd.
Note: Information provided on IrDA SIR mode in this section assumes that the reader is
fully familiar with the IrDA Serial Infrared Physical Layer Specifications. This
specification can be obtained from the following website: http://www.irda.org.
The data format is similar to the standard serial (sout and sin) data format. Each data
character is sent serially, beginning with a start bit, followed by 8 data bits, and ending
with at least one stop bit.
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Thus, the number of data bits that can be sent is fixed. No parity information can be
supplied and only one stop bit is used while in this mode.
Trying to adjust the number of data bits sent or enable parity with the Line Control
Register (LCR) has no effect. When the UART is configured to support IrDA 1.0 SIR it
can be enabled with Mode Control Register (MCR) bit 6. When the UART is not
configured to support IrDA SIR mode, none of the logic is implemented and the mode
cannot be activated, reducing total gate counts. When SIR mode is enabled, and active,
serial data is transmitted and received on the sir_out_n and sir_in ports, respectively.
Transmitting a single infrared pulse signals a logic zero, while a logic one is represented
by not sending a pulse. The width of each pulse is 3/16th of a normal serial bit time.
Thus, each new character begins with an infrared pulse for the start bit. However,
received data is inverted from transmitted data due to the infrared pulses energizing the
photo transistor base of the IrDA receiver, pulling its output low. This inverted transistor
output is then fed to the UART sir_in port, which then has correct UART polarity. Figure
23 shows the timing diagram for the IrDA SIR data format in comparison to the standard
serial format.
Figure 23 IrDA SIR Data Format
As detailed in the IrDA 1.0 SIR, the UART can be configured to support a low-power
reception mode. When the UART is configured in this mode, the reception of SIR pulses
of 1.41μs (minimum pulse duration) is possible, as well as nominal 3/16th of a normal
serial bit time. Using this low-power reception mode requires programming the Low
Power Divisor Latch (LPDLL/LPDLH) registers.
It should be noted that for all sclk frequencies greater than or equal to 7.37MHz (and
obey the requirements of the Low Power Divisor Latch registers), pulses of 1.41μs are
detectable. However, there are several values of sclk that do not allow the detection of
such a narrow pulse and these are as follows:
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Table: Low Power Divisor Latch Register Values:
SCLK
1.84 MHz
3.69 MHz
5.33 MHz
Low Power Divisor Latch Register Value
1
2
3
Min Pulse Width for Detection
3.77 μs
2.086 μs
1.584 μs
When IrDA SIR mode is enabled, the UART operation is similar to when the mode is
disabled, with one exception; data transfers can only occur in half-duplex fashion when
IrDA SIR mode is enabled. This is because the IrDA SIR physical layer specifies a
minimum of 10ms delay between transmission and reception. This 10ms delay must be
generated by software.
9.6.3 CLOCK SUPPORT
The UART has two system clocks (pclk and sclk). Having the second asynchronous
serial clock (sclk) implemented accommodates accurate serial baud rate settings, as
well as APB bus interface requirements.
With the two clock design a synchronization module is implemented for synchronization
of all control and data across the two system clock boundaries.
A serial clock faster than four-times the pclk does not leave enough time for a complete
incoming character to be received and pushed into the receiver FIFO. However, in most
cases, the pclk signal is faster than the serial clock and this should never be an issue.
The serial clock modules must have time to see new register values and reset their
respective state machines. This total time is guaranteed to be no more than eight clock
cycles of the slower of the two system clocks. Therefore, no data should be transmitted
or received before this maximum time expires, after initial configuration.
9.6.4 CLOCK SUPPORT
The assertion of the UART interrupt (UART_INT) occurs whenever one of the several
prioritized interrupt types are enabled and active. The following interrupt types can be
enabled with the IER register:
•
•
•
•
Receiver Error
Receiver Data Available
Character Timeout (in FIFO mode only)
Transmitter Holding Register Empty at/below threshold (in Programmable THRE
interrupt mode)
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When an interrupt occurs, the master accesses the UART_IIR_REG to determine the
source of the interrupt before dealing with it accordingly. These interrupt types are
described in more detail in below table
Interrupt ID
Bits [3-0]
0001
0110
Priority
Highest
Interrupt Set and Reset Functions
Interrupt Source
Interrupt Type
None
Receiver Line
status
Receiver Data
Available
0100
1
1100
2
Character timeout
indication
0010
3
Transmitter holding
register empty
0000
0111
4
Lowest
Reserved
Reserved
Interrupt Reset Control
Overrun/parity/ framing errors
or break interrupt
Receiver data available (nonFIFO mode or FIFOs disabled)
or
RCVR FIFO trigger level reached
(FIFO mode and FIFOs enabled)
No characters in or out of the
RCVR FIFO during the last 4
character times and there is at
least 1 character in it during this
time.
Transmitter holding register empty
(Prog. THRE Mode disabled) or
XMIT FIFO at
or
below threshold (Prog. THRE
Mode enabled).
Reading the line status
register
Reading the receiver buffer register (nonFIFO mode or FIFOs disabled)
or
the FIFO drops below the trigger level
(FIFO mode and FIFOs enabled)
Reading the receiver
buffer register
-
-
Reading the IIR register (if source of
interrupt);
or,
writing into THR (FIFOs or THRE Mode
not selected or disabled)
or
XMIT FIFO above threshold (FIFOs and
THRE Mode selected and enabled).
9.6.5 PROGRAMMABLE THRE INTERRUPT
The UART can be configured to have a Programmable THRE Interrupt mode available
to increase system performance.
When Programmable THRE Interrupt mode is selected it can be enabled via the
Interrupt Enable Register (IER[7]). When FIFOs and the THRE Mode are implemented
and enabled, THRE Interrupts are active at, and below, a programmed transmitter FIFO
empty threshold level, as opposed to empty, as shown in the flowchart in Figure 24.
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Figure 24 Flowchart of Interrupt Generation for Programmable THRE Interrupt Mode
This threshold level is programmed into FCR[5:4]. The available empty thresholds are:
empty, 2, ¼ and ½. See UART_FCR_REG for threshold setting details. Selection of the
best threshold value depends on the system's ability to begin a new transmission
sequence in a timely manner. However, one of these thresholds should prove optimum
in increasing system performance by preventing the transmitter FIFO from running
empty.
In addition to the interrupt change, Line Status Register (LSR[5]) also switches function
from indicating transmitter FIFO empty, to FIFO full. This allows software to fill the FIFO
each transmit sequence by polling LSR[5] before writing another character. The flow
then becomes, “fill transmitter FIFO whenever an interrupt occurs and there is data to
transmit”, instead of waiting until the FIFO is completely empty. Waiting until the FIFO is
empty causes a performance hit whenever the system is too busy to respond
immediately.
Even if everything else is selected and enabled, if the FIFOs are disabled via FCR[0],
the Programmable THRE Interrupt mode is also disabled. When not selected or
disabled, THRE interrupts and LSR[5] function normally (both reflecting an empty THR
or FIFO). The flowchart of THRE interrupt generation when not in programmable THRE
interrupt mode is shown in Figure 25.
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Figure 25 Flowchart of Interrupt Generation When Not in Programmable THRE Interrupt Mode
9.6.6 SHADOW REGISTERS
The shadow registers shadow some of the existing register bits that are regularly
modified by software. These can be used to reduce the software overhead that is
introduced by having to perform read-modify-writes.
•
•
•
•
•
UART_SRBR_REG support a host burst mode where the host increments its
address but still accesses the same Receive buffer register.
UART_STHR support a host burst mode where the host increments its address
but still accesses the same transmit holding register.
UART_SFE_REG accesses the FCR[0] register without accessing the other
UART_FCR_REG bits.
UART_SRT_REG accesses the FCR[7-6] register without accessing the other
UART_FCR_REG bits.
UART_STER_REG accesses the FCR[5-4] register without accessing the other
UART_FCR_REG bits.
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9.6.7 DIRECT TEST MODE
The on-chip UARTS can be used for the Direct Test Mode required for the final product
PHY layer testing. It can be done either over the HCI layer, which engages a full
CTS/RTS UART or using a 2- wire UART directly as described in the Bluetooth Low
Energy Specification (Volume 6, Part F).
9.7 SPI+ Interface
This interface supports a subset of the Serial Peripheral Interface (SPI™). The serial
interface can transmit and receive 8, 16 or 32 bits in master/slave mode and transmit 9
bits in master mode. The SPI+ interface has enhanced functionality with bidirectional
2x16-bit word FIFOs.
Features
• Slave and Master mode
• 8 bit, 9 bit, 16 bit or 32 bit operation
• Clock speeds up to 16 MHz for the SPI controller. Programmable output
frequencies of SPI source clock divided by 1, 2, 4, 8
• SPI clock line speed up to 8 MHz
• SPI mode 0, 1, 2, 3 support (clock edge and phase)
• Programmable SPI_DO idle level
• Maskable Interrupt generation
• Bus load reduction by unidirectional writes-only and reads-only modes.
• Built-in RX/TX FIFOs for continuous SPI bursts.
• DMA support
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Figure 26 SPI Block Diagram
9.7.1 OPERATION WITHOUT FIFOS
This mode is the default mode.
Master Mode
To enable SPITM operation, first the individual port signal must be enabled. Next the
SPI must be configured in SPI_CTRL_REG, for the desired mode. Finally bit SPI_ON
must be set to 1.
A SPI transfer cycle starts after writing to the SPI_RX_TX_REG0. In case of 32 bits
mode, the PI_RX_TX_REG1 must be written first. Writing to SPI_RX_TX_REG0 also
sets the SPI_TXH. As soon as the holding register is copied to the IO buffer, the
SPI_TXH is reset and a serial transfer cycle of 8/9/16/32 clock-cycles is started which
causes 8/9/16/32 bits to be transmitted on SPI_DO. Simultaneously, data is received on
SPI_DI and shifted into the IO buffer. The transfer cycle finishes after the
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8th/9th/16th/32nd clock cycle and SPI_INT_BIT bit is set in the SPI_CTRL_REG and
SPI_INT_PEND bit in (RE)SET_INT_PENDING_REG is set. The received bits in the IO
buffer are copied to the SPI_RX_TX_REG0 (and SPI_RX_TX_REG1 in case of 32 bits
mode) were they can be
read by the CPU.
Interrupts to the CPU can be disabled using the SPI_MINT bit. To clear the SPI interrupt
source, any value to SPI_CLEAR_INT_REG must be written. Note however that
SPI_INT will be set as long as the RX-FIFO contains unread data.
Slave Mode
The slave mode is selected with SPI_SMn set to 1 and the Px_MODE_REG must also
select SPI_CLK as input. The functionality of the IO buffer in slave and master mode is
identical. The SPI module clocks data in on SPI_DI and out on SPI_DO on every active
edge of SPI_CLK. As shown in Figure 24 to Figure 27, Figure 27: SPI Master/slave,
Mode 3: SPI_POL=1 and SPI_PHA=1. The SPI has an active low clock enable SPI_EN,
which can be enabled with bit SPI_EN_CTRL=1.
In slave mode the internal SPI clock must be more than four times the SPI_CLK
In slave mode the SPI_EN serves as a clock enable and bit synchronization If enabled
with bit SPI_EN_CTRL. As soon as SPI_EN is deactivated between the MSB and LSB
bits, the I/O buffer is reset.
SPI_POL and SPI_PHA
The phase and polarity of the serial clock can be changed with bits SPI_POL and
SPI_PHA in the SPI_CTRL_REG.
SPI_DO Idle Levels
The idle level of signal SPI_DO depends on the master or slave mode and polarity and
phase mode of the clock.
In master mode pin SPI_DO gets the value of bit SPI_DO if the SPI is idle in all modes.
Also, if slave in SPI modes 0 and 2, SPI_DO is the initial and final idle level.
In SPI modes 1 and 3 however there is no clock edge after the sampled lsb and pin
SPI_DO gets the lsb value of the IO buffer. If required, the SPI_DO can be forced to the
SPI_DO bit level by resetting the SPI to the idle state by shortly setting bit SPI_RST to
1. (Optionally SPI_FORCE_DO can be set, but this does not reset the IO buffer). The
following diagrams show the timing of the SPITM interface.
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Writes Only Mode
In “writes only” mode (SPI_FIFO_MODE = “10“) only the TX-FIFO is used. Received
data will be copied to the SPI_RX_TX_REGx, but if a new SPI transfer is finished before
the old data is read from the memory, this register will be overwritten.
SPI_INT acts as a tx_request signal, indicating that there is still place in the FIFO. It will
be ‘0’ when the FIFO is full or else ‘1’ when it’s not full. This is also indicated in the
SPI_CTRL_REG[SPI_TXH], which is ‘1’ if the TX-FIFO is full. Writing to the FIFO if this
bit is still 1, will result in transmission of undefined data. If all data has been transferred,
SPI_CTRL_REG1 [SPI_BUSY] will become ‘0’.
Reads Only Mode
In “reads only” mode (SPI_FIFO_MODE = “01“) only the RX-FIFO is used. Transfers will
start immediately when the SPI is turned on in this mode. In transmit direction the
SPI_DO pin will transmit the IO buffer contents being the actual value of the
SPI_TX_REGx (all 0’s after reset). This means that no dummy writes are needed for
reads only transfers.
In Slave mode transfers only take place if the external master initiates them, but in
master mode this means that transfers will continue until the RX-FIFO is full. If this
happens SPI_CTRL_REG1[SPI_BUSY] will become ‘0’. If exactly N words need to be
read from SPI device, first read (N - fifosize+1) words. Then wait until the SPI_BUSY
becomes ‘0’, set SPI_FIFO_MODE to “00” and finally read the remaining (fifosize +1)
words. Here fifosize is 4/2/1 words for 8/16/32 bits mode respectively.
If this is not done, more data will be read from the SPI device until the FIFO is
completely filled, or the SPI is turned off.
Bidirectional transfers with FIFO
If SPI_FIFO_MODE is “00“, both registers are used as a FIFO. SPI_TXH indicates that
TX-FIFO is full, SPI_INT indicates that there is data in the RX-FIFO.
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Figure 27 SPI Master/Slave, Mode 0: SPI_POL=0 and SPI_PHA=0
Note 1: If 9 bits SPI mode, the MSB bit in transmit direction is determined by bit
SPI_CTRL_REG[SPI_9BIT_VAL]. In receive direction, the MSB is received but not
stored.
Figure 28 SPI Master/Slave, Mode 1: SPI_POL=0 and SPI_PHA=1
For the MSB bit refer to Note 1
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Figure 29 SPI Master/Slave, Mode 2: SPI_POL=1 and SPI_PHA=0
For the MSB bit refer to Note 1.
Figure 30 SPI Master/slave, Mode 3: SPI_POL=1 and SPI_PHA=1
For the MSB bit refer to Note 1
9.8 Wake-Up Timer
The Wake-up timer can be programmed to wake up the ISM14585 from power down
mode after a pre-programmed number of GPIO events.
Each of the GPIO inputs can be selected to generate an event by programming the
corresponding WKUP_SELECT_Px_REG register. When all WKUP_SELECT_Px_REG
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registers are configured to generate a wake-up interrupt, a toggle on any GPIO will
wake up the system.
•
•
The input signal edge can be selected by programming the
WKUP_POL_Px_REG register.
The block diagram illustrating the Wake-up function is shown in Figure 31.
Features
• Monitors any GPIO state change
• Implements debouncing time from 0ms up to 63ms
• Accumulates external events and compares the number to a programmed value
• Generates an interrupt to the CPU
Figure 31 Wake-Up Timer Block Diagram
A LOW to HIGH level transition on the selected input port, while
WKUP_POL_Px_REG[y] = 0, sets internal signal “key_hit” to ‘1’. This signal triggers the
event counter state machine as shown in Figure 31. The debounce timer is loaded with
value WKUP_CTRL_REG[WKUP_DEB_VALUE]. The timer counts down every 1ms. If
the timer reaches 0 and the “key_hit” signal is still ‘1’, the event counter will be
incremented.
The event counter is edge sensitive. After detecting an active edge, a reverse edge
must be detected first before it goes back to the IDLE state and from there starts waiting
for a new active edge.
If the event counter is equal to the value set in the WKUP_COMPARE_REG register,
the counter will be reset, and an interrupt will be generated, if it was enabled by
WKUP_CTRL_REG[ENABLE_IRQ].
The interrupt can be cleared by writing any value to register WKUP_RESET_IRQ_REG.
The event counter can be reset by writing any value to register
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WKUP_RESET_CNTR_REG. The value of the event counter can be read at any time
by reading register WKUP_COUNTER_REG.
Figure 32 Event Counter State Machine for the Wake-Up Interrupt Generator
9.9 General Purpose Timers
The Timer block contains two timer modules that are software controlled, programmable
and can be used for various tasks. Timer 0 is a 16-bit general purpose timer with a
PWM output capability. Timer 2 is a 14-bit counter that generates three identical PWM
signals in a quite flexible manner.
9.9.1 TIMER 0
Timer 0 is a 16-bit general purpose software programmable timer, which has the ability
of generating Pulse Width Modulated signals, namely PWM0 and PWM1. It also
generates the SWTIM_IRQ interrupt to the ARM Cortex-M0. It can be configured in
various modes regarding output frequency, duty cycle and the modulation of the PWM
signals.
Features:
•
16-bit general purpose timer
•
Ability to generate 2 Pulse Width Modulated signals (PWM0 and PWM1)
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•
Programmable output frequency:
M = 0 to (216-1)
•
Programmable duty cycle:
•
Separately programmable interrupt timer:
with N = 0 to (216-1),
Figure 33 Timer 0 Block Diagram
Figure 33 shows the block diagram of Timer 0. The 16 bits timer consists of two
counters: T0-counter and ON-counter, and three registers: TIMER0_RELOAD_M_REG,
TIMER0_RELOAD_N_REG and TIMER0_ON_REG. Upon reset, the counter and
register values are 0x0000. Timer 0 will generate a Pulse Width Modulated signal
PWM0. The frequency and duty cycle of PWM0 are determined by the contents of the
TIMER0_RELOAD_N_REG and the TIMER0_RELOAD_M_REG registers.
The timer can run at five different clocks: 16 MHz, 8 MHz, 4 MHz, 2 MHz or 32 kHz. The
32 kHz clock is selected by default with bit TIM0_CLK_SEL in the TIMER0_CTRL_REG
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register. This ‘slow’ clock has no enabling bit. The other four options can be selected by
setting the TIM0_CLK_SEL bit and the TMR_ENABLE bit in the CLK_PER_REG
(default disabled). This register also controls the frequency via the TMR_DIV bits. An
extra clock divider is available that can be activated via bit TIM0_CLK_DIV of the timer
control register TIMER0_CTRL_REG. This clock divider is only used for the ON-counter
and always divides by 10. Timer 0 operates in PWM mode. The signals PWM0 and
PWM1 can be mapped to any GPIOs.
Timer 0 PWM Mode
If bit TIM0_CTRL in the TIMER0_CTRL_REG is set, Timer 0 will start running.
SWTIM_IRQ will be generated and the T0-counter will load its start value from the
TIMER0_RELOAD_M_REG register, and will decrement on each clock. The ONcounter also loads its start value from the TIMER0_ON_REG register and decrements
with the selected clock.
When the T0-counter reaches zero, the internal signal T0-toggle will be toggled to select
the TIMER0_RELOAD_N_REG whose value will be loaded in the T0-counter. Each
time the T0-counter reaches zero it will alternately be reloaded with the values of the
M0- and N0-shadow registers respectively. PWM0 will be high when the M0-value
decrements and low when the N0-value decrements. For PWM1 the opposite is
applicable since it is inverted. If bit PWM_MODE in the TIMER0_CTRL_REG register is
set, the PWM signals are not HIGH during the ‘high time’ but output a clock in that
stage. The frequency is based on the clock settings defined in the CLK_PER_REG
register (also in 32 kHz mode), but the selected clock frequency is divided by two to get
a 50 % duty cycle.
If the ON-counter reaches zero it will remain zero until the T0-counter also reaches
zero, while decrementing the value loaded from the TIMER0_RELOAD_N_REGregister
(PWM0 is low). The counter will then generate an interrupt (SWTIM_IRQ). The ONcounter will be reloaded with the value of the TIMER0_ON_REG register. The T0counter as well as the M0-shadow register will be loaded with the value of the
TIMER0_RELOAD_M_REG register. At the same time, the N0-shadow register
will be loaded by the TIMER0_RELOAD_N_REG register. Both counters will be
decremented on the next clock again and the sequence will be repeated.
Note that it is possible to generate interrupts at a high rate, when selecting a high clock
frequency in combination with low counter values. This could result in missed interrupt
events.
During the time that the ON-counter is non-zero, new values for the ON-register, M0register and N0-register can be written, but they are not used by the T0-counter until a
full cycle is finished. More specifically, the newly written values in the
TIMER0_RELOAD_M_REG and TIMER0_RELOAD_N_REG registers are only stored
into the shadow registers when the ON-counter and the T0-counter have both reached
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zero and the T0-counter was decrementing the value loaded from the
TIMER0_RELOAD_N_REG register (see Figure 34).
Figure 34 Timer 0 PWM Mode
At start-up both counters and the PWM0 signal are LOW so also at start-up an interrupt
is generated. If Timer 0 is disabled all flip-flops, counters and outputs are in reset state
except for the ON-register, the TIMER0_RELOAD_N_REG register and the
TIMER0_RELOAD_M_REG register.
The timer input registers ON-register, TIMER0_RELOAD_N_REGand
TIMER0_RELOAD_M_REG can be written, and the counter registers ON-counter and
T0-counter can be read. When reading from the address of the ON-register, the value of
the ON-counter is returned. Reading from the address of either the
TIMER0_RELOAD_N_REG or the TIMER0_RELOAD_M_REG register, returns the
value of the T0-counter.
It is possible to freeze Timer 0 with bit FRZ_SWTIM of the register SET_FREEZE_REG.
When the timer is frozen the timer counters are not decremented. This will freeze all the
timer registers at their last value. The timer will continue its operation again when bit
FRZ_SWTIM is cleared via register RESET_FREEZE_REG.
9.9.2 TIMER 2
Timer 2 has three Pulse Width Modulated (PWM) outputs. The block diagram is shown
in Figure 35
Features:
•
14-bit general purpose timer
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•
Ability to generate 3 Pulse Width Modulated signals (PWM2, PWM3 and PWM4)
•
Input clock frequency:
MHz or 32 kHz
•
Programmable output frequency:
•
Three outputs with programmable duty cycle from 0% to 100%
•
Used for white LED intensity (on/off) control
with N = 1, 2, 4 or 8 and sys_clk = 16
Figure 35 Timer 2 PWM Block Diagram
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The Timer 2 is clocked with the system clock divided by TMR_DIV (1, 2, 4 or 8) and can
be enabled with TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_ENABLE].
T2_FREQ_CNTR determines the output frequency of the T2_PMWn output. This
counter counts down from the value stored in register TRIPLE_PWM_FREQUENCY. At
counter value 0, T2_FREQ_CNTR sets the T2_PWMn output to ‘1’ and the counter is
reloaded again.
T2_DUTY_CNTR is an up-counter that determines the duty cycle of the T2_PWMn
output signal. After the block is enabled, the counter starts from 0. If T2_DUTY_CNTR
is equal to the value stored in the respective PWMn_DUTY_CYCLE register, this resets
the T2_PWMn output to 0. T2_DUTY_CNTR is reset when
TRIPLE_PWM_FREQUENCY is 0.
Note that the value of PWMn_DUTY_CYCLE must be less or equal than
TRIPLE_PWM_FREQUENCY.
The Timer 2 is enabled/disabled by programming the
TRIPLE_PWM_CTRL_REG[TRIPLE_PWM_EN] bit.
The timing diagram of Timer 2 is shown in Figure 36
Freeze function
During RF activity it may be desirable to temporarily suppress the PWM switching noise.
This can be done by setting TRIPLE_PWM_CTRL_REG[HW_PAUSE_EN] = 1. The
effect is that whenever there is a transmission or a reception process from the Radio,
T2_DUTY_CNTR is frozen and T2_PWMx output is switched to ‘0’ to disable the
selected T2_PWM1, T2_PWM2, T2_PWM3. As soon as the Radio is idle (i.e. RX_EN or
TX_EN signals are zero), T2_DUTY_CNTR resumes counting and finalizes the
remaining part of the PWM duty cycle.
TRIPLE_PWM_CTRL_REG[SW_PAUSE_EN] can be set to ‘0’ to disable the automatic,
hardware driven freeze function of the duty counter and keep the duty cycle constant.
Note that the RX_EN and TX_EN signals are not software driven but controlled by the
BLE core hardware.
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Figure 36 Timer 2 PWM Timing Diagram
9.10 Watchdog Timer
The Watchdog Timer is an 8-bit timer with sign bit that can be used to detect an
unexpected execution sequence caused by a software run-away and can generate a full
system reset or a Non- Maskable Interrupt (NMI).
Features:
• 8 bits down counter with sign bit, clocked with a 10.24ms clock for a maximum
2.6s time-out.
• Non-Maskable Interrupt (NMI) or WDOG reset.
• Optional automatic WDOG reset if NMI handler fails to update the Watchdog
register.
• Non-maskable Watchdog freeze of the Cortex-M0 Debug module when the
Cortex-M0 is halted in Debug state. Maskable Watchdog freeze by user program.
Figure 37 Watchdog Timer Block Diagram
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The 8 bits watchdog timer is decremented by 1 every 10.24ms. The timer value can be
accessed through the WATCHDOG_REG register which is set to 255 (FF16) at reset.
This results in a maximum watchdog time-out of ~2.6s. During write access the
WATCHDOG_REG[WDOG_WEN] bits must be 0. This provides extra filtering for a
software run-away writing all ones to the WATCHDOG_REG. If the watchdog counter
reaches 0, the counter value will get a negative value by setting bit 8. The counter
sequence becomes 1, 0, 1FF16 (-1), 1FE16(-2),...1F016 (-16).
If WATCHDOG_CTRL_REG[NMI_RST] = 0, the watchdog timer will generate an NMI if
the watchdog timer reaches 0 and a WDOG reset if the counter becomes less or equal
to -16 (1F016). The NMI handler must write any value > -16 to the WATCHDOG_REG
to prevent the generation of a WDOG reset at counter value -16 after 16*10.24 =
163.8ms.
If WATCHDOG_CTRL_REG[NMI_RST] = 1, the watchdog timer generates a WDOG
reset if the timer becomes less or equal than 0.
The WDOG reset is one of the SYS (system) reset sources and resets the whole
device, including setting the WATCHDOG_REG register to 255, except for the RST pin,
the Power On reset, the HW reset and the DBG (debug module) reset. Since the HW
reset is not triggered, the SYS_CTRL_REG[REMAP_ADR0] bits will retain their value
and the Cortex-M0 will start executing again from the current selected memory at
address zero. Refer to the POR, HW and SW Reset section for an overview of the
complete reset circuit and conditions.
For debugging purposes, the Cortex-M0 Debug module can always freeze the
watchdog by setting the DHCSR[DBGKEY | C_HALT | C_DEBUGEN] control bits
(reflected by the status bit S_HALT). This is automatically done by the debug tool, e.g.
during step-by-step debugging. Note that this bit also freezes the Wake-up Timer, the
Software Timer and the BLE master clock. For additional information also see the
DEBUG_REG[DEBUGS_FREEZE_EN] mask register. The C_DEBUGEN bit is not
accessible by the user software to prevent freezing the watchdog.
In addition to the S_HALT bit, the watchdog timer can also be frozen if NMI_RST=0 and
SET_FREEZE_REG[FRZ_WDOG] is set to ‘1’. The watchdog timer resumes counting
when RESET_FREEZE_REG[FRZ_WDOG] is set to ‘1’. The
WATCHDOG_CTRL_REG[NMI_RST] bit can only be set by software and will only be
reset on a SYS reset. Note that if the system is not remapped, i.e. SysRAM is at
address 0x20000000, then a watchdog fire will trigger the BootROM code to be
executed again.
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9.11 Input/Output Ports
The ISM14585-L35 has software-configurable I/O pin assignment, organized into ports
Port 0, Port 1.
.
Features:
•
•
•
•
•
•
Port 0: 8 pins, Port 1: 4 pins
Fully programmable pin assignment
Selectable 25kΩ pull-up, pull-down resistors per pin
Pull-up voltage either VBAT3V (BUCK mode) or VBAT1V (BOOST mode)
configurable per pin
Fixed assignment for analog pin ADC[3:0]
Pins can retain their last state when system enters the Extended or Deep Sleep
mode.
Figure 38 Port P0, and P1 with Programmable Pin Assignment
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9.11.1 PROGRAMMABLE PIN ASSIGNMENT
The Programmable Pin Assignment (PPA) provides a multiplexing function to the I/O
pins of on-chip peripherals. Any peripheral input or output signal can be freely mapped
to any I/O port bit by setting Pxy_MODE_REG[4-0]:
0x00 to 0x1F: Peripheral IO ID (PID)
Refer to the Px_MODE_REGs for an overview of the available PIDs. Analog ADC has
fixed pin assignment in order to limit interference with the digital domain. The SWD
interface (JTAG) is mapped on P1_4 and P1_5.
Priority
The firmware has the possibility to assign the same peripheral output to more than one
pin. It is the responsibility of the user to make a unique assignment.
In case more than one input signal is assigned to a peripheral input, the left most pin in
the lowest port pin number has priority. (e.g P00_MODE_REG has priority over
P01_MODE_REG).
Direction Control
The port direction is controlled by setting:
Pxy_MODE_REG[9-8]
00 = Input, no resistors selected
01 = Input, pull-up selected
10 = Input, Pull-down selected
11 = Output, no resistors selected
In output mode and analog mode, the pull-up/down resistors are automatically disabled.
9.11.2 GENERAL PURPOSE PORT REGISTERS
The general purpose ports are selected with PID=0. The port function is accessible
through registers:
•
•
•
Px_DATA_REG: Port data input/output register
Px_SET_OUTPUT_DATA_REG: Port set output register
Px_RESET_OUTPUT_DATA_REG: Port reset output register
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9.11.2.1
PORT DATA REGISTER
The registers input Px_DATA_REG and output Px_DATA_REG are mapped on the
same address.
The data input register (Px_DATA_REG) is a read-only register that returns the current
state on each port pin even if the output direction is selected, regardless of the
programmed PID, unless the analog function is selected (in this case it reads 0). The
ARM CPU can read this register at any time even when the pin is configured as an
output.
The data output register (Px_DATA_REG) holds the data to be driven on the output port
pins. In this configuration, writing to the register changes the output value.
9.11.2.2
PORT SET DATA OUTPUT REGISTER
Writing a 1 in the set data output register (Px_SET_OUTPUT_DATA_REG) sets the
corresponding output pin. Writing a 0 is ignored.
9.11.2.3
PORT RESET DATA OUTPUT REGISTER
Writing a 1 in the reset data output register (Px_RESET_OUTPUT_DATA_REG) resets
the corresponding output pin. Writing a 0 is ignored.
9.11.2.4
FIXED ASSIGNMENT FUNCTIONALITY
There are certain signals that have a fixed mapping on specific general purpose IOs.
This assignment is illustrated in the following table:
GPIO
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
QUAD DEC (Note 1)
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
CHY_A/CHX_A/CHZ_A
CHY_B/CHX_B/CHZ_B
ADC (Note 2)
ADC_0
ADC_1
ADC_2
ADC_3
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•
•
Note 1 The mapping of the Quad Decoder signals on the respective pins, is
overruled by the QDEC_CTRL2_REG[CHx_PORT_SEL] register.
Note 2 The ADC case can be selected by the PID bit field on the respective Px port.
9.12 General Purpose ADC
The ISM14585-L35 is equipped with a high-speed ultra-low power 10-bit general
purpose Analog-to-Digital Converter (GPADC). It can operate in unipolar (single ended)
mode as well as in bipolar (differential) mode. The ADC has its own voltage regulator
(LDO) of 1.2 V, which represents the full scale reference voltage.
Features:
•
•
•
•
•
•
•
•
•
10-bit dynamic ADC with 65 ns conversion time
Maximum sampling rate 3.3 Msample/s
Ultra-low power (5μA typical supply current at 100ksample/s)
Single-ended as well as differential input with two input scales
Four single-ended or two differential external input channels
Battery monitoring function
Chopper function
Offset and zero scale adjust
Common-mode input level adjust
Figure 39 Block Diagram of the General Purpose ADC
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9.12.1 INPUT CHANNELS AND INPUT SCALE
The ISM14585-L35 has a multiplexer between the ADC and four specific GPIO ports
(P0_0 to P0_3). Furthermore, the ADC can also be used to monitor the battery voltage
and several internal voltages of the system (see GP_ADC_CTRL_REG).
Single-ended or differential operation is selected via bit
GP_ADC_CTRL_REG[GP_ADC_SE]. In differential mode the voltage difference
between two GPIO input ports will be converted. Via bit
GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] the input scale can be enlarged by a factor
of three, as summarized in below table.
GP_ADC_ATTN3X
GP_ADC_SE
0
0
1
1
1
0
1
0
Input Channels
P0_0, P0_1, P0_2, P0_3
[P0_0, P0_1], [P0_2, P0_3]
P0_0, P0_1, P0_2, P0_3
[P0_0, P0_1], [P0_2, P0_3]
-
Input Scale
0 V to +1.2 V
-1.2 V to +1.2 V
0 V to +3.6 V
-3.6 V to +3.6 V
Input Limits
-0.1 V to +1.3 V
-1.3 V to +1.3 V
-0.1 V to +3.45 V
-3.45 V to +3.45 V
GPADC Input Channels and Voltage Scale
9.12.2 STARTING THE ADC AND SAMPLING RATE
The GPADC is a dynamic ADC and consumes no static power, except for the LDO
which consumes less than 5μA. Enabling/disabling of the ADC is triggered by
configuring bit GP_ADC_CTRL_REG[GP_ADC_LDO_EN]. After enabling the LDO, a
settling time of 20 μs is required before an AD-conversion can be started.
Each conversion has two phases: the sampling phase and the conversion phase. When
bit GP_ADC_CTRL_REG[GP_ADC_EN] is set to ‘1’, the ADC continuously tracks
(samples) the selected input voltage. Writing a '1' at bit
GP_ADC_CTRL_REG[GP_ADC_START] ends the sampling phase and triggers the
conversion phase. When the conversion is ready, the ADC resets bit GP_ADC_START
to ‘0’ and returns to the sampling phase.
The conversion itself is fast and takes approximately one clock cycle of 16 MHz, though
the data handling will require several additional clock cycles, depending on the software
code style. The fastest code can handle the data in four clock cycles of 16 MHz,
resulting to a highest sampling rate of 16 MHz/5 = 3.3 Msample/s.
At full speed the ADC consumes approximately 50μA. If the data rate is less than 100
ksample/s, the current consumption will be in the range of 5μA.
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9.12.3 NON-IDEAL EFFECTS
Besides Differential Non-Linearity (DNL) and Integral Non-Linearity (INL), each ADC
has a gain error (linear) and an offset error (linear). The gain error of the GPADC
slightly reduces the effective input scale (up to 50 mV). The offset error causes the
effective input scale to become non-centered. The offset error of the GPADC is less
than 20 mV and can be reduced by chopping or by offset calibration.
The ADC result will also include some noise. If the input signal itself is noise free
(inductive effects included), the average noise level will be ±1 LSB. Taking more
samples and calculating the average value will reduce the noise and increase the
resolution.
With a 'perfect' input signal (e.g. if a filter capacitor is placed close to the input pin) most
of the noise comes from the low-power voltage regulator (LDO) of the ADC. Since the
DA14585 is targeted for ultra-compact applications, there is no pin available to add a
capacitor at this voltage regulator output.
The dynamic current of the ADC causes extra noise at the regulator output. This noise
can be reduced by setting bits GP_ADC_CTRL2_REG[GP_ADC_I20U] and
GP_ADC_CTRL2_REG[GP_ADC_IDYN] to ‘1’. Bit GP_ADC_I20U enables a constant
20μA load current at the regulator output so that the current will not drop to zero. Bit
GP_ADC_IDYN enables a 10μA load current during sampling phase so that the load
current during sampling and conversion phase becomes approximately the same.
9.12.4 CHOPPING
Chopping is a technique to cancel offset by taking two samples with opposite signal
polarity. This method also smooths out other non-ideal effects and is recommended for
DC and slowly changing signals.
Chopping is enabled by setting bit GP_ADC_CTRL_REG[GP_ADC_CHOP] to ‘1’.
The mid-scale value of the ADC is the 'natural' zero point of the ADC (ADC result =
511.5 = 1FF or 200 Hex = 01.1111.1111 or 10.0000.0000 Bin). Ideally this corresponds
to Vi = 1.2 V/2 = 0.6 V in single-ended mode and Vi = 0.0 V in differential mode.
If bit GP_ADC_CTRL2_REG[GP_ADC_ATTN3X] is set to ‘1’, the zero point is 3 times
higher (1.8 V single-ended and 0.0 V differential).
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With bit GP_ADC_CTRL_REG[GP_ADC_MUTE], the ADC input is switched to the
center scale input level, so the ADC result ideally is 511.5. If instead a value of 515 is
observed, the output offset is +3.5 (adc_off_p = 3.5).
With bit GP_ADC_CTRL_REG[GP_ADC_SIGN] the sign of the ADC input and output is
changed. Two sign changes have no effect on the signal path, though the sign of the
ADC offset will change.
If adc_off_p = 3.5 the ADC_result with opposite GP_ADC_SIGN will be 508. The sum of
these equals 515 + 508 = 1023. This is the mid-scale value of an 11-bit ADC, so one
extra bit due to the over-sampling by a factor of two.
The LSB of this 11-bit word should be ignored if a 10-bit word is preferred. In that case
the result is 511.5, so the actual output value will be 511 or 512.
9.12.5 OFFSET CALIBRATION
A relative high offset caused by a very small dynamic comparator (up to 20 mV, so
approximately 20 LSB). This offset can be cancelled with the chopping function, but it
still causes unwanted saturation effects at zero scale or full scale. With the
GP_ADC_OFFP and GP_ADC_OFFN registers the offset can be compensated in the
ADC network itself.
To calibrate the ADC follow the steps in table below:
GPADC Calibration Procedure for Single-Ended and Differential Modes
Step
1
2
3
4
5
6
7
Single-Ended Mode (GP_ADC_SE = 1)
Set GP_ADC_OFFP = GP_ADC_OFFN=0x200;
GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0
Start conversion
adc_off_p = GP_ADC_RESULT - 0x200
Set GP_ADC_SIGN = 0x1
Start conversion
adc_off_n = GP_ADC_RESULT - 0x200
GP_ADC_OFFP = 0x200 - 2*adc_off_p
GP_ADC_OFFN = 0x200 - 2*adc_off_n
(Note 4)
Differential Mode (GP_ADC_SE = 0)
Set GP_ADC_OFFP=GP_ADC_OFFN = 0x200;
GP_ADC_MUTE = 0x1; GP_ADC_SIGN = 0x0
Start conversion
adc_off_p = GP_ADC_RESULT - 0x200
Set GP_ADC_SIGN = 0x1
Start conversion
adc_off_n = GP_ADC_RESULT - 0x200
GP_ADC_OFFP = 0x200 - adc_off_p
GP_ADC_OFFN = 0x200 - adc_off_n
(Note 4)
Note 4 The average of GP_ADC_OFFP and GP_ADC_OFFN should be 0x200 (with a margin of 20
LSB). It is recommended to implement the above calibration routine during the initialization
phase of the ISM14585-L35. To verify the calibration results, check whether the
GP_ADC_RESULT value is close to 0x200 while bit GP_ADC_MUTE = 1.
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9.12.6 ZERO-SCALE ADJUSTMENT
The GP_ADC_OFFP and GP_ADC_OFFN registers can also be used to set the zeroscale or full-scale input level at a certain target value. For instance, they can be used to
calibrate GP_ADC_RESULT to 0x000 at an input voltage of exactly 0.0 V, or to calibrate
the zero scale of a sensor.
9.12.7 COMMON MODE ADJUSTMENT
The common mode level of the differential signal must be 0.6 V (or 1.8 V with
GP_ADC_ATTN3X = 1). If the common mode input level of 0.6 V cannot be achieved,
the common mode level of the GP_ADC can be adjusted (the GP_ADC can tolerate a
common mode margin up to 50 mV) according to below table.
CM Voltage (Vcmm)
0.3 V
0.6 V
0.9 V
GP_ADC_OFFP = GP_ADC_OFFN
0x300
0x200
0x100
Common Mode Adjustment
Any other common mode level between 0.0 V and 1.2 V can be calculated from the
table above. Offset calibration can be combined with common mode adjustment by
replacing the 0x200 value in the offset calibration routine by the value required to get
the appropriate common mode level.
Note: The input voltage limits for the ADC in differential modes are: -1.3 V to +1.3 V (for
GP_ADC_ATTN3X = 0, see Table for GPADC Input Channels and Voltage Scale). The
differential input range of the ADC is: -1.2 V < V[P0_0,P0_1] < +1.2 V. Therefore, if
Vcmm < 0.5 V or Vcmm > 0.7 V, the input can no longer cover the whole ADC range.
9.12.8 INPUT IMPEDANCE, INDUCTANCE, AND INPUT SETTLING
The GPADC has no input buffer stage. During sampling phase a capacitor of 0.2 pF is
switched to the input line. The precharge of this capacitor is at mid-scale level so the
input impedance is infinite. At 100 ksample/s, zero or full-scale single-ended input
signal, this sampling capacitor will load the input with:
ILOAD = V * C * fS = ±0.6 V * 0.2 pF * 100 kHz = ±12 nA (differential: ±1.2 V * 0.2 pF *
100 kHz = ±24 nA at both pins).
During sampling phase a certain settling time is required. A 10-bit accuracy requires at
least 7 time constants of the output impedance of the input signal source and the 0.2 pF
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sampling capacitor. The conversion time is approximately one clock cycle of 16 MHz
(62.5 ns).
7 * ROUT * 0.2 pF - 62.5 ns < 1/fS
=> ROUT < (1 + 62.5 ns * fS) / (7 * 0.2 pF * fS)
Examples:
ROUT < 7.2 MΩ at fS = 100 kHz
ROUT < 760 kΩ at fS = 1 MHz
The inductance from the signal source to the ADC input pin must be very small.
Otherwise, filter capacitors are required from the input pins to ground (differential mode:
from pin to pin). To observe the noise level of the ADC and the voltage regulator, bit
GP_ADC_CTRL_REG[GP_ADC_MUTE] must be set to ‘1’. The noise should be less
than ±1 LSB on average, with occasionally a ±2 LSB peak value. If a higher noise level
is observed on the input channel(s), applying filter capacitor(s) will reduce the noise.
The 3x input attenuator is realized with a resistor divider network. When bit
GP_ADC_CTRL_REG2[GP_ADC_ATTN3X] is set to ‘1’, the input impedance of the
selected ADC input channel becomes 300 kΩ (typical) instead of infinite. In addition, the
resistor divider network will require more settling time in the sampling phase. The
general guideline with bit GP_ADC_ATTN3X = 1 is: select the input channel, then wait 1
μs (16 clock cycles) before starting the conversion. Only the required sampling time is
affected by the attenuator, the conversion time remains approximately one clock cycle
of 16 MHz (62.5 ns).
Note: Selecting the battery measurement channel automatically activates the 3x input
attenuator (bit GP_ADC_ATTN3X = 1). Therefore the 1 μs waiting time also applies
when measuring the battery voltage, otherwise the resulting Vbat level will be too low.
9.12.9 COMMON MODE ADJUSTMENT
The GPADC has a delay counter that can be used to add delays to several ADC control
signals. A delay of up to 32μs can be added for the bits GP_ADC_LDO_EN,
GP_ADC_START and GP_ADC_EN via registers GP_ADC_DELAY_REG and
GP_ADC_DELAY2_REG.
The reset values of these two registers are the recommended values for a correct startup, since it is not allowed to activate all signals at once.
To make use of the delay counter for a certain signal, the corresponding bit has to be
set in register GP_ADC_CTRL_REG and the delay counter must be enabled via bit
GP_ADC_DELAY_EN in register GP_ADC_CTRL2_REG. The delay counter starts
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counting when the GP_ADC_START bit is programmed while the
GP_ADC_DELAY_EN bit is set. The counter is stopped after the conversion is finished.
The delay counter must be reset before reuse, which is typically only required after the
LDO was disabled. Bit GP_ADC_DELAY_EN must be made zero to reset the counter. It
is recommended to check that this bit is zero before (re)activating it.
9.12.10
Sample Rate Converter (SRC)
The SRC is a HW accelerator used to convert the sample rate of audio samples
between various interfaces. Its primary purpose is to directly connect PCM and PDM
channels while converting the rate accordingly.
Features:
•
•
•
•
•
•
•
Supported conversions:
o SRC_IN (24 bits) to SRC_OUT (24 bits)
o PDM_IN (1bit) to SRC_OUT (24 bits)
o SRC_IN (24 bits) to PDM_OUT (1 bit)
SRC_IN, SRC_OUT Sample rates 8 kHz to 192 kHz
SNR > 100 dB
Single Buffer I/O with DMA support
Automatic mode to adjust sample rate to the applied frame sync (e.g. PCM_FSC)
Manual mode to generate interrupts at the programmed sample rate. Adjustment is done
by SW based on buffer pointers
SRC runs at 16 MHz
Figure 40 Sample Rate Converter block diagram
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9.12.11
SRC ARCHITECTURE
9.12.11.1 I/O CHANNELS
The SRC block converts two 24 bits channels either as a stereo pair or as two mono
channels. The PCM linear data pairs are received on SRC_IN and the output is 2x24
bits left aligned on SRC_OUT. The two 1 bit PDM data inputs are received on PDM_IN
and are converted to 2x24 bits, left aligned to SRC_OUT.
9.12.11.2 I/O MULTIPLEXERS
The SRCx_IN input multiplexer (Figure 40) is controlled by APU_MUX_REG. The input
of these multiplexers either comes from the audio interfaces of from registers
SRC1_IN1_REG and SRC1_IN2_REG. The data to these register is left aligned, bits
31-8 are mapped on bits 23-0 of the SRC.
The 24 bits SRCs outputs can be read in SRC1_OUT1_REG and SRC1_OUT2_REG
and is also routed to the PCM. This input selection of these multiplexers is also
controlled by APU_MUX_REG.
9.12.11.3 INPUT AND OUTPUT SAMPLE RATE CONVERSION
Depending on the use case the Sample Rate Converter operate in either manual or
automatic conversion mode. This mode can be set in the SRC1_CTRL_REG bits
SRC_IN_AMODE and bit SRC_OUT_AMODE.
9.12.11.4 SRC CONVERSION MODES OF OPERATION
Both at the input and at the output side, the SRC can operate in two mode of operation:
• Manual mode
• Automatic mode
In manual mode, the input/output sample rate is determined by SRC1_IN_FS_REG
/SRC1_OUT_FS_REG registers.
In automatic mode, the input/output sample rate is derived from the external
synchronization signals and can be read back from SRC1_IN_FS_REG /
SRC1_OUT_FS_REG registers. When the PDM is used (input/output), the SRC
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operates in automatic mode. The sample rate reported in SRC1_IN_FS_REG register is
PDM_CLK/64. Typical Use Cases of the SRC are given on the table below:.
9.12.11.5 DMA OPERATION
If more than one sample must be transfer to/from the CPU or the sample rate is so high
that it interrupts the CPU too often, the DMA controller must be engaged to perform the
transactions.
9.12.11.6 INTERRUPTS
After a Sample Rate Conversion, the input up-sampler and output down-sampler
generate edge triggered interrupts on SRC_IN_SYNC and SRC_OUT_SYNC to the
CPU which do not have to be cleared. Note that only one sample shall be read from or
written to a single register at a time (i.e. there are no FIFOs included).
9.12.11.7 SRC USE CASES
The Sample Rate Converter supports any sample rate between 8 kHz and 48 kHz.
Below table shows typical use cases of the Sample Rate Converter.
Use case
PCM/PDM to
BLE
BLE to
PCM / PDM
SRCx_IN_AMODE
DATA path
SRCx_IN_SYNC
Automatic
PDMx_IN_DATA
PCMx_SYNC
PCMx_IN_DATA
PCMx_SYNC
Manual
SRCx_IN_REG
SRCx_IN_SYNC
(out)
SRCx_OUT_AMODE
DATA path
SRCx_OUT_SYNC
Manual
SRCx_OUT_REG
up-to 192kHz
SRCx_OUT_SYNC
(out)
up-to 192kHz
Automatic
PDMx_IN_DATA
PCMx_SYNC
PCMx_IN_DATA
PCMx_SYNC
PCM to PCM resampler (output must be a multiple of 8 kHz)
Automatic
Automatic
PCM1_IN to
PCM1_IN
PCM2_OUT
PCM2_OUT
PCM1_FSC (input)
PCM2_FSC (output)
Automatic
Automatic
PCM2_IN to
PCM2_IN
PCM1_IN
PCM1_OUT
PCM2_FSC (input)
PCM1_FSC (output)
Table of Typical SRC use case
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9.13 PDM Interface
The Pulse Density Modulation (PDM) interface provides a serial connection for up-to 2
input devices (e.g MEMS microphones) or output devices. The interfaces have a
common clock PDM_CLK and one input PDM_DI which is capable of carrying two
channels. Figure 41 shows a typical connection of two microphones sharing one data
line.
The PDM input data has a 1-bit data length and is encoded so that the left channel is
clocked in on the falling edge of PDM_CLK and the right channel is clocked on the
rising edge of PDM_CLK as shown in Figure 42.
The 1 bit data stream is down-sampled to 24 bits PCM samples in the HW Sample Rate
Converter (SRC) for further processing in the DSP.
The interface supports MEMS microphone sleep mode by disabling the PDM_CLK.
The PDM interface signals are available through the PPA multiplexer. The interface
levels are determined by the IO group on which the PDM signals are mapped. Those
signals can be hard wired to 1.8 V and 3.3 V.
Features:
•
•
•
•
•
•
PDM_CLK frequency 62.5 kHz - 4 MHz
Down-sampling to 24 bits in SRC
PDM_CLK on/off to support Sleep mode
PDM_DATA (input): 1 Channel in stereo format
PDM_DATA (output): 2 Channels in mono format, 1 Channel in stereo format
Programmable Left/Right channel selection
Figure 41 PDM with dual mic interface
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Figure 42 PDM formats
Figure 43 PDM input transfer functions
It should be noted that the audio quality degrades when the oversampling ratio is less
than 64. For an 8 kHz sample rate the minimum recommended PDM clock rate is 64 x 8
kHz = 512 kHz.
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9.14 PCM Controller
The PCM controller is implementing an up-to 192kHz synchronous interface to external
audio devices, ISDN circuits and serial data interfaces.
It is accessed through the APB32 interface. PCM can individually operate in master or
slave mode. In slave mode, the phase between the external and internal frame sync can
be measured and used to compensate for drift.
The data IO registers have DMA support in order to reduce the interrupt overhead to the
CPU. Up-to 8 channels of 8 bits with a programmable delay are supported in received
and transmit direction.
The controller supports PCM, I2S, TDM and IOM2 formats.
Features:
•
•
•
•
•
•
•
•
•
PCM_CLK Master/slave
PCM_FSC
o Master/slave 4 kHz to 96 kHz
o Strobe Length 1, 8, 16, 24, 32, 40, 48 and 64 bits
o PCM_FSC before or on the first bit. (In Master mode)
2x32 channels
Programmable slot delay up-to 31*8bits
Formats
o PCM mode
o I2S mode (Left/Right channel selection) with N*8 for Left and N*8 for Right
o IOM2 mode (double clock per bit)
Programmable clock and frame sync inversion
Direct connection to Sample Rate Converter (SRC)
Interrupt line to the CPU
DMA support
Figure 44 PCM controller
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9.14.1 PCM ARCHITECTURE
9.14.1.1
•
•
•
•
INTERFACE SIGNALS
PCM_FSC, strobe signal input, output. Supports 8/16/32/48/96/128/192kHz. Can
generate an interrupt to the CPU.
PCM_CLK, PCM clock input, output.
PCM_DO, PCM Data output, push pull or open drain with external pull-up
resistor.
PCM_DI, PCM Data input.
PCM interface can be powered down by the PCM1_CTRL_REG[PCM_EN] = 0.
9.14.1.2
CHANNEL ACCESS
The PCM interface has two 32-bit channels for TX and RX. Channels are accessed
through 32 bits registers:
•
•
PCM1_OUT1_REG and PCM1_OUT2_REG,
PCM1_IN1_REG and PCM1_IN2_REG.
The registers are only word-wise (32 bits) accessible by the CPU or the DMA via the
APB-32 bridge
.
The 32 bits registers are arranged as 8 channels of 8 bits, named channel 1 to
channel8.
By a flexible clock inversion, channel delay and strobe length adjustment various format
like PCM, I2S, TDM and IOM2 can be made
9.14.1.3
CHANNEL DELAY
The 8 PCM channels can be delayed with a maximum delay of 31x8bits using the bit
field PCM1_CTRL_REG[PCM_CH_DEL]. Note that a high delay count in combination
with a slow clock, can lead to the PCM_FSC sync occurring before all channels are
shifted in or out. The received bits of the current channel may not be properly aligned in
that case.
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9.14.1.4
CLOCK GENERATION
Figure 45 shows the PCM clock generation block and the Table below, the
PCM_DIV_REG and PCM_FDIV_REG values for given PCM_FSC and PCM_CLK in
master mode. The PCM_DIV_REG[PCM_DIV] is a 12 bits field which holds the integer
part of the desired clock divider.
The fractional part of the divider is stored in the 16 bits PCM_FDIV_REG register. The
value of the register is calculated in the following way. The position of the left most '1' of
the value in binary format defines the denominator and the number of '1' bits define the
numerator of the fraction as shown in the Table below.
PCM_FDIV_REG (Hex)
0x0110
0x0101
0x1abc
0xbeef
0xfeee
PCM_FDIV_REG (Binary)
0b100010000
0b100000001
0b1101010111100
0b1011111011101111
0b1111111011101110
Numerator
2
2
8
13
13
Denominator
9
9
13
16
16
Fraction
2/9
2/9
8/13
13/16
13/16
PCM_FDIV_REG Example Calculations
Figure 45 PCM clock generation
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The PCM_DIV_REG calculations show the following use cases, with 8 bits, 16 bits, 32
bits and 48 bits.
XTAL 16000 kHz
Desired Divider
Sample
Rate
Bits
Desired Bit
Clock kHz
8
1*8
64
250
250
Actual
Word size
8
8
8
8
8
8
8
1*16
1*24
1*32
2*8
2*16
2*24
2*32
1*8
1*16
1*24
1*32
2*8
2*16
2*24
2*32
1*8
1*16
1*24
1*32
2*8
2*16
2*24
2*32
1*8
1*16
1*24
1*32
2*8
2*16
2*24
2*32
128
125
83,33333333
62,5
125
125
125
62,5
41,66666667
31,25
125
62,5
41,66666667
31,25
62,5
31,25
20,83333333
15,625
62,5
31,25
20,83333333
15,625
31,25
15,625
10,41666667
7,8125
41,66666667
20,83333333
13,88888889
10,41666667
20,83333333
10,41666667
6,944444444
5,208333333
50
40
25
8
16
25
40
8
20
25
40
8
20
25
40
10
20
25
50
10
20
25
50
10
25
25
50
N/A
N/A
N/A
N/A
N/A
N/A
N/A
16
16
16
16
16
16
16
16
32
32
32
32
32
32
32
32
48
48
48
48
48
48
48
48
192
256
128
256
384
512
128
256
384
512
256
512
768
1024
256
512
768
1024
512
1024
1536
2048
384
768
1152
1536
768
1536
2304
3072
80
50
125
50
40
25
50
25
20
10
50
25
20
10
25
10
10
5
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Alternatively
Actual
Divider
Divider: Integer
and Fractional
Part
=250
=125
=83 + 1/3
=62 + 1/2
=125
=62 + 1/2
=41 + 2/3
=31 + 1/4
=125
=62 + 1/2
=41 + 2/3
=31 + 1/4
=62 + 1/2
=31 + 1/4
=20 + 5/6
=15 + 5/8
=62 + 1/2
=31 + 1/4
=20 + 5/6
=15 + 5/8
=31 + 1/4
=15 + 5/8
=10 + 5/12
=7 + 13/16
=41 + 2/3
=20 + 5/6
=13 + 8/9
=10 + 5/12
=20 + 5/6
=10 + 5/12
N/A
Integer PCM_DIV_REG values for given frequencies and sample rates
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9.14.1.5
DATA FORMATS
9.14.1.5.1 PCM MASTER MODE
Master mode is selected if PCM1_CTRL_REG[PCM_MASTER] = 1.
In master mode PCM_FSC is output and falls always over Channel 0. The duration of
PCM_FSC is programmable with PCM1_CTRL_REG[PCM_FSCLEN]= 1 or 8,16, 24, 32
clock pulses high. The start position is programmable with
PCM1_CTRL_REG[PCM_FSCDEL] and can be placed before or on the first bit of
channel 0.
The repetition frequency of PCM_FSC is programmable in
PCM1_CTRL_REG[PCM_FSC_DIV] to from 8-192kHz.
If master mode selected, PCM_CLK is output and provides one or two clocks per data
bit programmable in PCM1_CTRL_REG[PCM_CLK_BIT].
The polarity of the signal can be inverted with bit PCM1_CTRL_REG[PCM_CLKINV].
The PCM_CLK frequency selection is described in Section 9.14.1.4.
9.14.1.5.2
PCM SLAVE MODE
In slave mode (bit MASTER = 0) PCM_FSC is input and determines the starting point of
channel 0.
The repetition rate of PCM_FSC must be equal to PCM_SYNC and must be high for at
least one PCM_CLK cycle. Within one frame, PCM_FSC must be low for at least
PCM_CLK cycle. Bit PCM_FSCDEL sets the start position of PCM_FSC before or on
the first bit (MSB).
In slave mode PCM_CLK is input. The minimum received frequency is 256 kHz, the
maximum is 12.288MHz.
In slave mode the main counter can be stopped and resumed on a PCM1_FSC or
PCM2_FSC rising edge.
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Figure 46 PCM interface formats
9.14.1.5.3 I2S FORMATS
The digital audio interface supports I2S mode, Left Justified mode, Right Justified mode
and TDM mode.
I2S mode
To support I2S mode, the MSB of the right channel is valid on the second rising edge of
the bit clock after the rising edge of the PCM_FSC, and the MSB of the left channel is
valid on the second rising edge of the bit clock after the falling edge of the PCM_FSC.
Settings for I2S mode:
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•
•
•
•
•
PCM_FSC_EDGE: 1 (all after PCM_FSC)
PCM_FSCLEN: 4 (4x8 High, 4x8 Low)
PCM_FSC_DEL: 0 (one bit delayed)
PCM_CLK_INV: 1 (output on falling edge)
PCM_CH0_DEL: 0 (no channel delay)
Figure 47 I2S Mode
TDM mode
A time is specified from the normal ‘start of frame’ condition using register bits
PCM_CH_DEL. In the left-justified TDM example illustrated in Figure 48, the left
channel data is valid PCM_CH_DEL clock cycles after the rising edge of the PCM_FSC,
and the right channel data is valid the same PCM_CH_DEL number of clock cycles after
the falling edge of the PCM_FSC.
By delaying the channels, also left and right alignment can be achieved.
Settings for TDM mode:
• PCM_FSC_EDGE: 1 (rising and falling PCM_FSC)
• PCM_FSCLEN: Master 1 to 4 Slave waiting for edge.
• PCM_FSC_DEL: 1 (no bit delay)
• PCM_CLK_INV: 1 (output on falling edge)
• PCM_CH0_DEL: Slave 0-31 (channel delay) Master 1-3
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Figure 48 I2S TDM mode (left justified mode)
9.14.1.5.4 IOM MODE
In the IOM format, the PCM_CLK frequency is twice the data bit cell duration. In slave
mode synchronization is on the first rising edge of PCM_FSC while data is clock in on
the second falling edge.
Settings for IOM mode:
• PCM_FSC_EDGE: 0 (rising edge PCM_FSC)
• PCM_FSCLEN: 0 (one cycle)
• PCM_FSC_DEL: 0 (no bit delay)
• PCM_CLK_INV: 0 (output on rising edge)
• PCM_CH0_DEL: 0 (no delay)
• PCM_CLK_BIT: 1
Figure 49 IOM format
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9.14.1.6
EXTERNAL SYNCHRONIZATION
With the PCM interface in slave mode, the PCM interface supports direct routing
through the sample rate converter (SRC). Any drift in PCM_FSC or other frame sync
frequencies like 44.1 kHz can be directly resampled to e.g 48kHz internal sample rate.
10 MECHANICAL SPECIFICATION
10.1 Size of the Module
The following paragraphs provide the requirements for the size and weight.
The size and thickness of the ISM14585-L35 SiP is:
•
•
6mm (W) x 8.6mm (L) x 1.2mm (H):
(Tolerance: +/- 0.1mm)
10.2 Mechanical Dimension
Dimension: 6 x 8.6 x 1.2 mm3
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11 Recommend Footprint (Board Design)
11.1 Module Dimension Measurement
Unit: mm
TOP View
Note:
• Please use Un-Solder Mask to design the Module Footprint.
• There are two types pad size in the Module.
o Rectangle : Pad size: 0.3 x 0.5 mm & Solder Mask size: 0.375 x 0.575 mm
o Circle: Pad size (Φ): 0.5 mm & Solder Mask size (Φ): 0.6 mm
• Please contact Inventek Systems for interest in a chip-down design.
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11.2 The X-Y Central Location Coordinates
Unit: mm (Drawn dimensions with chip 0,0 at bottom right corner)
(0,0)
PIN_NUMBER PAD Size (mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.575
0.575
0.575
0.575
0.575
0.575
0.575
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.375
0.375
0.375
0.375
0.375
0.375
0.375
Solder Mask_Size
(mm)
0.575
0.575
0.575
0.575
0.575
0.575
0.575
0.5
0.5
0.5
0.5
0.5
0.5
0.5
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0.375
0.375
0.375
0.375
0.375
0.375
0.375
0.3
0.3
0.3
0.3
0.3
0.3
0.3
PIN_X(mm) PIN_Y(mm)
0.4875
0.4875
0.4875
0.4875
0.4875
0.4875
0.4875
0.75
1.25
1.75
2.25
2.75
3.25
3.75
4.3
3.8
3.3
2.8
2.3
1.8
1.3
0.4875
0.4875
0.4875
0.4875
0.4875
0.4875
0.4875
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PIN_NUMBER PAD_Size (mm)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.5 mm (Φ)
Solder Mask_Size
(mm)
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.575 x 0.375
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.5 x 0.3
0.6 mm (Φ)
PIN_X(mm) PIN_Y(mm)
4.25
4.75
5.25
5.5125
5.5125
5.5125
5.5125
5.5125
5.5125
5.5125
5.25
4.75
4.25
3.75
3.25
2.75
2.25
1.75
1.25
0.75
0.98
0.4875
0.4875
0.4875
1.3
1.8
2.3
2.8
3.3
3.8
4.3
5.1125
5.1125
5.1125
5.1125
5.1125
5.1125
5.1125
5.1125
5.1125
5.1125
6.95
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12 Recommend Stencil
Unit: mm
TOP View
Recommend:
1. ≦ 0.08mm THK stencil will has better solder paste deposit.
2. Type 4 or 5 solder ( fine powder size) will has better solution no matter clean or nonclean solder paste.
3. Nitrogen reflow oven.
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13 Recommended Reflow Profile
Temperature
2450c
2170c
2000c
1500c
Time
Pre-heating
Soldering
90~120 sec
60~90 sec
14 Package and Storage Condition
14.1 Package Dimension
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15 REVISION CONTROL
Document: ISM14585-L35
External Release
Date
7/04/2018
5.0 BLE + Cortex M0 Module
DOC-DS-14585-201807-1.0
Author
AS
Revision
1.0
Comment
Preliminary
16 CONTACT INFORMATION
Inventek Systems
2 Republic Road
Billerica Ma, 01862
Tel: 978-667-1962
Sales@inventeksys.com
www.inventeksys.com
Copyright 2017, Inventek Systems. All Rights Reserved. This software, associated documentation and materials ("Software"),
referenced and provided with this documentation is owned by Inventek Systems and is protected by and subject to worldwide patent
protection (United States and foreign), United States copyright laws and international treaty provisions. Therefore, you may use this
Software only as provided in the license agreement accompanying the software package from which you obtained this Software
("EULA"). If no EULA applies, Inventek Systems hereby grants you a personal, non-exclusive, non-transferable license to copy,
modify, and compile the Software source code solely for use in connection with Inventek's integrated circuit products.
Any reproduction, modification, translation, compilation, or representation of this Software except as specified above is prohibited
without the express written permission of Inventek. Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO WARRANTY OF
ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
Inventek reserves the right to make changes to the Software without notice. Inventek does not assume any liability arising out of the
application or use of the Software or any product or circuit described in the Software. Inventek does not authorize its products for
use in any products where a malfunction or failure of the Inventek product may reasonably be expected to result in significant
property damage, injury, or death ("High Risk Product"). By including Inventek's product in a High Risk product, the manufacturer of
such system or application assumes all risk of such use and in doing so agrees to indemnify Inventek against all liability. Inventek
Systems reserves the right to make changes without further notice to any products or data herein to improve reliability, function, or
design. The information contained within is believed to be accurate and reliable. However, Inventek does not assume any liability
arising out of the application or use of this information, nor the application or use of any product or circuit described herein, neither
does it convey any license under its patent rights nor the rights of others.
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