GS1011MEE-SDK2-HW

GS1011M LOW-POWER WIRELESS SYSTEM-ON-CHIP WI-FI MODULE DATA SHEET Reference: GS1011M-DS Version: SP-1.6 Date: 1-Mar-13 GS1011M DATA SHEET Information in this document is provided in connection with GainSpan products. No license, express or implied, to any intellectual property rights is granted by this document. GainSpan assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of GainSpan products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. GainSpan products are not authorized for use as critical components in medical, lifesaving, or life-sustaining applications GainSpan may make changes to specifications and product descriptions at any time, without notice. *Other names and brands may be claimed as the property of others. Copyright © 2009-2011 by GainSpan Corporation. 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GainSpan Corporation +1 (408) 673-2900 Version Date 1.0 20-May-2011 Remarks Updated description of ext_resetn and UART RTS/CTS signals Added power consumption information for deep sleep Updated package information to match module package Updated min Vbat spec and Receiver sensitivity numbers Updated latency numbers for GS1011ME module in 2.4.1 1.1 14-June-2011 Updated package drawing to reflect measurements from datum in bottom right corner for the bottom view Updated section 3.1.1 to make signal state column match description column 1.2 20-June-2011 Updated bottom view drawing for GS1011MI in Fig 5-2 27-April-2012 Updated Sleep States Description with more details 1.4 Updated Layout guidelines with additional details Updated power consumption table with max current consumption values for GS1011Mxx Updated RF Parameter table (MI typical output to 9dBm) 1.5 15-Oct-2012 Updated ordering info for module rev 1.3 Added note related to module firmware in the ordering section 1.6 1-Mar-13 Updated section 5.2.1 reflow profile info and package info PAGE 2 OF 54 GS1011M DATA SHEET Table of Contents 1 1.1 1.2 Overview ................................................................................................................................. 7 Document Overview........................................................................................................... 7 Product Overview ............................................................................................................... 7 2 Architecture ............................................................................................................................. 9 2.1 G1011Mxx Block Diagram ................................................................................................ 9 2.2 Block Diagram Description .............................................................................................. 10 2.2.1 Overview ..................................................................................................................... 10 2.2.2 Wireless LAN and System Control Subsystem........................................................... 10 2.2.2.1 Onboard antenna / RF port / Radio ........................................................................ 11 2.2.3 Network Services Subsystem ...................................................................................... 11 2.2.3.1 APP CPU ............................................................................................................... 11 2.2.4 Memory Subsystem ..................................................................................................... 11 2.2.4.1 Overview ................................................................................................................ 11 2.2.5 Clock Circuitries ......................................................................................................... 11 2.2.5.1 Real Time Clock (RTC) Overview ........................................................................ 11 2.2.5.2 Real Time Counter ................................................................................................. 13 2.2.5.3 RTC Outputs .......................................................................................................... 13 2.2.5.3.1 DC_DC_CNTL .................................................................................................. 14 2.2.5.3.2 RTC_OUT1........................................................................................................ 14 2.2.5.4 RTC Alarm Inputs 1 and 2 ..................................................................................... 14 2.3 Peripherals ........................................................................................................................ 14 2.3.1 SPI ............................................................................................................................... 14 2.3.2 I2C ............................................................................................................................... 15 2.3.3 UART .......................................................................................................................... 16 2.3.4 JTAG ........................................................................................................................... 16 2.3.5 GPIO & LED Driver / GPIO ....................................................................................... 17 2.3.6 ADC ............................................................................................................................ 17 2.4 System States.................................................................................................................... 18 2.5 Power Supply ................................................................................................................... 21 2.5.1 Power Supply Connection Summary .......................................................................... 24 3 Pin-out and Signal Description .............................................................................................. 26 3.1 GS1011Mxx Device Pin-out Diagram (Module top view) .............................................. 26 3.1.1 GS1011Mxx Module Pins Description ....................................................................... 27 4 Electrical Characteristics ....................................................................................................... 31 4.1 Absolute Maximum Ratings ............................................................................................. 31 4.2 Operating Conditions ....................................................................................................... 31 4.3 Internal 1.8V regulator ..................................................................................................... 32 4.4 I/O DC Specifications ...................................................................................................... 32 4.4.1 Digital Input Specifications......................................................................................... 32 4.4.2 Digital Output Specification ....................................................................................... 32 4.4.3 I/O Digital Specifications (Tri-State) .......................................................................... 33 4.4.4 RTC Input Specifications (with Schmitt Trigger) ....................................................... 33 4.4.5 RTC Output Specifications ......................................................................................... 34 4.5 Power Consumption (Estimated)...................................................................................... 34 4.6 Radio Parameters.............................................................................................................. 34 4.7 ADC Parameters ............................................................................................................... 35 4.8 SPI Interface Timing ........................................................................................................ 36 PAGE 3 OF 54 GS1011M DATA SHEET 4.8.1 4.8.2 4.8.3 4.8.4 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 0 ..................................... 36 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 1 ..................................... 38 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0 ..................................... 40 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 1 ..................................... 42 5 Package and Layout Guidelines ............................................................................................ 44 5.1 GS1011Mxx Recommended PCB Footprint and Dimensions ......................................... 44 5.2 GS1011MxP Layout Guidelines....................................................................................... 46 5.2.1 Surface Mount Assembly ............................................................................................ 48 6 Ordering Information ............................................................................................................. 50 7 Regulatory Notes ................................................................................................................... 51 8 Limitations ............................................................................................................................. 53 9 References ............................................................................................................................. 54 PAGE 4 OF 54 GS1011M DATA SHEET Figures Figure 2-1: GS1011MIx Block Diagram ..................................................................................................... 9 Figure 2-2: GS1011MEx Block Diagram.................................................................................................... 9 Figure 2-4: GS1011Mxx System States .................................................................................................... 18 Figure 2-5 : GS1011Mxx Always ON Power Supply Connection ............................................................ 21 Figure 2-6: GS1011MIx Battery Powered with 3.3V IO and Standby Support ........................................ 22 Figure 2-7 : GS1011ME Battery Powered with 3.3V IO and Standby Support ........................................ 23 Figure 2-8 : GS1011MI Battery Powered with 1.8V only and Standby Support ...................................... 24 Figure 2-9: Single board design using either GS1011MI or GS1011ME modules with Standby Support 25 Figure 3-1: GS1011Mxx Device Pin-out Diagram (Module top view)..................................................... 26 Figure 3-2: Module pin connection diagram ............................................................................................. 30 Figure 4-1: timing diagram, Master mode, SPO=SPH=0. ........................................................................ 36 Figure 4-2: timing diagram, Slave mode, SPO=SPH=0. .......................................................................... 37 Figure 4-3: timing diagram, Master, SPO=0, SPH=1................................................................................ 38 Figure 4-4: timing diagram, Slave, SPO=0, SPH=1. ................................................................................. 39 Figure 4-5: timing diagram, Master mode, SPO=1, SPH=0. ..................................................................... 40 Figure 4-6: timing diagram, Slave mode, SPO=1, SPH=0. ....................................................................... 41 Figure 4-7: timing diagram, Master mode, SPO=SPH=1. ......................................................................... 42 Figure 4-8: timing diagram, Slave mode, SPO=SPH=1. ........................................................................... 43 Figure 5-1: GS1011MIx Module Recommended PCB Footprint (in inches)........................................... 44 Figure 5-2: GS1011MIx Module Dimensions (in inches) ........................................................................ 45 Figure 5-3: GS1011MEx Module Recommended PCB Footprint (in inches) ......................................... 45 Figure 5-4: GS1011MEx Module Dimensions (in inches) ....................................................................... 46 Figure 5-5: GS1011MxP module onboard antenna keep-out layout guidelines (dimensions are in inches) ............................................................................................................................................................ 46 Figure 5-6 Recommended keep out area to accommodate both GS1011MIP and GS1011MEP.............. 47 Figure 5-7 Recommended clearance above and below the GS1011MxP trace antenna ........................... 48 Figure 5-8: Reflow temperature profile. ................................................................................................... 48 PAGE 5 OF 54 GS1011M DATA SHEET Tables Table 3-1: Signal Description .................................................................................................................... 29 Table 4-1: Absolute Maximum Ratings .................................................................................................... 31 Table 4-2: Operating Conditions ............................................................................................................... 31 Table 4-3: Internal 1.8V Regulator ........................................................................................................... 32 Table 4-4: Digital Input Parameters .......................................................................................................... 32 Table 4-5: Digital Output Parameters........................................................................................................ 32 Table 4-6: I/O Digital Parameters ............................................................................................................. 33 Table 4-7: RTC Input Parameters.............................................................................................................. 33 Table 4-8: RTC Output Parameters ........................................................................................................... 34 Table 4-9: Power Consumption in Different States................................................................................... 34 Table 4-10: Radio Parameters ................................................................................................................... 35 Table 4-11: ADC Parameters .................................................................................................................... 35 Table 4-12: timing parameters, Master mode, SPO=SPH=0. ................................................................... 36 Table 4-13: timing parameters, Slave mode, SPO=SPH=0. ..................................................................... 37 Table 4-14: timing parameters, Master mode; SPO=0, SPH=1. ............................................................... 38 Table 4-15: timing parameters, Slave mode, SPO=0, SPH=1. .................................................................. 39 Table 4-16: timing parameters, Master mode, SPO=1, SPH=0................................................................ 40 Table 4-17: timing parameters, Slave mode, SPO=1, SPH=0. .................................................................. 41 Table 4-18: timing parameters, Master mode, SPO=SPH=1. ................................................................... 42 Table 4-19: timing parameters, Master mode, SPO=SPH=1. ................................................................... 43 Table 5-1: Recommended reflow parameters. .......................................................................................... 48 PAGE 6 OF 54 GS1011M DATA SHEET 1 Overview 1.1 Document Overview describes the GS1011Mxx Low Power module hardware specification. The GS1011 Tbased modules provide cost effective, low power, and flexible platform to add Wi-Fi® connectivity HIS DOCUMENT for embedded devices for a variety of applications, such as wireless sensors and thermostats. It combines ARM7-based processors with an RF transceiver, 802.11 MAC, security, & PHY functions, FLASH and SRAM, onboard and off module certified antenna options, and various RF front end options for end customer range needs in order to provide a WiFi and regulatory certified IEEE 802.11 radio with concurrent network processing services for variety of applications, while leverage existing 802.11 [1] wireless network infrastructures. 1.2 Product Overview ► Family of modules with different antenna and output power options:     GS1011MIx 1.280 inches by 0.900 inches by 0.143 inches (Length * Width * Height) 48-pin Dual Flat pack PCB Surface Mount Package. GS1011MEx 1.450 inches by 0.900 inches by 0.143 inches (Length * Width * Height) 48-pin Dual Flat pack PCB Surface Mount Package. GS1011MIP, GS1011MIE, GS1011MEP, and GS1011MEE are all pin to pin compatible (see section 6 Ordering Information), and the user has to account only for power consumption, module outline, and PCB antenna keep out (if used) to accommodate “one size fits all” for various end applications. Simple API for embedded markets covering large areas of applications ► Compliant with IEEE 802.11and regulatory domains:   Fully compatible with IEEE 802.11b/g/n. o DSSS modulation for data rates of 1 Mb/s and 2 Mb/s; CCK modulation rates of 5.5 and 11 Mb/s. Supports short preamble and short slot times. WiFi Certified Solution o Supports 802.11i security  WPA™ - Enterprise, Personal  WPA2™ - Enterprise, Personal  Vendor EAP Type(s)  EAP-TTLS/MSCHAPv2, PEAPv0/EAP-MSCHAPv2, PEAPv1/EAPGTC, EAP-FAST, EAP-TLS Hardware High-throughput AES and RC4 encryption/decryption engines for WEP, WPA/WPA2 (AES and TKIP). RoHS and CE compliant  FCC/IC/ ETSI Certified    GS1011MIP GS1011MIE GS1011MEP GS1011MEE FCC ID YOPGS1011MIP YOPGS1011MIE YOPGS1011MEP YOPGS1011MEE IC ID 9154A-GS1011MIP 9154A-GS1011MIE 9154A-GS1011MEP 9154A-GS1011MEE PAGE 7 OF 54 GS1011M DATA SHEET  Fully compliant with EU & meets the R&TTE Directive for Radio Spectrum  Japan Radio Type Approval (i.e. TELEC) pre-scan compliant ► Dual ARM7 Processor Platform:     1st ARM7 processor (WLAN CPU) for WLAN software 2nd ARM7 (APP CPU) for networking software Based on Advanced Microprocessor Bus Architecture (AMBA) system: o AMBA High-Speed Bus (AHB). o AMBA Peripheral Bus (APB). On-chip WLAN boot code located in dedicated boot ROM. ► Interfaces:           PCB or external antenna options, electronically selected. Two general-purpose SPI interfaces (each configurable as master or slave) for external sensors, memory, or external CPU interface; one interface may be configured as a high-speed Slave-only. Two multi-purpose UART interfaces. Up to 23 configure able general purpose I/O. Single 3.3V supply option o I/O supply voltage 1.8 ~ 3.3V option One PWM output I2C master/slave interface. Two 10-bit ADC channels, aggregate sample rate 32 kS/s. Two alarm inputs to asynchronously awaken the chip. Support of up to two control outputs for power supply and sensors. ► Embedded RTC (Real Time Clock) can run directly from battery. ► Power supply monitoring capability. ► Low-power mode operations ► Standby, Sleep, and Deep Sleep PAGE 8 OF 54 GS1011M DATA SHEET 2 Architecture 2.1 G1011Mxx Block Diagram Figure 2-1: GS1011MIx Block Diagram Figure 2-2: GS1011MEx Block Diagram PAGE 9 OF 54 GS1011M DATA SHEET 2.2 Block Diagram Description 2.2.1 Overview GS1011Mxx module is a highly integrated ultra low power Wi-Fi system-on-chip (SOC) that contains the following:  The module includes GS1011 SoC, which contains media access controller (MAC), baseband processor, security, on-chip flash memory and SRAM, and an applications processor in a single package.  The module contains two ARM7-based processors, one dedicated to Networking Subsystems, and the other dedicated to Wireless Subsystems.  The module carries an 802.11 radio with onboard 32 KHz & 44 MHz crystal circuitries, RF, and certified PCB antenna or external antenna options. o The low power module option has a capability of +9dBm output power at the antenna (see Figure 2-1). o The extended range module option has a capability of +18dBm output power at the antenna connector (see Figure 2-2).  Variety of interfaces are available such as two UART blocks using only two data lines per port with optional hardware flow controls, two SPI block (one dedicated as a serial slave with configurable hardware interrupt to the HOST), I2C with Master or slave operation, JTAG port, lowpower 10-bit ADC capable of running at up to 32 Ksamples/Sec., GPIO’s, and LED Drivers/GPIO with 20mA capabilities.  GS1011Mxx contains single power supply (VIN_3V3) with optional module controlled external regulator enable control pin (DC_DC_CNTL), a separate I/O supply (VDDIO) that can be tied to the HOST supply rail without the use of external voltage translators, Real Time Clock (RTC) with battery supply monitor option (VBAT), and two external alarm inputs enable wake-up of the system on external events & outputs (ALARM and RTC_OUT) to enable periodic wake-up of the remainder of the system. o The Module carries onboard single supply monitor for under voltage supply and onboard 1.8V regulator with enable/disable capabilities for power critical applications. 2.2.2 Wireless LAN and System Control Subsystem The Wireless subsystem provides the WLAN PHY, MAC and baseband functionality. It contains the WLAN CPU, a 32-bit ARM7 TDMI-S core running at up to 44 MHz. It includes an IEEE 802.11b/g compatible RF transceiver, which supports Direct Sequence Spread Spectrum (DSSS) 1 Mb/s and 2 Mb/s data rates, and Complementary Code Keyed (CCK) 5.5 Mb/s and 11 Mb/s data rates. The WLAN subsystem includes an integrated power amplifier, and provides management capabilities for an optional external power amplifier. In addition, it contains hardware support for AES-CCMP encryption (for WPA2) and RC4 encryption (for WEP & WPA/WPA2 TKIP) encryption/decryption. The WLAN subsystem contains the control logic and state machines required to drive the low power DSSS modem, and perform pre-processing (in transmit mode) or post-processing (in receive mode) of the data stream. The WLAN subsystem manages DMA accesses, data encryption/decryption using the AES algorithm, and CRC computation. PAGE 10 OF 54 GS1011M DATA SHEET 2.2.2.1 Onboard antenna / RF port / Radio The GS1011Mxx modules have fully integrated RF frequency synthesizer, reference clock, low power PA, and high power PA for extended range applications. Both TX and RX chain in the module incorporate internal power control loops. The GS1011Mxx modules also incorporate onboard printed antenna option plus a variety of regulatory certified antenna options for various application needs. 2.2.3 Network Services Subsystem 2.2.3.1 APP CPU The Network services subsystem consists of an APP CPU which is based on an ARM7 TDMI-S core. It incorporates an AHB interface and a JTAG debug interface. The network RTOS, network stack, and customer application code can reside on this CPU. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. 2.2.4 Memory Subsystem 2.2.4.1 Overview The GS1011 module contains several memory blocks: ► Boot ROM blocks. ► The software contained in this ROM provides the capability to download new firmware via the SPI Slave or UART interfaces and to control the update of WLAN and APP Flash Memory. ► 384 KBytes of Embedded Flash to store program code. ► Three embedded Flash blocks of 128K bytes each ► WLAN Flash (contains the wireless LAN and system control subsystem software) ► APP Flash 0 and 1 (contain the Network/Application Software) ► 128 Kbytes of RAM shared between the two integrated CPU’s. ► 512 bytes of RTC memory ((retains data in all states, as long as the battery or other voltage supply is present) For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. 2.2.5 Clock Circuitries The GS1011MXX architecture uses a low-power oscillator (i.e. 32 kHz) to provide a minimal subset of functions when the chip is in its low-power deep sleep mode, and a high-speed 44 MHz oscillator to provide clock signals for the processors, bus, and interfaces during active operation. Intermediate modes of operation, in which the 44 MHz oscillator is active but some modules are inactive, are obtained by gating the clock signal to different subsystems. The Clock & Reset Controller, within the device, is responsible for generation, selection and gating of the clocks used in the module to reduce power consumption in various power states. 2.2.5.1 Real Time Clock (RTC) Overview To provide global time (and date) to the system, the GS1011MXX Chip is equipped with a low-power Real Time Clock (RTC). PAGE 11 OF 54 GS1011M DATA SHEET RTC key features include: ► 32.768 kHz crystal support. ► Two external alarm inputs to wake up the device. ► Two programmable periodic outputs (one for a DC/DC regulator and one for a sensor). ► Embedded 128x32 non-volatile (battery-powered) RAM. ► Embedded Power On Reset. ► Real Time Counter (48 bits; 46 bits effective). An overview of RTC block diagram is shown in Figure 2-3. The RTC contains a low-power oscillator that can use 32.768 kHz crystals. In normal operation the RTC is always powered up, even in the Power up state (see Figure 2-3). Two programmable embedded alarm counters (wrap-around) are provided to enable periodic wake-up of the remainder of the system, and one independent external component (typically a sensor). Two external alarm inputs enable wake-up of the system on external events. The global times are recorded on each external event and if the system is in the Power-ON state (see Figure 2-8), an interrupt is provided. The RTC includes a Power-On Reset (POR) circuit, to eliminate the need for an external component. The RTC contains low-leakage non-volatile (battery-powered) RAM, to enable storage of data that needs to be preserved. Total current consumption of the RTC in the worst case is typically less than 7 µA without data storage, using the 32.768 kHz oscillator. PAGE 12 OF 54 GS1011M DATA SHEET Figure 2-2: RTC Interface Diagram Resolution of the wake-up timer is one clock cycle, and, with onboard 32KHz. CLK, each 32bit effective register can provide up to 1.5 days’ worth of standby duration as the longest standby period. Polarity of the rtc_out1 pin is programmable. 2.2.5.2 Real Time Counter The Real Time Counter features: ► 48-bit length (with absolute duration dependent on the crystal frequency used). ► Low-power design. This counter is automatically reset by power-on-reset. This counter wraps around (returns to “all-0” once it has reached the highest possible “all-1” value). 2.2.5.3 RTC Outputs There are two RTC outputs (dc_dc_cntl and rtc_out1) that can be used to control external devices, such as sensors or voltage regulators. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. PAGE 13 OF 54 GS1011M DATA SHEET 2.2.5.3.1 DC_DC_CNTL During RTC Power-on-Reset (e.g. when the battery is connected), the dc_dc_cntl pin is held low; it goes high to indicate completion of RTC power-on-reset. This pin can be used as an enable into an external device such as voltage regulator. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. 2.2.5.3.2 RTC_OUT1 The rtc_out1 signal can be disabled or driven by the Wake-up Counter 2. This counter is 34 bits long, and operates in the same fashion as Wake-up Counter 1. The rtc_out1 signal can be configured to output the low-power crystal oscillator clock (i.e. the 32 kHz clock) instead of a simple state transition. Wakeup Counter 2 is automatically reset at Power-on-Reset. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. 2.2.5.4 RTC Alarm Inputs 1 and 2 The RTC inputs alarm1 and alarm2 operate as follows: ► dc_dc_cntl is set to “1” (typically enabling the power supply to the rest of the GS1011) whenever either of these inputs changes state. ► The RTC counter value is stored each time either of these inputs changes state. The inputs alarm1 and alarm2 have programmable polarity. Their task is to wake up the system (by setting dc_dc_cntl output pin to “1”) when an external event occurs. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. 2.3 Peripherals Note: For register identification and additional details on the use of shared peripherals, refer to the GS1011 Peripheral and Register Description [3]. 2.3.1 SPI There are two general-purpose SPI interfaces (each configurable as master or slave) for external sensors, memory, or external CPU interface; The slave SPI (SSPI) may be configured as a fast-speed Slave-only. The fast SPI Slave is not shared, and is accessible only by the APP CPU. The fast SPI operates only in the Motorola-compatible SPI slave modem using 8-bit words and a 64-word FIFO buffer for both transmit and receive. The serial to Wi-Fi firmware which uses the SPI interfaces uses this fast SPI mode. The master SPI block provides dual synchronous serial communication interfaces. The Master SPI block can be used in one of two modes of operations: as a serial master or a serial slave. Each block provides synchronous serial communication with slave or master devices, using one of the following protocols: ► Motorola Serial Peripheral Interface (SPI). ► Texas Instruments Synchronous Serial Protocol (SSP). ► National Semiconductor Microwire Protocol. Only Motorola Serial Peripheral Interface (SPI) timing is shown in this data sheet; however, National Semiconductor Microwire Protocol or Texas Instruments Synchronous Serial Protocol (SSP) modes are certainly supported. The SPI interface can also be used to access non-volatile external memory, such as an EEPROM block. The interface uses the SPI master mode to allow easy connection to industrystandard EEPROMs. The shared SPI blocks provide the following general features: PAGE 14 OF 54 GS1011M DATA SHEET ► 32-bit AMBA APB interface to allow access to data, control, and status information by the host processor. ► Full-duplex serial-master or serial-slave operation. ► Two clock design:  APB bus clock for bus interface and registers.  Serial input clock for core logic. ► Support of external EEPROM or other non-volatile memory. ► Programmable choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. ► Programmable control of the serial bit rate of the data transfer in serial-master mode of operation. ► Programmable phase and polarity of the bit rate clock. ► Programmable transfer modes to perform transmit and receive, transmit only, receive only and EEPROM read transfers. ► Programmable data word size (8, 16, 24 & 32 bits) for each data transfer. ► Transmit and receive FIFO buffer depth 8 words (of the selected size). ► Configurable number of slave select outputs in serial-master mode of operation: 1 to 4 serial slave- select output signals can be generated. ► Combined interrupt line with independent masking of interrupts. ► Transmit FIFO overflow, transmit FIFO empty, transmit FIFO underflow, receive FIFO full, receive FIFO underflow, receive FIFO overflow, and receive FIFO timeout interrupts. ► Transmit FIFO empty and receive FIFO full interrupts provide programmable threshold values. Both SPI blocks are configured to provide a FIFO depth of eight entries. The SPI master interface can be used to access external sensor devices, and EEPROM containing system parameters, under software control while the SPI slave interface can be used to provide control of the GS1011M from an external CPU. The recommended clock speed when using external Host to communicate with the module is 1.4MHz SPI chip select (MSPI_CS0 or MPSI_CS1) signals frame each data word. If the chip select is required to remain asserted for multiple data words, then a GPIO pin should be used for the chip select instead of the SPI chip select signals. For clock architecture and rates, please refer to section 7.1 Clock Architecture of GS1011 Peripheral and Register Description [2]. For other SPI Interface Timing, please refer to section 4.8 2.3.2 I2C The I2C block provides a two-wire I2C serial interface. It provides the following features: ► 32-bit AMBA APB interface to allow access to data, control, and status Information by the host processor. 2 2 ► Serial 2-wire I C bus, compliant to the I C Bus Specification Version 2.1. ► Supports only one transfer in Standard mode (100 Kb/s) and fast speed mode with a bit rate of up to 392 Kb/s. 2 ► Supports Multi-Master System Architecture through I C bus SCL line Synchronization and Arbitration. PAGE 15 OF 54 GS1011M DATA SHEET 2 ► Transmitter and Receiver: The I C block can act as the Transmitter or Receiver depending on the operation being performed. 2 ► Master or slave I C operation. ► 7- or 10-bit addressing. 2 2 ► Ignores CBUS addresses (an older ancestor of I C that used to share the I C bus). ► Interrupt or polled mode operation. ► Combined interrupt line triggered by:         Tx FIFO not FULL. Rx FIFO not EMPTY. Rx FIFO FULL (can be used to transfer data by host interface in bursts). Tx FIFO EMPTY (can be used to transfer data by host interface in bursts). Rx FIFO OVER RUN. Master mode to Slave Transfer Request. Slave Transmit Request. Break Interrupt (master mode): No Acknowledge received from slave for slave address or write data. ► Digital de-bounce logic for the received SDA and SCL lines. ► Hold Delay Insertion on SDA line. 2.3.3 UART The GS1011MXX includes two UART blocks. Each UART block provides an asynchronous communication interface, using only two data lines: Rx data and Tx data. Hardware flow control using RTS/CTS signaling is provided as an option. The UART is a standard asynchronous serial interface, 16450/16550 compatible. It provides the following features: ► Operation in full-duplex mode. ► All standard bit rates up to 921.6 kbps are supported. ► RTS/CTS flow control handshake (standard 16550 approach). ► 5, 6, 7 and 8-bit character format. ► 1 or 2 stop bits (1.5 in case of a 5-bit character format). ► Parity bit: none, even, odd, mark, or space. ► 16-byte Rx and 16-byte Tx FIFOs. The UART Serial port can be used to communicate with a PC or other devices, for debug or additional functionality. 2.3.4 JTAG The JTAG ports facilitate debugging of the board and system designs. This block has the following features: ► Compliant to IEEE-1149.1 TAP ports. ► One JTAG boundary scans TAP port. ► One set of JTAG pins, that support the following mode of operation: PAGE 16 OF 54 GS1011M DATA SHEET  APP ARM7TDMI-S Debug Mode. A detailed example of JTAG debug access is described in GainSpan Application Note AN-011 [4]. 2.3.5 GPIO & LED Driver / GPIO The GPIO ports are referenced to VDDIO. Two GPIO pins called GPIO30_LED1 & GPO31_LED2 have the capability to sink/source 20 mA typical (VDDIO=3.3V) to connect to devices such as switch contacts or LEDs. I2C_DATA/GPIO8 & I2C_CLK/GPIO9 have the capability to sink/source 12 mA typical (VDDIO=3.3V). Other GPIO’s have the capability to sink/source 4 mA typical (VDDIO=3.3V). All inputs are capable of generating processor interrupts. They can be individually programmed to provide edge- or level-triggered interrupts. For details on configuring GPIO ports, refer to the GS1011 Peripheral and Register Description [2]. 2.3.6 ADC The ADC is a 10-bit, low-power, A-to-D converter capable of running at up to 32 ksps. The ADC contains an internal band-gap reference which provides a stable 1.2 V reference voltage. The ADC can be programmed to use the 1.8 V supply as the full-scale reference. The ADC uses an input clock with a maximum frequency of 1 MHz. A conversion requires 32 clock cycles. When the internal band-gap reference is used, the reported integer Value at temperature T (ºC) is related to the voltage Vactual at the input pin as:  1.2444  0.00014 25  T  Vactual  Value    1023 When the 1.8V supply voltage is used as the reference, the corresponding relation is:  0.036  V Vactual  Value  DD, ADC   1023 To reduce power consumption the ADC can be disabled automatically between periodic measurements and after single measurements. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. PAGE 17 OF 54 GS1011M DATA SHEET 2.4 System States Figure 2-8 shows the power management/clock states of the GS1011Mxx system. Figure 2-3: GS1011Mxx System States The system states of the GS1011MXX system are as follows: Power OFF: No power source connected to the system. I/Os should not be driven high by an external device during this state. Standby: In the standby state, only the RTC portion of the GS1011 chip is powered from the VBAT pin. The other power supplies are turned off by the DC_DC_CNTL pin being low. Power supplies that MUST be powered on and off together, controlled by the DC_DC_CNTL pin, include the EN_1V8 pin (which controls VOUT_1V8), VDDIO, and (for the GS1011MEx but not the GS1011MIx) the VIN_3V3 pin. In standby state, the 32.768KHz oscillator keeps running and only the RTC RAM retains the state. SRAM, CPUs and I/Os are all in OFF state, as there is no 1.8V and no VDDIO being supplied to the GS1011 device. I/O pins (except alarms) should not be driven high by an external device during standby state due to diodes in the internal ESD protection PAGE 18 OF 54 GS1011M DATA SHEET circuitry. Driving I/O pins high during standby could result in incorrect operation on exit from standby state. This is the lowest-power-consumption state. In a typical application, the system returns to the Standby state between periods of activity, to keep the average power very low and enable years of operation using conventional batteries. During standby, the RTC isolates itself from the rest of the chip, since the signals from the rest of the chip are invalid. This prevents corruption of the RTC registers. Exit from standby occurs when a pre-specified wakeup time occurs, or when one of the two alarm pins sees the programmed polarity of signal edge. When one of the wakeup conditions occurs, the RTC asserts reset to the chip and sets the DC_DC_CNTL pin high to enable power to the rest of the module. After 3mS, the power to the rest of the module is assumed to be good, the isolation between the RTC and the rest of the chip is released, and the EXT_RESETn pin is released. The WLAN CPU now runs at 32KHz up to 10mS until the 44MHz oscillator is stable, at which time it switches over to running at 22MHz. Another ~25mS are required to initialize the application software. Note that the alarm pins are strictly edge detected, and cannot be read like GPIO pins. If it is necessary to read the DC level of an alarm input, the signal must be connected to a GPIO pin thru an over-voltage tolerant buffer, powered from VDDIO, so that it stops driving the GPIO pin when VDDIO is turned off in standby mode. Note: During first battery plug, i.e. when power is applied the first time to the RTC power rail (VBAT), the power detection circuit in the RTC also causes a wakeup request. The RTC startup up latency will be at least a couple of hundred ms (and may be as much as 3 seconds) as it is waiting for stabilization of the 32KHz crystal. After the oscillator startup delay, at first battery plug, there is a 7.8mS delay for power to be assumed good and a 31.25mS delay for 44MHz oscillator startup. These delays are reduced for subsequent startups by the first battery plug software. Again, ~25mS are required to initialize the application software. System Configuration: When a power-up is requested, the system transitions from the Standby state to the System Configuration state. In this state, the WLAN CPU is released from reset by the RTC. The APP CPU remains in the reset state during System Configuration. The WLAN CPU then executes the required system configurations, releases the APP CPU from reset, and transitions to the Power-ON state. The System Configuration state is also entered on transition from the Power-ON state to the Standby state, to complete necessary preparations before shutting off the power to the core system. Finally, the System Configuration state is used for firmware updates. Power-ON: This is the active state where all system components can be running. The Power-ON state has various sub-states, in which unused parts of the system can be in sleep mode, reducing power consumption. Sleep states are implemented by gating the clock signal off for a specific system component. Sleep: In the Sleep state, the 44MHz crystal remains running, but it is gated off to one or both CPUs. Each CPU can independently control its own entry into Sleep state. Any enabled interrupt will cause the interrupted CPU to exit from Sleep state, and this will occur within a few clock cycles. Deep Sleep: Deep sleep is entered only when both CPUs agree that the wakeup latency is OK. In Deep Sleep mode, the 44MHz crystal oscillator is turned off to save power, but all power supplies remain turned on. Thus all registers, memory, and I/O pins retain their state. Any enabled interrupt will cause an exit from Deep Sleep state, but this now requires startup of the 44MHz oscillator, which requires up to 10mS. The following are not system states, but are related design notes: PAGE 19 OF 54 GS1011M DATA SHEET Power Control: The GS1011 chip was designed with the intent that power to the nonRTC portions of the chip be controlled from the DC_DC_CNTL signal. In applications where it is preferred that an external host control the power, this is OK if ALL power, including VBAT power, is turned on and off by the external host. In this case, all state is lost when power goes off, and the latencies from first battery plug apply. If these latencies are not acceptable, then the GS1011 chip MUST control power. The external host would use an alarm to wake it up, and a serial command to put it into standby. And the DC_DC_CNTL pin would control the power supplies. It is NOT reliable for the external host to directly control the power supplies if VBAT is to be left turned on. This is because the RTC would not know when to isolate itself from the rest of the chip, and might get corrupted during power up or power down. EXT_RESETn pin: If the external host is driving the EXT_RESETn pin, it MUST do so with an open drain driver. This is because this pin also must be able to be driven low by the RTC and by the voltage monitor chip on the GS module. In addition, if an external host is connected to the EXT_RESETn pin, there must be an external 10K ohm pull-up resistor on the board, pulling up to VDDIO. This is needed to overcome a possible pull-down in the host at first power application. It is also recommended that the host not actively assert EXT_RESETn until all the startup latencies have expired. One possible usage of the EXT_RESETn pin by an external host is to monitor the pin as an input to detect when the 32KHz oscillator has started up after first application of VBAT power. When the EXT_RESETn pin goes high, the oscillator has started. Under most conditions, this will be considerably faster than the 3 second worst case. It should also be noted that the constraint that I/O pins not be driven high during standby also applies to the EXT_RESETn pin. It should be pulled only to VDDIO, which shuts off in standby mode. For more information, consult the GS1011 Peripheral and Register Description [2] and GS1011 SoC data sheet [3] for detailed descriptions. PAGE 20 OF 54 GS1011M DATA SHEET 2.5 Power Supply In this section, diagrams are shown for various application power supply connection. Figure 2-4 : GS1011Mxx Always ON Power Supply Connection Notes: 1) Always On is obtained by tying EN_1V8 to 1 which is the enable for the 1.8V voltage regulator. 2) In this state system can still go to deep sleep state and take advantage of low power consumption, but system will not go into the lowest power consumption state (i.e. standby state). PAGE 21 OF 54 GS1011M DATA SHEET Figure 2-5: GS1011MIx Battery Powered with 3.3V IO and Standby Support This connection applies for designs (typically battery operated) using GS1011MI module and want to utilize standby (lowest current consumption) state of the module. In this connection it is important to note the following: 1) Input voltage to VBAT must always be ON to keep the RTC powered so that the 32KHz crystal is running. 2) VDDIO power should be OFF during this state. Recommendation is to use DC_DC_CNTL to also control the unit supplying the voltage to VDDIO 3) DC_DC_CNTL must be connected to EN_1V8 to so that the internal 1.8V regulator gets turned OFF when system goes to standby state (i.e. DC_DC_CNTL is de-asserted). PAGE 22 OF 54 GS1011M DATA SHEET Figure 2-6 : GS1011ME Battery Powered with 3.3V IO and Standby Support Applications that require Standby Mode and use GS1011ME MUST use this connection configuration to take advantage of the lowest power consumption during standby mode. In this connection it is important to note the following: 1) GS1011ME, module PA is supplied with VIN_3V3 and in-rush current for PA transmission; thus, the 3.3V DC/DC Regulator may have to be an Up/Down regulator depending on the battery used 2) For GS1011ME, VDDIO and VIN_3V3 power MUST be shut OFF in standby mode so there is no leakage from PA device and thus achieve the lowest current consumption. PAGE 23 OF 54 GS1011M DATA SHEET GS1011MIx Figure 2-7 : GS1011MI Battery Powered with 1.8V only and Standby Support This connection applies only to GS1011MI based designs that want standby support and use 1.8V power. 1) DC_DC_CNTL should be tied to EN_1V8 to turn off the built-in 1.8V regulator in standby mode. This keeps the current consumption to the minimum 2.5.1 Power Supply Connection Summary Module Standby Support required 1V8_EN Connection VIN_3V3 in Standby VDDIO VDDIO in Standby Standby Wake-Up Latency Refer to Figure GS1011MI No (always on or deep sleep) Supply Voltage ON 3.3V ON NA Fig 2.4 GS1011MI Yes DC_DC_CNTL ON 3.3V OFF < 15ms Fig 2.5 GS1011MI Yes DC_DC_CNTL ON 1.8V OFF < 15ms Fig 2.7 GS1011ME rev 1.1 Yes DC_DC_CNTL OFF 3.3V OFF < 15ms Fig 2.6 PAGE 24 OF 54 GS1011M DATA SHEET GS1011ME rev 1.1 No (always on or deep sleep) Supply Voltage ON 3.3V ON NA Fig 2.4 For designs that plan to use standby and would like to use a single baseboard that supports either the GS1011MI or GS1011ME module, then they should follow Figure 2-8 example for connections. Figure 2-8: Single board design using either GS1011MI or GS1011ME modules with Standby Support Resistor R1 and R2 are stuffing options depending on the type of Module used. See table below: Module Stuffing Option Equivalent Circuit GS1011MI R1 Only Fig 2.5 GS1011ME R2 Only Fig 2.6 PAGE 25 OF 54 GS1011M DATA SHEET 3 Pin-out and Signal Description 3.1 GS1011Mxx Device Pin-out Diagram (Module top view) Figure 3-1: GS1011Mxx Device Pin-out Diagram (Module top view) PAGE 26 OF 54 GS1011M DATA SHEET 3.1.1 GS1011Mxx Module Pins Description Pins Name Voltage Domain Internal Bias after hardware reset Signal State Description 1 GND 0V Not Applicable Analog port Ground 2 JTAG_TCK VDDIO Pull-up (See Note 1) Digital Input Joint Test Action Group Test Clock 3 JTAG_TDO VDDIO Not Applicable Digital Output Joint Test Action Group Test Data Out 4 JTAG_TDI VDDIO Pull-up (See Note 1) Digital Input Joint Test Action Group Test Data In 5 JTAG_TMS VDDIO Pull-up (See Note 1) Digital Input Joint Test Action Group Test Mode Select 6 JTAG_nTRST VDDIO Pull-up (See Note 1) Digital Input Joint Test Action Group Test Mode Reset Active Low 7 ALARM1 VBAT Pull-down (See Note 1) RTC Input Embedded Real Time Clock Wake Up Input 1 8 RTC_OUT1 VBAT Not Applicable RTC Output Embedded Real Time Clock Wake Up Output 1 9 VBAT VBAT Not Applicable Analog port Embedded Real Time Clock Power Supply 10 DC_DC_CNTL VBAT Not Applicable Digital Output VIN_3V3 Regulator Control Output 11 ADC1 VDD18 Not Applicable Analog Input General Analog to Digital Converter 1 Not Applicable Analog Input General Analog to Digital Converter 2 (internal) 12 ADC2 VDD18 (internal) 13 ALARM2 VBAT Pull-down (See Note 1) RTC Input Embedded Real Time Clock Wake Up Input 2 14 MSPI_DIN / GPIO6 VDDIO Pull-down Digital Input / Output Master Serial Peripheral Interface Bus Data Input / General Purpose Input Output 15 MSPI_DOUT / GPIO7 VDDIO Pull-down Digital Input / Output Master Serial Peripheral Interface Bus Data Output / General Purpose Input Output 16 VOUT_1V8 VIN_3V3 Not Applicable Analog port Internal 1.8V Vout (internally regulated) 17 GND 0V Not Applicable Analog port Ground 18 MSPI_CLK / GPIO5 VDDIO Pull-down Digital Input / Output Master Serial Peripheral Interface Bus Clock / General Purpose Input Output 19 MSPI_CS0 / GPIO4 VDDIO Pull-down Digital Input / Output Master Serial Peripheral Interface Bus Chip Select 0 / General Purpose Input Output 20 MSPI_CS1 / GPIO13 VDDIO Pull-down Digital Input / Output Master Serial Peripheral Interface Bus Chip Select 1 / General Purpose Input Output 21 GPO21_11MHZ VDDIO Pull-down Digital Input / Output Internal Clock Circuitry Test Point / General Purpose Input Output 22 GPO20_22MHZ VDDIO Pull-down Digital Input / Output Internal Clock Circuitry Test Point / General Purpose Input Output PAGE 27 OF 54 GS1011M DATA SHEET Pins Name Voltage Domain Internal Bias after hardware reset Signal State Description 23 GPO19_44MHZ VDDIO Pull-down Digital Input / Output Internal Clock Circuitry Test Point / General Purpose Input Output 24 PWM0 / GPIO10 VDDIO Pull-down Digital Input / Output Pulse Width Modulator / General Purpose Input Output 25 I2C_CLK/GPIO9 VDDIO Pull-down (NOTE 4) Digital Input / Output Inter-Integrated Circuit Clock / General Purpose Input Output 26 I2C_DATA/GPIO8 VDDIO Pull-down (NOTE 4) Digital Input / Output Inter-Integrated Circuit Data / General Purpose Input Output 27 SSPI_DOUT VDDIO Pull-up (See Note 1) Digital Output 28 SSPI_CLK VDDIO Pull-up (See Note 1) Digital Input SPI Slave Transmit Data Output to the HOST SPI Slave Clock Input from the HOST 29 SSPI_CS VDDIO Pull-up (See Note 1) Digital Input 30 SSPI_DIN VDDIO Pull-down (See Note 1) Digital Input SPI Slave Chip Select Input from the HOST SPI Slave Receive Data Input from the HOST 31 VIN_3V3 VIN_3V3 Not Applicable Analog port Single Supply Port 32 GND 0V Not Applicable Analog port Ground 33 EN_1V8 VDDIO Need to be driven HIGH or LOW externally Digital Input Internal 1.8V regulator enable port-Active High 34 VDDIO VDDIO Not Applicable Analog port All I/O voltage domain (can be tied to VIN_3V3 or tied to HOST I/O supply) 35 UART1_CTS / GPIO26 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 1 Clear to Send Input (See Note 6) / General Purpose Input Output 36 UART1_RTS / GPIO27 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 1 Request to Send Output (See Note 6) / General Purpose Input Output UART1_RX / GPIO3 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 1 Receive Input / General Purpose Input Output VDDIO Pull-down Digital Input/ Output Universal Asynchronous Receiver Transmitter 1 Transmitter Output / General Purpose Input Output 37 38 UART1_TX/ GPIO2 (See Note 2) 39 UART0_TX / GPIO1 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 0 Transmitter Output / General Purpose Input Output 40 UART0_RTS / GPIO25 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 0 Request to Send Output (See Note 6) / General Purpose Input Output 41 UART0_RX / GPIO0 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 0 Receive Input / General Purpose Input Output PAGE 28 OF 54 GS1011M DATA SHEET Pins Name Voltage Domain Internal Bias after hardware reset Signal State Description 42 UART0_CTS / GPIO24 VDDIO Pull-down Digital Input / Output Universal Asynchronous Receiver Transmitter 0 Clear to Send Input (See Note 6) / General Purpose Input Output 43 GPO31_LED2 VDDIO Pull-down Digital Input / Output Light Emitting Diode Driver / General Purpose Input Output 44 GPIO30_LED1 VDDIO Pull-down Digital Input / Output Light Emitting Diode Driver / General Purpose Input Output 45 GPIO29 VDDIO Pull-down Digital Input / Output General Purpose Input Output Digital Input / Output General Purpose Input Output Digital Open Drain Module Hardware Reset Input and Power Supply Reset Monitor Indictor Input / Output Active Low Analog port Ground (See Note 3) 46 GPIO28 VDDIO Pull-down (See Note 3) 47 EXT_RESETn VDDIO Pull-up (See Note 5) 48 GND 0V Not Applicable Table 3-1: Signal Description Notes: 1. These pins have onboard hardware configured pull-ups/downs and cannot be changed by software. 2. If UART1_RTS (GPIO27) is high during reset or power on, then the GS1011M will wait for Flash download via UART0 or SSPI interface. Route this pin on the base board so it can be pulled up to VDDIO for programming the module. 3. GPIO 28 and 29 are sampled at reset to establish JTAG configuration for debugging. These signals should not be driven from an external device. If using JTAG, configure these pins as outputs. 4. If I C interface is used, provide 2K Ohm pull-ups, to VDDIO, for pins 25 and 26 (I2C_CLK and I2C_DATA) 5. EXT_RESETn is an active low signal. It is an output during power up, indicating to the system when GS1011 device is out of power-on-reset. After power-on-reset, this pin is an input. It is not necessary to assert reset to the GS1011M after power on, since the GS1011 has a built-in power on reset. Also, the EXT_RESETn signal does not clear the RTC RAM or the SRAM. If the external host is driving the EXT_RESETn pin, it MUST do so with an open drain driver. This is because this pin also must be able to be driven low by the RTC and by the voltage monitor chip on the GS module. In addition, if an external host is connected to the EXT_RESETn pin, there must be an external 10K ohm pull-up resistor on the board, pulling up to VDDIO. 6. CTS and RTS signals indicate it is clear to send or ready to send when they are LOW. If signals are high, indicates device is not ready. 2 PAGE 29 OF 54 GS1011M DATA SHEET Figure 3-2: Module pin connection diagram Note 1) For the noted pin configurations, please refer to data sheet power supply section. Note 2) If I2C interface is used, provide 2KOhm pull-ups, to VDDIO, for pins 25 and 26 (I2C_CLK and I2C_DATA). If not used, leave pins 25 and 26 as No Connects. Note 3) Connect to external HOST SPI (can be left as No Connects if not used). Note 4) Connect to external serial HOST UART (can be left as No Connections if not used) Note 5) Modules ship with only test firmware and so design must bring out this pin so to enable programming of GS1011M onboard flash. Switch is recommended for development purposes. For production it is recommended designers provide option to pull this pin (GPIO27) high during reset or power-on for in-circuit programming of the module. Note 6) The need for external flash memory depends on advanced firmware features selected/required such as factory backup, a more robust over-the-air firmware update, or web pages. The serial flash memory should be instruction set compliant with Micron M25P80. See module design guidelines document for supported flash sizes and devices. PAGE 30 OF 54 GS1011M DATA SHEET 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Conditions beyond those cited in Table 4-1 may cause permanent damage to the GS1011MXX, and must be avoided. Sustained operation, beyond the normal operating conditions, my affect the long term reliability of the module. Parameter Storage temperature RTC Power Supply I/O Supply voltage Single Supply Port Signal Pin Voltage 1 Symbol TST Vbat VDDIO VIN_3V3 Minimum -55 -0.5 -0.5 0.5 VI -0.3 Typical 3.3 Maximum +125 4.0 4.0 4.0 Voltage Domain + 0.3 Unit ºC V V V V Table 4-1: Absolute Maximum Ratings NOTE: 1Reference domain voltage is the Voltage Domain per section 3.1.1 For limitations on state voltage ranges, please consult section 3.1.1 4.2 Operating Conditions Parameter Extended temp. range RTC Power Supply I/O Supply voltage Single Supply Port GS1011MIx (as configured per Figure 2-4, 5, & 7) Single Supply Port GS1011MEx (as configured per Figure 2-6) Signal Pin Voltage 1 Symbol TA Vbat VDDIO Minimum -40 1.6 1.7 Typical 3.3 3.3 Maximum +85 3.6 3.6 Unit ºC V V VIN_3V3 2.7 3.3 3.6 V VIN_3V3 3.0 3.3 3.6 V VI 0 Voltage Domain V Table 4-2: Operating Conditions NOTE: 1Reference domain voltage is the Voltage Domain per section 3.1.1 PAGE 31 OF 54 GS1011M DATA SHEET 4.3 Internal 1.8V regulator VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC fOSC=3.0MHz Parameter Test conditions Symbol Output Voltage Maximum Output Current Oscillation Frequency 1.8V Regulator Enable "H" Voltage 1.8V Regulator Enable "L" Voltage Minimum Typical Maximum Unit VOUT_1V8 IVOUT_1V8 fOSC 1.8 30 1.6 50 3.45 V mA MHz EN_1V8 1.0 VIN_3V3 V EN_1V8 0 0.25 V Table 4-3: Internal 1.8V Regulator 4.4 I/O DC Specifications 4.4.1 Digital Input Specifications Parameter Input Low Voltage Symbol VIL Input High Voltage VIH Minimum -0.3 0.8* VDDIO Typical Maximum 0.25* VDDIO Unit V VDDIO V Note Table 4-4: Digital Input Parameters 4.4.2 Digital Output Specification Parameter Output Low Voltage Output High Voltage Output rise time @ VDDIO=3.3V Output fall time @ VDDIO=3.3V Symbol Mininum VOL 0 Typical Maximum Unit Note 0.4 V With 4 mA load 2.4V VOH VDDIO V tTLH 7 ns tTHL 7 ns 1.3V VDDIO=3.0V, DC current load 4.0 mA VDDIO =1.62 V, DC current load 2.0 mA With 4 mA, 33 pF load With 4 mA, 33 pF load Table 4-5: Digital Output Parameters PAGE 32 OF 54 GS1011M DATA SHEET 4.4.3 I/O Digital Specifications (Tri-State) Parameter Input Low Voltage Input High Voltage Schmitt trig. Low to High threshold point Schmitt trig. High to Low threshold point Input Leakage Current Tri-State Output Leakage Current Pull-Up Resistor Pull-Down Resistor Output Low Voltage Symbol VIL VIH Mininum -0.3 0.8* VDDIO VT+ 1.5 Typical Maximum 0.25* VDDIO Unit V VDDIO V V VT- 1 V IL 5 A OzL 5 A Ru 0.05 1 M Rd 0.05 1 M VOL 0 0.4 V VDDIO V tToLH 7 ns tToHL 7 ns tTiLH tTiHL 7 7 ns ns 2.4V Output High Voltage VOH 1.3 V Output rise time @ VDDIO =3.3V Output fall time @ VDDIO = 3.3V Input rise time Input fall time Note Pull up/down disabled Pull up/down disabled With 4/12/20 mA load VDDIO=3.0V With 4/12/20 mA load VDDIO =1.62 V With 2/6/10 mA load With 4/12/20 mA load, 33 pF With 4/12/20 mA load, 33 pF Table 4-6: I/O Digital Parameters 4.4.4 RTC Input Specifications (with Schmitt Trigger) Parameter I/O Supply Voltage Input Low Voltage Input High Voltage Schmitt trig. Low to High threshold point Schmitt trig. High to Low threshold point Input Leakage Current Symbol VDDRTC VIL VIH Mininum 1.2 -0.3 0.8*VDDRTC VT+ VTIL Typical Maximum Vbat 0.25*VDDRTC VDDRTC Unit V V V 0.57*VDDRTC 0.68*VDDRTC V 0.27*VDDRTC 0.35*VDDRTC V 260 Note pA Table 4-7: RTC Input Parameters PAGE 33 OF 54 GS1011M DATA SHEET 4.4.5 RTC Output Specifications Parameter I/O Supply Voltage Output Low Voltage Output High Voltage Output rise time Output fall time Input Leakage Current Symbol VDDRTC VOL VOH tTLH tTHL IL Mininum 1.2 0 0.8*VDDRTC 19 21 Typical Maximum Vbat 0.4 VDDRTC 142 195 Unit V V V ns ns pA 730 Note 50 pF load 50 pF load Table 4-8: RTC Output Parameters 4.5 Power Consumption (Estimated) Typical Conditions: VDD33=VDDIO=Vbat=3.3V Temp=25ºC; Max is across operating conditions System state Standby Deep Sleep (GS1011MI) Deep Sleep (GS1011ME) Receive (GS1011Mxx; -81 dBm RX sens. @ 11Mb/Sec. Transmit (GS1011MIx; +9 dBm at antenna port @ 11Mb/Sec.) Transmit (GS1011MEx; +18 dBm at antenna port @ 11Mb/Sec.) Current (Typ.) 7uA 150uA 200uA 140mA 150mA 250mA Current (Max) 250mA 350mA Table 4-9: Power Consumption in Different States 4.6 Radio Parameters Test Conditions: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC Parameter RF Frequency range Radio bit rate Minimum 2412 1 Typical Maximum 2497 11 Unit MHz Mbps Notes Ch 14 max is 2 Mbps TX/RX specification for GS1011MIx Output power (average) 9 dBm Modulated signal at antenna port; 11Mb/Sec. dBr Modulated signal at antenna port dBm 11 Mbps CCK, 8% PER 5.5 Mbps CCK, 8% PER 2 Mbps QPSK, 8% PER 1 Mbps BPSK, 8% PER Spectrum Mask F0 +/- 11 MHz Offset >= 22 MHz Receive Sensitivity at antenna port -30 -50 -83 -86 -90 -92 PAGE 34 OF 54 GS1011M DATA SHEET Parameter Minimum Typical Maximum Unit Notes dBm Modulated signal at antenna port; 11Mb/Sec. dBr Modulated signal at antenna port dBm 11 Mbps CCK, 8% PER 5.5 Mbps CCK, 8% PER 2 Mbps QPSK, 8% PER 1 Mbps BPSK, 8% PER TX/RX specification for GS1011MEx Output power (average) 18 Spectrum Mask F0 +/- 11 MHz Offset >= 22 MHz -30 -50 -83 -86 -90 -92 Receive Sensitivity at antenna port 100-byte packet Table 4-10: Radio Parameters 4.7 ADC Parameters Test Conditions: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC Parameter ADC Resolution ADC Sample Freq ADC input Clock Freq ADC Full Scale Voltage Minimum 1.024 Typical 10 - Maximum 31.25 Unit Bits ksps 32.768 - 1000 kHz - VOUT_1V8 – 0.036 VOUT_1V8 V 1.169 1.24 1.311 3.527 3.73 3.913 Conversion Time 32 Clocks ADC Integral Non-Linearity (INL) -2.0 - 2.0 LSB ADC Differential non-linearity (DNL) -1.0 - 1.0 LSB - 400 800 A ADC Offset Error -10 - 10 mV ADC Gain Error -10 - 10 mV - 1 S AVDD Power Supply current (operational) Settling Time Input resistance 1 - - MOhm Input Capacitance - 10 - pF 1.179 1.24 1.301 V Bandgap Output Voltage (Vref) (T = 25 ºC) Notes Reference =VOUT_1V8 Reference = bandgap Measuring Vbat Based on internally generated 1MHz or 32.768 KHz Clocks Table 4-11: ADC Parameters PAGE 35 OF 54 GS1011M DATA SHEET 4.8 SPI Interface Timing Test Conditions: VIN_3V3=VDDIO=Vbat=3.3V Temp=25ºC 4.8.1 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 0 Parameter Figure 4-1: timing diagram, Master mode, SPO=SPH=0. Description Minimum Maximum tSSetup Minimum time between falling edge of Select line and first rising edge of SPI clock tTxdDelay Delay in Master asserting TX line after falling edge of Select line tRxdSetup tRxdHold tSSHold Time before rising edge of SPI clock by which received data must be ready Time for which received data must be stable after rising edge of SPI clock Time for which the Select line will be held after the sampling edge for the final bit to be transferred Unit MSPI clock period 1 2 core SPI clock periods + 3 nsec mixed 30 nsec 10 nsec 1 MSPI clock period Table 4-12: timing parameters, Master mode, SPO=SPH=0. PAGE 36 OF 54 GS1011M DATA SHEET Figure 4-2: timing diagram, Slave mode, SPO=SPH=0. Parameter tSSetup tTxdDelay tRxdSetup Description Minimum Minimum time between falling edge of Select line and first rising edge of SPI clock. 4 core SPI clock periods + 68 ns Delay in Slave asserting TX line after falling edge of SPI clock, or the first bit after falling edge of the Select line. Time before rising edge of SPI clock by which received data must be ready tRxdHold Time for which received data must be stable after rising edge of SPI clock tSSHold Time for which the Select line will be held after the sampling edge for the final bit to be transferred Maximum Unit mixed 4 core SPI clock periods + 68 ns 15 3 core SPI clock periods + 14 ns 3 core SPI clock periods + 14 ns mixed ns mixed mixed Table 4-13: timing parameters, Slave mode, SPO=SPH=0. PAGE 37 OF 54 GS1011M DATA SHEET 4.8.2 Motorola SPI, clock polarity SPO = 0, clock phase SPH = 1 Parameter tSSetup tTxdDelay tRxdSetup tRxdHold tSSHold Figure 4-3: timing diagram, Master, SPO=0, SPH=1. Description Minimum Maximum Minimum time between falling edge of select line and first rising edge of SPI clock. Delay in Master asserting TX line after rising edge of SPI clock. Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. Unit MSPI clock period 1.5 0 ns 30 ns 10 ns 0.5 MSPI clock period Table 4-14: timing parameters, Master mode; SPO=0, SPH=1. PAGE 38 OF 54 GS1011M DATA SHEET Figure 4-4: timing diagram, Slave, SPO=0, SPH=1. Parameter Description tSSetup Minimum time between falling edge of select line and first rising edge of SPI clock. tTxdDelay Delay in Slave asserting TX line after rising edge of SPI clock. tRxdSetup Time before falling edge of SPI clock by which received data must be ready. tRxdHold Time for which received data must be stable after falling edge of SPI clock. tSSHold Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. Minimum Maximum 15 Unit ns 4 core SPI clock periods + 68 ns 15 3 core SPI clock periods + 14 ns 3 core SPI clock periods + 14 ns mixed ns mixed mixed Table 4-15: timing parameters, Slave mode, SPO=0, SPH=1. PAGE 39 OF 54 GS1011M DATA SHEET 4.8.3 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 0 Figure 4-5: timing diagram, Master mode, SPO=1, SPH=0. Parameter Description Minimum tSSetup Minimum time between falling edge of select line and first falling edge of SPI clock. 1 tTxdDelay Delay in Master asserting TX line after falling edge of Select line. tRxdSetup tRxdHold tSSHold Time before falling edge of SPI clock by which received data must be ready. Time for which received data must be stable after falling edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. Maximum Unit MSPI clock period 2 core SPI clock periods + 3 ns mixed 30 ns 10 ns 1 MSPI clock period Table 4-16: timing parameters, Master mode, SPO=1, SPH=0. PAGE 40 OF 54 GS1011M DATA SHEET Parameter tSSetup tTxdDelay tRxdSetup Figure 4-6: timing diagram, Slave mode, SPO=1, SPH=0. Description Minimum Maximum Minimum time between falling edge of Select line and first falling edge of SPI clock. Delay in Slave asserting TX line after rising edge of SPI clock, or the first bit after falling edge of the Select line. Time before falling edge of SPI clock by which received data must be ready. tRxdHold Time for which received data must be stable after falling edge of SPI clock. tSSHold Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. 4 core SPI clock periods + 68 ns Unit Mixed 4 core SPI clock periods + 68 ns 15 3 core SPI clock periods + 14 ns 3 core SPI clock periods + 14 ns Mixed ns Mixed MSPI clock period Table 4-17: timing parameters, Slave mode, SPO=1, SPH=0. PAGE 41 OF 54 GS1011M DATA SHEET 4.8.4 Motorola SPI, clock polarity SPO = 1, clock phase SPH = 1 Parameter tSSetup tTxdDelay tRxdSetup tRxdHold tSSHold Figure 4-7: timing diagram, Master mode, SPO=SPH=1. Description Minimum Maximum Minimum time between falling edge of select line and first falling edge of SPI clock. Delay in Master asserting TX line after falling edge of SPI clock. Time before rising edge of SPI clock by which received data must be ready. Time for which received data must be stable after rising edge of SPI clock. Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. Unit MSPI clock period 1.5 0 ns 30 ns 10 ns 0.5 MSPI clock period Table 4-18: timing parameters, Master mode, SPO=SPH=1. PAGE 42 OF 54 GS1011M DATA SHEET Parameter Figure 4-8: timing diagram, Slave mode, SPO=SPH=1. Description Minimum Maximum tSSetup Minimum time between falling edge of select line and first falling edge of SPI clock. tTxdDelay Delay in Slave asserting TX line after falling edge of SPI clock. tRxdSetup Time before rising edge of SPI clock by which received data must be ready. tRxdHold Time for which received data must be stable after rising edge of SPI clock. tSSHold Time for which the Select line will be held low after the sampling edge for the final bit to be transferred. 15 Unit ns 4 core SPI clock periods + 68 ns 15 3 core SPI clock periods + 14 ns 3 core SPI clock periods + 14 ns Mixed ns Mixed Mixed Table 4-19: timing parameters, Master mode, SPO=SPH=1. PAGE 43 OF 54 GS1011M DATA SHEET 5 Package and Layout Guidelines 5.1 GS1011Mxx Recommended PCB Footprint and Dimensions Figure 5-1: GS1011MIx Module Recommended PCB Footprint (in inches) PAGE 44 OF 54 GS1011M DATA SHEET Figure 5-2: GS1011MIx Module Dimensions (in inches) Figure 5-3: GS1011MEx Module Recommended PCB Footprint (in inches) PAGE 45 OF 54 GS1011M DATA SHEET Figure 5-4: GS1011MEx Module Dimensions (in inches) 5.2 GS1011MxP Layout Guidelines Figure 5-5: GS1011MxP module onboard antenna keep-out layout guidelines (dimensions are in inches) If application baseboard is being designed to accommodate both GS1011MIP and GS1011MEP, then customer may follow the recommendation as shown in PAGE 46 OF 54 GS1011M DATA SHEET Figure 5-6 Recommended keep out area to accommodate both GS1011MIP and GS1011MEP Notes: 1. All Dimensions are in inches. Tolerances shall be ±0.010 inches. 2. Absolutely no metal trace or ground layer underneath this area. 3. It is recommended not to run circuit traces underneath the module especially near these holes; The RF shield mounting holes are grounded. If traces must be routed under the GS1011Mxx, it is recommended that extra thick solder mask (5 mils) be used to prevent shorting. High speed signals should be kept as far as possible from the antenna and RF areas of the GS1011Mxx. 4. In performing SMT or manual soldering of the module to the base board, first align the row of pins from #18 thru 31 onto the base board and then match the other two rows. In addition to the guidelines in Figure 5-6, note the following suggestions: GS1011MEx and GS1011MIx  External Bypass capacitors for all module supplies should be as close as possible to the module pins.  Never place the antenna very close to metallic objects.  External monopole antennas need a reasonable ground plane area for antenna efficiency. GS1011MxP on board PCB antenna specific  For best RF performance, it is recommended that the PCB antenna hang over the edge of the base board, so that there is no FR4 under it or next to it.  The PCB antenna keep out area, as shown in Figure 5-4, must be adhered to. Ground plane on the base board should be kept further away if possible, and should not fully enclose the PCB antenna.  Do not use a metallic or metalized plastic for the end product enclosure.  Recommendation is to keep plastic enclosure clearance of 1cm from top and bottom of the GS1011M PCB antenna keep-out area, if possible. 5-mm (0.2 in) clearance shall be the minimum as shown in Figure 5-7. PAGE 47 OF 54 GS1011M DATA SHEET Figure 5-7 Recommended clearance above and below the GS1011MxP trace antenna 5.2.1 Surface Mount Assembly The reflow profile1 is shown in Figure 5-8. Recommended reflow parameters are summarized in Table 5-1. Figure 5-8: Reflow temperature profile. PreHeat 2 Temperature Ramp up rate for (A) 1.5~3.5 C/s Pre-heat time (B)3 (130 – 200  C) Pre-heat ending temperature (C)4 80 to 130 seconds 180 to 200  C 5 Heating Peak Temperature range (D) Melting time that is the time over 220 C (E) Cool Down Ramp (F) 240 to 250 C 50 to 75 seconds >2 C/s Table 5-1: Recommended reflow parameters. PAGE 48 OF 54 GS1011M DATA SHEET Note: 1. Perform adequate test in advance as the reflow temperature profile will vary accordingly to the conditions of the parts and boards, and the specifications of the reflow furnace. 2. Max number of reflows supported are two 3. Be careful about rapid temperature rise in preheat zone as it may cause excessive slumping of the solder paste. 4. If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will generate in clusters at a time. 5. If the temperature is too low, non-melting tends to be caused in the area with large heat capacity after reflow. 6. Be careful about sudden rise in temperature as it may worsen the slump of solder paste. 7. Be careful about slow cooling as it may cause the positional shift of parts and decline in joining strength at times. 8. A no clean flux should be used during SMT process. Note: The modules are shipped in sealed trays with the following conditions: 250 PAGE 49 OF 54 GS1011M DATA SHEET 6 Ordering Information DEVICE DESCRIPTION ORDERING NUMBER Rev Extended range module using PCB antenna GS1011MEP 1.1 Extended range module using external antenna GS1011MEE 1.1 Extended range module using PCB antenna GS1011MEP 1.31 Extended range module using external antenna GS1011MEE 1.31 DEVICE DESCRIPTION ORDERING NUMBER Low power module using PCB antenna GS1011MIP 1.2 Low power module using external antenna GS1011MIE 1.2 Low power module using PCB antenna GS1011MIP 1.31 Low power module using external antenna GS1011MIE 1.31 1. Rev 1.3 uses B0 version of the GS1011 SoC Note: Modules ship with only test code. Designers must first program the modules with a released firmware version. Designers should bring out GPIO27 pin (option to pull this pin to VDDIO during reset or power-on) and UART0 or SSPI pins to enable programming of firmware into the module. For details refer to the Programming GainSpan Modules document. PAGE 50 OF 54 GS1011M DATA SHEET 7 Regulatory Notes Federal Communication Commission Interference Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: - Reorient or relocate the receiving antenna. - Increase the separation between the equipment and receiver. - Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. - Consult the dealer or an experienced radio/TV technician for help. FCC Caution: To assure continued compliance, (example - use only shielded interface cables when connecting to computer or peripheral devices). Any changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate this equipment. This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. IMPORTANT NOTE: FCC & IC Radiation Exposure Statement: This equipment complies with FCC & IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20cm between the radiator & your body. This transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. This device is intended only for OEM integrators under the following conditions: 1) The antenna must be installed such that 20 cm is maintained between the antenna and users, and 2) The transmitter module may not be co-located with any other transmitter or antenna. As long as 2 conditions above are met, further transmitter test will not be required. However, the OEM integrator is still responsible for testing their end-product for any additional compliance requirements required with this module installed (for example, digital device emissions, PC peripheral requirements, etc.). IMPORTANT NOTE: In the event that these conditions cannot be met (for example certain laptop configurations or co-location with another transmitter), then the FCC & IC authorizations are no longer considered valid and the FCC & IC IDs cannot be used on the final product. In these circumstances, the OEM integrator will be responsible for re-evaluating the end product (including the transmitter) and obtaining separate FCC & IC authorizations. End Product Labeling This transmitter module is authorized only for use in device where the antenna may be installed such that 20 cm may be maintained between the antenna and users (for example access points, routers, wireless ADSL modems, and similar equipment). The final end product must be labeled in a visible area with the corresponding FCC ID number. IC Certification — Canada PAGE 51 OF 54 GS1011M DATA SHEET The labeling requirements for Industry Canada are similar to those of the FCC. A visible label on the outside of the final product must display the IC labeling. The user is responsible for the end product to comply with IC ICES-003 (Unintentional radiators) Manual Information That Must be Included The user’s manual for end users must include the following in-formation in a prominent location. IMPORTANT NOTE: To comply with FCC & IC RF exposure compliance requirements, the antenna used for this transmitter must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter. Other notes: GainSpan modules have been built or under development for near body exposure applications. The 20cm statement is a standard note because absorption rate testing (commonly known as SAR or Specific absorption rate) is not modularly transferable for FCC/IC. Thus, if a radio is being used against the body, the end user is still responsible to test for regulatory near body exposure testing (for USA, please refer to the following): • FCC Part 1.1037 • FCC Part 2.1091 Mobile Devices • FCC Part 2.1093 Portable Devices • FCC Part 15.247 (b) (4) PAGE 52 OF 54 GS1011M DATA SHEET 8 Limitations THIS DEVICE AND ASSOCIATED SOFTWARE ARE NOT DESIGNED, MANUFACTURED OR INTENDED FOR USE OR RESALE FOR THE OPERATION OF APPLICATION IN A HAZARDOUS ENVIRONMENT, OR REQUIRING FAIL-SAFE PERFORMANCE, OR IN WHICH THE FAILURE OF PRODUCTS COULD LEAD DIRECTLY TO DEATH, PERSONAL INJURY, OR SEVERE PHYSICAL OR ENVIRONMENTAL DAMAGE (COLLECTIVELY, "HIGH RISK APPLICATIONS"). YOU AGREE AND ACKNOWLEDGE THAT YOU HAVE NO LICENSE TO, AND SHALL NOT (AND SHALL NOT ALLOW A THIRD PARTY TO) USE THE TECHNOLOGY IN ANY HIGH RISK APPLICATIONS, AND LICENSOR SPECIFICALLY DISCLAIMS ANY WARRANTY REGARDING, AND ANY LIABILITY ARISING OUT OF, HIGH RISK APPLICATIONS. PAGE 53 OF 54 GS1011M DATA SHEET 9 References [1] [2] [3] [4] Title Reference Version Source Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications IEEE Standard 802.11-2007 Title Reference Version Source GS1011 Peripheral and Register Description GS1011-PRD Title Reference Version Source GS1011 ULTRA LOW-POWER WIRELESS SYSTEM-ON-CHIP DATA SHEET GS1011-DS Title Reference Version Source Programming the GainSpan Modules PG001 IEEE GainSpan GainSpan GainSpan PAGE 54 OF 54